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NuBusFPGA
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NuBusFPGA/nubus-to-ztex-gateware
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Romain Dolbeau 3f3371a054 fix messed up timing... 2022-07-14 08:54:23 +02:00
..
ConsoleTest update to first tested version 2022-04-17 11:25:48 +02:00
DeclROM detect slot in INIT; detect slot in RAMDsk driver ; auto-mount RAMDDsk 2022-06-26 12:31:43 +02:00
NuBusFPGAInit checking in slot 2022-06-26 13:22:12 +02:00
.gitignore LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650 2022-06-24 23:37:18 +02:00
74fct245.v push to github 2021-12-21 08:26:30 +01:00
CG6.scala commit current Vex config 2022-06-05 18:04:00 +02:00
DepVideoEqu.a update to first tested version 2022-04-17 11:25:48 +02:00
GenGoblinAccel.scala LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650 2022-06-24 23:37:18 +02:00
MakeFile push to github 2021-12-21 08:26:30 +01:00
NuBusFPGADrvr.a update to first tested version 2022-04-17 11:25:48 +02:00
NuBusFPGAPrimaryInit.a update to first tested version 2022-04-17 11:25:48 +02:00
NuBusFPGASecondaryInit.a update to first tested version 2022-04-17 11:25:48 +02:00
VexRiscv_FbAccel.v LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650 2022-06-24 23:37:18 +02:00
blit.c better patterns 2022-06-25 12:54:10 +02:00
blit.lds Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag) 2022-05-15 14:43:15 +02:00
blit.sh LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650 2022-06-24 23:37:18 +02:00
do DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus 2022-06-04 09:53:09 +02:00
fb_dma.py update to first tested version 2022-04-17 11:25:48 +02:00
fb_video.py update to first tested version 2022-04-17 11:25:48 +02:00
goblin_accel.py HW-acceel big pattern (not sure about alignment...), add basic Icon w/ ShowInitIcon 2022-06-25 08:51:17 +02:00
goblin_fb.py Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag) 2022-05-15 14:43:15 +02:00
ldsdsupport.h LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650 2022-06-24 23:37:18 +02:00
nubus-to-ztex-io-signal.xdc push to github 2021-12-21 08:26:30 +01:00
nubus-to-ztex-pin-signal.xdc push to github 2021-12-21 08:26:30 +01:00
nubus.py DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus 2022-06-04 09:53:09 +02:00
nubus.v DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus 2022-06-04 09:53:09 +02:00
nubus_arbiter.v update to first tested version 2022-04-17 11:25:48 +02:00
nubus_cpld.ucf update to first tested version 2022-04-17 11:25:48 +02:00
nubus_cpld.v DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus 2022-06-04 09:53:09 +02:00
nubus_cpu_wb.py Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag) 2022-05-15 14:43:15 +02:00
nubus_fpga_V1_0_timings.xdc fix messed up timing... 2022-07-14 08:54:23 +02:00
nubus_full.py draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel 2022-06-06 23:36:43 +02:00
nubus_full_sampling.py in _sampling, map whole SDRAm in superslot and use the first 248 Mib as a RAM disk with driver in the DeclRom 2022-06-07 23:05:08 +02:00
nubus_master_tst.py stat module 2022-06-04 18:56:41 +02:00
nubus_mem_wb.py buffers (fifo) write from NuBus to Wishbone, to improve write BW 2022-05-30 13:15:20 +02:00
nubus_memfifo_wb.py pingmaster sort-of-work 2022-05-30 19:06:33 +02:00
nubus_sampling.v DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus 2022-06-04 09:53:09 +02:00
nubus_stat.py stat module 2022-06-04 18:56:41 +02:00
nubus_to_fpga_export.py more updates 2022-01-29 11:03:47 +01:00
nubus_to_fpga_soc.py draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel 2022-06-06 23:36:43 +02:00
post_process_timings.sh update to first tested version 2022-04-17 11:25:48 +02:00
rom.a update to first tested version 2022-04-17 11:25:48 +02:00
sdram_init.py Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag) 2022-05-15 14:43:15 +02:00
slave_tb.sv draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel 2022-06-06 23:36:43 +02:00
sn74lvt125.v more updates 2022-01-29 11:03:47 +01:00
ztex213_nubus.py update to first tested version 2022-04-17 11:25:48 +02:00