mirror of
https://github.com/rdolbeau/NuBusFPGA.git
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72 lines
3.0 KiB
Verilog
72 lines
3.0 KiB
Verilog
module nubus_cpld
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(
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input fpga_to_cpld_clk, // unused (extra line from FPGA to CPLD, pin is a clk input)
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inout fpga_to_cpld_signal, // unused (extra line from FPGA to CPLD)
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inout fpga_to_cpld_signal_2, // unused (extra line from FPGA to CPLD)
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input tmoen,
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input [3:0] id_n_5v, // ID of this card
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input [3:0] arb_n_5v, // NuBus arbiter's lines
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output [3:0] arb_o_n, // NuBus arbiter's control lines
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input arb, // enable arbitter
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output grant, // Grant access
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input reset_n_5v, // reset from NuBus, forwarded
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input nubus_oe, // disable all 5v drivers
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output reset_n_3v3, // nubus reset to FPGA
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input nubus_master_dir, // direction of signals, i.e. are we in master mode
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output clk_n_3v3, // nubus clk to FPGA
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output clk2x_n_3v3, // nubus90 clk to FPGA
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output [3:0] id_n_3v3, // nubus ID of this card to FPGA
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inout tm0_n_3v3, // nubus tm0 to/from FPGA
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inout tm1_n_3v3, // nubus tm1 to/from FPGA
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inout tm2_n_3v3, // nubus tm2 to/from FPGA
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inout tm0_n_5v, // tm0 from/to NuBus
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inout tm1_n_5v, // tm1 from/to NuBus
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inout tm2_n_5v, // tm2 from/to NuBus
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input clk_n_5v, // clk from NuBus
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input clk2x_n_5v, // clk from NuBus90
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inout start_n_3v3, // start to/from FPGA
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inout ack_n_3v3, // ack from/to FPGA
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inout start_n_5v, // start from/to NuBus
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inout ack_n_5v, // ack to/from NuBus
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input rqst_n_5v,
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inout rqst_n_3v3,
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output rqst_o_n
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);
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// placeholder to make pretend we use the signals
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assign fpga_to_cpld_signal_2 = fpga_to_cpld_signal ^ fpga_to_cpld_clk;
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// placeholders
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assign clk2x_n_3v3 = clk2x_n_5v;
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assign tm2_n_3v3 = tm2_n_5v;
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// clock and pure in -> out pass_through are always on
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assign clk_n_3v3 = clk_n_5v;
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assign id_n_3v3 = id_n_5v;
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assign reset_n_3v3 = reset_n_5v;
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// nubus_master_dir-controlled signals, Z when nubus_oe is off
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assign start_n_5v = nubus_oe ? 'bZ : ( nubus_master_dir ? start_n_3v3 : 'bZ); // master out
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assign start_n_3v3 = nubus_oe ? 'bZ : (~nubus_master_dir ? start_n_5v : 'bZ); // master in
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// rqst_o is always driven and is active high
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assign rqst_o_n = nubus_oe ? 'b1 : ( nubus_master_dir ? rqst_n_3v3 : 'b1); // master out
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assign rqst_n_3v3 = nubus_oe ? 'bZ : (~nubus_master_dir ? rqst_n_5v : 'bZ); // master in
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assign ack_n_5v = nubus_oe ? 'bZ : ((nubus_master_dir ^ ~tmoen) ? ack_n_3v3 : 'bZ); // slave out/in
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assign tm0_n_5v = nubus_oe ? 'bZ : ((nubus_master_dir ^ ~tmoen) ? tm0_n_3v3 : 'bZ); // slave out/in
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assign tm1_n_5v = nubus_oe ? 'bZ : ((nubus_master_dir ^ ~tmoen) ? tm1_n_3v3 : 'bZ); // slave out/in
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assign ack_n_3v3 = nubus_oe ? 'bZ : ((nubus_master_dir ^ tmoen) ? ack_n_5v : 'bZ); // slave out/in
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assign tm0_n_3v3 = nubus_oe ? 'bZ : ((nubus_master_dir ^ tmoen) ? tm0_n_5v : 'bZ); // slave in/out
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assign tm1_n_3v3 = nubus_oe ? 'bZ : ((nubus_master_dir ^ tmoen) ? tm1_n_5v : 'bZ); // slave in/out
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nubus_arbiter UArbiter
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(
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.idn(id_n_5v),
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.arbn(arb_n_5v),
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.arbon(arb_o_n),
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.arbcyn(arb),
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.grant(grant)
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);
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endmodule // nubus_cpld
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