mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-06-02 03:41:29 +00:00
366 lines
16 KiB
Python
366 lines
16 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import stream
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.code_tmds import TMDSEncoder
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from litex.build.io import SDROutput, DDROutput
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from litex.soc.cores.video import *
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from fb_video import *
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from math import ceil
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cmap_layout = [
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("color", 2),
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("address", 8),
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("data", 8),
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]
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omap_layout = [
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("color", 2),
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("address", 2),
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("data", 8),
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]
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def goblin_rounded_size(hres, vres):
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mib = int(ceil(((hres * vres) + 0) / 1048576))
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if (mib == 3):
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mib = 4
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if (mib > 4 and mib < 8):
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mib = 8
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if (mib > 8 or mib < 1):
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print(f"{mib} mebibytes framebuffer not supported")
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assert(False)
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return int(1048576 * mib)
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class VideoFrameBuffer256c(Module, AutoCSR):
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"""Video FrameBuffer256c"""
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def __init__(self, dram_port, upd_clut_fifo = None, hres=800, vres=600, base=0x00000000, fifo_depth=65536, clock_domain="sys", clock_faster_than_sys=False):
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print(f"FRAMEBUFFER: dram_port.data_width = {dram_port.data_width}, {hres}x{vres}, 0x{base:x}, in {clock_domain}, clock_faster_than_sys={clock_faster_than_sys}")
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npixelsdiv8 = hres * vres // 8
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# mode, as x in 2^x (so 1, 2, 4, 8 bits)
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# should only be changed while in reset
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self.mode = Signal(2, reset = 3)
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self.vblping = Signal(reset = 0)
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self.vtg_sink = vtg_sink = stream.Endpoint(video_timing_layout)
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self.source = source = stream.Endpoint(video_data_layout)
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self.underflow = Signal()
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#source_buf_ready = Signal()
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source_buf_valid = Signal()
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source_buf_de = Signal()
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source_buf_hsync = Signal()
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source_buf_vsync = Signal()
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data_buf = Signal(8)
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#source_out_ready = Signal()
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source_out_valid = Signal()
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source_out_de = Signal()
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source_out_hsync = Signal()
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source_out_vsync = Signal()
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source_out_r = Signal(8)
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source_out_g = Signal(8)
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source_out_b = Signal(8)
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# # #
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# First the Color Look-up Table (for all but 1 bit)
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# updated from the FIFO
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# 8-and-less-than-8-bits mode used the 2^x first entries
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clut = Array(Array(Signal(8, reset = (255-i)) for i in range(0, 256)) for j in range(0, 3))
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upd_clut_fifo_dout = Record(cmap_layout)
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self.comb += upd_clut_fifo_dout.raw_bits().eq(upd_clut_fifo.dout)
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vga_sync = getattr(self.sync, clock_domain)
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vga_sync += [
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If(upd_clut_fifo.readable,
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upd_clut_fifo.re.eq(1),
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clut[upd_clut_fifo_dout.color][upd_clut_fifo_dout.address].eq(upd_clut_fifo_dout.data),
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).Else(
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upd_clut_fifo.re.eq(0),
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)
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]
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# # #
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# Video DMA.
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from fb_dma import LiteDRAMFBDMAReader
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# length should be changed to match mode
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self.submodules.fb_dma = LiteDRAMFBDMAReader(dram_port,
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fifo_depth=fifo_depth//(dram_port.data_width//8),
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default_base = base,
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default_length = npixelsdiv8 * 8)
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# If DRAM Data Width > 8-bit and Video clock is faster than sys_clk:
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# actually always use that case to simplify the design
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# if (dram_port.data_width > 8) and clock_faster_than_sys:
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# Do Clock Domain Crossing first...
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self.submodules.cdc = stream.ClockDomainCrossing([("data", dram_port.data_width)], cd_from="sys", cd_to=clock_domain)
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self.comb += self.fb_dma.source.connect(self.cdc.sink)
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# ... and then Data-Width Conversion.
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# we have 4 possible conversion and mux/connect the appropriate one
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self.submodules.conv8 = ClockDomainsRenamer({"sys": clock_domain})(stream.Converter(dram_port.data_width, 8))
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self.submodules.conv4 = ClockDomainsRenamer({"sys": clock_domain})(stream.Converter(dram_port.data_width, 4))
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self.submodules.conv2 = ClockDomainsRenamer({"sys": clock_domain})(stream.Converter(dram_port.data_width, 2))
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self.submodules.conv1 = ClockDomainsRenamer({"sys": clock_domain})(stream.Converter(dram_port.data_width, 1))
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self.comb += Case(self.mode, {
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0x3: self.cdc.source.connect(self.conv8.sink),
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0x2: self.cdc.source.connect(self.conv4.sink),
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0x1: self.cdc.source.connect(self.conv2.sink),
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0x0: self.cdc.source.connect(self.conv1.sink),
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})
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# Video Generation.
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# buffered by 1 cycle to accomodate the look-ups
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self.comb += [
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vtg_sink.ready.eq(1),
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If(vtg_sink.valid & vtg_sink.de,
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Case(self.mode, {
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0x3: [ source_buf_valid.eq(self.conv8.source.valid),
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self.conv8.source.connect(source, keep={"ready"}),
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data_buf.eq(self.conv8.source.data),
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],
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0x2: [ source_buf_valid.eq(self.conv4.source.valid),
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self.conv4.source.connect(source, keep={"ready"}),
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data_buf.eq(Cat(self.conv4.source.data, Signal(4, reset = 0))),
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],
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0x1: [ source_buf_valid.eq(self.conv2.source.valid),
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self.conv2.source.connect(source, keep={"ready"}),
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data_buf.eq(Cat(self.conv2.source.data, Signal(6, reset = 0))),
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],
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0x0: [ source_buf_valid.eq(self.conv1.source.valid),
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self.conv1.source.connect(source, keep={"ready"}),
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data_buf.eq(Replicate(self.conv2.source.data, 8)),
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],
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}),
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vtg_sink.ready.eq(source_buf_valid & source.ready),
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),
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source_buf_de.eq(vtg_sink.de),
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source_buf_hsync.eq(vtg_sink.hsync),
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source_buf_vsync.eq(vtg_sink.vsync),
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]
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vga_sync += [
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source_out_de.eq(source_buf_de),
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source_out_hsync.eq(source_buf_hsync),
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source_out_vsync.eq(source_buf_vsync),
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source_out_valid.eq(source_buf_valid),
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#source_buf_ready.eq(source_out_ready), # ready flow the other way
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If(source_buf_de,
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If(self.mode == 0x0,
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source_out_r.eq(data_buf),
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source_out_g.eq(data_buf),
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source_out_b.eq(data_buf)
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).Else(
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source_out_r.eq(clut[0][data_buf]),
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source_out_g.eq(clut[1][data_buf]),
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source_out_b.eq(clut[2][data_buf])
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)
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).Else(source_out_r.eq(0),
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source_out_g.eq(0),
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source_out_b.eq(0)
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) ]
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self.comb += [
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source.de.eq(source_out_de),
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source.hsync.eq(source_out_hsync),
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source.vsync.eq(source_out_vsync),
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source.valid.eq(source_out_valid),
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#source_out_ready.eq(source.ready), # ready flow the other way
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source.r.eq(source_out_r),
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source.g.eq(source_out_g),
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source.b.eq(source_out_b),
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]
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# Underflow.
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self.comb += self.underflow.eq(~source.valid)
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# track mode changes
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# in sys cd, not vga cd, as that's where the DMA runs
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# whenever the mode change, we fully reset the DMA
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# (we also need to reset the VTG at the same time)
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old_mode = Signal(2, reset = 3)
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force_reset = Signal(reset = 0)
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finish_reset = Signal(reset = 0)
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old_enable = Signal()
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self.sync += [
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old_mode.eq(self.mode),
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If(old_mode != self.mode,
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force_reset.eq(1),),
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If(force_reset == 1,
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old_enable.eq(self.fb_dma.enable),
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self.fb_dma.enable.eq(0),
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self.fb_dma.length.eq(npixelsdiv8 << self.mode),
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force_reset.eq(0),
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finish_reset.eq(1),),
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If(finish_reset == 1,
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self.fb_dma.enable.eq(old_enable),
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finish_reset.eq(0)),
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]
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# VBL handling
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# create a pulse in self.vlbping in sys at the end of the frame
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from migen.genlib.cdc import PulseSynchronizer
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old_last = Signal()
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vga_vblping = Signal()
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vga_sync += [
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old_last.eq(vtg_sink.last),
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If((vtg_sink.last == 1) & (old_last == 0),
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vga_vblping.eq(1),
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).Else(
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vga_vblping.eq(0)
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)
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]
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self.submodules.vbl_ps = PulseSynchronizer(idomain = clock_domain, odomain = "sys")
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self.comb += self.vbl_ps.i.eq(vga_vblping)
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self.comb += self.vblping.eq(self.vbl_ps.o)
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class goblin(Module, AutoCSR):
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def __init__(self, soc, phy=None, timings = None, clock_domain="sys"):
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# 2 bits for color (0/r, 1/g, 2/b), 8 for @ and 8 for value
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self.submodules.upd_cmap_fifo = upd_cmap_fifo = ClockDomainsRenamer({"read": "vga", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(cmap_layout), depth=8))
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upd_cmap_fifo_din = Record(cmap_layout)
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self.comb += self.upd_cmap_fifo.din.eq(upd_cmap_fifo_din.raw_bits())
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name = "video_framebuffer"
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# near duplicate of plaform.add_video_framebuffer
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# Video Timing Generator.
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vtg = FBVideoTimingGenerator(default_video_timings=timings if isinstance(timings, str) else timings[1])
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vtg = ClockDomainsRenamer(clock_domain)(vtg)
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setattr(self.submodules, f"{name}_vtg", vtg)
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# Video FrameBuffer.
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timings = timings if isinstance(timings, str) else timings[0]
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base = soc.mem_map.get(name)
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print(f"goblin: visible memory at {base:x}")
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hres = int(timings.split("@")[0].split("x")[0])
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vres = int(timings.split("@")[0].split("x")[1])
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freq = vtg.video_timings["pix_clk"]
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print(f"goblin: using {hres} x {vres}, {freq/1e6} MHz pixclk")
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vfb = VideoFrameBuffer256c(dram_port = soc.sdram.crossbar.get_port(),
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upd_clut_fifo = upd_cmap_fifo,
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hres = hres,
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vres = vres,
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base = base,
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clock_domain = clock_domain,
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clock_faster_than_sys = (vtg.video_timings["pix_clk"] > soc.sys_clk_freq))
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setattr(self.submodules, name, vfb)
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# Connect Video Timing Generator to Video FrameBuffer.
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self.comb += vtg.source.connect(vfb.vtg_sink)
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# Connect Video FrameBuffer to Video PHY.
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self.comb += vfb.source.connect(phy if isinstance(phy, stream.Endpoint) else phy.sink)
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# Constants.
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soc.add_constant("VIDEO_FRAMEBUFFER_BASE", base)
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soc.add_constant("VIDEO_FRAMEBUFFER_HRES", hres)
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soc.add_constant("VIDEO_FRAMEBUFFER_VRES", vres)
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# goblin registers
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# struct bt_regs {
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# u_int bt_addr; /* map address register */
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# u_int bt_cmap; /* colormap data register */
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# u_int bt_ctrl; /* control register */
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# u_int bt_omap; /* overlay (cursor) map register */
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# };
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self.bus = bus = wishbone.Interface()
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# current cmap logic for the goblin, similar to the cg6, minus the HW cursor
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bt_mode = Signal(4, reset = 0) # 0 is 3, 2 is 0, 4 is 1, 8 is 2, and bit depth is 2^
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bt_addr = Signal(8, reset = 0)
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bt_cmap_state = Signal(2, reset = 0)
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m_vbl_disable = Signal(reset = 1)
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vbl_signal = Signal(reset = 0)
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vbl_irq = soc.platform.request("nmrq_3v3_n")
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self.comb += vbl_irq.eq(~vbl_signal | m_vbl_disable) # active low
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#self.comb += Case(bt_mode, {
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# 0x0: self.video_framebuffer.mode.eq(3),
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# 0x2: self.video_framebuffer.mode.eq(0),
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# 0x4: self.video_framebuffer.mode.eq(1),
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# 0x8: self.video_framebuffer.mode.eq(2),
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# })
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self.submodules.wishbone_fsm = wishbone_fsm = FSM(reset_state = "Reset")
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wishbone_fsm.act("Reset",
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NextValue(bus.ack, 0),
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NextState("Idle"))
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wishbone_fsm.act("Idle",
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If(bus.cyc & bus.stb & bus.we & ~bus.ack & upd_cmap_fifo.writable, #write
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# FIXME: should check for prefix?
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Case(bus.adr[0:18], {
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# gobofb_mode
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0x0: [ NextValue(bt_mode, bus.dat_w[0:8]), ],
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# gobofb_lut_addr
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0x5: [ NextValue(bt_addr, bus.dat_w[0:8]),
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NextValue(bt_cmap_state, 0),
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],
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# gobofb_lut
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0x6: [ upd_cmap_fifo.we.eq(1),
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upd_cmap_fifo_din.color.eq(bt_cmap_state),
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upd_cmap_fifo_din.address.eq(bt_addr),
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upd_cmap_fifo_din.data.eq(bus.dat_w[0:8]),
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Case(bt_cmap_state, {
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0: [ NextValue(bt_cmap_state, 1), ],
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1: [ NextValue(bt_cmap_state, 2), ],
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2: [ NextValue(bt_cmap_state, 0), NextValue(bt_addr, (bt_addr+1) & 0xFF), ],
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"default": NextValue(bt_cmap_state, 0),
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}),
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],
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# set vbl
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0x1: [ NextValue(m_vbl_disable, ~bus.dat_w[0:1]), ],
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# clear irq
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0x3: [ NextValue(vbl_signal, 0), ],
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"default": [],
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}),
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NextValue(bus.ack, 1),
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).Elif(bus.cyc & bus.stb & ~bus.we & ~bus.ack, #read
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Case(bus.adr[0:18], {
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# bt_addr
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0x0: [ NextValue(bus.dat_r, bt_mode), ],
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"default": [ NextValue(bus.dat_r, 0xDEADBEEF)],
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}),
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NextValue(bus.ack, 1),
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).Else(
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NextValue(bus.ack, 0),
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),
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)
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# mode switch logic
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old_bt_mode = Signal(4)
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vtg_reset_counter = Signal(4, reset = 0) # to put the VTG in reset for a few cyles so that the DMA can restart
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self.sync += [ old_bt_mode.eq(bt_mode),
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If(old_bt_mode != bt_mode,
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Case(bt_mode, {
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0x2: self.video_framebuffer.mode.eq(0),
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0x4: self.video_framebuffer.mode.eq(1),
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0x8: self.video_framebuffer.mode.eq(2),
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0x0: self.video_framebuffer.mode.eq(3),
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}),
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vtg_reset_counter.eq(15),
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vtg._enable.eq(0),),
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If(vtg_reset_counter == 1,
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vtg._enable.eq(1),),
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If(vtg_reset_counter > 0,
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vtg_reset_counter.eq(vtg_reset_counter - 1),),
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]
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# VBL logic
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self.sync += [
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If(self.video_framebuffer.vblping == 1,
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vbl_signal.eq(1),
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),]
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