more

2021-06-21 12:13:28 -04:00 · 2021-06-21 12:13:28 -04:00 · d9db6b7aa8
parent 7041819469
commit d9db6b7aa8
220 changed files with 552668 additions and 23624 deletions
--- a/GW4190-4MB-SOJ/Documentation/BackIsom.png
+++ b/GW4190-4MB-SOJ/Documentation/BackIsom.png
--- a/GW4190-4MB-SOJ/Documentation/FrontIsom.png
+++ b/GW4190-4MB-SOJ/Documentation/FrontIsom.png
--- a/GW4190-4MB-SOJ/Documentation/Placement.pdf
+++ b/GW4190-4MB-SOJ/Documentation/Placement.pdf
--- a/GW4190-4MB-SOJ/Documentation/Schematic.pdf
+++ b/GW4190-4MB-SOJ/Documentation/Schematic.pdf
--- a/GW4190-4MB-SOJ/GW4190-4MB-SOJ-gerber.zip
+++ b/GW4190-4MB-SOJ/GW4190-4MB-SOJ-gerber.zip
--- a/GW4190-4MB-2chip-SOJ/simm-30-4mb-cache.lib
+++ b/GW4190-4MB-2chip-SOJ/simm-30-4mb-cache.lib
--- a/GW4190-4MB-2chip-SOP/simm-30-4mb.kicad_pcb
+++ b/GW4190-4MB-2chip-SOP/simm-30-4mb.kicad_pcb
--- a/GW4190-4MB-2chip-SOP/simm-30-4mb.pro
+++ b/GW4190-4MB-2chip-SOP/simm-30-4mb.pro
@ -1,4 +1,4 @@
-update=Wednesday, June 09, 2021 at 11:45:00 AM
+update=Monday, June 21, 2021 at 04:47:08 AM
 version=1
 last_client=kicad
 [general]
@ -12,20 +12,10 @@ NetIExt=net
 version=1
 LibDir=
 [eeschema/libraries]
-[schematic_editor]
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-SubpartFirstId=65
-NetFmtName=Pcbnew
-SpiceAjustPassiveValues=0
-LabSize=50
-ERC_TestSimilarLabels=1
 [pcbnew]
 version=1
 PageLayoutDescrFile=
-LastNetListRead=simm-30-4mb.net
+LastNetListRead=GW4190-SOJ.net
 CopperLayerCount=4
 BoardThickness=1.6
 AllowMicroVias=0
@ -81,7 +71,7 @@ OthersTextUpright=1
 SolderMaskClearance=0.07619999999999999
 SolderMaskMinWidth=0.127
 SolderPasteClearance=-0.03809999999999999
-SolderPasteRatio=-0
+SolderPasteRatio=0
 [pcbnew/Layer.F.Cu]
 Name=F.Cu
 Type=0
@ -260,3 +250,13 @@ uViaDrill=0.1
 dPairWidth=0.2
 dPairGap=0.25
 dPairViaGap=0.25
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
--- a/GW4190-4MB-2chip-SOP/simm-30-4mb.sch
+++ b/GW4190-4MB-2chip-SOP/simm-30-4mb.sch
@ -4,10 +4,10 @@ EELAYER END
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 Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
+Title "GW4190A"
+Date "2021-06-19"
+Rev "2.0"
+Comp "Garrett's Workshop"
 Comment1 ""
 Comment2 ""
 Comment3 ""
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--- a/GW4190-4MB-2chip-SOJ/fp-lib-table
+++ b/GW4190-4MB-2chip-SOJ/fp-lib-table
--- a/GW4190-4MB-SOJ/gerber/GW4190-SOJ-B_Cu.gbl
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--- a/GW4190-4MB-SOJ/gerber/GW4190-SOJ-B_Mask.gbs
+++ b/GW4190-4MB-SOJ/gerber/GW4190-SOJ-B_Mask.gbs
--- a/GW4190-4MB-SOJ/gerber/GW4190-SOJ-B_SilkS.gbo
+++ b/GW4190-4MB-SOJ/gerber/GW4190-SOJ-B_SilkS.gbo
--- a/GW4190-4MB-SOJ/gerber/GW4190-SOJ-Edge_Cuts.gm1
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--- a/GW4190-4MB-SOJ/gerber/GW4190-SOJ-F_Mask.gts
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--- a/GW4190-4MB-SOJ/gerber/GW4190-SOJ-F_Paste.gtp
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+++ b/GW4190-4MB-SOJ/gerber/GW4190-SOJ-F_SilkS.gto
--- a/GW4190-4MB-SOJ/gerber/GW4190-SOJ-In1_Cu.g2
+++ b/GW4190-4MB-SOJ/gerber/GW4190-SOJ-In1_Cu.g2
--- a/GW4190-4MB-SOJ/gerber/GW4190-SOJ-In2_Cu.g3
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--- a/GW4190-4MB-SOJ/gerber/GW4190-SOJ-top.pos
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--- a/GW4190-4MB-SOJ/gerber/GW4190-SOJ.drl
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--- a/GW4190-4MB-2chip-SOJ/sym-lib-table
+++ b/GW4190-4MB-2chip-SOJ/sym-lib-table
--- a/GW4190-4MB-SOP/Documentation/BackIsom.png
+++ b/GW4190-4MB-SOP/Documentation/BackIsom.png
--- a/GW4190-4MB-SOP/Documentation/FrontIsom.png
+++ b/GW4190-4MB-SOP/Documentation/FrontIsom.png
--- a/GW4190-4MB-SOP/Documentation/Placement.pdf
+++ b/GW4190-4MB-SOP/Documentation/Placement.pdf
--- a/GW4190-4MB-SOP/Documentation/Schematic.pdf
+++ b/GW4190-4MB-SOP/Documentation/Schematic.pdf
--- a/GW4190-4MB-SOP/GW4190-4MB-SOP-gerber.zip
+++ b/GW4190-4MB-SOP/GW4190-4MB-SOP-gerber.zip
--- a/GW4190-4MB-2chip-SOP/simm-30-4mb-cache.lib
+++ b/GW4190-4MB-2chip-SOP/simm-30-4mb-cache.lib
--- a/GW4190-4MB-2chip-SOJ/simm-30-4mb.kicad_pcb
+++ b/GW4190-4MB-2chip-SOJ/simm-30-4mb.kicad_pcb
--- a/GW4190-4MB-2chip-SOJ/simm-30-4mb.pro
+++ b/GW4190-4MB-2chip-SOJ/simm-30-4mb.pro
@ -1,4 +1,4 @@
-update=Wednesday, June 09, 2021 at 11:45:00 AM
+update=Monday, June 21, 2021 at 04:48:16 AM
 version=1
 last_client=kicad
 [general]
@ -12,20 +12,10 @@ NetIExt=net
 version=1
 LibDir=
 [eeschema/libraries]
-[schematic_editor]
-version=1
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-PlotDirectoryName=
-SubpartIdSeparator=0
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-NetFmtName=Pcbnew
-SpiceAjustPassiveValues=0
-LabSize=50
-ERC_TestSimilarLabels=1
 [pcbnew]
 version=1
 PageLayoutDescrFile=
-LastNetListRead=simm-30-4mb.net
+LastNetListRead=GW4190-SOP.net
 CopperLayerCount=4
 BoardThickness=1.6
 AllowMicroVias=0
@ -81,7 +71,7 @@ OthersTextUpright=1
 SolderMaskClearance=0.07619999999999999
 SolderMaskMinWidth=0.127
 SolderPasteClearance=-0.03809999999999999
-SolderPasteRatio=-0
+SolderPasteRatio=0
 [pcbnew/Layer.F.Cu]
 Name=F.Cu
 Type=0
@ -260,3 +250,13 @@ uViaDrill=0.1
 dPairWidth=0.2
 dPairGap=0.25
 dPairViaGap=0.25
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
--- a/GW4190-4MB-2chip-SOJ/simm-30-4mb.sch
+++ b/GW4190-4MB-2chip-SOJ/simm-30-4mb.sch
@ -4,10 +4,10 @@ EELAYER END
 $Descr USLetter 11000 8500
 encoding utf-8
 Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
+Title "GW4190A"
+Date "2021-06-19"
+Rev "2.0"
+Comp "Garrett's Workshop"
 Comment1 ""
 Comment2 ""
 Comment3 ""
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--- a/GW4190-4MB-2chip-SOP/fp-lib-table
+++ b/GW4190-4MB-2chip-SOP/fp-lib-table
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-B_Cu.gbl
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-B_Cu.gbl
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-B_Mask.gbs
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-B_Mask.gbs
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-B_SilkS.gbo
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-B_SilkS.gbo
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-Edge_Cuts.gm1
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-Edge_Cuts.gm1
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--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-F_Cu.gtl
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-F_Cu.gtl
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-F_Mask.gts
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-F_Mask.gts
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-F_Paste.gtp
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-F_Paste.gtp
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-F_SilkS.gto
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-F_SilkS.gto
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-In1_Cu.g2
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-In1_Cu.g2
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-In2_Cu.g3
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-In2_Cu.g3
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-bottom-pos.csv
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-bottom-pos.csv
@ -0,0 +1 @@
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--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-bottom.pos
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-bottom.pos
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+### Module positions - created on Monday, June 21, 2021 at 04:48:25 AM ###
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+## End
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-drl_map.ps
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-drl_map.ps
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-top-pos.csv
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--- a/GW4190-4MB-SOP/gerber/GW4190-SOP-top.pos
+++ b/GW4190-4MB-SOP/gerber/GW4190-SOP-top.pos
@ -0,0 +1,15 @@
+### Module positions - created on Monday, June 21, 2021 at 04:48:25 AM ###
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+## Side : top
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+U2        4C4M4     SOP-24-26_300mil    95.2500   -89.6620   90.0000  top
+## End
--- a/GW4190-4MB-SOP/gerber/GW4190-SOP.drl
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--- a/GW4190-4MB-2chip-SOP/sym-lib-table
+++ b/GW4190-4MB-2chip-SOP/sym-lib-table
--- a/GW4191-4MB-parity-SOJ/Documentation/BackIsom.png
+++ b/GW4191-4MB-parity-SOJ/Documentation/BackIsom.png
--- a/GW4191-4MB-parity-SOJ/Documentation/FrontIsom.png
+++ b/GW4191-4MB-parity-SOJ/Documentation/FrontIsom.png
--- a/GW4191-4MB-parity-SOJ/Documentation/Placement.pdf
+++ b/GW4191-4MB-parity-SOJ/Documentation/Placement.pdf
--- a/GW4191-4MB-parity-SOJ/Documentation/Schematic.pdf
+++ b/GW4191-4MB-parity-SOJ/Documentation/Schematic.pdf
--- a/GW4191-4MB-parity-SOJ/GW4191-4MB-parity-SOJ-gerber.zip
+++ b/GW4191-4MB-parity-SOJ/GW4191-4MB-parity-SOJ-gerber.zip
--- a/GW4191-4MB-parity-2chip-SOJ/simm-30-4mb-cache.lib
+++ b/GW4191-4MB-parity-2chip-SOJ/simm-30-4mb-cache.lib
--- a/GW4191-4MB-parity-2chip-SOJ/simm-30-4mb.kicad_pcb
+++ b/GW4191-4MB-parity-2chip-SOJ/simm-30-4mb.kicad_pcb
--- a/GW4191-4MB-parity-2chip-SOJ/simm-30-4mb.pro
+++ b/GW4191-4MB-parity-2chip-SOJ/simm-30-4mb.pro
@ -1,4 +1,4 @@
-update=Wednesday, June 09, 2021 at 11:45:00 AM
+update=Monday, June 21, 2021 at 04:50:01 AM
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@ -260,3 +250,13 @@ uViaDrill=0.1
 dPairWidth=0.2
 dPairGap=0.25
 dPairViaGap=0.25
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--- a/GW4191-4MB-parity-2chip-SOJ/simm-30-4mb.sch
+++ b/GW4191-4MB-parity-2chip-SOJ/simm-30-4mb.sch
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-Title ""
-Date ""
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-Comp ""
+Title "GW4191A"
+Date "2021-06-19"
+Rev "1.0"
+Comp "Garrett's Workshop"
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--- a/GW4191-4MB-parity-2chip-SOJ/fp-lib-table
+++ b/GW4191-4MB-parity-2chip-SOJ/fp-lib-table
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-B_Mask.gbs
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-B_SilkS.gbo
+++ b/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-B_SilkS.gbo
--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-Edge_Cuts.gm1
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-F_Cu.gtl
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-F_Mask.gts
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-F_Paste.gtp
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-F_SilkS.gto
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-In1_Cu.g2
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-In2_Cu.g3
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-bottom-pos.csv
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-bottom.pos
+++ b/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-bottom.pos
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-drl_map.ps
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-top-pos.csv
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--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-top.pos
+++ b/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ-top.pos
@ -0,0 +1,16 @@
+### Module positions - created on Monday, June 21, 2021 at 04:50:11 AM ###
+### Printed by Pcbnew version kicad (5.1.10-1-10_14)
+## Unit = mm, Angle = deg.
+## Side : top
+# Ref     Val       Package                PosX       PosY       Rot  Side
+C1        2u2       C_0805              85.0900   -93.2570  270.0000  top
+C2        2u2       C_0805             105.4100   -93.2570  270.0000  top
+C3        2u2       C_0805             111.1250   -93.2570  270.0000  top
+C4        2u2       C_0805             131.4450   -93.2570  270.0000  top
+C5        2u2       C_0805             157.4800   -93.2570   90.0000  top
+R1        EDO       R_0805              82.7000   -86.5000  180.0000  top
+R2        FPM       R_0805              82.7000   -84.5000    0.0000  top
+U1        4C4M4     SOJ-24-26_300mil   121.2850   -89.6620   90.0000  top
+U2        4C4M4     SOJ-24-26_300mil    95.2500   -89.6620   90.0000  top
+U3        4C4M1     SOJ-20-26_300mil   147.3200   -89.6620   90.0000  top
+## End
--- a/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ.drl
+++ b/GW4191-4MB-parity-SOJ/gerber/GW4191-SOJ.drl
@ -0,0 +1,197 @@
+M48
+; DRILL file {KiCad (5.1.10-1-10_14)} date Monday, June 21, 2021 at 04:50:07 AM
+; FORMAT={-:-/ absolute / inch / decimal}
+; #@! TF.CreationDate,2021-06-21T04:50:07-04:00
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+T0
+M30
--- a/GW4191-4MB-parity-2chip-SOJ/sym-lib-table
+++ b/GW4191-4MB-parity-2chip-SOJ/sym-lib-table
--- a/GW4191-4MB-parity-SOP/Documentation/FrontIsom.png
+++ b/GW4191-4MB-parity-SOP/Documentation/FrontIsom.png
--- a/GW4191-4MB-parity-SOP/Documentation/Placement.pdf
+++ b/GW4191-4MB-parity-SOP/Documentation/Placement.pdf
--- a/GW4191-4MB-parity-SOP/Documentation/RearIsom.png
+++ b/GW4191-4MB-parity-SOP/Documentation/RearIsom.png
--- a/GW4191-4MB-parity-SOP/Documentation/Schematic.pdf
+++ b/GW4191-4MB-parity-SOP/Documentation/Schematic.pdf
--- a/GW4191-4MB-parity-SOP/GW4191-4MB-parity-SOP-gerber.zip
+++ b/GW4191-4MB-parity-SOP/GW4191-4MB-parity-SOP-gerber.zip
--- a/GW4191-4MB-parity-SOP/GW4191-SOP-cache.lib
+++ b/GW4191-4MB-parity-SOP/GW4191-SOP-cache.lib
@ -0,0 +1,217 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Connector_Generic_Conn_01x30
+#
+DEF Connector_Generic_Conn_01x30 J 0 40 Y N 1 F N
+F0 "J" 0 1500 50 H V C CNN
+F1 "Connector_Generic_Conn_01x30" 0 -1600 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_1x??_*
+$ENDFPLIST
+DRAW
+S -50 -1495 0 -1505 1 1 6 N
+S -50 -1395 0 -1405 1 1 6 N
+S -50 -1295 0 -1305 1 1 6 N
+S -50 -1195 0 -1205 1 1 6 N
+S -50 -1095 0 -1105 1 1 6 N
+S -50 -995 0 -1005 1 1 6 N
+S -50 -895 0 -905 1 1 6 N
+S -50 -795 0 -805 1 1 6 N
+S -50 -695 0 -705 1 1 6 N
+S -50 -595 0 -605 1 1 6 N
+S -50 -495 0 -505 1 1 6 N
+S -50 -395 0 -405 1 1 6 N
+S -50 -295 0 -305 1 1 6 N
+S -50 -195 0 -205 1 1 6 N
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 105 0 95 1 1 6 N
+S -50 205 0 195 1 1 6 N
+S -50 305 0 295 1 1 6 N
+S -50 405 0 395 1 1 6 N
+S -50 505 0 495 1 1 6 N
+S -50 605 0 595 1 1 6 N
+S -50 705 0 695 1 1 6 N
+S -50 805 0 795 1 1 6 N
+S -50 905 0 895 1 1 6 N
+S -50 1005 0 995 1 1 6 N
+S -50 1105 0 1095 1 1 6 N
+S -50 1205 0 1195 1 1 6 N
+S -50 1305 0 1295 1 1 6 N
+S -50 1405 0 1395 1 1 6 N
+S -50 1450 50 -1550 1 1 10 f
+X Pin_1 1 -200 1400 150 R 50 50 1 1 P
+X Pin_10 10 -200 500 150 R 50 50 1 1 P
+X Pin_11 11 -200 400 150 R 50 50 1 1 P
+X Pin_12 12 -200 300 150 R 50 50 1 1 P
+X Pin_13 13 -200 200 150 R 50 50 1 1 P
+X Pin_14 14 -200 100 150 R 50 50 1 1 P
+X Pin_15 15 -200 0 150 R 50 50 1 1 P
+X Pin_16 16 -200 -100 150 R 50 50 1 1 P
+X Pin_17 17 -200 -200 150 R 50 50 1 1 P
+X Pin_18 18 -200 -300 150 R 50 50 1 1 P
+X Pin_19 19 -200 -400 150 R 50 50 1 1 P
+X Pin_2 2 -200 1300 150 R 50 50 1 1 P
+X Pin_20 20 -200 -500 150 R 50 50 1 1 P
+X Pin_21 21 -200 -600 150 R 50 50 1 1 P
+X Pin_22 22 -200 -700 150 R 50 50 1 1 P
+X Pin_23 23 -200 -800 150 R 50 50 1 1 P
+X Pin_24 24 -200 -900 150 R 50 50 1 1 P
+X Pin_25 25 -200 -1000 150 R 50 50 1 1 P
+X Pin_26 26 -200 -1100 150 R 50 50 1 1 P
+X Pin_27 27 -200 -1200 150 R 50 50 1 1 P
+X Pin_28 28 -200 -1300 150 R 50 50 1 1 P
+X Pin_29 29 -200 -1400 150 R 50 50 1 1 P
+X Pin_3 3 -200 1200 150 R 50 50 1 1 P
+X Pin_30 30 -200 -1500 150 R 50 50 1 1 P
+X Pin_4 4 -200 1100 150 R 50 50 1 1 P
+X Pin_5 5 -200 1000 150 R 50 50 1 1 P
+X Pin_6 6 -200 900 150 R 50 50 1 1 P
+X Pin_7 7 -200 800 150 R 50 50 1 1 P
+X Pin_8 8 -200 700 150 R 50 50 1 1 P
+X Pin_9 9 -200 600 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_C_Small
+#
+DEF Device_C_Small C 0 10 N N 1 F N
+F0 "C" 10 70 50 H V L CNN
+F1 "Device_C_Small" 10 -80 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 13 -60 -20 60 -20 N
+P 2 0 1 12 -60 20 60 20 N
+X ~ 1 0 100 80 D 50 50 1 1 P
+X ~ 2 0 -100 80 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_R_Small
+#
+DEF Device_R_Small R 0 10 N N 1 F N
+F0 "R" 30 20 50 H V L CNN
+F1 "Device_R_Small" 30 -40 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+S -30 70 30 -70 0 1 8 N
+X ~ 1 0 100 30 D 50 50 1 1 P
+X ~ 2 0 -100 30 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GW_RAM_DRAM-4Mx1-SOP-20
+#
+DEF GW_RAM_DRAM-4Mx1-SOP-20 U 0 20 Y Y 1 F N
+F0 "U" 0 650 50 H V C CNN
+F1 "GW_RAM_DRAM-4Mx1-SOP-20" 0 0 50 V V C CNN
+F2 "stdpads:SOP-24-26-300mil" 0 -650 50 H I C CNN
+F3 "" 0 -600 50 H I C CNN
+$FPLIST
+ SOJ*10.16x23.49mm*P1.27mm*
+$ENDFPLIST
+DRAW
+S -300 600 300 -600 0 1 10 f
+X D 1 400 400 100 L 50 50 1 1 I
+X A1 10 -400 400 100 R 50 50 1 1 I
+X A2 11 -400 300 100 R 50 50 1 1 I
+X A3 12 -400 200 100 R 50 50 1 1 I
+X VDD 13 400 500 100 L 50 50 1 1 W
+X A4 14 -400 100 100 R 50 50 1 1 I
+X A5 15 -400 0 100 R 50 50 1 1 I
+X A6 16 -400 -100 100 R 50 50 1 1 I
+X A7 17 -400 -200 100 R 50 50 1 1 I
+X A8 18 -400 -300 100 R 50 50 1 1 I
+X ~WE~ 2 400 -300 100 L 50 50 1 1 I
+X A9 22 -400 -400 100 R 50 50 1 1 I
+X NC 23 400 0 100 L 50 50 1 1 N N
+X ~CAS~ 24 400 -100 100 L 50 50 1 1 I
+X Q 25 400 300 100 L 50 50 1 1 T
+X GND 26 400 -500 100 L 50 50 1 1 W
+X ~RAS~ 3 400 -200 100 L 50 50 1 1 I
+X NC 4 400 50 100 L 50 50 1 1 N N
+X A10 5 -400 -500 100 R 50 50 1 1 I
+X A0 9 -400 500 100 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# GW_RAM_DRAM-4Mx4-SOP-24
+#
+DEF GW_RAM_DRAM-4Mx4-SOP-24 U 0 20 Y Y 1 F N
+F0 "U" 0 650 50 H V C CNN
+F1 "GW_RAM_DRAM-4Mx4-SOP-24" 0 0 50 V V C CNN
+F2 "stdpads:SOP-24-26-300mil" 0 -650 50 H I C CNN
+F3 "" 0 -600 50 H I C CNN
+$FPLIST
+ SOJ*10.16x23.49mm*P1.27mm*
+$ENDFPLIST
+DRAW
+S -300 600 300 -600 0 1 10 f
+X VDD 1 400 500 100 L 50 50 1 1 W
+X A1 10 -400 400 100 R 50 50 1 1 I
+X A2 11 -400 300 100 R 50 50 1 1 I
+X A3 12 -400 200 100 R 50 50 1 1 I
+X VDD 13 400 500 100 L 50 50 1 1 W N
+X GND 14 400 -500 100 L 50 50 1 1 W N
+X A4 15 -400 100 100 R 50 50 1 1 I
+X A5 16 -400 0 100 R 50 50 1 1 I
+X A6 17 -400 -100 100 R 50 50 1 1 I
+X A7 18 -400 -200 100 R 50 50 1 1 I
+X A8 19 -400 -300 100 R 50 50 1 1 I
+X D0 2 400 400 100 L 50 50 1 1 B
+X NC 20 400 0 100 L 50 50 1 1 N N
+X A9 21 -400 -400 100 R 50 50 1 1 I
+X ~OE~ 22 400 -400 100 L 50 50 1 1 I
+X ~CAS~ 23 400 -100 100 L 50 50 1 1 I
+X D2 24 400 200 100 L 50 50 1 1 B
+X D3 25 400 100 100 L 50 50 1 1 B
+X GND 26 400 -500 100 L 50 50 1 1 W
+X D1 3 400 300 100 L 50 50 1 1 B
+X ~WE~ 4 400 -300 100 L 50 50 1 1 I
+X ~RAS~ 5 400 -200 100 L 50 50 1 1 I
+X NC 7 400 0 100 L 50 50 1 1 N N
+X A10 8 -400 -500 100 R 50 50 1 1 I
+X A0 9 -400 500 100 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# power_+5V
+#
+DEF power_+5V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_+5V" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +5V 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# power_GND
+#
+DEF power_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "power_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library
--- a/GW4191-4MB-parity-SOP/GW4191-SOP.kicad_pcb
+++ b/GW4191-4MB-parity-SOP/GW4191-SOP.kicad_pcb
--- a/GW4194-4MB-2chip-WEGATE-SOJ/simm-30-4mb.pro
+++ b/GW4194-4MB-2chip-WEGATE-SOJ/simm-30-4mb.pro
@ -1,4 +1,4 @@
-update=Wednesday, June 09, 2021 at 11:45:00 AM
+update=Monday, June 21, 2021 at 04:51:14 AM
 version=1
 last_client=kicad
 [general]
@ -12,20 +12,10 @@ NetIExt=net
 version=1
 LibDir=
 [eeschema/libraries]
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=Pcbnew
-SpiceAjustPassiveValues=0
-LabSize=50
-ERC_TestSimilarLabels=1
 [pcbnew]
 version=1
 PageLayoutDescrFile=
-LastNetListRead=simm-30-4mb.net
+LastNetListRead=GW4191-SOP.net
 CopperLayerCount=4
 BoardThickness=1.6
 AllowMicroVias=0
@ -81,7 +71,7 @@ OthersTextUpright=1
 SolderMaskClearance=0.07619999999999999
 SolderMaskMinWidth=0.127
 SolderPasteClearance=-0.03809999999999999
-SolderPasteRatio=-0
+SolderPasteRatio=0
 [pcbnew/Layer.F.Cu]
 Name=F.Cu
 Type=0
@ -260,3 +250,13 @@ uViaDrill=0.1
 dPairWidth=0.2
 dPairGap=0.25
 dPairViaGap=0.25
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
--- a/GW4191-4MB-parity-SOP/GW4191-SOP.sch
+++ b/GW4191-4MB-parity-SOP/GW4191-SOP.sch
@ -0,0 +1,703 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr USLetter 11000 8500
+encoding utf-8
+Sheet 1 1
+Title "GW4191A"
+Date "2021-06-19"
+Rev "1.0"
+Comp "Garrett's Workshop"
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Connector_Generic:Conn_01x30 J1
+U 1 1 5C2E1E12
+P 4450 3450
+F 0 "J1" V 4574 3396 50  0000 C CNN
+F 1 "DRAM-SIMM-30" V 4665 3396 50  0000 C CNN
+F 2 "stdpads:SIMM-30_Edge" H 4450 3450 50  0001 C CNN
+F 3 "~" H 4450 3450 50  0001 C CNN
+	1    4450 3450
+	0    -1   1    0   
+$EndComp
+$Comp
+L power:+5V #PWR0101
+U 1 1 5C2E1ED2
+P 5950 3250
+F 0 "#PWR0101" H 5950 3100 50  0001 C CNN
+F 1 "+5V" H 5950 3400 50  0000 C CNN
+F 2 "" H 5950 3250 50  0001 C CNN
+F 3 "" H 5950 3250 50  0001 C CNN
+	1    5950 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:+5V #PWR0102
+U 1 1 5C2E1F89
+P 3050 3250
+F 0 "#PWR0102" H 3050 3100 50  0001 C CNN
+F 1 "+5V" H 3050 3400 50  0000 C CNN
+F 2 "" H 3050 3250 50  0001 C CNN
+F 3 "" H 3050 3250 50  0001 C CNN
+	1    3050 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND #PWR0103
+U 1 1 5C2E2010
+P 5150 3250
+F 0 "#PWR0103" H 5150 3000 50  0001 C CNN
+F 1 "GND" H 5150 3100 50  0000 C CNN
+F 2 "" H 5150 3250 50  0001 C CNN
+F 3 "" H 5150 3250 50  0001 C CNN
+	1    5150 3250
+	-1   0    0    1   
+$EndComp
+$Comp
+L power:GND #PWR0104
+U 1 1 5C2E2033
+P 3850 3250
+F 0 "#PWR0104" H 3850 3000 50  0001 C CNN
+F 1 "GND" H 3850 3100 50  0000 C CNN
+F 2 "" H 3850 3250 50  0001 C CNN
+F 3 "" H 3850 3250 50  0001 C CNN
+	1    3850 3250
+	-1   0    0    1   
+$EndComp
+Text Label 3150 3250 1    50   ~ 0
+~CAS~
+Text Label 3250 3250 1    50   ~ 0
+D0
+Text Label 3350 3250 1    50   ~ 0
+A0
+Text Label 3450 3250 1    50   ~ 0
+A1
+Text Label 3550 3250 1    50   ~ 0
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+Text Label 3750 3250 1    50   ~ 0
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+Text Label 3950 3250 1    50   ~ 0
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+Text Label 4050 3250 1    50   ~ 0
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+++ b/GW4191-4MB-parity-SOP/gerber/GW4191-SOP-F_Paste.gtp
--- a/GW4191-4MB-parity-SOP/gerber/GW4191-SOP-F_SilkS.gto
+++ b/GW4191-4MB-parity-SOP/gerber/GW4191-SOP-F_SilkS.gto
--- a/GW4191-4MB-parity-SOP/gerber/GW4191-SOP-In1_Cu.g2
+++ b/GW4191-4MB-parity-SOP/gerber/GW4191-SOP-In1_Cu.g2
--- a/Show More
+++ b/Show More