mirror of
https://github.com/fhgwright/SCSI2SD.git
synced 2025-04-10 01:37:07 +00:00
Add SPI flash initialisation
This commit is contained in:
parent
d1e5c214e9
commit
0c3d1bcdd3
@ -195,6 +195,33 @@ scsiTestCommand()
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hidPacket_send(response, sizeof(response));
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}
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static void
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deviceListCommand()
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{
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int deviceCount;
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S2S_Device** devices = s2s_GetDevices(&deviceCount);
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uint8_t response[16] = // Make larger if there can be more than 2 devices
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{
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deviceCount
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};
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int pos = 1;
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for (int i = 0; i < deviceCount; ++i)
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{
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response[pos++] = devices[i]->deviceType;
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uint32_t capacity = devices[i]->getCapacity(devices[i]);
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response[pos++] = capacity >> 24;
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response[pos++] = capacity >> 16;
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response[pos++] = capacity >> 8;
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response[pos++] = capacity;
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}
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hidPacket_send(response, pos);
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}
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static void
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processCommand(const uint8_t* cmd, size_t cmdSize)
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{
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@ -224,6 +251,10 @@ processCommand(const uint8_t* cmd, size_t cmdSize)
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scsiTestCommand();
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break;
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case S2S_CMD_DEV_LIST:
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deviceListCommand();
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break;
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case CONFIG_NONE: // invalid
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default:
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break;
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160
software/SCSI2SD/src/flash.c
Normal file
160
software/SCSI2SD/src/flash.c
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@ -0,0 +1,160 @@
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// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
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//
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// This file is part of SCSI2SD.
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//
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// SCSI2SD is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// SCSI2SD is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
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#include "device.h"
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#include "flash.h"
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#include "config.h"
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#include "led.h"
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#include "time.h"
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typedef struct
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{
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S2S_Device dev;
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S2S_Target targets[MAX_SCSI_TARGETS];
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uint32_t capacity; // in 512 byte blocks
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// CFI info
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uint8_t manufacturerID;
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uint8_t deviceID[2];
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} SpiFlash;
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static void spiFlash_earlyInit(S2S_Device* dev);
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static void spiFlash_init(S2S_Device* dev);
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static S2S_Target* spiFlash_getTargets(S2S_Device* dev, int* count);
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static uint32_t spiFlash_getCapacity(S2S_Device* dev);
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static int spiFlash_pollMediaChange(S2S_Device* dev);
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static void spiFlash_pollMediaBusy(S2S_Device* dev);
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SpiFlash spiFlash = {
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{
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spiFlash_earlyInit,
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spiFlash_init,
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spiFlash_getTargets,
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spiFlash_getCapacity,
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spiFlash_pollMediaChange,
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spiFlash_pollMediaBusy,
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0, // initial mediaState
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CONFIG_STOREDEVICE_FLASH
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}
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};
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S2S_Device* spiFlashDevice = &(spiFlash.dev);
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// Read and write 1 byte.
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static uint8_t spiFlashByte(uint8_t value)
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{
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NOR_SPI_WriteTxData(value);
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while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {}
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return NOR_SPI_ReadRxData();
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}
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static void spiFlash_earlyInit(S2S_Device* dev)
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{
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SpiFlash* spiFlash = (SpiFlash*)dev;
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for (int i = 0; i < MAX_SCSI_TARGETS; ++i)
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{
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spiFlash->targets[i].device = dev;
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const S2S_TargetCfg* cfg = getConfigByIndex(i);
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if (cfg->storageDevice == CONFIG_STOREDEVICE_FLASH)
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{
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spiFlash->targets[i].cfg = (S2S_TargetCfg*)cfg;
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}
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else
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{
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spiFlash->targets[i].cfg = NULL;
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}
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}
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// Don't require the host to send us a START STOP UNIT command
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spiFlash->dev.mediaState = MEDIA_STARTED;
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}
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static void spiFlash_init(S2S_Device* dev)
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{
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SpiFlash* spiFlash = (SpiFlash*)dev;
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spiFlash->capacity = 0;
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nNOR_WP_Write(0); // Enable Write Protect
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nNOR_CS_Write(1); // Deselect
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NOR_SPI_Start();
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CyDelayUs(1);
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nNOR_CS_Write(0); // Select
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// JEDEC standard "Read Identification" command
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// returns CFI information
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spiFlashByte(0x9F);
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// 1 byte manufacturer ID
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spiFlash->manufacturerID = spiFlashByte(0xFF);
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// 2 bytes device ID
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spiFlash->deviceID[0] = spiFlashByte(0xFF);
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spiFlash->deviceID[1] = spiFlashByte(0xFF);
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uint8_t bytesFollowing = spiFlashByte(0xFF);
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// Chances are this says 0, which means up to 512 bytes.
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// But ignore it for now and just get the capacity.
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for (int i = 0; i < 0x23; ++i)
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{
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spiFlashByte(0xFF);
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}
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// Capacity is 2^n at offset 0x27
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//spiFlash->capacity = (1 << spiFlashByte(0xFF)) / 512;
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// Record value in 512-byte sectors.
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spiFlash->capacity = 1 << (spiFlashByte(0xFF) - 9);
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// Don't bother reading the rest. Deselecting will cancel the command.
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nNOR_CS_Write(1); // Deselect
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}
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static S2S_Target* spiFlash_getTargets(S2S_Device* dev, int* count)
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{
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SpiFlash* spiFlash = (SpiFlash*)dev;
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*count = MAX_SCSI_TARGETS;
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return spiFlash->targets;
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}
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static uint32_t spiFlash_getCapacity(S2S_Device* dev)
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{
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SpiFlash* spiFlash = (SpiFlash*)dev;
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return spiFlash->capacity;
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}
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static int spiFlash_pollMediaChange(S2S_Device* dev)
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{
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// Non-removable
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return 0;
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}
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static void spiFlash_pollMediaBusy(S2S_Device* dev)
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{
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// Non-removable
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}
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25
software/SCSI2SD/src/flash.h
Normal file
25
software/SCSI2SD/src/flash.h
Normal file
@ -0,0 +1,25 @@
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// Copyright (C) 2020 Michael McMaster <michael@codesrc.com>
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//
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// This file is part of SCSI2SD.
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//
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// SCSI2SD is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// SCSI2SD is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
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#ifndef S2S_FLASH_H
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#define S2S_FLASH_H
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#include "storedevice.h"
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extern S2S_Device* spiFlashDevice;
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#endif
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@ -61,7 +61,7 @@ int main()
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++delaySeconds;
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}
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sdCheckPresent();
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s2s_deviceInit();
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while (1)
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{
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@ -665,11 +665,14 @@ static void process_SelectionPhase()
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S2S_Target* target = NULL;
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for (int testIdx = 0; testIdx < 8; ++testIdx)
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{
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target = s2s_DeviceFindByScsiId(testIdx);
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if (target)
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{
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break;
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}
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if (mask & (1 << testIdx))
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{
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target = s2s_DeviceFindByScsiId(testIdx);
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if (target)
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{
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break;
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}
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}
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}
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sel &= (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL);
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@ -1052,11 +1055,11 @@ void scsiInit()
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scsiDev.compatMode = COMPAT_UNKNOWN;
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int deviceCount;
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S2S_Device* allDevices = s2s_GetDevices(&deviceCount);
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S2S_Device** allDevices = s2s_GetDevices(&deviceCount);
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for (int devIdx = 0; devIdx < deviceCount; ++devIdx)
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{
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int targetCount;
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S2S_Target* targets = allDevices[devIdx].getTargets(allDevices + devIdx, &targetCount);
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S2S_Target* targets = allDevices[devIdx]->getTargets(allDevices[devIdx], &targetCount);
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for (int i = 0; i < targetCount; ++i)
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{
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@ -1068,7 +1071,10 @@ void scsiInit()
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state->sense.code = NO_SENSE;
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state->sense.asc = NO_ADDITIONAL_SENSE_INFORMATION;
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state->bytesPerSector = targets[i].cfg->bytesPerSector;
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if (targets[i].cfg)
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{
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state->bytesPerSector = targets[i].cfg->bytesPerSector;
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}
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}
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}
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}
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@ -29,6 +29,7 @@
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#include <string.h>
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static void sd_earlyInit(S2S_Device* dev);
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static void sd_deviceInit(S2S_Device* dev);
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static S2S_Target* sd_getTargets(S2S_Device* dev, int* count);
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static uint32_t sd_getCapacity(S2S_Device* dev);
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static int sd_pollMediaChange(S2S_Device* dev);
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@ -38,10 +39,13 @@ static void sd_pollMediaBusy(S2S_Device* dev);
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SdCard sdCard = {
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{
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sd_earlyInit,
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sd_deviceInit,
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sd_getTargets,
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sd_getCapacity,
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sd_pollMediaChange,
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sd_pollMediaBusy
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sd_pollMediaBusy,
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0, // initial mediaState
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CONFIG_STOREDEVICE_SD
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}
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};
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S2S_Device* sdDevice = &(sdCard.dev);
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@ -1038,13 +1042,26 @@ static void sd_earlyInit(S2S_Device* dev)
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for (int i = 0; i < MAX_SCSI_TARGETS; ++i)
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{
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sdCardDevice->targets[i].device = dev;
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sdCardDevice->targets[i].cfg = getConfigByIndex(i);
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const S2S_TargetCfg* cfg = getConfigByIndex(i);
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if (cfg->storageDevice == CONFIG_STOREDEVICE_SD)
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{
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sdCardDevice->targets[i].cfg = (S2S_TargetCfg*)cfg;
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}
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else
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{
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sdCardDevice->targets[i].cfg = NULL;
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}
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}
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sdCardDevice->lastPollMediaTime = getTime_ms();
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// Don't require the host to send us a START STOP UNIT command
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sdCardDevice->dev.mediaState = MEDIA_STARTED;
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}
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static void sd_deviceInit(S2S_Device* dev)
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{
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sdCheckPresent();
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}
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static S2S_Target* sd_getTargets(S2S_Device* dev, int* count)
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@ -16,6 +16,12 @@
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// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
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#include "storedevice.h"
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#include "device.h"
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#ifdef NOR_SPI_DATA_WIDTH
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#include "flash.h"
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#endif
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#include "sd.h"
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#include <stddef.h>
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@ -24,15 +30,16 @@
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S2S_Target* s2s_DeviceFindByScsiId(int scsiId)
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{
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int deviceCount;
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S2S_Device* devices = s2s_GetDevices(&deviceCount);
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S2S_Device** devices = s2s_GetDevices(&deviceCount);
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for (int deviceIdx = 0; deviceIdx < deviceCount; ++deviceIdx)
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{
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int targetCount;
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S2S_Target* targets = devices[deviceIdx].getTargets(devices + deviceIdx, &targetCount);
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S2S_Target* targets = devices[deviceIdx]->getTargets(devices[deviceIdx], &targetCount);
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for (int targetIdx = 0; targetIdx < targetCount; ++targetIdx)
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{
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S2S_Target* target = targets + targetIdx;
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if (target &&
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target->cfg &&
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(target->cfg->scsiId & CONFIG_TARGET_ENABLED) &&
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((target->cfg->scsiId & CONFIG_TARGET_ID_BITS) == scsiId))
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{
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@ -44,19 +51,38 @@ S2S_Target* s2s_DeviceFindByScsiId(int scsiId)
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return NULL;
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}
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S2S_Device* s2s_GetDevices(int* count)
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S2S_Device** s2s_GetDevices(int* count)
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{
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*count = 1;
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return sdDevice;
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static S2S_Device* allDevices[2];
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*count = 1;
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allDevices[0] = sdDevice;
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#ifdef NOR_SPI_DATA_WIDTH
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*count = 2;
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allDevices[0] = spiFlashDevice;
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#endif
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return &allDevices;
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}
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void s2s_deviceEarlyInit()
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{
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int count;
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S2S_Device* devices = s2s_GetDevices(&count);
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S2S_Device** devices = s2s_GetDevices(&count);
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for (int i = 0; i < count; ++i)
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{
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devices[i].earlyInit(&(devices[i]));
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devices[i]->earlyInit(devices[i]);
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}
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}
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void s2s_deviceInit()
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{
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int count;
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S2S_Device** devices = s2s_GetDevices(&count);
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for (int i = 0; i < count; ++i)
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{
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devices[i]->init(devices[i]);
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}
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}
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@ -64,10 +90,10 @@ int s2s_pollMediaChange()
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{
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int result = 0;
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int count;
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S2S_Device* devices = s2s_GetDevices(&count);
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S2S_Device** devices = s2s_GetDevices(&count);
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for (int i = 0; i < count; ++i)
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{
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int devResult = devices[i].pollMediaChange(&(devices[i]));
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int devResult = devices[i]->pollMediaChange(devices[i]);
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result = result || devResult;
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}
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return result;
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@ -66,6 +66,7 @@ struct S2S_TargetStruct
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struct S2S_DeviceStruct
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{
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void (*earlyInit)(S2S_Device* dev);
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void (*init)(S2S_Device* dev);
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S2S_Target* (*getTargets)(S2S_Device* dev, int* count);
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@ -76,13 +77,15 @@ struct S2S_DeviceStruct
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void (*pollMediaBusy)(S2S_Device* dev);
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MEDIA_STATE mediaState;
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CONFIG_STOREDEVICE deviceType;
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};
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S2S_Target* s2s_DeviceFindByScsiId(int scsiId);
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S2S_Device* s2s_GetDevices(int* count);
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S2S_Device** s2s_GetDevices(int* count);
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void s2s_deviceEarlyInit();
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void s2s_deviceInit();
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int s2s_pollMediaChange();
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#endif
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@ -424,34 +424,34 @@
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#define NOR_SO__SLW CYREG_PRT15_SLW
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/* SDCard */
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK
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#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK
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#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK
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#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK
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#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL
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#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL
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#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL
|
||||
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK
|
||||
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
|
||||
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK
|
||||
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
|
||||
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
|
||||
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
|
||||
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
|
||||
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
|
||||
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
|
||||
#define SDCard_BSPIM_RxStsReg__4__POS 4
|
||||
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
|
||||
@ -459,13 +459,9 @@
|
||||
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
|
||||
#define SDCard_BSPIM_RxStsReg__6__POS 6
|
||||
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
|
||||
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
|
||||
#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
|
||||
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB04_MSK
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB04_ST
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
|
||||
@ -483,12 +479,14 @@
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
|
||||
#define SDCard_BSPIM_TxStsReg__0__POS 0
|
||||
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
|
||||
#define SDCard_BSPIM_TxStsReg__1__POS 1
|
||||
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
|
||||
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
|
||||
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
|
||||
#define SDCard_BSPIM_TxStsReg__2__POS 2
|
||||
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
|
||||
@ -496,9 +494,9 @@
|
||||
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
|
||||
#define SDCard_BSPIM_TxStsReg__4__POS 4
|
||||
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
|
||||
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB06_MSK
|
||||
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB06_ST
|
||||
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
|
||||
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
|
||||
|
||||
/* SD_SCK */
|
||||
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1
|
||||
@ -534,30 +532,6 @@
|
||||
#define SD_SCK__SHIFT 1u
|
||||
#define SD_SCK__SLW CYREG_PRT3_SLW
|
||||
|
||||
/* NOR_CTL */
|
||||
#define NOR_CTL_Sync_ctrl_reg__0__MASK 0x01u
|
||||
#define NOR_CTL_Sync_ctrl_reg__0__POS 0
|
||||
#define NOR_CTL_Sync_ctrl_reg__1__MASK 0x02u
|
||||
#define NOR_CTL_Sync_ctrl_reg__1__POS 1
|
||||
#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
|
||||
#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
|
||||
#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
|
||||
#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
|
||||
#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
|
||||
#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
|
||||
#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
|
||||
#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
|
||||
#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
|
||||
#define NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
|
||||
#define NOR_CTL_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB06_CTL
|
||||
#define NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
|
||||
#define NOR_CTL_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB06_CTL
|
||||
#define NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
|
||||
#define NOR_CTL_Sync_ctrl_reg__MASK 0x03u
|
||||
#define NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
|
||||
#define NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
|
||||
#define NOR_CTL_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB06_MSK
|
||||
|
||||
/* NOR_SCK */
|
||||
#define NOR_SCK__0__INTTYPE CYREG_PICU3_INTTYPE7
|
||||
#define NOR_SCK__0__MASK 0x80u
|
||||
@ -593,34 +567,34 @@
|
||||
#define NOR_SCK__SLW CYREG_PRT3_SLW
|
||||
|
||||
/* NOR_SPI */
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
|
||||
#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB08_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB08_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB08_MSK
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB08_MSK
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB08_ST
|
||||
#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
|
||||
#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
|
||||
#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
|
||||
#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL
|
||||
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST
|
||||
#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
|
||||
#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
|
||||
#define NOR_SPI_BSPIM_RxStsReg__4__MASK 0x10u
|
||||
#define NOR_SPI_BSPIM_RxStsReg__4__POS 4
|
||||
#define NOR_SPI_BSPIM_RxStsReg__5__MASK 0x20u
|
||||
@ -628,32 +602,34 @@
|
||||
#define NOR_SPI_BSPIM_RxStsReg__6__MASK 0x40u
|
||||
#define NOR_SPI_BSPIM_RxStsReg__6__POS 6
|
||||
#define NOR_SPI_BSPIM_RxStsReg__MASK 0x70u
|
||||
#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK
|
||||
#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
|
||||
#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1
|
||||
#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
|
||||
#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
|
||||
#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
|
||||
#define NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
|
||||
#define NOR_SPI_BSPIM_TxStsReg__0__MASK 0x01u
|
||||
#define NOR_SPI_BSPIM_TxStsReg__0__POS 0
|
||||
#define NOR_SPI_BSPIM_TxStsReg__1__MASK 0x02u
|
||||
#define NOR_SPI_BSPIM_TxStsReg__1__POS 1
|
||||
#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
|
||||
#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
|
||||
#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
|
||||
#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
|
||||
#define NOR_SPI_BSPIM_TxStsReg__2__MASK 0x04u
|
||||
#define NOR_SPI_BSPIM_TxStsReg__2__POS 2
|
||||
#define NOR_SPI_BSPIM_TxStsReg__3__MASK 0x08u
|
||||
@ -661,9 +637,9 @@
|
||||
#define NOR_SPI_BSPIM_TxStsReg__4__MASK 0x10u
|
||||
#define NOR_SPI_BSPIM_TxStsReg__4__POS 4
|
||||
#define NOR_SPI_BSPIM_TxStsReg__MASK 0x1Fu
|
||||
#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
|
||||
#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
|
||||
#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
|
||||
#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK
|
||||
#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
|
||||
#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST
|
||||
|
||||
/* SCSI_In */
|
||||
#define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1
|
||||
@ -1784,15 +1760,15 @@
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
|
||||
@ -1805,35 +1781,35 @@
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
|
||||
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
|
||||
#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
|
||||
#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
|
||||
@ -2843,58 +2819,58 @@
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
|
||||
|
||||
/* SCSI_Glitch_Ctl */
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
|
||||
|
||||
/* SCSI_Parity_Error */
|
||||
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
|
||||
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
|
||||
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
|
||||
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
|
||||
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
|
||||
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
|
||||
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
|
||||
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
|
||||
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
|
||||
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
|
||||
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB08_MSK
|
||||
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
|
||||
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB08_ST
|
||||
|
||||
/* Miscellaneous */
|
||||
#define BCLK__BUS_CLK__HZ 50000000U
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -424,34 +424,34 @@
|
||||
.set NOR_SO__SLW, CYREG_PRT15_SLW
|
||||
|
||||
/* SDCard */
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
|
||||
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
|
||||
.set SDCard_BSPIM_RxStsReg__4__POS, 4
|
||||
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
|
||||
@ -459,13 +459,9 @@
|
||||
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
|
||||
.set SDCard_BSPIM_RxStsReg__6__POS, 6
|
||||
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
|
||||
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
|
||||
.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
|
||||
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB04_MSK
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB04_ST
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
|
||||
@ -483,12 +479,14 @@
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
|
||||
.set SDCard_BSPIM_TxStsReg__0__POS, 0
|
||||
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
|
||||
.set SDCard_BSPIM_TxStsReg__1__POS, 1
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
|
||||
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
|
||||
.set SDCard_BSPIM_TxStsReg__2__POS, 2
|
||||
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
|
||||
@ -496,9 +494,9 @@
|
||||
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
|
||||
.set SDCard_BSPIM_TxStsReg__4__POS, 4
|
||||
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
|
||||
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB06_MSK
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB06_ST
|
||||
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
|
||||
|
||||
/* SD_SCK */
|
||||
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE1
|
||||
@ -534,30 +532,6 @@
|
||||
.set SD_SCK__SHIFT, 1
|
||||
.set SD_SCK__SLW, CYREG_PRT3_SLW
|
||||
|
||||
/* NOR_CTL */
|
||||
.set NOR_CTL_Sync_ctrl_reg__0__MASK, 0x01
|
||||
.set NOR_CTL_Sync_ctrl_reg__0__POS, 0
|
||||
.set NOR_CTL_Sync_ctrl_reg__1__MASK, 0x02
|
||||
.set NOR_CTL_Sync_ctrl_reg__1__POS, 1
|
||||
.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
|
||||
.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
|
||||
.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
|
||||
.set NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
|
||||
.set NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
|
||||
.set NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
|
||||
.set NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
|
||||
.set NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
|
||||
.set NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
|
||||
.set NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
|
||||
.set NOR_CTL_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB06_CTL
|
||||
.set NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
|
||||
.set NOR_CTL_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB06_CTL
|
||||
.set NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
|
||||
.set NOR_CTL_Sync_ctrl_reg__MASK, 0x03
|
||||
.set NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
|
||||
.set NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
|
||||
.set NOR_CTL_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB06_MSK
|
||||
|
||||
/* NOR_SCK */
|
||||
.set NOR_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE7
|
||||
.set NOR_SCK__0__MASK, 0x80
|
||||
@ -593,34 +567,34 @@
|
||||
.set NOR_SCK__SLW, CYREG_PRT3_SLW
|
||||
|
||||
/* NOR_SPI */
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
|
||||
.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB08_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB08_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB08_MSK
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB08_MSK
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB08_ST
|
||||
.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
|
||||
.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
|
||||
.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
|
||||
.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL
|
||||
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST
|
||||
.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
|
||||
.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
|
||||
.set NOR_SPI_BSPIM_RxStsReg__4__MASK, 0x10
|
||||
.set NOR_SPI_BSPIM_RxStsReg__4__POS, 4
|
||||
.set NOR_SPI_BSPIM_RxStsReg__5__MASK, 0x20
|
||||
@ -628,32 +602,34 @@
|
||||
.set NOR_SPI_BSPIM_RxStsReg__6__MASK, 0x40
|
||||
.set NOR_SPI_BSPIM_RxStsReg__6__POS, 6
|
||||
.set NOR_SPI_BSPIM_RxStsReg__MASK, 0x70
|
||||
.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK
|
||||
.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
|
||||
.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1
|
||||
.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
|
||||
.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
|
||||
.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set NOR_SPI_BSPIM_TxStsReg__0__MASK, 0x01
|
||||
.set NOR_SPI_BSPIM_TxStsReg__0__POS, 0
|
||||
.set NOR_SPI_BSPIM_TxStsReg__1__MASK, 0x02
|
||||
.set NOR_SPI_BSPIM_TxStsReg__1__POS, 1
|
||||
.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
|
||||
.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
|
||||
.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
|
||||
.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
|
||||
.set NOR_SPI_BSPIM_TxStsReg__2__MASK, 0x04
|
||||
.set NOR_SPI_BSPIM_TxStsReg__2__POS, 2
|
||||
.set NOR_SPI_BSPIM_TxStsReg__3__MASK, 0x08
|
||||
@ -661,9 +637,9 @@
|
||||
.set NOR_SPI_BSPIM_TxStsReg__4__MASK, 0x10
|
||||
.set NOR_SPI_BSPIM_TxStsReg__4__POS, 4
|
||||
.set NOR_SPI_BSPIM_TxStsReg__MASK, 0x1F
|
||||
.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
|
||||
.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
|
||||
.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
|
||||
.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
|
||||
.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
|
||||
.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
|
||||
|
||||
/* SCSI_In */
|
||||
.set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1
|
||||
@ -1784,15 +1760,15 @@
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
|
||||
@ -1805,35 +1781,35 @@
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB09_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB09_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB09_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
|
||||
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
|
||||
.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX
|
||||
.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE
|
||||
@ -2843,58 +2819,58 @@
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK
|
||||
|
||||
/* SCSI_Glitch_Ctl */
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
|
||||
|
||||
/* SCSI_Parity_Error */
|
||||
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
|
||||
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
|
||||
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
|
||||
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
|
||||
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
|
||||
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
|
||||
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
|
||||
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
|
||||
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
|
||||
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
|
||||
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB08_MSK
|
||||
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
|
||||
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB08_ST
|
||||
|
||||
/* Miscellaneous */
|
||||
.set BCLK__BUS_CLK__HZ, 50000000
|
||||
|
@ -423,34 +423,34 @@ NOR_SO__SHIFT EQU 2
|
||||
NOR_SO__SLW EQU CYREG_PRT15_SLW
|
||||
|
||||
/* SDCard */
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
|
||||
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_RxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
|
||||
@ -458,13 +458,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
|
||||
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
|
||||
SDCard_BSPIM_RxStsReg__6__POS EQU 6
|
||||
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
|
||||
@ -482,12 +478,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
|
||||
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
|
||||
SDCard_BSPIM_TxStsReg__0__POS EQU 0
|
||||
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
|
||||
SDCard_BSPIM_TxStsReg__1__POS EQU 1
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
|
||||
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
|
||||
SDCard_BSPIM_TxStsReg__2__POS EQU 2
|
||||
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
|
||||
@ -495,9 +493,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
|
||||
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_TxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
|
||||
|
||||
/* SD_SCK */
|
||||
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
|
||||
@ -533,30 +531,6 @@ SD_SCK__PS EQU CYREG_PRT3_PS
|
||||
SD_SCK__SHIFT EQU 1
|
||||
SD_SCK__SLW EQU CYREG_PRT3_SLW
|
||||
|
||||
/* NOR_CTL */
|
||||
NOR_CTL_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
NOR_CTL_Sync_ctrl_reg__0__POS EQU 0
|
||||
NOR_CTL_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
NOR_CTL_Sync_ctrl_reg__1__POS EQU 1
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
NOR_CTL_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB06_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB06_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__MASK EQU 0x03
|
||||
NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
NOR_CTL_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB06_MSK
|
||||
|
||||
/* NOR_SCK */
|
||||
NOR_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE7
|
||||
NOR_SCK__0__MASK EQU 0x80
|
||||
@ -592,34 +566,34 @@ NOR_SCK__SHIFT EQU 7
|
||||
NOR_SCK__SLW EQU CYREG_PRT3_SLW
|
||||
|
||||
/* NOR_SPI */
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK
|
||||
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
|
||||
NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK
|
||||
NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST
|
||||
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
|
||||
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
|
||||
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
|
||||
NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
|
||||
NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
|
||||
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10
|
||||
NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4
|
||||
NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20
|
||||
@ -627,32 +601,34 @@ NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5
|
||||
NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40
|
||||
NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6
|
||||
NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70
|
||||
NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
|
||||
NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
|
||||
NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1
|
||||
NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01
|
||||
NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0
|
||||
NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02
|
||||
NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1
|
||||
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
|
||||
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
|
||||
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
|
||||
NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04
|
||||
NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2
|
||||
NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08
|
||||
@ -660,9 +636,9 @@ NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3
|
||||
NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10
|
||||
NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4
|
||||
NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F
|
||||
NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
|
||||
NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
|
||||
NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
|
||||
NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
|
||||
NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
|
||||
|
||||
/* SCSI_In */
|
||||
SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
|
||||
@ -1783,15 +1759,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
|
||||
@ -1804,35 +1780,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
|
||||
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
|
||||
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
|
||||
SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
|
||||
@ -2842,58 +2818,58 @@ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
|
||||
|
||||
/* SCSI_Glitch_Ctl */
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
|
||||
|
||||
/* SCSI_Parity_Error */
|
||||
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
|
||||
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST
|
||||
|
||||
/* Miscellaneous */
|
||||
BCLK__BUS_CLK__HZ EQU 50000000
|
||||
|
@ -423,34 +423,34 @@ NOR_SO__SHIFT EQU 2
|
||||
NOR_SO__SLW EQU CYREG_PRT15_SLW
|
||||
|
||||
; SDCard
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
|
||||
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_RxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
|
||||
@ -458,13 +458,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
|
||||
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
|
||||
SDCard_BSPIM_RxStsReg__6__POS EQU 6
|
||||
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
|
||||
@ -482,12 +478,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
|
||||
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
|
||||
SDCard_BSPIM_TxStsReg__0__POS EQU 0
|
||||
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
|
||||
SDCard_BSPIM_TxStsReg__1__POS EQU 1
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
|
||||
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
|
||||
SDCard_BSPIM_TxStsReg__2__POS EQU 2
|
||||
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
|
||||
@ -495,9 +493,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
|
||||
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_TxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
|
||||
|
||||
; SD_SCK
|
||||
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
|
||||
@ -533,30 +531,6 @@ SD_SCK__PS EQU CYREG_PRT3_PS
|
||||
SD_SCK__SHIFT EQU 1
|
||||
SD_SCK__SLW EQU CYREG_PRT3_SLW
|
||||
|
||||
; NOR_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
NOR_CTL_Sync_ctrl_reg__0__POS EQU 0
|
||||
NOR_CTL_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
NOR_CTL_Sync_ctrl_reg__1__POS EQU 1
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
NOR_CTL_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB06_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB06_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
NOR_CTL_Sync_ctrl_reg__MASK EQU 0x03
|
||||
NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
NOR_CTL_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB06_MSK
|
||||
|
||||
; NOR_SCK
|
||||
NOR_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE7
|
||||
NOR_SCK__0__MASK EQU 0x80
|
||||
@ -592,34 +566,34 @@ NOR_SCK__SHIFT EQU 7
|
||||
NOR_SCK__SLW EQU CYREG_PRT3_SLW
|
||||
|
||||
; NOR_SPI
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK
|
||||
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
|
||||
NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK
|
||||
NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST
|
||||
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
|
||||
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
|
||||
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
|
||||
NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
|
||||
NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
|
||||
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10
|
||||
NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4
|
||||
NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20
|
||||
@ -627,32 +601,34 @@ NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5
|
||||
NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40
|
||||
NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6
|
||||
NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70
|
||||
NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
|
||||
NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
|
||||
NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1
|
||||
NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01
|
||||
NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0
|
||||
NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02
|
||||
NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1
|
||||
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
|
||||
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
|
||||
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
|
||||
NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04
|
||||
NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2
|
||||
NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08
|
||||
@ -660,9 +636,9 @@ NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3
|
||||
NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10
|
||||
NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4
|
||||
NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F
|
||||
NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
|
||||
NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
|
||||
NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
|
||||
NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
|
||||
NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
|
||||
|
||||
; SCSI_In
|
||||
SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
|
||||
@ -1783,15 +1759,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
|
||||
@ -1804,35 +1780,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
|
||||
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
|
||||
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
|
||||
SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
|
||||
@ -2842,58 +2818,58 @@ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
|
||||
|
||||
; SCSI_Glitch_Ctl
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
|
||||
|
||||
; SCSI_Parity_Error
|
||||
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
|
||||
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST
|
||||
|
||||
; Miscellaneous
|
||||
BCLK__BUS_CLK__HZ EQU 50000000
|
||||
|
@ -81,7 +81,6 @@
|
||||
#include "nNOR_HOLD.h"
|
||||
#include "NOR_SI_aliases.h"
|
||||
#include "NOR_SI.h"
|
||||
#include "NOR_CTL.h"
|
||||
#include "nNOR_CS_aliases.h"
|
||||
#include "nNOR_CS.h"
|
||||
#include "nNOR_WP_aliases.h"
|
||||
|
@ -5,16 +5,16 @@
|
||||
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="TERM_EN" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Parity_Error_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">
|
||||
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006568" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006588" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006598" bitWidth="8" desc="" hidden="false">
|
||||
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="Enable counter" />
|
||||
<value name="DISABLED" value="0" desc="Disable counter" />
|
||||
@ -76,22 +76,8 @@
|
||||
</register>
|
||||
</block>
|
||||
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="NOR_SI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="NOR_CTL" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="NOR_CTL_CONTROL_REG" address="0x40006576" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="NOR_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="nNOR_HOLD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="nNOR_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="nNOR_WP" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="NOR_SO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="NOR_SI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="NOR_SPI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
@ -99,8 +85,20 @@
|
||||
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
</block>
|
||||
<block name="not_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="NOR_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="nNOR_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="nNOR_WP" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="NOR_Clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="NOR_SO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
@ -111,7 +109,7 @@
|
||||
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
@ -119,15 +117,71 @@
|
||||
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">
|
||||
<field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." hidden="false" />
|
||||
</register>
|
||||
<register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">
|
||||
<field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." hidden="false" />
|
||||
<field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)" hidden="false">
|
||||
<value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
|
||||
<value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
|
||||
</field>
|
||||
<field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." hidden="false" />
|
||||
<field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." hidden="false" />
|
||||
<field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" hidden="false" />
|
||||
<field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively." hidden="false">
|
||||
<value name="Timer" value="0" desc="CMP and TC are output." />
|
||||
<value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
|
||||
</field>
|
||||
<field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" hidden="false" />
|
||||
</register>
|
||||
<register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">
|
||||
<field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" hidden="false" />
|
||||
<field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled." hidden="false">
|
||||
<value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
|
||||
<value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
|
||||
</field>
|
||||
<field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." hidden="false" />
|
||||
<field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." hidden="false" />
|
||||
<field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." hidden="false" />
|
||||
<field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." hidden="false" />
|
||||
</register>
|
||||
<register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">
|
||||
<field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ" hidden="false">
|
||||
<value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
|
||||
<value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
|
||||
<value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
|
||||
<value name="Irq" value="11" desc="Timer runs until IRQ." />
|
||||
</field>
|
||||
<field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." hidden="false" />
|
||||
<field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" hidden="false" />
|
||||
<field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations" hidden="false">
|
||||
<value name="Equal" value="0" desc="Compare Equal " />
|
||||
<value name="Less than" value="1" desc="Compare Less Than " />
|
||||
<value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
|
||||
<value name="Greater" value="11" desc="Compare Greater Than ." />
|
||||
<value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
|
||||
</field>
|
||||
<field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." hidden="false" />
|
||||
</register>
|
||||
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
|
||||
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
|
||||
</block>
|
||||
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">
|
||||
<block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
@ -986,7 +1040,7 @@
|
||||
<field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />
|
||||
</register>
|
||||
</block>
|
||||
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
@ -994,69 +1048,12 @@
|
||||
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
</block>
|
||||
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">
|
||||
<field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." hidden="false" />
|
||||
</register>
|
||||
<register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">
|
||||
<field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." hidden="false" />
|
||||
<field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)" hidden="false">
|
||||
<value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
|
||||
<value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
|
||||
</field>
|
||||
<field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." hidden="false" />
|
||||
<field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." hidden="false" />
|
||||
<field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" hidden="false" />
|
||||
<field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively." hidden="false">
|
||||
<value name="Timer" value="0" desc="CMP and TC are output." />
|
||||
<value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
|
||||
</field>
|
||||
<field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" hidden="false" />
|
||||
</register>
|
||||
<register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">
|
||||
<field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" hidden="false" />
|
||||
<field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled." hidden="false">
|
||||
<value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
|
||||
<value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
|
||||
</field>
|
||||
<field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." hidden="false" />
|
||||
<field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." hidden="false" />
|
||||
<field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." hidden="false" />
|
||||
<field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." hidden="false" />
|
||||
</register>
|
||||
<register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">
|
||||
<field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ" hidden="false">
|
||||
<value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
|
||||
<value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
|
||||
<value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
|
||||
<value name="Irq" value="11" desc="Timer runs until IRQ." />
|
||||
</field>
|
||||
<field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." hidden="false" />
|
||||
<field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" hidden="false" />
|
||||
<field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations" hidden="false">
|
||||
<value name="Equal" value="0" desc="Compare Equal " />
|
||||
<value name="Less than" value="1" desc="Compare Less Than " />
|
||||
<value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
|
||||
<value name="Greater" value="11" desc="Compare Greater Than ." />
|
||||
<value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
|
||||
</field>
|
||||
<field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." hidden="false" />
|
||||
</register>
|
||||
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
|
||||
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
|
||||
</block>
|
||||
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006479" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
</blockRegMap>
|
Binary file not shown.
@ -158,6 +158,13 @@
|
||||
<build_action v="SOURCE_C;;;;" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="flash.c" persistent="..\..\src\flash.c">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="SOURCE_C;;;;" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
</dependencies>
|
||||
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
|
||||
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
|
||||
@ -336,6 +343,13 @@
|
||||
<build_action v="HEADER;;;;" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="flash.h" persistent="..\..\src\flash.h">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="HEADER;;;;" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
</dependencies>
|
||||
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
|
||||
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
|
||||
@ -2517,27 +2531,27 @@
|
||||
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">
|
||||
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="NOR_CTL" persistent="">
|
||||
<Hidden v="False" />
|
||||
<Hidden v="True" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemListSerialize" version="2">
|
||||
<dependencies>
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="NOR_CTL.h" persistent="Generated_Source\PSoC5\NOR_CTL.h">
|
||||
<Hidden v="False" />
|
||||
<Hidden v="True" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="HEADER;;;;" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="NOR_CTL.c" persistent="Generated_Source\PSoC5\NOR_CTL.c">
|
||||
<Hidden v="False" />
|
||||
<Hidden v="True" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="SOURCE_C;CortexM3;;;" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="NOR_CTL_PM.c" persistent="Generated_Source\PSoC5\NOR_CTL_PM.c">
|
||||
<Hidden v="False" />
|
||||
<Hidden v="True" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="SOURCE_C;CortexM3;;;" />
|
||||
<PropertyDeltas />
|
||||
|
@ -19,7 +19,7 @@
|
||||
<register>
|
||||
<name>SCSI_Glitch_Ctl_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x4000647D</addressOffset>
|
||||
<addressOffset>0x4000647C</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
@ -40,7 +40,7 @@
|
||||
<register>
|
||||
<name>SCSI_Parity_Error_STATUS_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x4000646B</addressOffset>
|
||||
<addressOffset>0x40006568</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
@ -49,7 +49,7 @@
|
||||
<register>
|
||||
<name>SCSI_Parity_Error_MASK_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x4000648B</addressOffset>
|
||||
<addressOffset>0x40006588</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
@ -58,7 +58,7 @@
|
||||
<register>
|
||||
<name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x4000649B</addressOffset>
|
||||
<addressOffset>0x40006598</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
@ -337,27 +337,6 @@
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>NOR_CTL</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x0</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>NOR_CTL_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x40006576</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_CTL_PHASE</name>
|
||||
<description>No description available</description>
|
||||
@ -371,7 +350,7 @@
|
||||
<register>
|
||||
<name>SCSI_CTL_PHASE_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x4000647C</addressOffset>
|
||||
<addressOffset>0x4000647D</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
@ -379,6 +358,298 @@
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>Debug_Timer</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x0</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>Debug_Timer_GLOBAL_ENABLE</name>
|
||||
<description>PM.ACT.CFG</description>
|
||||
<addressOffset>0x400043A3</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>en_timer</name>
|
||||
<description>Enable timer/counters.</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>Debug_Timer_CONTROL</name>
|
||||
<description>TMRx.CFG0</description>
|
||||
<addressOffset>0x40004F00</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>EN</name>
|
||||
<description>Enables timer/comparator.</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>0</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>MODE</name>
|
||||
<description>Mode. (0 = Timer; 1 = Comparator)</description>
|
||||
<lsb>1</lsb>
|
||||
<msb>1</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Timer</name>
|
||||
<description>Timer mode. CNT/CMP register holds timer count value.</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Comparator</name>
|
||||
<description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>ONESHOT</name>
|
||||
<description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
|
||||
<lsb>2</lsb>
|
||||
<msb>2</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>CMP_BUFF</name>
|
||||
<description>Buffer compare register. Compare register updates only on timer terminal count.</description>
|
||||
<lsb>3</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>INV</name>
|
||||
<description>Invert sense of TIMEREN signal</description>
|
||||
<lsb>4</lsb>
|
||||
<msb>4</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>DB</name>
|
||||
<description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
|
||||
<lsb>5</lsb>
|
||||
<msb>5</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Timer</name>
|
||||
<description>CMP and TC are output.</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Deadband</name>
|
||||
<description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>DEADBAND_PERIOD</name>
|
||||
<description>Deadband Period</description>
|
||||
<lsb>6</lsb>
|
||||
<msb>7</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>Debug_Timer_CONTROL2</name>
|
||||
<description>TMRx.CFG1</description>
|
||||
<addressOffset>0x40004F01</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>IRQ_SEL</name>
|
||||
<description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>0</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>FTC</name>
|
||||
<description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
|
||||
<lsb>1</lsb>
|
||||
<msb>1</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Disable_FTC</name>
|
||||
<description>Disable the single cycle pulse, which signifies the timer is starting.</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Enable_FTC</name>
|
||||
<description>Enable the single cycle pulse, which signifies the timer is starting.</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>DCOR</name>
|
||||
<description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
|
||||
<lsb>2</lsb>
|
||||
<msb>2</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>DBMODE</name>
|
||||
<description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
|
||||
<lsb>3</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>CLK_BUS_EN_SEL</name>
|
||||
<description>Digital Global Clock selection.</description>
|
||||
<lsb>4</lsb>
|
||||
<msb>6</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>BUS_CLK_SEL</name>
|
||||
<description>Bus Clock selection.</description>
|
||||
<lsb>7</lsb>
|
||||
<msb>7</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>Debug_Timer_CONTROL3_</name>
|
||||
<description>TMRx.CFG2</description>
|
||||
<addressOffset>0x40004F02</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>TMR_CFG</name>
|
||||
<description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>1</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Continuous</name>
|
||||
<description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Pulsewidth</name>
|
||||
<description>Timer runs from positive to negative edge of TIMEREN.</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Period</name>
|
||||
<description>Timer runs from positive to positive edge of TIMEREN.</description>
|
||||
<value>2</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Irq</name>
|
||||
<description>Timer runs until IRQ.</description>
|
||||
<value>3</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>COD</name>
|
||||
<description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
|
||||
<lsb>2</lsb>
|
||||
<msb>2</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>ROD</name>
|
||||
<description>Reset On Disable (ROD). Resets internal state of output logic</description>
|
||||
<lsb>3</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>CMP_CFG</name>
|
||||
<description>Comparator configurations</description>
|
||||
<lsb>4</lsb>
|
||||
<msb>6</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Equal</name>
|
||||
<description>Compare Equal </description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Less_than</name>
|
||||
<description>Compare Less Than </description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Less_than_or_equal</name>
|
||||
<description>Compare Less Than or Equal .</description>
|
||||
<value>2</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Greater</name>
|
||||
<description>Compare Greater Than .</description>
|
||||
<value>3</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Greater_than_or_equal</name>
|
||||
<description>Compare Greater Than or Equal </description>
|
||||
<value>4</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>HW_EN</name>
|
||||
<description>When set Timer Enable controls counting.</description>
|
||||
<lsb>7</lsb>
|
||||
<msb>7</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>Debug_Timer_PERIOD</name>
|
||||
<description>TMRx.PER0 - Assigned Period</description>
|
||||
<addressOffset>0x40004F04</addressOffset>
|
||||
<size>16</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
<register>
|
||||
<name>Debug_Timer_COUNTER</name>
|
||||
<description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
|
||||
<addressOffset>0x40004F06</addressOffset>
|
||||
<size>16</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>USBFS</name>
|
||||
<description>USBFS</description>
|
||||
@ -2617,319 +2888,6 @@
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_Out_Ctl</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x0</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>SCSI_Out_Ctl_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x40006473</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>Debug_Timer</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x0</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>Debug_Timer_GLOBAL_ENABLE</name>
|
||||
<description>PM.ACT.CFG</description>
|
||||
<addressOffset>0x400043A3</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>en_timer</name>
|
||||
<description>Enable timer/counters.</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>Debug_Timer_CONTROL</name>
|
||||
<description>TMRx.CFG0</description>
|
||||
<addressOffset>0x40004F00</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>EN</name>
|
||||
<description>Enables timer/comparator.</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>0</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>MODE</name>
|
||||
<description>Mode. (0 = Timer; 1 = Comparator)</description>
|
||||
<lsb>1</lsb>
|
||||
<msb>1</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Timer</name>
|
||||
<description>Timer mode. CNT/CMP register holds timer count value.</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Comparator</name>
|
||||
<description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>ONESHOT</name>
|
||||
<description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
|
||||
<lsb>2</lsb>
|
||||
<msb>2</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>CMP_BUFF</name>
|
||||
<description>Buffer compare register. Compare register updates only on timer terminal count.</description>
|
||||
<lsb>3</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>INV</name>
|
||||
<description>Invert sense of TIMEREN signal</description>
|
||||
<lsb>4</lsb>
|
||||
<msb>4</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>DB</name>
|
||||
<description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
|
||||
<lsb>5</lsb>
|
||||
<msb>5</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Timer</name>
|
||||
<description>CMP and TC are output.</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Deadband</name>
|
||||
<description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>DEADBAND_PERIOD</name>
|
||||
<description>Deadband Period</description>
|
||||
<lsb>6</lsb>
|
||||
<msb>7</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>Debug_Timer_CONTROL2</name>
|
||||
<description>TMRx.CFG1</description>
|
||||
<addressOffset>0x40004F01</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>IRQ_SEL</name>
|
||||
<description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>0</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>FTC</name>
|
||||
<description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
|
||||
<lsb>1</lsb>
|
||||
<msb>1</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Disable_FTC</name>
|
||||
<description>Disable the single cycle pulse, which signifies the timer is starting.</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Enable_FTC</name>
|
||||
<description>Enable the single cycle pulse, which signifies the timer is starting.</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>DCOR</name>
|
||||
<description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
|
||||
<lsb>2</lsb>
|
||||
<msb>2</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>DBMODE</name>
|
||||
<description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
|
||||
<lsb>3</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>CLK_BUS_EN_SEL</name>
|
||||
<description>Digital Global Clock selection.</description>
|
||||
<lsb>4</lsb>
|
||||
<msb>6</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>BUS_CLK_SEL</name>
|
||||
<description>Bus Clock selection.</description>
|
||||
<lsb>7</lsb>
|
||||
<msb>7</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>Debug_Timer_CONTROL3_</name>
|
||||
<description>TMRx.CFG2</description>
|
||||
<addressOffset>0x40004F02</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>TMR_CFG</name>
|
||||
<description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>1</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Continuous</name>
|
||||
<description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Pulsewidth</name>
|
||||
<description>Timer runs from positive to negative edge of TIMEREN.</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Period</name>
|
||||
<description>Timer runs from positive to positive edge of TIMEREN.</description>
|
||||
<value>2</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Irq</name>
|
||||
<description>Timer runs until IRQ.</description>
|
||||
<value>3</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>COD</name>
|
||||
<description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
|
||||
<lsb>2</lsb>
|
||||
<msb>2</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>ROD</name>
|
||||
<description>Reset On Disable (ROD). Resets internal state of output logic</description>
|
||||
<lsb>3</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>CMP_CFG</name>
|
||||
<description>Comparator configurations</description>
|
||||
<lsb>4</lsb>
|
||||
<msb>6</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Equal</name>
|
||||
<description>Compare Equal </description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Less_than</name>
|
||||
<description>Compare Less Than </description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Less_than_or_equal</name>
|
||||
<description>Compare Less Than or Equal .</description>
|
||||
<value>2</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Greater</name>
|
||||
<description>Compare Greater Than .</description>
|
||||
<value>3</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Greater_than_or_equal</name>
|
||||
<description>Compare Greater Than or Equal </description>
|
||||
<value>4</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>HW_EN</name>
|
||||
<description>When set Timer Enable controls counting.</description>
|
||||
<lsb>7</lsb>
|
||||
<msb>7</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>Debug_Timer_PERIOD</name>
|
||||
<description>TMRx.PER0 - Assigned Period</description>
|
||||
<addressOffset>0x40004F04</addressOffset>
|
||||
<size>16</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
<register>
|
||||
<name>Debug_Timer_COUNTER</name>
|
||||
<description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
|
||||
<addressOffset>0x40004F06</addressOffset>
|
||||
<size>16</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_Out_Bits</name>
|
||||
<description>No description available</description>
|
||||
@ -2943,7 +2901,28 @@
|
||||
<register>
|
||||
<name>SCSI_Out_Bits_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x40006479</addressOffset>
|
||||
<addressOffset>0x40006473</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_Out_Ctl</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x0</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>SCSI_Out_Ctl_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x40006471</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
Binary file not shown.
@ -24,9 +24,9 @@ extern "C" {
|
||||
|
||||
#define USBHID_LEN 64
|
||||
|
||||
// Maximum packet payload length. Must be large enough to support a flash row
|
||||
// + flash array index + flash row index
|
||||
#define HIDPACKET_MAX_LEN 260
|
||||
// Maximum packet payload length. Must be large enough to support a SD sector
|
||||
// + sector number + device number
|
||||
#define HIDPACKET_MAX_LEN 520
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
@ -141,6 +141,12 @@ typedef enum
|
||||
CONFIG_SPEED_ASYNC_15
|
||||
} CONFIG_SPEED;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
CONFIG_STOREDEVICE_SD,
|
||||
CONFIG_STOREDEVICE_FLASH
|
||||
} CONFIG_STOREDEVICE;
|
||||
|
||||
typedef struct __attribute__((packed))
|
||||
{
|
||||
uint8_t deviceType;
|
||||
@ -178,8 +184,12 @@ typedef struct __attribute__((packed))
|
||||
char serial[16];
|
||||
|
||||
uint16_t quirks; // CONFIG_QUIRKS
|
||||
|
||||
// 0 == SD card
|
||||
// 1 == SPI Flash
|
||||
uint8_t storageDevice; // CONFIG_STOREDEVICE
|
||||
|
||||
uint8_t reserved[960]; // Pad out to 1024 bytes for main section.
|
||||
uint8_t reserved[959]; // Pad out to 1024 bytes for main section.
|
||||
|
||||
uint8_t modePages[1024];
|
||||
uint8_t vpd[1024];
|
||||
@ -244,7 +254,87 @@ typedef enum
|
||||
// Response:
|
||||
// CONFIG_STATUS
|
||||
// uint8_t result code (0 = passed)
|
||||
CONFIG_SCSITEST
|
||||
CONFIG_SCSITEST,
|
||||
|
||||
// Not implemented, V6 only
|
||||
// Command content:
|
||||
// uint8_t S2S_CMD_DEVINFO
|
||||
// Response:
|
||||
// uint16_t protocol version (MSB)
|
||||
// uint16_t firmware version (MSB)
|
||||
// uint32_t SD capacity(MSB)
|
||||
S2S_CMD_DEVINFO_OBSOLETE,
|
||||
|
||||
// Not implemented, V6 only
|
||||
// Command content:
|
||||
// uint8_t S2S_CMD_SD_WRITE
|
||||
// uint32_t Sector Number (MSB)
|
||||
// uint8_t[512] data
|
||||
// Response:
|
||||
// S2S_CMD_STATUS
|
||||
S2S_CMD_SD_WRITE,
|
||||
|
||||
// Not implemented, V6 only
|
||||
// Command content:
|
||||
// uint8_t S2S_CMD_SD_READ
|
||||
// uint32_t Sector Number (MSB)
|
||||
// Response:
|
||||
// 512 bytes of data
|
||||
S2S_CMD_SD_READ,
|
||||
|
||||
// Not implemented, V6 only
|
||||
// Command content:
|
||||
// uint8_t S2S_CMD_DEBUG
|
||||
// Response:
|
||||
S2S_CMD_DEBUG,
|
||||
|
||||
// Command content:
|
||||
// uint8_t S2S_CMD_DEV_LIST
|
||||
// Response:
|
||||
// uint8_t Number of devices
|
||||
// For each device:
|
||||
// uint8_t device type
|
||||
// 0 == SD card
|
||||
// 1 == NOR FLASH
|
||||
// uint32_t capacity(MSB)
|
||||
S2S_CMD_DEV_LIST,
|
||||
|
||||
// Command content:
|
||||
// uint8_t S2S_CMD_DEV_INFO
|
||||
// uint8_t Device Number
|
||||
// Response:
|
||||
// SD card:
|
||||
// uint8_t[16] CSD
|
||||
// uint8_t[16] CID
|
||||
// NOR Flash:
|
||||
// uint8_t[512] JEDEC CFI from RDID command
|
||||
S2S_CMD_DEV_INFO,
|
||||
|
||||
// Command content:
|
||||
// uint8_t S2S_CMD_DEV_ERASE
|
||||
// uint8_t Device Number
|
||||
// uint32_t Sector Number (MSB)
|
||||
// uint32_t Sector Count (MSB)
|
||||
// Response:
|
||||
// S2S_CMD_STATUS
|
||||
S2S_CMD_DEV_ERASE,
|
||||
|
||||
// Command content:
|
||||
// uint8_t S2S_CMD_DEV_WRITE
|
||||
// uint8_t Device Number (MSB)
|
||||
// uint32_t Sector Number (MSB)
|
||||
// uint8_t[512] data
|
||||
// Response:
|
||||
// S2S_CMD_STATUS
|
||||
S2S_CMD_DEV_WRITE,
|
||||
|
||||
// Command content:
|
||||
// uint8_t S2S_CMD_DEV_READ
|
||||
// uint8_t Device Number (MSB)
|
||||
// uint32_t Sector Number (MSB)
|
||||
// Response:
|
||||
// 512 bytes of data
|
||||
S2S_CMD_DEV_READ,
|
||||
} CONFIG_COMMAND;
|
||||
|
||||
typedef enum
|
||||
|
Loading…
x
Reference in New Issue
Block a user