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Code Issues Projects Releases Wiki Activity

Updating Powerbook firmware with the latest mainline changes.

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This commit is contained in:
Michael McMaster 2014-06-23 13:52:05 +10:00
parent 092541dd02
commit 5ede6f0d07
58 changed files with 9089 additions and 1772 deletions
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3
readme.txt
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@ -75,3 +75,6 @@ Users have reported success on these systems:
HP 16601A logic analyzer
Apple IIgs using Apple II High Speed SCSI controller card (from v3.3)
Symbolics List Machine XL1200, using 1280 byte sectors (from v3.4)
Fluke 9100 series
PDP-11/73 running RSX11M+ V4.6
Amiga 500+ with GVP A530

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software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cycdx Executable file → Normal file
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software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cyfit Executable file → Normal file
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software/SCSI2SD/pbook/bootloader.cydsn/bootloader.svd Executable file → Normal file
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software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Debug_Timer.c Normal file
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/*******************************************************************************
* File Name: Debug_Timer.c
* Version 2.50
*
* Description:
* The Timer component consists of a 8, 16, 24 or 32-bit timer with
* a selectable period between 2 and 2^Width - 1. The timer may free run
* or be used as a capture timer as well. The capture can be initiated
* by a positive or negative edge signal as well as via software.
* A trigger input can be programmed to enable the timer on rising edge
* falling edge, either edge or continous run.
* Interrupts may be generated due to a terminal count condition
* or a capture event.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include "Debug_Timer.h"
uint8 Debug_Timer_initVar = 0u;
/*******************************************************************************
* Function Name: Debug_Timer_Init
********************************************************************************
*
* Summary:
* Initialize to the schematic state
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_Init(void)
{
#if(!Debug_Timer_UsingFixedFunction)
/* Interrupt State Backup for Critical Region*/
uint8 Debug_Timer_interruptState;
#endif /* Interrupt state back up for Fixed Function only */
#if (Debug_Timer_UsingFixedFunction)
/* Clear all bits but the enable bit (if it's already set) for Timer operation */
Debug_Timer_CONTROL &= Debug_Timer_CTRL_ENABLE;
/* Clear the mode bits for continuous run mode */
#if (CY_PSOC5A)
Debug_Timer_CONTROL2 &= ((uint8)(~Debug_Timer_CTRL_MODE_MASK));
#endif /* Clear bits in CONTROL2 only in PSOC5A */
#if (CY_PSOC3 || CY_PSOC5LP)
Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_MODE_MASK));
#endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */
/* Check if One Shot mode is enabled i.e. RunMode !=0*/
#if (Debug_Timer_RunModeUsed != 0x0u)
/* Set 3rd bit of Control register to enable one shot mode */
Debug_Timer_CONTROL |= 0x04u;
#endif /* One Shot enabled only when RunModeUsed is not Continuous*/
#if (Debug_Timer_RunModeUsed == 2)
#if (CY_PSOC5A)
/* Set last 2 bits of control2 register if one shot(halt on
interrupt) is enabled*/
Debug_Timer_CONTROL2 |= 0x03u;
#endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Set last 2 bits of control3 register if one shot(halt on
interrupt) is enabled*/
Debug_Timer_CONTROL3 |= 0x03u;
#endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */
#endif /* Remove section if One Shot Halt on Interrupt is not enabled */
#if (Debug_Timer_UsingHWEnable != 0)
#if (CY_PSOC5A)
/* Set the default Run Mode of the Timer to Continuous */
Debug_Timer_CONTROL2 |= Debug_Timer_CTRL_MODE_PULSEWIDTH;
#endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Clear and Set ROD and COD bits of CFG2 register */
Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_RCOD_MASK));
Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_RCOD;
/* Clear and Enable the HW enable bit in CFG2 register */
Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_ENBL_MASK));
Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_ENBL;
/* Set the default Run Mode of the Timer to Continuous */
Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_MODE_CONTINUOUS;
#endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */
#endif /* Configure Run Mode with hardware enable */
/* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */
Debug_Timer_RT1 &= ((uint8)(~Debug_Timer_RT1_MASK));
Debug_Timer_RT1 |= Debug_Timer_SYNC;
/*Enable DSI Sync all all inputs of the Timer*/
Debug_Timer_RT1 &= ((uint8)(~Debug_Timer_SYNCDSI_MASK));
Debug_Timer_RT1 |= Debug_Timer_SYNCDSI_EN;
/* Set the IRQ to use the status register interrupts */
Debug_Timer_CONTROL2 |= Debug_Timer_CTRL2_IRQ_SEL;
#endif /* Configuring registers of fixed function implementation */
/* Set Initial values from Configuration */
Debug_Timer_WritePeriod(Debug_Timer_INIT_PERIOD);
Debug_Timer_WriteCounter(Debug_Timer_INIT_PERIOD);
#if (Debug_Timer_UsingHWCaptureCounter)/* Capture counter is enabled */
Debug_Timer_CAPTURE_COUNT_CTRL |= Debug_Timer_CNTR_ENABLE;
Debug_Timer_SetCaptureCount(Debug_Timer_INIT_CAPTURE_COUNT);
#endif /* Configure capture counter value */
#if (!Debug_Timer_UsingFixedFunction)
#if (Debug_Timer_SoftwareCaptureMode)
Debug_Timer_SetCaptureMode(Debug_Timer_INIT_CAPTURE_MODE);
#endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */
#if (Debug_Timer_SoftwareTriggerMode)
if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
{
Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
}
#endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */
/* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
/* Enter Critical Region*/
Debug_Timer_interruptState = CyEnterCriticalSection();
/* Use the interrupt output of the status register for IRQ output */
Debug_Timer_STATUS_AUX_CTRL |= Debug_Timer_STATUS_ACTL_INT_EN_MASK;
/* Exit Critical Region*/
CyExitCriticalSection(Debug_Timer_interruptState);
#if (Debug_Timer_EnableTriggerMode)
Debug_Timer_EnableTrigger();
#endif /* Set Trigger enable bit for UDB implementation in the control register*/
#if (Debug_Timer_InterruptOnCaptureCount)
#if (!Debug_Timer_ControlRegRemoved)
Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
#endif /* Set interrupt count in control register if control register is not removed */
#endif /*Set interrupt count in UDB implementation if interrupt count feature is checked.*/
Debug_Timer_ClearFIFO();
#endif /* Configure additional features of UDB implementation */
Debug_Timer_SetInterruptMode(Debug_Timer_INIT_INTERRUPT_MODE);
}
/*******************************************************************************
* Function Name: Debug_Timer_Enable
********************************************************************************
*
* Summary:
* Enable the Timer
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_Enable(void)
{
/* Globally Enable the Fixed Function Block chosen */
#if (Debug_Timer_UsingFixedFunction)
Debug_Timer_GLOBAL_ENABLE |= Debug_Timer_BLOCK_EN_MASK;
Debug_Timer_GLOBAL_STBY_ENABLE |= Debug_Timer_BLOCK_STBY_EN_MASK;
#endif /* Set Enable bit for enabling Fixed function timer*/
/* Remove assignment if control register is removed */
#if (!Debug_Timer_ControlRegRemoved || Debug_Timer_UsingFixedFunction)
Debug_Timer_CONTROL |= Debug_Timer_CTRL_ENABLE;
#endif /* Remove assignment if control register is removed */
}
/*******************************************************************************
* Function Name: Debug_Timer_Start
********************************************************************************
*
* Summary:
* The start function initializes the timer with the default values, the
* enables the timerto begin counting. It does not enable interrupts,
* the EnableInt command should be called if interrupt generation is required.
*
* Parameters:
* void
*
* Return:
* void
*
* Global variables:
* Debug_Timer_initVar: Is modified when this function is called for the
* first time. Is used to ensure that initialization happens only once.
*
*******************************************************************************/
void Debug_Timer_Start(void)
{
if(Debug_Timer_initVar == 0u)
{
Debug_Timer_Init();
Debug_Timer_initVar = 1u; /* Clear this bit for Initialization */
}
/* Enable the Timer */
Debug_Timer_Enable();
}
/*******************************************************************************
* Function Name: Debug_Timer_Stop
********************************************************************************
*
* Summary:
* The stop function halts the timer, but does not change any modes or disable
* interrupts.
*
* Parameters:
* void
*
* Return:
* void
*
* Side Effects: If the Enable mode is set to Hardware only then this function
* has no effect on the operation of the timer.
*
*******************************************************************************/
void Debug_Timer_Stop(void)
{
/* Disable Timer */
#if(!Debug_Timer_ControlRegRemoved || Debug_Timer_UsingFixedFunction)
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_ENABLE));
#endif /* Remove assignment if control register is removed */
/* Globally disable the Fixed Function Block chosen */
#if (Debug_Timer_UsingFixedFunction)
Debug_Timer_GLOBAL_ENABLE &= ((uint8)(~Debug_Timer_BLOCK_EN_MASK));
Debug_Timer_GLOBAL_STBY_ENABLE &= ((uint8)(~Debug_Timer_BLOCK_STBY_EN_MASK));
#endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/
}
/*******************************************************************************
* Function Name: Debug_Timer_SetInterruptMode
********************************************************************************
*
* Summary:
* This function selects which of the interrupt inputs may cause an interrupt.
* The twosources are caputure and terminal. One, both or neither may
* be selected.
*
* Parameters:
* interruptMode: This parameter is used to enable interrups on either/or
* terminal count or capture.
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_SetInterruptMode(uint8 interruptMode)
{
Debug_Timer_STATUS_MASK = interruptMode;
}
/*******************************************************************************
* Function Name: Debug_Timer_SoftwareCapture
********************************************************************************
*
* Summary:
* This function forces a capture independent of the capture signal.
*
* Parameters:
* void
*
* Return:
* void
*
* Side Effects:
* An existing hardware capture could be overwritten.
*
*******************************************************************************/
void Debug_Timer_SoftwareCapture(void)
{
/* Generate a software capture by reading the counter register */
(void)Debug_Timer_COUNTER_LSB;
/* Capture Data is now in the FIFO */
}
/*******************************************************************************
* Function Name: Debug_Timer_ReadStatusRegister
********************************************************************************
*
* Summary:
* Reads the status register and returns it's state. This function should use
* defined types for the bit-field information as the bits in this register may
* be permuteable.
*
* Parameters:
* void
*
* Return:
* The contents of the status register
*
* Side Effects:
* Status register bits may be clear on read.
*
*******************************************************************************/
uint8 Debug_Timer_ReadStatusRegister(void)
{
return (Debug_Timer_STATUS);
}
#if (!Debug_Timer_ControlRegRemoved) /* Remove API if control register is removed */
/*******************************************************************************
* Function Name: Debug_Timer_ReadControlRegister
********************************************************************************
*
* Summary:
* Reads the control register and returns it's value.
*
* Parameters:
* void
*
* Return:
* The contents of the control register
*
*******************************************************************************/
uint8 Debug_Timer_ReadControlRegister(void)
{
return ((uint8)Debug_Timer_CONTROL);
}
/*******************************************************************************
* Function Name: Debug_Timer_WriteControlRegister
********************************************************************************
*
* Summary:
* Sets the bit-field of the control register.
*
* Parameters:
* control: The contents of the control register
*
* Return:
*
*******************************************************************************/
void Debug_Timer_WriteControlRegister(uint8 control)
{
Debug_Timer_CONTROL = control;
}
#endif /* Remove API if control register is removed */
/*******************************************************************************
* Function Name: Debug_Timer_ReadPeriod
********************************************************************************
*
* Summary:
* This function returns the current value of the Period.
*
* Parameters:
* void
*
* Return:
* The present value of the counter.
*
*******************************************************************************/
uint16 Debug_Timer_ReadPeriod(void)
{
#if(Debug_Timer_UsingFixedFunction)
return ((uint16)CY_GET_REG16(Debug_Timer_PERIOD_LSB_PTR));
#else
return (CY_GET_REG16(Debug_Timer_PERIOD_LSB_PTR));
#endif /* (Debug_Timer_UsingFixedFunction) */
}
/*******************************************************************************
* Function Name: Debug_Timer_WritePeriod
********************************************************************************
*
* Summary:
* This function is used to change the period of the counter. The new period
* will be loaded the next time terminal count is detected.
*
* Parameters:
* period: This value may be between 1 and (2^Resolution)-1. A value of 0 will
* result in the counter remaining at zero.
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_WritePeriod(uint16 period)
{
#if(Debug_Timer_UsingFixedFunction)
uint16 period_temp = (uint16)period;
CY_SET_REG16(Debug_Timer_PERIOD_LSB_PTR, period_temp);
#else
CY_SET_REG16(Debug_Timer_PERIOD_LSB_PTR, period);
#endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */
}
/*******************************************************************************
* Function Name: Debug_Timer_ReadCapture
********************************************************************************
*
* Summary:
* This function returns the last value captured.
*
* Parameters:
* void
*
* Return:
* Present Capture value.
*
*******************************************************************************/
uint16 Debug_Timer_ReadCapture(void)
{
#if(Debug_Timer_UsingFixedFunction)
return ((uint16)CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
#else
return (CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
#endif /* (Debug_Timer_UsingFixedFunction) */
}
/*******************************************************************************
* Function Name: Debug_Timer_WriteCounter
********************************************************************************
*
* Summary:
* This funtion is used to set the counter to a specific value
*
* Parameters:
* counter: New counter value.
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_WriteCounter(uint16 counter) \
{
#if(Debug_Timer_UsingFixedFunction)
/* This functionality is removed until a FixedFunction HW update to
* allow this register to be written
*/
CY_SET_REG16(Debug_Timer_COUNTER_LSB_PTR, (uint16)counter);
#else
CY_SET_REG16(Debug_Timer_COUNTER_LSB_PTR, counter);
#endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */
}
/*******************************************************************************
* Function Name: Debug_Timer_ReadCounter
********************************************************************************
*
* Summary:
* This function returns the current counter value.
*
* Parameters:
* void
*
* Return:
* Present compare value.
*
*******************************************************************************/
uint16 Debug_Timer_ReadCounter(void)
{
/* Force capture by reading Accumulator */
/* Must first do a software capture to be able to read the counter */
/* It is up to the user code to make sure there isn't already captured data in the FIFO */
(void)Debug_Timer_COUNTER_LSB;
/* Read the data from the FIFO (or capture register for Fixed Function)*/
#if(Debug_Timer_UsingFixedFunction)
return ((uint16)CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
#else
return (CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
#endif /* (Debug_Timer_UsingFixedFunction) */
}
#if(!Debug_Timer_UsingFixedFunction) /* UDB Specific Functions */
/*******************************************************************************
* The functions below this point are only available using the UDB
* implementation. If a feature is selected, then the API is enabled.
******************************************************************************/
#if (Debug_Timer_SoftwareCaptureMode)
/*******************************************************************************
* Function Name: Debug_Timer_SetCaptureMode
********************************************************************************
*
* Summary:
* This function sets the capture mode to either rising or falling edge.
*
* Parameters:
* captureMode: This parameter sets the capture mode of the UDB capture feature
* The parameter values are defined using the
* #define Debug_Timer__B_TIMER__CM_NONE 0
#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1
#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2
#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3
#define Debug_Timer__B_TIMER__CM_SOFTWARE 4
identifiers
* The following are the possible values of the parameter
* Debug_Timer__B_TIMER__CM_NONE - Set Capture mode to None
* Debug_Timer__B_TIMER__CM_RISINGEDGE - Rising edge of Capture input
* Debug_Timer__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input
* Debug_Timer__B_TIMER__CM_EITHEREDGE - Either edge of Capture input
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_SetCaptureMode(uint8 captureMode)
{
/* This must only set to two bits of the control register associated */
captureMode = ((uint8)((uint8)captureMode << Debug_Timer_CTRL_CAP_MODE_SHIFT));
captureMode &= (Debug_Timer_CTRL_CAP_MODE_MASK);
/* Clear the Current Setting */
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
/* Write The New Setting */
Debug_Timer_CONTROL |= captureMode;
}
#endif /* Remove API if Capture Mode is not Software Controlled */
#if (Debug_Timer_SoftwareTriggerMode)
/*******************************************************************************
* Function Name: Debug_Timer_SetTriggerMode
********************************************************************************
*
* Summary:
* This function sets the trigger input mode
*
* Parameters:
* triggerMode: Pass one of the pre-defined Trigger Modes (except Software)
#define Debug_Timer__B_TIMER__TM_NONE 0x00u
#define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u
#define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u
#define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu
#define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_SetTriggerMode(uint8 triggerMode)
{
/* This must only set to two bits of the control register associated */
triggerMode &= Debug_Timer_CTRL_TRIG_MODE_MASK;
/* Clear the Current Setting */
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
/* Write The New Setting */
Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
}
#endif /* Remove API if Trigger Mode is not Software Controlled */
#if (Debug_Timer_EnableTriggerMode)
/*******************************************************************************
* Function Name: Debug_Timer_EnableTrigger
********************************************************************************
*
* Summary:
* Sets the control bit enabling Hardware Trigger mode
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_EnableTrigger(void)
{
#if (!Debug_Timer_ControlRegRemoved) /* Remove assignment if control register is removed */
Debug_Timer_CONTROL |= Debug_Timer_CTRL_TRIG_EN;
#endif /* Remove code section if control register is not used */
}
/*******************************************************************************
* Function Name: Debug_Timer_DisableTrigger
********************************************************************************
*
* Summary:
* Clears the control bit enabling Hardware Trigger mode
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_DisableTrigger(void)
{
#if (!Debug_Timer_ControlRegRemoved) /* Remove assignment if control register is removed */
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_EN));
#endif /* Remove code section if control register is not used */
}
#endif /* Remove API is Trigger Mode is set to None */
#if(Debug_Timer_InterruptOnCaptureCount)
#if (!Debug_Timer_ControlRegRemoved) /* Remove API if control register is removed */
/*******************************************************************************
* Function Name: Debug_Timer_SetInterruptCount
********************************************************************************
*
* Summary:
* This function sets the capture count before an interrupt is triggered.
*
* Parameters:
* interruptCount: A value between 0 and 3 is valid. If the value is 0, then
* an interrupt will occur each time a capture occurs.
* A value of 1 to 3 will cause the interrupt
* to delay by the same number of captures.
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_SetInterruptCount(uint8 interruptCount)
{
/* This must only set to two bits of the control register associated */
interruptCount &= Debug_Timer_CTRL_INTCNT_MASK;
/* Clear the Current Setting */
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
/* Write The New Setting */
Debug_Timer_CONTROL |= interruptCount;
}
#endif /* Remove API if control register is removed */
#endif /* Debug_Timer_InterruptOnCaptureCount */
#if (Debug_Timer_UsingHWCaptureCounter)
/*******************************************************************************
* Function Name: Debug_Timer_SetCaptureCount
********************************************************************************
*
* Summary:
* This function sets the capture count
*
* Parameters:
* captureCount: A value between 2 and 127 inclusive is valid. A value of 1
* to 127 will cause the interrupt to delay by the same number of
* captures.
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_SetCaptureCount(uint8 captureCount)
{
Debug_Timer_CAP_COUNT = captureCount;
}
/*******************************************************************************
* Function Name: Debug_Timer_ReadCaptureCount
********************************************************************************
*
* Summary:
* This function reads the capture count setting
*
* Parameters:
* void
*
* Return:
* Returns the Capture Count Setting
*
*******************************************************************************/
uint8 Debug_Timer_ReadCaptureCount(void)
{
return ((uint8)Debug_Timer_CAP_COUNT);
}
#endif /* Debug_Timer_UsingHWCaptureCounter */
/*******************************************************************************
* Function Name: Debug_Timer_ClearFIFO
********************************************************************************
*
* Summary:
* This function clears all capture data from the capture FIFO
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_ClearFIFO(void)
{
while(0u != (Debug_Timer_ReadStatusRegister() & Debug_Timer_STATUS_FIFONEMP))
{
(void)Debug_Timer_ReadCapture();
}
}
#endif /* UDB Specific Functions */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: Debug_Timer.h
* Version 2.50
*
* Description:
* Contains the function prototypes and constants available to the timer
* user module.
*
* Note:
* None
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#if !defined(CY_Timer_v2_30_Debug_Timer_H)
#define CY_Timer_v2_30_Debug_Timer_H
#include "cytypes.h"
#include "cyfitter.h"
#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */
extern uint8 Debug_Timer_initVar;
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
#error Component Timer_v2_50 requires cy_boot v3.0 or later
#endif /* (CY_ PSOC5LP) */
/**************************************
* Parameter Defaults
**************************************/
#define Debug_Timer_Resolution 16u
#define Debug_Timer_UsingFixedFunction 1u
#define Debug_Timer_UsingHWCaptureCounter 0u
#define Debug_Timer_SoftwareCaptureMode 0u
#define Debug_Timer_SoftwareTriggerMode 0u
#define Debug_Timer_UsingHWEnable 0u
#define Debug_Timer_EnableTriggerMode 0u
#define Debug_Timer_InterruptOnCaptureCount 0u
#define Debug_Timer_RunModeUsed 0u
#define Debug_Timer_ControlRegRemoved 0u
/***************************************
* Type defines
***************************************/
/**************************************************************************
* Sleep Wakeup Backup structure for Timer Component
*************************************************************************/
typedef struct
{
uint8 TimerEnableState;
#if(!Debug_Timer_UsingFixedFunction)
#if (CY_UDB_V0)
uint16 TimerUdb; /* Timer internal counter value */
uint16 TimerPeriod; /* Timer Period value */
uint8 InterruptMaskValue; /* Timer Compare Value */
#if (Debug_Timer_UsingHWCaptureCounter)
uint8 TimerCaptureCounter; /* Timer Capture Counter Value */
#endif /* variable declaration for backing up Capture Counter value*/
#endif /* variables for non retention registers in CY_UDB_V0 */
#if (CY_UDB_V1)
uint16 TimerUdb;
uint8 InterruptMaskValue;
#if (Debug_Timer_UsingHWCaptureCounter)
uint8 TimerCaptureCounter;
#endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
#endif /* (CY_UDB_V1) */
#if (!Debug_Timer_ControlRegRemoved)
uint8 TimerControlRegister;
#endif /* variable declaration for backing up enable state of the Timer */
#endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
}Debug_Timer_backupStruct;
/***************************************
* Function Prototypes
***************************************/
void Debug_Timer_Start(void) ;
void Debug_Timer_Stop(void) ;
void Debug_Timer_SetInterruptMode(uint8 interruptMode) ;
uint8 Debug_Timer_ReadStatusRegister(void) ;
/* Deprecated function. Do not use this in future. Retained for backward compatibility */
#define Debug_Timer_GetInterruptSource() Debug_Timer_ReadStatusRegister()
#if(!Debug_Timer_ControlRegRemoved)
uint8 Debug_Timer_ReadControlRegister(void) ;
void Debug_Timer_WriteControlRegister(uint8 control) \
;
#endif /* (!Debug_Timer_ControlRegRemoved) */
uint16 Debug_Timer_ReadPeriod(void) ;
void Debug_Timer_WritePeriod(uint16 period) \
;
uint16 Debug_Timer_ReadCounter(void) ;
void Debug_Timer_WriteCounter(uint16 counter) \
;
uint16 Debug_Timer_ReadCapture(void) ;
void Debug_Timer_SoftwareCapture(void) ;
#if(!Debug_Timer_UsingFixedFunction) /* UDB Prototypes */
#if (Debug_Timer_SoftwareCaptureMode)
void Debug_Timer_SetCaptureMode(uint8 captureMode) ;
#endif /* (!Debug_Timer_UsingFixedFunction) */
#if (Debug_Timer_SoftwareTriggerMode)
void Debug_Timer_SetTriggerMode(uint8 triggerMode) ;
#endif /* (Debug_Timer_SoftwareTriggerMode) */
#if (Debug_Timer_EnableTriggerMode)
void Debug_Timer_EnableTrigger(void) ;
void Debug_Timer_DisableTrigger(void) ;
#endif /* (Debug_Timer_EnableTriggerMode) */
#if(Debug_Timer_InterruptOnCaptureCount)
#if(!Debug_Timer_ControlRegRemoved)
void Debug_Timer_SetInterruptCount(uint8 interruptCount) \
;
#endif /* (!Debug_Timer_ControlRegRemoved) */
#endif /* (Debug_Timer_InterruptOnCaptureCount) */
#if (Debug_Timer_UsingHWCaptureCounter)
void Debug_Timer_SetCaptureCount(uint8 captureCount) \
;
uint8 Debug_Timer_ReadCaptureCount(void) ;
#endif /* (Debug_Timer_UsingHWCaptureCounter) */
void Debug_Timer_ClearFIFO(void) ;
#endif /* UDB Prototypes */
/* Sleep Retention APIs */
void Debug_Timer_Init(void) ;
void Debug_Timer_Enable(void) ;
void Debug_Timer_SaveConfig(void) ;
void Debug_Timer_RestoreConfig(void) ;
void Debug_Timer_Sleep(void) ;
void Debug_Timer_Wakeup(void) ;
/***************************************
* Enumerated Types and Parameters
***************************************/
/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */
#define Debug_Timer__B_TIMER__CM_NONE 0
#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1
#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2
#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3
#define Debug_Timer__B_TIMER__CM_SOFTWARE 4
/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */
#define Debug_Timer__B_TIMER__TM_NONE 0x00u
#define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u
#define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u
#define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu
#define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u
/***************************************
* Initialial Parameter Constants
***************************************/
#define Debug_Timer_INIT_PERIOD 31999u
#define Debug_Timer_INIT_CAPTURE_MODE ((uint8)((uint8)0u << Debug_Timer_CTRL_CAP_MODE_SHIFT))
#define Debug_Timer_INIT_TRIGGER_MODE ((uint8)((uint8)0u << Debug_Timer_CTRL_TRIG_MODE_SHIFT))
#if (Debug_Timer_UsingFixedFunction)
#define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \
((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)))
#else
#define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \
((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)) | \
((uint8)((uint8)0 << Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT)))
#endif /* (Debug_Timer_UsingFixedFunction) */
#define Debug_Timer_INIT_CAPTURE_COUNT (2u)
#define Debug_Timer_INIT_INT_CAPTURE_COUNT ((uint8)((uint8)(1u - 1u) << Debug_Timer_CTRL_INTCNT_SHIFT))
/***************************************
* Registers
***************************************/
#if (Debug_Timer_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */
/***************************************
* Fixed Function Registers
***************************************/
#define Debug_Timer_STATUS (*(reg8 *) Debug_Timer_TimerHW__SR0 )
/* In Fixed Function Block Status and Mask are the same register */
#define Debug_Timer_STATUS_MASK (*(reg8 *) Debug_Timer_TimerHW__SR0 )
#define Debug_Timer_CONTROL (*(reg8 *) Debug_Timer_TimerHW__CFG0)
#define Debug_Timer_CONTROL2 (*(reg8 *) Debug_Timer_TimerHW__CFG1)
#define Debug_Timer_CONTROL2_PTR ( (reg8 *) Debug_Timer_TimerHW__CFG1)
#define Debug_Timer_RT1 (*(reg8 *) Debug_Timer_TimerHW__RT1)
#define Debug_Timer_RT1_PTR ( (reg8 *) Debug_Timer_TimerHW__RT1)
#if (CY_PSOC3 || CY_PSOC5LP)
#define Debug_Timer_CONTROL3 (*(reg8 *) Debug_Timer_TimerHW__CFG2)
#define Debug_Timer_CONTROL3_PTR ( (reg8 *) Debug_Timer_TimerHW__CFG2)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#define Debug_Timer_GLOBAL_ENABLE (*(reg8 *) Debug_Timer_TimerHW__PM_ACT_CFG)
#define Debug_Timer_GLOBAL_STBY_ENABLE (*(reg8 *) Debug_Timer_TimerHW__PM_STBY_CFG)
#define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerHW__CAP0 )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__CAP0 )
#define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerHW__PER0 )
#define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__PER0 )
#define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerHW__CNT_CMP0 )
#define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__CNT_CMP0 )
/***************************************
* Register Constants
***************************************/
/* Fixed Function Block Chosen */
#define Debug_Timer_BLOCK_EN_MASK Debug_Timer_TimerHW__PM_ACT_MSK
#define Debug_Timer_BLOCK_STBY_EN_MASK Debug_Timer_TimerHW__PM_STBY_MSK
/* Control Register Bit Locations */
/* Interrupt Count - Not valid for Fixed Function Block */
#define Debug_Timer_CTRL_INTCNT_SHIFT 0x00u
/* Trigger Polarity - Not valid for Fixed Function Block */
#define Debug_Timer_CTRL_TRIG_MODE_SHIFT 0x00u
/* Trigger Enable - Not valid for Fixed Function Block */
#define Debug_Timer_CTRL_TRIG_EN_SHIFT 0x00u
/* Capture Polarity - Not valid for Fixed Function Block */
#define Debug_Timer_CTRL_CAP_MODE_SHIFT 0x00u
/* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */
#define Debug_Timer_CTRL_ENABLE_SHIFT 0x00u
/* Control Register Bit Masks */
#define Debug_Timer_CTRL_ENABLE ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT))
/* Control2 Register Bit Masks */
/* As defined in Register Map, Part of the TMRX_CFG1 register */
#define Debug_Timer_CTRL2_IRQ_SEL_SHIFT 0x00u
#define Debug_Timer_CTRL2_IRQ_SEL ((uint8)((uint8)0x01u << Debug_Timer_CTRL2_IRQ_SEL_SHIFT))
#if (CY_PSOC5A)
/* Use CFG1 Mode bits to set run mode */
/* As defined by Verilog Implementation */
#define Debug_Timer_CTRL_MODE_SHIFT 0x01u
#define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Control3 Register Bit Locations */
#define Debug_Timer_CTRL_RCOD_SHIFT 0x02u
#define Debug_Timer_CTRL_ENBL_SHIFT 0x00u
#define Debug_Timer_CTRL_MODE_SHIFT 0x00u
/* Control3 Register Bit Masks */
#define Debug_Timer_CTRL_RCOD_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */
#define Debug_Timer_CTRL_ENBL_MASK ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */
#define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_MODE_SHIFT)) /* Run mode bit mask */
#define Debug_Timer_CTRL_RCOD ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT))
#define Debug_Timer_CTRL_ENBL ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT))
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */
#define Debug_Timer_RT1_SHIFT 0x04u
/* Sync TC and CMP bit masks */
#define Debug_Timer_RT1_MASK ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT))
#define Debug_Timer_SYNC ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT))
#define Debug_Timer_SYNCDSI_SHIFT 0x00u
/* Sync all DSI inputs with Mask */
#define Debug_Timer_SYNCDSI_MASK ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT))
/* Sync all DSI inputs */
#define Debug_Timer_SYNCDSI_EN ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT))
#define Debug_Timer_CTRL_MODE_PULSEWIDTH ((uint8)((uint8)0x01u << Debug_Timer_CTRL_MODE_SHIFT))
#define Debug_Timer_CTRL_MODE_PERIOD ((uint8)((uint8)0x02u << Debug_Timer_CTRL_MODE_SHIFT))
#define Debug_Timer_CTRL_MODE_CONTINUOUS ((uint8)((uint8)0x00u << Debug_Timer_CTRL_MODE_SHIFT))
/* Status Register Bit Locations */
/* As defined in Register Map, part of TMRX_SR0 register */
#define Debug_Timer_STATUS_TC_SHIFT 0x07u
/* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
#define Debug_Timer_STATUS_CAPTURE_SHIFT 0x06u
/* As defined in Register Map, part of TMRX_SR0 register */
#define Debug_Timer_STATUS_TC_INT_MASK_SHIFT (Debug_Timer_STATUS_TC_SHIFT - 0x04u)
/* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
#define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT (Debug_Timer_STATUS_CAPTURE_SHIFT - 0x04u)
/* Status Register Bit Masks */
#define Debug_Timer_STATUS_TC ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
#define Debug_Timer_STATUS_CAPTURE ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
/* Interrupt Enable Bit-Mask for interrupt on TC */
#define Debug_Timer_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT))
/* Interrupt Enable Bit-Mask for interrupt on Capture */
#define Debug_Timer_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT))
#else /* UDB Registers and Register Constants */
/***************************************
* UDB Registers
***************************************/
#define Debug_Timer_STATUS (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_REG )
#define Debug_Timer_STATUS_MASK (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__MASK_REG)
#define Debug_Timer_STATUS_AUX_CTRL (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG)
#define Debug_Timer_CONTROL (* (reg8 *) Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG )
#if(Debug_Timer_Resolution <= 8u) /* 8-bit Timer */
#define Debug_Timer_CAPTURE_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_PERIOD_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_PERIOD_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_COUNTER_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#define Debug_Timer_COUNTER_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#elif(Debug_Timer_Resolution <= 16u) /* 8-bit Timer */
#if(CY_PSOC3) /* 8-bit addres space */
#define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#else /* 16-bit address space */
#define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
#define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
#define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
#define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
#define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
#endif /* CY_PSOC3 */
#elif(Debug_Timer_Resolution <= 24u)/* 24-bit Timer */
#define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#else /* 32-bit Timer */
#if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */
#define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#else /* 32-bit address space */
#define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
#define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
#define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
#define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
#define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
#endif /* CY_PSOC3 || CY_PSOC5 */
#endif
#if (Debug_Timer_UsingHWCaptureCounter)
#define Debug_Timer_CAP_COUNT (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
#define Debug_Timer_CAP_COUNT_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
#define Debug_Timer_CAPTURE_COUNT_CTRL (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
#define Debug_Timer_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
#endif /* (Debug_Timer_UsingHWCaptureCounter) */
/***************************************
* Register Constants
***************************************/
/* Control Register Bit Locations */
#define Debug_Timer_CTRL_INTCNT_SHIFT 0x00u /* As defined by Verilog Implementation */
#define Debug_Timer_CTRL_TRIG_MODE_SHIFT 0x02u /* As defined by Verilog Implementation */
#define Debug_Timer_CTRL_TRIG_EN_SHIFT 0x04u /* As defined by Verilog Implementation */
#define Debug_Timer_CTRL_CAP_MODE_SHIFT 0x05u /* As defined by Verilog Implementation */
#define Debug_Timer_CTRL_ENABLE_SHIFT 0x07u /* As defined by Verilog Implementation */
/* Control Register Bit Masks */
#define Debug_Timer_CTRL_INTCNT_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_INTCNT_SHIFT))
#define Debug_Timer_CTRL_TRIG_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_TRIG_MODE_SHIFT))
#define Debug_Timer_CTRL_TRIG_EN ((uint8)((uint8)0x01u << Debug_Timer_CTRL_TRIG_EN_SHIFT))
#define Debug_Timer_CTRL_CAP_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_CAP_MODE_SHIFT))
#define Debug_Timer_CTRL_ENABLE ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT))
/* Bit Counter (7-bit) Control Register Bit Definitions */
/* As defined by the Register map for the AUX Control Register */
#define Debug_Timer_CNTR_ENABLE 0x20u
/* Status Register Bit Locations */
#define Debug_Timer_STATUS_TC_SHIFT 0x00u /* As defined by Verilog Implementation */
#define Debug_Timer_STATUS_CAPTURE_SHIFT 0x01u /* As defined by Verilog Implementation */
#define Debug_Timer_STATUS_TC_INT_MASK_SHIFT Debug_Timer_STATUS_TC_SHIFT
#define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT Debug_Timer_STATUS_CAPTURE_SHIFT
#define Debug_Timer_STATUS_FIFOFULL_SHIFT 0x02u /* As defined by Verilog Implementation */
#define Debug_Timer_STATUS_FIFONEMP_SHIFT 0x03u /* As defined by Verilog Implementation */
#define Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT Debug_Timer_STATUS_FIFOFULL_SHIFT
/* Status Register Bit Masks */
/* Sticky TC Event Bit-Mask */
#define Debug_Timer_STATUS_TC ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
/* Sticky Capture Event Bit-Mask */
#define Debug_Timer_STATUS_CAPTURE ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
/* Interrupt Enable Bit-Mask */
#define Debug_Timer_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
/* Interrupt Enable Bit-Mask */
#define Debug_Timer_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
/* NOT-Sticky FIFO Full Bit-Mask */
#define Debug_Timer_STATUS_FIFOFULL ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT))
/* NOT-Sticky FIFO Not Empty Bit-Mask */
#define Debug_Timer_STATUS_FIFONEMP ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFONEMP_SHIFT))
/* Interrupt Enable Bit-Mask */
#define Debug_Timer_STATUS_FIFOFULL_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT))
#define Debug_Timer_STATUS_ACTL_INT_EN 0x10u /* As defined for the ACTL Register */
/* Datapath Auxillary Control Register definitions */
#define Debug_Timer_AUX_CTRL_FIFO0_CLR 0x01u /* As defined by Register map */
#define Debug_Timer_AUX_CTRL_FIFO1_CLR 0x02u /* As defined by Register map */
#define Debug_Timer_AUX_CTRL_FIFO0_LVL 0x04u /* As defined by Register map */
#define Debug_Timer_AUX_CTRL_FIFO1_LVL 0x08u /* As defined by Register map */
#define Debug_Timer_STATUS_ACTL_INT_EN_MASK 0x10u /* As defined for the ACTL Register */
#endif /* Implementation Specific Registers and Register Constants */
#endif /* CY_Timer_v2_30_Debug_Timer_H */
/* [] END OF FILE */

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software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.c Normal file
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/*******************************************************************************
* File Name: Debug_Timer_Interrupt.c
* Version 1.70
*
* Description:
* API for controlling the state of an interrupt.
*
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include <CyLib.h>
#include <Debug_Timer_Interrupt.h>
#if !defined(Debug_Timer_Interrupt__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Place your includes, defines and code here
********************************************************************************/
/* `#START Debug_Timer_Interrupt_intc` */
/* `#END` */
#ifndef CYINT_IRQ_BASE
#define CYINT_IRQ_BASE 16
#endif /* CYINT_IRQ_BASE */
#ifndef CYINT_VECT_TABLE
#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
#endif /* CYINT_VECT_TABLE */
/* Declared in startup, used to set unused interrupts to. */
CY_ISR_PROTO(IntDefaultHandler);
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_Start
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_Start(void)
{
/* For all we know the interrupt is active. */
Debug_Timer_Interrupt_Disable();
/* Set the ISR to point to the Debug_Timer_Interrupt Interrupt. */
Debug_Timer_Interrupt_SetVector(&Debug_Timer_Interrupt_Interrupt);
/* Set the priority. */
Debug_Timer_Interrupt_SetPriority((uint8)Debug_Timer_Interrupt_INTC_PRIOR_NUMBER);
/* Enable it. */
Debug_Timer_Interrupt_Enable();
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_StartEx
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_StartEx(cyisraddress address)
{
/* For all we know the interrupt is active. */
Debug_Timer_Interrupt_Disable();
/* Set the ISR to point to the Debug_Timer_Interrupt Interrupt. */
Debug_Timer_Interrupt_SetVector(address);
/* Set the priority. */
Debug_Timer_Interrupt_SetPriority((uint8)Debug_Timer_Interrupt_INTC_PRIOR_NUMBER);
/* Enable it. */
Debug_Timer_Interrupt_Enable();
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_Stop
********************************************************************************
*
* Summary:
* Disables and removes the interrupt.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_Stop(void)
{
/* Disable this interrupt. */
Debug_Timer_Interrupt_Disable();
/* Set the ISR to point to the passive one. */
Debug_Timer_Interrupt_SetVector(&IntDefaultHandler);
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_Interrupt
********************************************************************************
*
* Summary:
* The default Interrupt Service Routine for Debug_Timer_Interrupt.
*
* Add custom code between the coments to keep the next version of this file
* from over writting your code.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
CY_ISR(Debug_Timer_Interrupt_Interrupt)
{
/* Place your Interrupt code here. */
/* `#START Debug_Timer_Interrupt_Interrupt` */
/* `#END` */
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_SetVector
********************************************************************************
*
* Summary:
* Change the ISR vector for the Interrupt. Note calling Debug_Timer_Interrupt_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use Debug_Timer_Interrupt_StartEx instead.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_SetVector(cyisraddress address)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
ramVectorTable[CYINT_IRQ_BASE + (uint32)Debug_Timer_Interrupt__INTC_NUMBER] = address;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_GetVector
********************************************************************************
*
* Summary:
* Gets the "address" of the current ISR vector for the Interrupt.
*
* Parameters:
* None
*
* Return:
* Address of the ISR in the interrupt vector table.
*
*******************************************************************************/
cyisraddress Debug_Timer_Interrupt_GetVector(void)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
return ramVectorTable[CYINT_IRQ_BASE + (uint32)Debug_Timer_Interrupt__INTC_NUMBER];
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_SetPriority
********************************************************************************
*
* Summary:
* Sets the Priority of the Interrupt. Note calling Debug_Timer_Interrupt_Start
* or Debug_Timer_Interrupt_StartEx will override any effect this method
* would have had. This method should only be called after
* Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called. To set
* the initial priority for the component use the cydwr file in the tool.
*
* Parameters:
* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_SetPriority(uint8 priority)
{
*Debug_Timer_Interrupt_INTC_PRIOR = priority << 5;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_GetPriority
********************************************************************************
*
* Summary:
* Gets the Priority of the Interrupt.
*
* Parameters:
* None
*
* Return:
* Priority of the interrupt. 0 - 7, 0 being the highest.
*
*******************************************************************************/
uint8 Debug_Timer_Interrupt_GetPriority(void)
{
uint8 priority;
priority = *Debug_Timer_Interrupt_INTC_PRIOR >> 5;
return priority;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_Enable
********************************************************************************
*
* Summary:
* Enables the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_Enable(void)
{
/* Enable the general interrupt. */
*Debug_Timer_Interrupt_INTC_SET_EN = Debug_Timer_Interrupt__INTC_MASK;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_GetState
********************************************************************************
*
* Summary:
* Gets the state (enabled, disabled) of the Interrupt.
*
* Parameters:
* None
*
* Return:
* 1 if enabled, 0 if disabled.
*
*******************************************************************************/
uint8 Debug_Timer_Interrupt_GetState(void)
{
/* Get the state of the general interrupt. */
return ((*Debug_Timer_Interrupt_INTC_SET_EN & (uint32)Debug_Timer_Interrupt__INTC_MASK) != 0u) ? 1u:0u;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_Disable
********************************************************************************
*
* Summary:
* Disables the Interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_Disable(void)
{
/* Disable the general interrupt. */
*Debug_Timer_Interrupt_INTC_CLR_EN = Debug_Timer_Interrupt__INTC_MASK;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_SetPending
********************************************************************************
*
* Summary:
* Causes the Interrupt to enter the pending state, a software method of
* generating the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_SetPending(void)
{
*Debug_Timer_Interrupt_INTC_SET_PD = Debug_Timer_Interrupt__INTC_MASK;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_ClearPending
********************************************************************************
*
* Summary:
* Clears a pending interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_ClearPending(void)
{
*Debug_Timer_Interrupt_INTC_CLR_PD = Debug_Timer_Interrupt__INTC_MASK;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

70
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.h Normal file
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/*******************************************************************************
* File Name: Debug_Timer_Interrupt.h
* Version 1.70
*
* Description:
* Provides the function definitions for the Interrupt Controller.
*
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_ISR_Debug_Timer_Interrupt_H)
#define CY_ISR_Debug_Timer_Interrupt_H
#include <cytypes.h>
#include <cyfitter.h>
/* Interrupt Controller API. */
void Debug_Timer_Interrupt_Start(void);
void Debug_Timer_Interrupt_StartEx(cyisraddress address);
void Debug_Timer_Interrupt_Stop(void);
CY_ISR_PROTO(Debug_Timer_Interrupt_Interrupt);
void Debug_Timer_Interrupt_SetVector(cyisraddress address);
cyisraddress Debug_Timer_Interrupt_GetVector(void);
void Debug_Timer_Interrupt_SetPriority(uint8 priority);
uint8 Debug_Timer_Interrupt_GetPriority(void);
void Debug_Timer_Interrupt_Enable(void);
uint8 Debug_Timer_Interrupt_GetState(void);
void Debug_Timer_Interrupt_Disable(void);
void Debug_Timer_Interrupt_SetPending(void);
void Debug_Timer_Interrupt_ClearPending(void);
/* Interrupt Controller Constants */
/* Address of the INTC.VECT[x] register that contains the Address of the Debug_Timer_Interrupt ISR. */
#define Debug_Timer_Interrupt_INTC_VECTOR ((reg32 *) Debug_Timer_Interrupt__INTC_VECT)
/* Address of the Debug_Timer_Interrupt ISR priority. */
#define Debug_Timer_Interrupt_INTC_PRIOR ((reg8 *) Debug_Timer_Interrupt__INTC_PRIOR_REG)
/* Priority of the Debug_Timer_Interrupt interrupt. */
#define Debug_Timer_Interrupt_INTC_PRIOR_NUMBER Debug_Timer_Interrupt__INTC_PRIOR_NUM
/* Address of the INTC.SET_EN[x] byte to bit enable Debug_Timer_Interrupt interrupt. */
#define Debug_Timer_Interrupt_INTC_SET_EN ((reg32 *) Debug_Timer_Interrupt__INTC_SET_EN_REG)
/* Address of the INTC.CLR_EN[x] register to bit clear the Debug_Timer_Interrupt interrupt. */
#define Debug_Timer_Interrupt_INTC_CLR_EN ((reg32 *) Debug_Timer_Interrupt__INTC_CLR_EN_REG)
/* Address of the INTC.SET_PD[x] register to set the Debug_Timer_Interrupt interrupt state to pending. */
#define Debug_Timer_Interrupt_INTC_SET_PD ((reg32 *) Debug_Timer_Interrupt__INTC_SET_PD_REG)
/* Address of the INTC.CLR_PD[x] register to clear the Debug_Timer_Interrupt interrupt. */
#define Debug_Timer_Interrupt_INTC_CLR_PD ((reg32 *) Debug_Timer_Interrupt__INTC_CLR_PD_REG)
#endif /* CY_ISR_Debug_Timer_Interrupt_H */
/* [] END OF FILE */

194
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c Normal file
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/*******************************************************************************
* File Name: Debug_Timer_PM.c
* Version 2.50
*
* Description:
* This file provides the power management source code to API for the
* Timer.
*
* Note:
* None
*
*******************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include "Debug_Timer.h"
static Debug_Timer_backupStruct Debug_Timer_backup;
/*******************************************************************************
* Function Name: Debug_Timer_SaveConfig
********************************************************************************
*
* Summary:
* Save the current user configuration
*
* Parameters:
* void
*
* Return:
* void
*
* Global variables:
* Debug_Timer_backup: Variables of this global structure are modified to
* store the values of non retention configuration registers when Sleep() API is
* called.
*
*******************************************************************************/
void Debug_Timer_SaveConfig(void)
{
#if (!Debug_Timer_UsingFixedFunction)
/* Backup the UDB non-rentention registers for CY_UDB_V0 */
#if (CY_UDB_V0)
Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
Debug_Timer_backup.TimerPeriod = Debug_Timer_ReadPeriod();
Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
#if (Debug_Timer_UsingHWCaptureCounter)
Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
#endif /* Backup the UDB non-rentention register capture counter for CY_UDB_V0 */
#endif /* Backup the UDB non-rentention registers for CY_UDB_V0 */
#if (CY_UDB_V1)
Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
#if (Debug_Timer_UsingHWCaptureCounter)
Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
#endif /* Back Up capture counter register */
#endif /* Backup non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
#if(!Debug_Timer_ControlRegRemoved)
Debug_Timer_backup.TimerControlRegister = Debug_Timer_ReadControlRegister();
#endif /* Backup the enable state of the Timer component */
#endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */
}
/*******************************************************************************
* Function Name: Debug_Timer_RestoreConfig
********************************************************************************
*
* Summary:
* Restores the current user configuration.
*
* Parameters:
* void
*
* Return:
* void
*
* Global variables:
* Debug_Timer_backup: Variables of this global structure are used to
* restore the values of non retention registers on wakeup from sleep mode.
*
*******************************************************************************/
void Debug_Timer_RestoreConfig(void)
{
#if (!Debug_Timer_UsingFixedFunction)
/* Restore the UDB non-rentention registers for CY_UDB_V0 */
#if (CY_UDB_V0)
/* Interrupt State Backup for Critical Region*/
uint8 Debug_Timer_interruptState;
Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
Debug_Timer_WritePeriod(Debug_Timer_backup.TimerPeriod);
/* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
/* Enter Critical Region*/
Debug_Timer_interruptState = CyEnterCriticalSection();
/* Use the interrupt output of the status register for IRQ output */
Debug_Timer_STATUS_AUX_CTRL |= Debug_Timer_STATUS_ACTL_INT_EN_MASK;
/* Exit Critical Region*/
CyExitCriticalSection(Debug_Timer_interruptState);
Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
#if (Debug_Timer_UsingHWCaptureCounter)
Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
#endif /* Restore the UDB non-rentention register capture counter for CY_UDB_V0 */
#endif /* Restore the UDB non-rentention registers for CY_UDB_V0 */
#if (CY_UDB_V1)
Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
#if (Debug_Timer_UsingHWCaptureCounter)
Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
#endif /* Restore Capture counter register*/
#endif /* Restore up non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
#if(!Debug_Timer_ControlRegRemoved)
Debug_Timer_WriteControlRegister(Debug_Timer_backup.TimerControlRegister);
#endif /* Restore the enable state of the Timer component */
#endif /* Restore non retention registers in the UDB implementation only */
}
/*******************************************************************************
* Function Name: Debug_Timer_Sleep
********************************************************************************
*
* Summary:
* Stop and Save the user configuration
*
* Parameters:
* void
*
* Return:
* void
*
* Global variables:
* Debug_Timer_backup.TimerEnableState: Is modified depending on the
* enable state of the block before entering sleep mode.
*
*******************************************************************************/
void Debug_Timer_Sleep(void)
{
#if(!Debug_Timer_ControlRegRemoved)
/* Save Counter's enable state */
if(Debug_Timer_CTRL_ENABLE == (Debug_Timer_CONTROL & Debug_Timer_CTRL_ENABLE))
{
/* Timer is enabled */
Debug_Timer_backup.TimerEnableState = 1u;
}
else
{
/* Timer is disabled */
Debug_Timer_backup.TimerEnableState = 0u;
}
#endif /* Back up enable state from the Timer control register */
Debug_Timer_Stop();
Debug_Timer_SaveConfig();
}
/*******************************************************************************
* Function Name: Debug_Timer_Wakeup
********************************************************************************
*
* Summary:
* Restores and enables the user configuration
*
* Parameters:
* void
*
* Return:
* void
*
* Global variables:
* Debug_Timer_backup.enableState: Is used to restore the enable state of
* block on wakeup from sleep mode.
*
*******************************************************************************/
void Debug_Timer_Wakeup(void)
{
Debug_Timer_RestoreConfig();
#if(!Debug_Timer_ControlRegRemoved)
if(Debug_Timer_backup.TimerEnableState == 1u)
{ /* Enable Timer's operation */
Debug_Timer_Enable();
} /* Do nothing if Timer was disabled before */
#endif /* Remove this code section if Control register is removed */
}
/* [] END OF FILE */

63
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c Normal file
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@ -0,0 +1,63 @@
/*******************************************************************************
* File Name: SCSI_CTL_PHASE.c
* Version 1.70
*
* Description:
* This file contains API to enable firmware control of a Control Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_CTL_PHASE.h"
#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Function Name: SCSI_CTL_PHASE_Write
********************************************************************************
*
* Summary:
* Write a byte to the Control Register.
*
* Parameters:
* control: The value to be assigned to the Control Register.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_CTL_PHASE_Write(uint8 control)
{
SCSI_CTL_PHASE_Control = control;
}
/*******************************************************************************
* Function Name: SCSI_CTL_PHASE_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Control Register.
*
* Parameters:
* None.
*
* Return:
* Returns the current value in the Control Register.
*
*******************************************************************************/
uint8 SCSI_CTL_PHASE_Read(void)
{
return SCSI_CTL_PHASE_Control;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

42
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h Normal file
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@ -0,0 +1,42 @@
/*******************************************************************************
* File Name: SCSI_CTL_PHASE.h
* Version 1.70
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */
#define CY_CONTROL_REG_SCSI_CTL_PHASE_H
#include "cytypes.h"
/***************************************
* Function Prototypes
***************************************/
void SCSI_CTL_PHASE_Write(uint8 control) ;
uint8 SCSI_CTL_PHASE_Read(void) ;
/***************************************
* Registers
***************************************/
/* Control Register */
#define SCSI_CTL_PHASE_Control (* (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
#define SCSI_CTL_PHASE_Control_PTR ( (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
#endif /* End CY_CONTROL_REG_SCSI_CTL_PHASE_H */
/* [] END OF FILE */

63
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c Normal file
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@ -0,0 +1,63 @@
/*******************************************************************************
* File Name: SCSI_Out_Bits.c
* Version 1.70
*
* Description:
* This file contains API to enable firmware control of a Control Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_Out_Bits.h"
#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Function Name: SCSI_Out_Bits_Write
********************************************************************************
*
* Summary:
* Write a byte to the Control Register.
*
* Parameters:
* control: The value to be assigned to the Control Register.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Out_Bits_Write(uint8 control)
{
SCSI_Out_Bits_Control = control;
}
/*******************************************************************************
* Function Name: SCSI_Out_Bits_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Control Register.
*
* Parameters:
* None.
*
* Return:
* Returns the current value in the Control Register.
*
*******************************************************************************/
uint8 SCSI_Out_Bits_Read(void)
{
return SCSI_Out_Bits_Control;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

42
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h Normal file
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@ -0,0 +1,42 @@
/*******************************************************************************
* File Name: SCSI_Out_Bits.h
* Version 1.70
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CONTROL_REG_SCSI_Out_Bits_H) /* CY_CONTROL_REG_SCSI_Out_Bits_H */
#define CY_CONTROL_REG_SCSI_Out_Bits_H
#include "cytypes.h"
/***************************************
* Function Prototypes
***************************************/
void SCSI_Out_Bits_Write(uint8 control) ;
uint8 SCSI_Out_Bits_Read(void) ;
/***************************************
* Registers
***************************************/
/* Control Register */
#define SCSI_Out_Bits_Control (* (reg8 *) SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG )
#define SCSI_Out_Bits_Control_PTR ( (reg8 *) SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG )
#endif /* End CY_CONTROL_REG_SCSI_Out_Bits_H */
/* [] END OF FILE */

63
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c Normal file
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@ -0,0 +1,63 @@
/*******************************************************************************
* File Name: SCSI_Out_Ctl.c
* Version 1.70
*
* Description:
* This file contains API to enable firmware control of a Control Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_Out_Ctl.h"
#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Function Name: SCSI_Out_Ctl_Write
********************************************************************************
*
* Summary:
* Write a byte to the Control Register.
*
* Parameters:
* control: The value to be assigned to the Control Register.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Out_Ctl_Write(uint8 control)
{
SCSI_Out_Ctl_Control = control;
}
/*******************************************************************************
* Function Name: SCSI_Out_Ctl_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Control Register.
*
* Parameters:
* None.
*
* Return:
* Returns the current value in the Control Register.
*
*******************************************************************************/
uint8 SCSI_Out_Ctl_Read(void)
{
return SCSI_Out_Ctl_Control;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

42
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h Normal file
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@ -0,0 +1,42 @@
/*******************************************************************************
* File Name: SCSI_Out_Ctl.h
* Version 1.70
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CONTROL_REG_SCSI_Out_Ctl_H) /* CY_CONTROL_REG_SCSI_Out_Ctl_H */
#define CY_CONTROL_REG_SCSI_Out_Ctl_H
#include "cytypes.h"
/***************************************
* Function Prototypes
***************************************/
void SCSI_Out_Ctl_Write(uint8 control) ;
uint8 SCSI_Out_Ctl_Read(void) ;
/***************************************
* Registers
***************************************/
/* Control Register */
#define SCSI_Out_Ctl_Control (* (reg8 *) SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG )
#define SCSI_Out_Ctl_Control_PTR ( (reg8 *) SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG )
#endif /* End CY_CONTROL_REG_SCSI_Out_Ctl_H */
/* [] END OF FILE */

4
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h Executable file → Normal file
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@ -41,9 +41,9 @@
#define SCSI_Out_BSY SCSI_Out__BSY__PC
#define SCSI_Out_ACK SCSI_Out__ACK__PC
#define SCSI_Out_RST SCSI_Out__RST__PC
#define SCSI_Out_MSG SCSI_Out__MSG__PC
#define SCSI_Out_MSG_raw SCSI_Out__MSG_raw__PC
#define SCSI_Out_SEL SCSI_Out__SEL__PC
#define SCSI_Out_CD SCSI_Out__CD__PC
#define SCSI_Out_CD_raw SCSI_Out__CD_raw__PC
#define SCSI_Out_REQ SCSI_Out__REQ__PC
#define SCSI_Out_IO_raw SCSI_Out__IO_raw__PC

356
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.c Normal file
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/*******************************************************************************
* File Name: SCSI_RX_DMA_COMPLETE.c
* Version 1.70
*
* Description:
* API for controlling the state of an interrupt.
*
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include <CyLib.h>
#include <SCSI_RX_DMA_COMPLETE.h>
#if !defined(SCSI_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Place your includes, defines and code here
********************************************************************************/
/* `#START SCSI_RX_DMA_COMPLETE_intc` */
/* `#END` */
#ifndef CYINT_IRQ_BASE
#define CYINT_IRQ_BASE 16
#endif /* CYINT_IRQ_BASE */
#ifndef CYINT_VECT_TABLE
#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
#endif /* CYINT_VECT_TABLE */
/* Declared in startup, used to set unused interrupts to. */
CY_ISR_PROTO(IntDefaultHandler);
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_Start
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RX_DMA_COMPLETE_Start(void)
{
/* For all we know the interrupt is active. */
SCSI_RX_DMA_COMPLETE_Disable();
/* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */
SCSI_RX_DMA_COMPLETE_SetVector(&SCSI_RX_DMA_COMPLETE_Interrupt);
/* Set the priority. */
SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
/* Enable it. */
SCSI_RX_DMA_COMPLETE_Enable();
}
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_StartEx
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address)
{
/* For all we know the interrupt is active. */
SCSI_RX_DMA_COMPLETE_Disable();
/* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */
SCSI_RX_DMA_COMPLETE_SetVector(address);
/* Set the priority. */
SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
/* Enable it. */
SCSI_RX_DMA_COMPLETE_Enable();
}
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_Stop
********************************************************************************
*
* Summary:
* Disables and removes the interrupt.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RX_DMA_COMPLETE_Stop(void)
{
/* Disable this interrupt. */
SCSI_RX_DMA_COMPLETE_Disable();
/* Set the ISR to point to the passive one. */
SCSI_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
}
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_Interrupt
********************************************************************************
*
* Summary:
* The default Interrupt Service Routine for SCSI_RX_DMA_COMPLETE.
*
* Add custom code between the coments to keep the next version of this file
* from over writting your code.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
CY_ISR(SCSI_RX_DMA_COMPLETE_Interrupt)
{
/* Place your Interrupt code here. */
/* `#START SCSI_RX_DMA_COMPLETE_Interrupt` */
/* `#END` */
}
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_SetVector
********************************************************************************
*
* Summary:
* Change the ISR vector for the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_RX_DMA_COMPLETE_StartEx instead.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER] = address;
}
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_GetVector
********************************************************************************
*
* Summary:
* Gets the "address" of the current ISR vector for the Interrupt.
*
* Parameters:
* None
*
* Return:
* Address of the ISR in the interrupt vector table.
*
*******************************************************************************/
cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER];
}
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_SetPriority
********************************************************************************
*
* Summary:
* Sets the Priority of the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
* or SCSI_RX_DMA_COMPLETE_StartEx will override any effect this method
* would have had. This method should only be called after
* SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. To set
* the initial priority for the component use the cydwr file in the tool.
*
* Parameters:
* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority)
{
*SCSI_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
}
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_GetPriority
********************************************************************************
*
* Summary:
* Gets the Priority of the Interrupt.
*
* Parameters:
* None
*
* Return:
* Priority of the interrupt. 0 - 7, 0 being the highest.
*
*******************************************************************************/
uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void)
{
uint8 priority;
priority = *SCSI_RX_DMA_COMPLETE_INTC_PRIOR >> 5;
return priority;
}
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_Enable
********************************************************************************
*
* Summary:
* Enables the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RX_DMA_COMPLETE_Enable(void)
{
/* Enable the general interrupt. */
*SCSI_RX_DMA_COMPLETE_INTC_SET_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_GetState
********************************************************************************
*
* Summary:
* Gets the state (enabled, disabled) of the Interrupt.
*
* Parameters:
* None
*
* Return:
* 1 if enabled, 0 if disabled.
*
*******************************************************************************/
uint8 SCSI_RX_DMA_COMPLETE_GetState(void)
{
/* Get the state of the general interrupt. */
return ((*SCSI_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
}
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_Disable
********************************************************************************
*
* Summary:
* Disables the Interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RX_DMA_COMPLETE_Disable(void)
{
/* Disable the general interrupt. */
*SCSI_RX_DMA_COMPLETE_INTC_CLR_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_SetPending
********************************************************************************
*
* Summary:
* Causes the Interrupt to enter the pending state, a software method of
* generating the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RX_DMA_COMPLETE_SetPending(void)
{
*SCSI_RX_DMA_COMPLETE_INTC_SET_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_RX_DMA_COMPLETE_ClearPending
********************************************************************************
*
* Summary:
* Clears a pending interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RX_DMA_COMPLETE_ClearPending(void)
{
*SCSI_RX_DMA_COMPLETE_INTC_CLR_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_RX_DMA_COMPLETE.h
* Version 1.70
*
* Description:
* Provides the function definitions for the Interrupt Controller.
*
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_ISR_SCSI_RX_DMA_COMPLETE_H)
#define CY_ISR_SCSI_RX_DMA_COMPLETE_H
#include <cytypes.h>
#include <cyfitter.h>
/* Interrupt Controller API. */
void SCSI_RX_DMA_COMPLETE_Start(void);
void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address);
void SCSI_RX_DMA_COMPLETE_Stop(void);
CY_ISR_PROTO(SCSI_RX_DMA_COMPLETE_Interrupt);
void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address);
cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void);
void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority);
uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void);
void SCSI_RX_DMA_COMPLETE_Enable(void);
uint8 SCSI_RX_DMA_COMPLETE_GetState(void);
void SCSI_RX_DMA_COMPLETE_Disable(void);
void SCSI_RX_DMA_COMPLETE_SetPending(void);
void SCSI_RX_DMA_COMPLETE_ClearPending(void);
/* Interrupt Controller Constants */
/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RX_DMA_COMPLETE ISR. */
#define SCSI_RX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_VECT)
/* Address of the SCSI_RX_DMA_COMPLETE ISR priority. */
#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG)
/* Priority of the SCSI_RX_DMA_COMPLETE interrupt. */
#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM
/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RX_DMA_COMPLETE interrupt. */
#define SCSI_RX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG)
/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RX_DMA_COMPLETE interrupt. */
#define SCSI_RX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG)
/* Address of the INTC.SET_PD[x] register to set the SCSI_RX_DMA_COMPLETE interrupt state to pending. */
#define SCSI_RX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG)
/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RX_DMA_COMPLETE interrupt. */
#define SCSI_RX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG)
#endif /* CY_ISR_SCSI_RX_DMA_COMPLETE_H */
/* [] END OF FILE */

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/***************************************************************************
* File Name: SCSI_RX_DMA_dma.c
* Version 1.70
*
* Description:
* Provides an API for the DMAC component. The API includes functions
* for the DMA controller, DMA channels and Transfer Descriptors.
*
*
* Note:
* This module requires the developer to finish or fill in the auto
* generated funcions and setup the dma channel and TD's.
*
********************************************************************************
* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include <CYLIB.H>
#include <CYDMAC.H>
#include <SCSI_RX_DMA_dma.H>
/****************************************************************************
*
* The following defines are available in Cyfitter.h
*
*
*
* SCSI_RX_DMA__DRQ_CTL_REG
*
*
* SCSI_RX_DMA__DRQ_NUMBER
*
* Number of TD's used by this channel.
* SCSI_RX_DMA__NUMBEROF_TDS
*
* Priority of this channel.
* SCSI_RX_DMA__PRIORITY
*
* True if SCSI_RX_DMA_TERMIN_SEL is used.
* SCSI_RX_DMA__TERMIN_EN
*
* TERMIN interrupt line to signal terminate.
* SCSI_RX_DMA__TERMIN_SEL
*
*
* True if SCSI_RX_DMA_TERMOUT0_SEL is used.
* SCSI_RX_DMA__TERMOUT0_EN
*
*
* TERMOUT0 interrupt line to signal completion.
* SCSI_RX_DMA__TERMOUT0_SEL
*
*
* True if SCSI_RX_DMA_TERMOUT1_SEL is used.
* SCSI_RX_DMA__TERMOUT1_EN
*
*
* TERMOUT1 interrupt line to signal completion.
* SCSI_RX_DMA__TERMOUT1_SEL
*
****************************************************************************/
/* Zero based index of SCSI_RX_DMA dma channel */
uint8 SCSI_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
/*********************************************************************
* Function Name: uint8 SCSI_RX_DMA_DmaInitalize
**********************************************************************
* Summary:
* Allocates and initialises a channel of the DMAC to be used by the
* caller.
*
* Parameters:
* BurstCount.
*
*
* ReqestPerBurst.
*
*
* UpperSrcAddress.
*
*
* UpperDestAddress.
*
*
* Return:
* The channel that can be used by the caller for DMA activity.
* DMA_INVALID_CHANNEL (0xFF) if there are no channels left.
*
*
*******************************************************************/
uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress)
{
/* Allocate a DMA channel. */
SCSI_RX_DMA_DmaHandle = (uint8)SCSI_RX_DMA__DRQ_NUMBER;
/* Configure the channel. */
(void)CyDmaChSetConfiguration(SCSI_RX_DMA_DmaHandle,
BurstCount,
ReqestPerBurst,
(uint8)SCSI_RX_DMA__TERMOUT0_SEL,
(uint8)SCSI_RX_DMA__TERMOUT1_SEL,
(uint8)SCSI_RX_DMA__TERMIN_SEL);
/* Set the extended address for the transfers */
(void)CyDmaChSetExtendedAddress(SCSI_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
/* Set the priority for this channel */
(void)CyDmaChPriority(SCSI_RX_DMA_DmaHandle, (uint8)SCSI_RX_DMA__PRIORITY);
return SCSI_RX_DMA_DmaHandle;
}
/*********************************************************************
* Function Name: void SCSI_RX_DMA_DmaRelease
**********************************************************************
* Summary:
* Frees the channel associated with SCSI_RX_DMA.
*
*
* Parameters:
* void.
*
*
*
* Return:
* void.
*
*******************************************************************/
void SCSI_RX_DMA_DmaRelease(void)
{
/* Disable the channel */
(void)CyDmaChDisable(SCSI_RX_DMA_DmaHandle);
}

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/******************************************************************************
* File Name: SCSI_RX_DMA_dma.h
* Version 1.70
*
* Description:
* Provides the function definitions for the DMA Controller.
*
*
********************************************************************************
* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#if !defined(CY_DMA_SCSI_RX_DMA_DMA_H__)
#define CY_DMA_SCSI_RX_DMA_DMA_H__
#include <CYDMAC.H>
#include <CYFITTER.H>
#define SCSI_RX_DMA__TD_TERMOUT_EN (((0 != SCSI_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
(SCSI_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
/* Zero based index of SCSI_RX_DMA dma channel */
extern uint8 SCSI_RX_DMA_DmaHandle;
uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
void SCSI_RX_DMA_DmaRelease(void) ;
/* CY_DMA_SCSI_RX_DMA_DMA_H__ */
#endif

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/*******************************************************************************
* File Name: SCSI_TX_DMA_COMPLETE.c
* Version 1.70
*
* Description:
* API for controlling the state of an interrupt.
*
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include <CyLib.h>
#include <SCSI_TX_DMA_COMPLETE.h>
#if !defined(SCSI_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Place your includes, defines and code here
********************************************************************************/
/* `#START SCSI_TX_DMA_COMPLETE_intc` */
/* `#END` */
#ifndef CYINT_IRQ_BASE
#define CYINT_IRQ_BASE 16
#endif /* CYINT_IRQ_BASE */
#ifndef CYINT_VECT_TABLE
#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
#endif /* CYINT_VECT_TABLE */
/* Declared in startup, used to set unused interrupts to. */
CY_ISR_PROTO(IntDefaultHandler);
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_Start
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_TX_DMA_COMPLETE_Start(void)
{
/* For all we know the interrupt is active. */
SCSI_TX_DMA_COMPLETE_Disable();
/* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */
SCSI_TX_DMA_COMPLETE_SetVector(&SCSI_TX_DMA_COMPLETE_Interrupt);
/* Set the priority. */
SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
/* Enable it. */
SCSI_TX_DMA_COMPLETE_Enable();
}
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_StartEx
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address)
{
/* For all we know the interrupt is active. */
SCSI_TX_DMA_COMPLETE_Disable();
/* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */
SCSI_TX_DMA_COMPLETE_SetVector(address);
/* Set the priority. */
SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
/* Enable it. */
SCSI_TX_DMA_COMPLETE_Enable();
}
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_Stop
********************************************************************************
*
* Summary:
* Disables and removes the interrupt.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
void SCSI_TX_DMA_COMPLETE_Stop(void)
{
/* Disable this interrupt. */
SCSI_TX_DMA_COMPLETE_Disable();
/* Set the ISR to point to the passive one. */
SCSI_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
}
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_Interrupt
********************************************************************************
*
* Summary:
* The default Interrupt Service Routine for SCSI_TX_DMA_COMPLETE.
*
* Add custom code between the coments to keep the next version of this file
* from over writting your code.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
CY_ISR(SCSI_TX_DMA_COMPLETE_Interrupt)
{
/* Place your Interrupt code here. */
/* `#START SCSI_TX_DMA_COMPLETE_Interrupt` */
/* `#END` */
}
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_SetVector
********************************************************************************
*
* Summary:
* Change the ISR vector for the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_TX_DMA_COMPLETE_StartEx instead.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER] = address;
}
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_GetVector
********************************************************************************
*
* Summary:
* Gets the "address" of the current ISR vector for the Interrupt.
*
* Parameters:
* None
*
* Return:
* Address of the ISR in the interrupt vector table.
*
*******************************************************************************/
cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER];
}
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_SetPriority
********************************************************************************
*
* Summary:
* Sets the Priority of the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
* or SCSI_TX_DMA_COMPLETE_StartEx will override any effect this method
* would have had. This method should only be called after
* SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. To set
* the initial priority for the component use the cydwr file in the tool.
*
* Parameters:
* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority)
{
*SCSI_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
}
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_GetPriority
********************************************************************************
*
* Summary:
* Gets the Priority of the Interrupt.
*
* Parameters:
* None
*
* Return:
* Priority of the interrupt. 0 - 7, 0 being the highest.
*
*******************************************************************************/
uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void)
{
uint8 priority;
priority = *SCSI_TX_DMA_COMPLETE_INTC_PRIOR >> 5;
return priority;
}
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_Enable
********************************************************************************
*
* Summary:
* Enables the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_TX_DMA_COMPLETE_Enable(void)
{
/* Enable the general interrupt. */
*SCSI_TX_DMA_COMPLETE_INTC_SET_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_GetState
********************************************************************************
*
* Summary:
* Gets the state (enabled, disabled) of the Interrupt.
*
* Parameters:
* None
*
* Return:
* 1 if enabled, 0 if disabled.
*
*******************************************************************************/
uint8 SCSI_TX_DMA_COMPLETE_GetState(void)
{
/* Get the state of the general interrupt. */
return ((*SCSI_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
}
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_Disable
********************************************************************************
*
* Summary:
* Disables the Interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_TX_DMA_COMPLETE_Disable(void)
{
/* Disable the general interrupt. */
*SCSI_TX_DMA_COMPLETE_INTC_CLR_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_SetPending
********************************************************************************
*
* Summary:
* Causes the Interrupt to enter the pending state, a software method of
* generating the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_TX_DMA_COMPLETE_SetPending(void)
{
*SCSI_TX_DMA_COMPLETE_INTC_SET_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_TX_DMA_COMPLETE_ClearPending
********************************************************************************
*
* Summary:
* Clears a pending interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_TX_DMA_COMPLETE_ClearPending(void)
{
*SCSI_TX_DMA_COMPLETE_INTC_CLR_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_TX_DMA_COMPLETE.h
* Version 1.70
*
* Description:
* Provides the function definitions for the Interrupt Controller.
*
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_ISR_SCSI_TX_DMA_COMPLETE_H)
#define CY_ISR_SCSI_TX_DMA_COMPLETE_H
#include <cytypes.h>
#include <cyfitter.h>
/* Interrupt Controller API. */
void SCSI_TX_DMA_COMPLETE_Start(void);
void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address);
void SCSI_TX_DMA_COMPLETE_Stop(void);
CY_ISR_PROTO(SCSI_TX_DMA_COMPLETE_Interrupt);
void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address);
cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void);
void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority);
uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void);
void SCSI_TX_DMA_COMPLETE_Enable(void);
uint8 SCSI_TX_DMA_COMPLETE_GetState(void);
void SCSI_TX_DMA_COMPLETE_Disable(void);
void SCSI_TX_DMA_COMPLETE_SetPending(void);
void SCSI_TX_DMA_COMPLETE_ClearPending(void);
/* Interrupt Controller Constants */
/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_TX_DMA_COMPLETE ISR. */
#define SCSI_TX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_VECT)
/* Address of the SCSI_TX_DMA_COMPLETE ISR priority. */
#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG)
/* Priority of the SCSI_TX_DMA_COMPLETE interrupt. */
#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM
/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_TX_DMA_COMPLETE interrupt. */
#define SCSI_TX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG)
/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_TX_DMA_COMPLETE interrupt. */
#define SCSI_TX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG)
/* Address of the INTC.SET_PD[x] register to set the SCSI_TX_DMA_COMPLETE interrupt state to pending. */
#define SCSI_TX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG)
/* Address of the INTC.CLR_PD[x] register to clear the SCSI_TX_DMA_COMPLETE interrupt. */
#define SCSI_TX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG)
#endif /* CY_ISR_SCSI_TX_DMA_COMPLETE_H */
/* [] END OF FILE */

141
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.c Normal file
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@ -0,0 +1,141 @@
/***************************************************************************
* File Name: SCSI_TX_DMA_dma.c
* Version 1.70
*
* Description:
* Provides an API for the DMAC component. The API includes functions
* for the DMA controller, DMA channels and Transfer Descriptors.
*
*
* Note:
* This module requires the developer to finish or fill in the auto
* generated funcions and setup the dma channel and TD's.
*
********************************************************************************
* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include <CYLIB.H>
#include <CYDMAC.H>
#include <SCSI_TX_DMA_dma.H>
/****************************************************************************
*
* The following defines are available in Cyfitter.h
*
*
*
* SCSI_TX_DMA__DRQ_CTL_REG
*
*
* SCSI_TX_DMA__DRQ_NUMBER
*
* Number of TD's used by this channel.
* SCSI_TX_DMA__NUMBEROF_TDS
*
* Priority of this channel.
* SCSI_TX_DMA__PRIORITY
*
* True if SCSI_TX_DMA_TERMIN_SEL is used.
* SCSI_TX_DMA__TERMIN_EN
*
* TERMIN interrupt line to signal terminate.
* SCSI_TX_DMA__TERMIN_SEL
*
*
* True if SCSI_TX_DMA_TERMOUT0_SEL is used.
* SCSI_TX_DMA__TERMOUT0_EN
*
*
* TERMOUT0 interrupt line to signal completion.
* SCSI_TX_DMA__TERMOUT0_SEL
*
*
* True if SCSI_TX_DMA_TERMOUT1_SEL is used.
* SCSI_TX_DMA__TERMOUT1_EN
*
*
* TERMOUT1 interrupt line to signal completion.
* SCSI_TX_DMA__TERMOUT1_SEL
*
****************************************************************************/
/* Zero based index of SCSI_TX_DMA dma channel */
uint8 SCSI_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
/*********************************************************************
* Function Name: uint8 SCSI_TX_DMA_DmaInitalize
**********************************************************************
* Summary:
* Allocates and initialises a channel of the DMAC to be used by the
* caller.
*
* Parameters:
* BurstCount.
*
*
* ReqestPerBurst.
*
*
* UpperSrcAddress.
*
*
* UpperDestAddress.
*
*
* Return:
* The channel that can be used by the caller for DMA activity.
* DMA_INVALID_CHANNEL (0xFF) if there are no channels left.
*
*
*******************************************************************/
uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress)
{
/* Allocate a DMA channel. */
SCSI_TX_DMA_DmaHandle = (uint8)SCSI_TX_DMA__DRQ_NUMBER;
/* Configure the channel. */
(void)CyDmaChSetConfiguration(SCSI_TX_DMA_DmaHandle,
BurstCount,
ReqestPerBurst,
(uint8)SCSI_TX_DMA__TERMOUT0_SEL,
(uint8)SCSI_TX_DMA__TERMOUT1_SEL,
(uint8)SCSI_TX_DMA__TERMIN_SEL);
/* Set the extended address for the transfers */
(void)CyDmaChSetExtendedAddress(SCSI_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
/* Set the priority for this channel */
(void)CyDmaChPriority(SCSI_TX_DMA_DmaHandle, (uint8)SCSI_TX_DMA__PRIORITY);
return SCSI_TX_DMA_DmaHandle;
}
/*********************************************************************
* Function Name: void SCSI_TX_DMA_DmaRelease
**********************************************************************
* Summary:
* Frees the channel associated with SCSI_TX_DMA.
*
*
* Parameters:
* void.
*
*
*
* Return:
* void.
*
*******************************************************************/
void SCSI_TX_DMA_DmaRelease(void)
{
/* Disable the channel */
(void)CyDmaChDisable(SCSI_TX_DMA_DmaHandle);
}

35
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.h Normal file
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@ -0,0 +1,35 @@
/******************************************************************************
* File Name: SCSI_TX_DMA_dma.h
* Version 1.70
*
* Description:
* Provides the function definitions for the DMA Controller.
*
*
********************************************************************************
* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#if !defined(CY_DMA_SCSI_TX_DMA_DMA_H__)
#define CY_DMA_SCSI_TX_DMA_DMA_H__
#include <CYDMAC.H>
#include <CYFITTER.H>
#define SCSI_TX_DMA__TD_TERMOUT_EN (((0 != SCSI_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
(SCSI_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
/* Zero based index of SCSI_TX_DMA dma channel */
extern uint8 SCSI_TX_DMA_DmaHandle;
uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
void SCSI_TX_DMA_DmaRelease(void) ;
/* CY_DMA_SCSI_TX_DMA_DMA_H__ */
#endif

4
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard.h Executable file → Normal file
View File

@ -147,7 +147,7 @@ extern uint8 SDCard_initVar;
#define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT))
#define SDCard_INT_ON_TX_EMPTY ((uint8) (0u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \
#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (1u << \
SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))
#define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT))
#define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT))
@ -165,7 +165,7 @@ extern uint8 SDCard_initVar;
#define SDCard_INT_ON_RX_FULL ((uint8) (0u << \
SDCard_STS_RX_FIFO_FULL_SHIFT))
#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \
#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (1u << \
SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT))
#define SDCard_INT_ON_RX_OVER ((uint8) (0u << \
SDCard_STS_RX_FIFO_OVERRUN_SHIFT))

356
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.c Normal file
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@ -0,0 +1,356 @@
/*******************************************************************************
* File Name: SD_RX_DMA_COMPLETE.c
* Version 1.70
*
* Description:
* API for controlling the state of an interrupt.
*
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include <CyLib.h>
#include <SD_RX_DMA_COMPLETE.h>
#if !defined(SD_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Place your includes, defines and code here
********************************************************************************/
/* `#START SD_RX_DMA_COMPLETE_intc` */
/* `#END` */
#ifndef CYINT_IRQ_BASE
#define CYINT_IRQ_BASE 16
#endif /* CYINT_IRQ_BASE */
#ifndef CYINT_VECT_TABLE
#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
#endif /* CYINT_VECT_TABLE */
/* Declared in startup, used to set unused interrupts to. */
CY_ISR_PROTO(IntDefaultHandler);
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_Start
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SD_RX_DMA_COMPLETE_Start(void)
{
/* For all we know the interrupt is active. */
SD_RX_DMA_COMPLETE_Disable();
/* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */
SD_RX_DMA_COMPLETE_SetVector(&SD_RX_DMA_COMPLETE_Interrupt);
/* Set the priority. */
SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
/* Enable it. */
SD_RX_DMA_COMPLETE_Enable();
}
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_StartEx
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address)
{
/* For all we know the interrupt is active. */
SD_RX_DMA_COMPLETE_Disable();
/* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */
SD_RX_DMA_COMPLETE_SetVector(address);
/* Set the priority. */
SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
/* Enable it. */
SD_RX_DMA_COMPLETE_Enable();
}
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_Stop
********************************************************************************
*
* Summary:
* Disables and removes the interrupt.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
void SD_RX_DMA_COMPLETE_Stop(void)
{
/* Disable this interrupt. */
SD_RX_DMA_COMPLETE_Disable();
/* Set the ISR to point to the passive one. */
SD_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
}
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_Interrupt
********************************************************************************
*
* Summary:
* The default Interrupt Service Routine for SD_RX_DMA_COMPLETE.
*
* Add custom code between the coments to keep the next version of this file
* from over writting your code.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
CY_ISR(SD_RX_DMA_COMPLETE_Interrupt)
{
/* Place your Interrupt code here. */
/* `#START SD_RX_DMA_COMPLETE_Interrupt` */
/* `#END` */
}
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_SetVector
********************************************************************************
*
* Summary:
* Change the ISR vector for the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SD_RX_DMA_COMPLETE_StartEx instead.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER] = address;
}
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_GetVector
********************************************************************************
*
* Summary:
* Gets the "address" of the current ISR vector for the Interrupt.
*
* Parameters:
* None
*
* Return:
* Address of the ISR in the interrupt vector table.
*
*******************************************************************************/
cyisraddress SD_RX_DMA_COMPLETE_GetVector(void)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER];
}
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_SetPriority
********************************************************************************
*
* Summary:
* Sets the Priority of the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
* or SD_RX_DMA_COMPLETE_StartEx will override any effect this method
* would have had. This method should only be called after
* SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. To set
* the initial priority for the component use the cydwr file in the tool.
*
* Parameters:
* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
*
* Return:
* None
*
*******************************************************************************/
void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority)
{
*SD_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
}
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_GetPriority
********************************************************************************
*
* Summary:
* Gets the Priority of the Interrupt.
*
* Parameters:
* None
*
* Return:
* Priority of the interrupt. 0 - 7, 0 being the highest.
*
*******************************************************************************/
uint8 SD_RX_DMA_COMPLETE_GetPriority(void)
{
uint8 priority;
priority = *SD_RX_DMA_COMPLETE_INTC_PRIOR >> 5;
return priority;
}
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_Enable
********************************************************************************
*
* Summary:
* Enables the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SD_RX_DMA_COMPLETE_Enable(void)
{
/* Enable the general interrupt. */
*SD_RX_DMA_COMPLETE_INTC_SET_EN = SD_RX_DMA_COMPLETE__INTC_MASK;
}
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_GetState
********************************************************************************
*
* Summary:
* Gets the state (enabled, disabled) of the Interrupt.
*
* Parameters:
* None
*
* Return:
* 1 if enabled, 0 if disabled.
*
*******************************************************************************/
uint8 SD_RX_DMA_COMPLETE_GetState(void)
{
/* Get the state of the general interrupt. */
return ((*SD_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
}
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_Disable
********************************************************************************
*
* Summary:
* Disables the Interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SD_RX_DMA_COMPLETE_Disable(void)
{
/* Disable the general interrupt. */
*SD_RX_DMA_COMPLETE_INTC_CLR_EN = SD_RX_DMA_COMPLETE__INTC_MASK;
}
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_SetPending
********************************************************************************
*
* Summary:
* Causes the Interrupt to enter the pending state, a software method of
* generating the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SD_RX_DMA_COMPLETE_SetPending(void)
{
*SD_RX_DMA_COMPLETE_INTC_SET_PD = SD_RX_DMA_COMPLETE__INTC_MASK;
}
/*******************************************************************************
* Function Name: SD_RX_DMA_COMPLETE_ClearPending
********************************************************************************
*
* Summary:
* Clears a pending interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SD_RX_DMA_COMPLETE_ClearPending(void)
{
*SD_RX_DMA_COMPLETE_INTC_CLR_PD = SD_RX_DMA_COMPLETE__INTC_MASK;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

70
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.h Normal file
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@ -0,0 +1,70 @@
/*******************************************************************************
* File Name: SD_RX_DMA_COMPLETE.h
* Version 1.70
*
* Description:
* Provides the function definitions for the Interrupt Controller.
*
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_ISR_SD_RX_DMA_COMPLETE_H)
#define CY_ISR_SD_RX_DMA_COMPLETE_H
#include <cytypes.h>
#include <cyfitter.h>
/* Interrupt Controller API. */
void SD_RX_DMA_COMPLETE_Start(void);
void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address);
void SD_RX_DMA_COMPLETE_Stop(void);
CY_ISR_PROTO(SD_RX_DMA_COMPLETE_Interrupt);
void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address);
cyisraddress SD_RX_DMA_COMPLETE_GetVector(void);
void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority);
uint8 SD_RX_DMA_COMPLETE_GetPriority(void);
void SD_RX_DMA_COMPLETE_Enable(void);
uint8 SD_RX_DMA_COMPLETE_GetState(void);
void SD_RX_DMA_COMPLETE_Disable(void);
void SD_RX_DMA_COMPLETE_SetPending(void);
void SD_RX_DMA_COMPLETE_ClearPending(void);
/* Interrupt Controller Constants */
/* Address of the INTC.VECT[x] register that contains the Address of the SD_RX_DMA_COMPLETE ISR. */
#define SD_RX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SD_RX_DMA_COMPLETE__INTC_VECT)
/* Address of the SD_RX_DMA_COMPLETE ISR priority. */
#define SD_RX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SD_RX_DMA_COMPLETE__INTC_PRIOR_REG)
/* Priority of the SD_RX_DMA_COMPLETE interrupt. */
#define SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM
/* Address of the INTC.SET_EN[x] byte to bit enable SD_RX_DMA_COMPLETE interrupt. */
#define SD_RX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_EN_REG)
/* Address of the INTC.CLR_EN[x] register to bit clear the SD_RX_DMA_COMPLETE interrupt. */
#define SD_RX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG)
/* Address of the INTC.SET_PD[x] register to set the SD_RX_DMA_COMPLETE interrupt state to pending. */
#define SD_RX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_PD_REG)
/* Address of the INTC.CLR_PD[x] register to clear the SD_RX_DMA_COMPLETE interrupt. */
#define SD_RX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG)
#endif /* CY_ISR_SD_RX_DMA_COMPLETE_H */
/* [] END OF FILE */

141
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.c Normal file
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@ -0,0 +1,141 @@
/***************************************************************************
* File Name: SD_RX_DMA_dma.c
* Version 1.70
*
* Description:
* Provides an API for the DMAC component. The API includes functions
* for the DMA controller, DMA channels and Transfer Descriptors.
*
*
* Note:
* This module requires the developer to finish or fill in the auto
* generated funcions and setup the dma channel and TD's.
*
********************************************************************************
* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include <CYLIB.H>
#include <CYDMAC.H>
#include <SD_RX_DMA_dma.H>
/****************************************************************************
*
* The following defines are available in Cyfitter.h
*
*
*
* SD_RX_DMA__DRQ_CTL_REG
*
*
* SD_RX_DMA__DRQ_NUMBER
*
* Number of TD's used by this channel.
* SD_RX_DMA__NUMBEROF_TDS
*
* Priority of this channel.
* SD_RX_DMA__PRIORITY
*
* True if SD_RX_DMA_TERMIN_SEL is used.
* SD_RX_DMA__TERMIN_EN
*
* TERMIN interrupt line to signal terminate.
* SD_RX_DMA__TERMIN_SEL
*
*
* True if SD_RX_DMA_TERMOUT0_SEL is used.
* SD_RX_DMA__TERMOUT0_EN
*
*
* TERMOUT0 interrupt line to signal completion.
* SD_RX_DMA__TERMOUT0_SEL
*
*
* True if SD_RX_DMA_TERMOUT1_SEL is used.
* SD_RX_DMA__TERMOUT1_EN
*
*
* TERMOUT1 interrupt line to signal completion.
* SD_RX_DMA__TERMOUT1_SEL
*
****************************************************************************/
/* Zero based index of SD_RX_DMA dma channel */
uint8 SD_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
/*********************************************************************
* Function Name: uint8 SD_RX_DMA_DmaInitalize
**********************************************************************
* Summary:
* Allocates and initialises a channel of the DMAC to be used by the
* caller.
*
* Parameters:
* BurstCount.
*
*
* ReqestPerBurst.
*
*
* UpperSrcAddress.
*
*
* UpperDestAddress.
*
*
* Return:
* The channel that can be used by the caller for DMA activity.
* DMA_INVALID_CHANNEL (0xFF) if there are no channels left.
*
*
*******************************************************************/
uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress)
{
/* Allocate a DMA channel. */
SD_RX_DMA_DmaHandle = (uint8)SD_RX_DMA__DRQ_NUMBER;
/* Configure the channel. */
(void)CyDmaChSetConfiguration(SD_RX_DMA_DmaHandle,
BurstCount,
ReqestPerBurst,
(uint8)SD_RX_DMA__TERMOUT0_SEL,
(uint8)SD_RX_DMA__TERMOUT1_SEL,
(uint8)SD_RX_DMA__TERMIN_SEL);
/* Set the extended address for the transfers */
(void)CyDmaChSetExtendedAddress(SD_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
/* Set the priority for this channel */
(void)CyDmaChPriority(SD_RX_DMA_DmaHandle, (uint8)SD_RX_DMA__PRIORITY);
return SD_RX_DMA_DmaHandle;
}
/*********************************************************************
* Function Name: void SD_RX_DMA_DmaRelease
**********************************************************************
* Summary:
* Frees the channel associated with SD_RX_DMA.
*
*
* Parameters:
* void.
*
*
*
* Return:
* void.
*
*******************************************************************/
void SD_RX_DMA_DmaRelease(void)
{
/* Disable the channel */
(void)CyDmaChDisable(SD_RX_DMA_DmaHandle);
}

35
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.h Normal file
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@ -0,0 +1,35 @@
/******************************************************************************
* File Name: SD_RX_DMA_dma.h
* Version 1.70
*
* Description:
* Provides the function definitions for the DMA Controller.
*
*
********************************************************************************
* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#if !defined(CY_DMA_SD_RX_DMA_DMA_H__)
#define CY_DMA_SD_RX_DMA_DMA_H__
#include <CYDMAC.H>
#include <CYFITTER.H>
#define SD_RX_DMA__TD_TERMOUT_EN (((0 != SD_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
(SD_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
/* Zero based index of SD_RX_DMA dma channel */
extern uint8 SD_RX_DMA_DmaHandle;
uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
void SD_RX_DMA_DmaRelease(void) ;
/* CY_DMA_SD_RX_DMA_DMA_H__ */
#endif

356
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.c Normal file
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@ -0,0 +1,356 @@
/*******************************************************************************
* File Name: SD_TX_DMA_COMPLETE.c
* Version 1.70
*
* Description:
* API for controlling the state of an interrupt.
*
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include <CyLib.h>
#include <SD_TX_DMA_COMPLETE.h>
#if !defined(SD_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Place your includes, defines and code here
********************************************************************************/
/* `#START SD_TX_DMA_COMPLETE_intc` */
/* `#END` */
#ifndef CYINT_IRQ_BASE
#define CYINT_IRQ_BASE 16
#endif /* CYINT_IRQ_BASE */
#ifndef CYINT_VECT_TABLE
#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
#endif /* CYINT_VECT_TABLE */
/* Declared in startup, used to set unused interrupts to. */
CY_ISR_PROTO(IntDefaultHandler);
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_Start
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SD_TX_DMA_COMPLETE_Start(void)
{
/* For all we know the interrupt is active. */
SD_TX_DMA_COMPLETE_Disable();
/* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */
SD_TX_DMA_COMPLETE_SetVector(&SD_TX_DMA_COMPLETE_Interrupt);
/* Set the priority. */
SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
/* Enable it. */
SD_TX_DMA_COMPLETE_Enable();
}
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_StartEx
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address)
{
/* For all we know the interrupt is active. */
SD_TX_DMA_COMPLETE_Disable();
/* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */
SD_TX_DMA_COMPLETE_SetVector(address);
/* Set the priority. */
SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
/* Enable it. */
SD_TX_DMA_COMPLETE_Enable();
}
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_Stop
********************************************************************************
*
* Summary:
* Disables and removes the interrupt.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
void SD_TX_DMA_COMPLETE_Stop(void)
{
/* Disable this interrupt. */
SD_TX_DMA_COMPLETE_Disable();
/* Set the ISR to point to the passive one. */
SD_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
}
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_Interrupt
********************************************************************************
*
* Summary:
* The default Interrupt Service Routine for SD_TX_DMA_COMPLETE.
*
* Add custom code between the coments to keep the next version of this file
* from over writting your code.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
CY_ISR(SD_TX_DMA_COMPLETE_Interrupt)
{
/* Place your Interrupt code here. */
/* `#START SD_TX_DMA_COMPLETE_Interrupt` */
/* `#END` */
}
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_SetVector
********************************************************************************
*
* Summary:
* Change the ISR vector for the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SD_TX_DMA_COMPLETE_StartEx instead.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER] = address;
}
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_GetVector
********************************************************************************
*
* Summary:
* Gets the "address" of the current ISR vector for the Interrupt.
*
* Parameters:
* None
*
* Return:
* Address of the ISR in the interrupt vector table.
*
*******************************************************************************/
cyisraddress SD_TX_DMA_COMPLETE_GetVector(void)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER];
}
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_SetPriority
********************************************************************************
*
* Summary:
* Sets the Priority of the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
* or SD_TX_DMA_COMPLETE_StartEx will override any effect this method
* would have had. This method should only be called after
* SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. To set
* the initial priority for the component use the cydwr file in the tool.
*
* Parameters:
* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
*
* Return:
* None
*
*******************************************************************************/
void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority)
{
*SD_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
}
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_GetPriority
********************************************************************************
*
* Summary:
* Gets the Priority of the Interrupt.
*
* Parameters:
* None
*
* Return:
* Priority of the interrupt. 0 - 7, 0 being the highest.
*
*******************************************************************************/
uint8 SD_TX_DMA_COMPLETE_GetPriority(void)
{
uint8 priority;
priority = *SD_TX_DMA_COMPLETE_INTC_PRIOR >> 5;
return priority;
}
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_Enable
********************************************************************************
*
* Summary:
* Enables the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SD_TX_DMA_COMPLETE_Enable(void)
{
/* Enable the general interrupt. */
*SD_TX_DMA_COMPLETE_INTC_SET_EN = SD_TX_DMA_COMPLETE__INTC_MASK;
}
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_GetState
********************************************************************************
*
* Summary:
* Gets the state (enabled, disabled) of the Interrupt.
*
* Parameters:
* None
*
* Return:
* 1 if enabled, 0 if disabled.
*
*******************************************************************************/
uint8 SD_TX_DMA_COMPLETE_GetState(void)
{
/* Get the state of the general interrupt. */
return ((*SD_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
}
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_Disable
********************************************************************************
*
* Summary:
* Disables the Interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SD_TX_DMA_COMPLETE_Disable(void)
{
/* Disable the general interrupt. */
*SD_TX_DMA_COMPLETE_INTC_CLR_EN = SD_TX_DMA_COMPLETE__INTC_MASK;
}
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_SetPending
********************************************************************************
*
* Summary:
* Causes the Interrupt to enter the pending state, a software method of
* generating the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SD_TX_DMA_COMPLETE_SetPending(void)
{
*SD_TX_DMA_COMPLETE_INTC_SET_PD = SD_TX_DMA_COMPLETE__INTC_MASK;
}
/*******************************************************************************
* Function Name: SD_TX_DMA_COMPLETE_ClearPending
********************************************************************************
*
* Summary:
* Clears a pending interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SD_TX_DMA_COMPLETE_ClearPending(void)
{
*SD_TX_DMA_COMPLETE_INTC_CLR_PD = SD_TX_DMA_COMPLETE__INTC_MASK;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

70
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.h Normal file
View File

@ -0,0 +1,70 @@
/*******************************************************************************
* File Name: SD_TX_DMA_COMPLETE.h
* Version 1.70
*
* Description:
* Provides the function definitions for the Interrupt Controller.
*
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_ISR_SD_TX_DMA_COMPLETE_H)
#define CY_ISR_SD_TX_DMA_COMPLETE_H
#include <cytypes.h>
#include <cyfitter.h>
/* Interrupt Controller API. */
void SD_TX_DMA_COMPLETE_Start(void);
void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address);
void SD_TX_DMA_COMPLETE_Stop(void);
CY_ISR_PROTO(SD_TX_DMA_COMPLETE_Interrupt);
void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address);
cyisraddress SD_TX_DMA_COMPLETE_GetVector(void);
void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority);
uint8 SD_TX_DMA_COMPLETE_GetPriority(void);
void SD_TX_DMA_COMPLETE_Enable(void);
uint8 SD_TX_DMA_COMPLETE_GetState(void);
void SD_TX_DMA_COMPLETE_Disable(void);
void SD_TX_DMA_COMPLETE_SetPending(void);
void SD_TX_DMA_COMPLETE_ClearPending(void);
/* Interrupt Controller Constants */
/* Address of the INTC.VECT[x] register that contains the Address of the SD_TX_DMA_COMPLETE ISR. */
#define SD_TX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SD_TX_DMA_COMPLETE__INTC_VECT)
/* Address of the SD_TX_DMA_COMPLETE ISR priority. */
#define SD_TX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SD_TX_DMA_COMPLETE__INTC_PRIOR_REG)
/* Priority of the SD_TX_DMA_COMPLETE interrupt. */
#define SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM
/* Address of the INTC.SET_EN[x] byte to bit enable SD_TX_DMA_COMPLETE interrupt. */
#define SD_TX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_EN_REG)
/* Address of the INTC.CLR_EN[x] register to bit clear the SD_TX_DMA_COMPLETE interrupt. */
#define SD_TX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG)
/* Address of the INTC.SET_PD[x] register to set the SD_TX_DMA_COMPLETE interrupt state to pending. */
#define SD_TX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_PD_REG)
/* Address of the INTC.CLR_PD[x] register to clear the SD_TX_DMA_COMPLETE interrupt. */
#define SD_TX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG)
#endif /* CY_ISR_SD_TX_DMA_COMPLETE_H */
/* [] END OF FILE */

141
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.c Normal file
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@ -0,0 +1,141 @@
/***************************************************************************
* File Name: SD_TX_DMA_dma.c
* Version 1.70
*
* Description:
* Provides an API for the DMAC component. The API includes functions
* for the DMA controller, DMA channels and Transfer Descriptors.
*
*
* Note:
* This module requires the developer to finish or fill in the auto
* generated funcions and setup the dma channel and TD's.
*
********************************************************************************
* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include <CYLIB.H>
#include <CYDMAC.H>
#include <SD_TX_DMA_dma.H>
/****************************************************************************
*
* The following defines are available in Cyfitter.h
*
*
*
* SD_TX_DMA__DRQ_CTL_REG
*
*
* SD_TX_DMA__DRQ_NUMBER
*
* Number of TD's used by this channel.
* SD_TX_DMA__NUMBEROF_TDS
*
* Priority of this channel.
* SD_TX_DMA__PRIORITY
*
* True if SD_TX_DMA_TERMIN_SEL is used.
* SD_TX_DMA__TERMIN_EN
*
* TERMIN interrupt line to signal terminate.
* SD_TX_DMA__TERMIN_SEL
*
*
* True if SD_TX_DMA_TERMOUT0_SEL is used.
* SD_TX_DMA__TERMOUT0_EN
*
*
* TERMOUT0 interrupt line to signal completion.
* SD_TX_DMA__TERMOUT0_SEL
*
*
* True if SD_TX_DMA_TERMOUT1_SEL is used.
* SD_TX_DMA__TERMOUT1_EN
*
*
* TERMOUT1 interrupt line to signal completion.
* SD_TX_DMA__TERMOUT1_SEL
*
****************************************************************************/
/* Zero based index of SD_TX_DMA dma channel */
uint8 SD_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
/*********************************************************************
* Function Name: uint8 SD_TX_DMA_DmaInitalize
**********************************************************************
* Summary:
* Allocates and initialises a channel of the DMAC to be used by the
* caller.
*
* Parameters:
* BurstCount.
*
*
* ReqestPerBurst.
*
*
* UpperSrcAddress.
*
*
* UpperDestAddress.
*
*
* Return:
* The channel that can be used by the caller for DMA activity.
* DMA_INVALID_CHANNEL (0xFF) if there are no channels left.
*
*
*******************************************************************/
uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress)
{
/* Allocate a DMA channel. */
SD_TX_DMA_DmaHandle = (uint8)SD_TX_DMA__DRQ_NUMBER;
/* Configure the channel. */
(void)CyDmaChSetConfiguration(SD_TX_DMA_DmaHandle,
BurstCount,
ReqestPerBurst,
(uint8)SD_TX_DMA__TERMOUT0_SEL,
(uint8)SD_TX_DMA__TERMOUT1_SEL,
(uint8)SD_TX_DMA__TERMIN_SEL);
/* Set the extended address for the transfers */
(void)CyDmaChSetExtendedAddress(SD_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
/* Set the priority for this channel */
(void)CyDmaChPriority(SD_TX_DMA_DmaHandle, (uint8)SD_TX_DMA__PRIORITY);
return SD_TX_DMA_DmaHandle;
}
/*********************************************************************
* Function Name: void SD_TX_DMA_DmaRelease
**********************************************************************
* Summary:
* Frees the channel associated with SD_TX_DMA.
*
*
* Parameters:
* void.
*
*
*
* Return:
* void.
*
*******************************************************************/
void SD_TX_DMA_DmaRelease(void)
{
/* Disable the channel */
(void)CyDmaChDisable(SD_TX_DMA_DmaHandle);
}

35
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.h Normal file
View File

@ -0,0 +1,35 @@
/******************************************************************************
* File Name: SD_TX_DMA_dma.h
* Version 1.70
*
* Description:
* Provides the function definitions for the DMA Controller.
*
*
********************************************************************************
* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#if !defined(CY_DMA_SD_TX_DMA_DMA_H__)
#define CY_DMA_SD_TX_DMA_DMA_H__
#include <CYDMAC.H>
#include <CYFITTER.H>
#define SD_TX_DMA__TD_TERMOUT_EN (((0 != SD_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
(SD_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
/* Zero based index of SD_TX_DMA dma channel */
extern uint8 SD_TX_DMA_DmaHandle;
uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
void SD_TX_DMA_DmaRelease(void) ;
/* CY_DMA_SD_TX_DMA_DMA_H__ */
#endif

11
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS.h Executable file → Normal file
View File

@ -77,6 +77,11 @@
#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u)
#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u)
#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u)
#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE (65u)
#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_IN_RPTS (1u)
#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE (65u)
#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_OUT_RPTS (1u)
#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT (1u)
#define USBFS_ENABLE_HID_CLASS
#define USBFS_HID_RPT_1_SIZE_LSB (0x24u)
#define USBFS_HID_RPT_1_SIZE_MSB (0x00u)
@ -86,12 +91,12 @@
#define USBFS_EXTERN_VBUS (0u)
#define USBFS_EXTERN_VND (0u)
#define USBFS_EXTERN_CLS (0u)
#define USBFS_MAX_INTERFACES_NUMBER (1u)
#define USBFS_MAX_INTERFACES_NUMBER (2u)
#define USBFS_EP0_ISR_REMOVE (0u)
#define USBFS_EP1_ISR_REMOVE (0u)
#define USBFS_EP2_ISR_REMOVE (0u)
#define USBFS_EP3_ISR_REMOVE (1u)
#define USBFS_EP4_ISR_REMOVE (1u)
#define USBFS_EP3_ISR_REMOVE (0u)
#define USBFS_EP4_ISR_REMOVE (0u)
#define USBFS_EP5_ISR_REMOVE (1u)
#define USBFS_EP6_ISR_REMOVE (1u)
#define USBFS_EP7_ISR_REMOVE (1u)

116
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_descr.c Executable file → Normal file
View File

@ -55,11 +55,11 @@ const uint8 CYCODE USBFS_DEVICE0_DESCR[18u] = {
/*********************************************************************
* Config Descriptor
*********************************************************************/
const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u] = {
const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u] = {
/* Config Descriptor Length */ 0x09u,
/* DescriptorType: CONFIG */ 0x02u,
/* wTotalLength */ 0x29u, 0x00u,
/* bNumInterfaces */ 0x01u,
/* wTotalLength */ 0x49u, 0x00u,
/* bNumInterfaces */ 0x02u,
/* bConfigurationValue */ 0x01u,
/* iConfiguration */ 0x00u,
/* bmAttributes */ 0x80u,
@ -104,6 +104,47 @@ const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u] = {
/* bEndpointAddress */ 0x82u,
/* bmAttributes */ 0x03u,
/* wMaxPacketSize */ 0x40u, 0x00u,
/* bInterval */ 0x40u,
/*********************************************************************
* Interface Descriptor
*********************************************************************/
/* Interface Descriptor Length */ 0x09u,
/* DescriptorType: INTERFACE */ 0x04u,
/* bInterfaceNumber */ 0x01u,
/* bAlternateSetting */ 0x00u,
/* bNumEndpoints */ 0x02u,
/* bInterfaceClass */ 0x03u,
/* bInterfaceSubClass */ 0x00u,
/* bInterfaceProtocol */ 0x00u,
/* iInterface */ 0x00u,
/*********************************************************************
* HID Class Descriptor
*********************************************************************/
/* HID Class Descriptor Length */ 0x09u,
/* DescriptorType: HID_CLASS */ 0x21u,
/* bcdHID */ 0x11u, 0x01u,
/* bCountryCode */ 0x00u,
/* bNumDescriptors */ 0x01u,
/* bDescriptorType */ 0x22u,
/* wDescriptorLength (LSB) */ USBFS_HID_RPT_1_SIZE_LSB,
/* wDescriptorLength (MSB) */ USBFS_HID_RPT_1_SIZE_MSB,
/*********************************************************************
* Endpoint Descriptor
*********************************************************************/
/* Endpoint Descriptor Length */ 0x07u,
/* DescriptorType: ENDPOINT */ 0x05u,
/* bEndpointAddress */ 0x03u,
/* bmAttributes */ 0x03u,
/* wMaxPacketSize */ 0x40u, 0x00u,
/* bInterval */ 0x80u,
/*********************************************************************
* Endpoint Descriptor
*********************************************************************/
/* Endpoint Descriptor Length */ 0x07u,
/* DescriptorType: ENDPOINT */ 0x05u,
/* bEndpointAddress */ 0x84u,
/* bmAttributes */ 0x03u,
/* wMaxPacketSize */ 0x40u, 0x00u,
/* bInterval */ 0x40u
};
@ -221,6 +262,53 @@ const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_
{0x01u, (const void *)&USBFS_DEVICE0_CONFIGURATION0_DESCR[18]}
};
#endif /* USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_HID_RPT_STORAGE */
#if !defined(USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_HID_RPT_STORAGE)
/*********************************************************************
* HID Input Report Storage
*********************************************************************/
T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_SCB;
uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF[
USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE];
/*********************************************************************
* HID Input Report TD Table
*********************************************************************/
const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_TABLE[1u] = {
{USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE,
&USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF[0u],
&USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_SCB},
};
/*********************************************************************
* HID Output Report Storage
*********************************************************************/
T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_SCB;
uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF[
USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE];
/*********************************************************************
* HID Output Report TD Table
*********************************************************************/
const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_TABLE[1u] = {
{USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE,
&USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF[0u],
&USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_SCB},
};
/*********************************************************************
* HID Report Look Up Table This table has four entries:
* IN Report Table
* OUT Report Table
* Feature Report Table
* HID Report Descriptor
* HID Class Descriptor
*********************************************************************/
const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_TABLE[5u] = {
{0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_TABLE},
{0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_TABLE},
{0x00u, NULL},
{0x01u, (const void *)&USBFS_HIDREPORT_DESCRIPTOR1[0]},
{0x01u, (const void *)&USBFS_DEVICE0_CONFIGURATION0_DESCR[50]}
};
#endif /* USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_HID_RPT_STORAGE */
/*********************************************************************
* Interface Dispatch Table -- Points to the Class Dispatch Tables
@ -230,29 +318,39 @@ const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u] = {
&USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE}
};
/*********************************************************************
* Interface Dispatch Table -- Points to the Class Dispatch Tables
*********************************************************************/
const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_TABLE[1u] = {
{USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT,
&USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_TABLE}
};
/*********************************************************************
* Endpoint Setting Table -- This table contain the endpoint setting
* for each endpoint in the configuration. It
* contains the necessary information to
* configure the endpoint hardware for each
* interface and alternate setting.
*********************************************************************/
const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u] = {
const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[4u] = {
/* IFC ALT EPAddr bmAttr MaxPktSize Class ********************/
{0x00u, 0x00u, 0x01u, 0x03u, 0x0040u, 0x03u},
{0x00u, 0x00u, 0x82u, 0x03u, 0x0040u, 0x03u}
{0x00u, 0x00u, 0x82u, 0x03u, 0x0040u, 0x03u},
{0x01u, 0x00u, 0x03u, 0x03u, 0x0040u, 0x03u},
{0x01u, 0x00u, 0x84u, 0x03u, 0x0040u, 0x03u}
};
const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u] = {
0x03u
const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[2u] = {
0x03u, 0x03u
};
/*********************************************************************
* Config Dispatch Table -- Points to the Config Descriptor and each of
* and endpoint setup table and to each
* interface table if it specifies a USB Class
*********************************************************************/
const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u] = {
const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[5u] = {
{0x01u, &USBFS_DEVICE0_CONFIGURATION0_DESCR},
{0x02u, &USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE},
{0x04u, &USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE},
{0x01u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE},
{0x01u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_TABLE},
{0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS}
};
/*********************************************************************

18
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_pvt.h Executable file → Normal file
View File

@ -26,11 +26,12 @@
/* Generated external references for descriptors*/
extern const uint8 CYCODE USBFS_DEVICE0_DESCR[18u];
extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u];
extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u];
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u];
extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u];
extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u];
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u];
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_TABLE[1u];
extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[4u];
extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[2u];
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[5u];
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u];
extern const T_USBFS_LUT CYCODE USBFS_TABLE[1u];
extern const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10];
@ -41,10 +42,19 @@ extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[
extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB;
extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[
USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE];
extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_SCB;
extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF[
USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE];
extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_SCB;
extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF[
USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE];
extern const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[40u];
extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE[1u];
extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE[1u];
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE[5u];
extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_TABLE[1u];
extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_TABLE[1u];
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_TABLE[5u];
extern const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH];

598
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter.h Executable file → Normal file
View File

@ -3,6 +3,74 @@
#include <cydevice.h>
#include <cydevice_trm.h>
/* Debug_Timer_Interrupt */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define Debug_Timer_Interrupt__INTC_MASK 0x02u
#define Debug_Timer_Interrupt__INTC_NUMBER 1u
#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u
#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1
#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_RX_DMA_COMPLETE */
#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u
#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u
#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0
#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_TX_DMA_COMPLETE */
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x04u
#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 2u
#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2
#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* Debug_Timer_TimerHW */
#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0
#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1
#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0
#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1
#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2
#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0
#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1
#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0
#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1
#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u
#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u
#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0
#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1
#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0
/* SD_RX_DMA_COMPLETE */
#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define SD_RX_DMA_COMPLETE__INTC_MASK 0x08u
#define SD_RX_DMA_COMPLETE__INTC_NUMBER 3u
#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3
#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SD_TX_DMA_COMPLETE */
#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define SD_TX_DMA_COMPLETE__INTC_MASK 0x10u
#define SD_TX_DMA_COMPLETE__INTC_NUMBER 4u
#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_bus_reset */
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
@ -13,6 +81,68 @@
#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
/* SCSI_Out_Bits */
#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3
#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u
#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4
#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u
#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5
#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
/* USBFS_arb_int */
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
@ -33,6 +163,28 @@
#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB08_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB08_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB08_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB08_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB08_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB08_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX
@ -478,34 +630,23 @@
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB11_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB11_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB11_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB11_ST
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB11_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB11_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB11_MSK
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@ -513,13 +654,13 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB10_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB10_ST
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
@ -529,26 +670,30 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1
#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1
#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0
#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1
#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1
#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0
#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1
#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB08_MSK
#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL
#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB08_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB08_09_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB08_09_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB08_09_D0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB08_09_D1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB08_09_F0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB08_09_F1
#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB08_A0_A1
#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB08_A0
#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB08_A1
#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB08_D0_D1
#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB08_D0
#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB08_D1
#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB08_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB08_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB08_F1
/* USBFS_dp_int */
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -560,19 +705,6 @@
#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_CTL_IO */
#define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL
#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL
#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL
#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL
#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL
#define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u
#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK
#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
/* SCSI_In_DBx */
#define SCSI_In_DBx__0__AG CYREG_PRT5_AG
#define SCSI_In_DBx__0__AMUX CYREG_PRT5_AMUX
@ -1003,6 +1135,30 @@
#define SCSI_In_DBx__DB7__SHIFT 4
#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW
/* SCSI_RX_DMA */
#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
#define SCSI_RX_DMA__DRQ_NUMBER 0u
#define SCSI_RX_DMA__NUMBEROF_TDS 0u
#define SCSI_RX_DMA__PRIORITY 2u
#define SCSI_RX_DMA__TERMIN_EN 0u
#define SCSI_RX_DMA__TERMIN_SEL 0u
#define SCSI_RX_DMA__TERMOUT0_EN 1u
#define SCSI_RX_DMA__TERMOUT0_SEL 0u
#define SCSI_RX_DMA__TERMOUT1_EN 0u
#define SCSI_RX_DMA__TERMOUT1_SEL 0u
/* SCSI_TX_DMA */
#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
#define SCSI_TX_DMA__DRQ_NUMBER 1u
#define SCSI_TX_DMA__NUMBEROF_TDS 0u
#define SCSI_TX_DMA__PRIORITY 2u
#define SCSI_TX_DMA__TERMIN_EN 0u
#define SCSI_TX_DMA__TERMIN_SEL 0u
#define SCSI_TX_DMA__TERMOUT0_EN 1u
#define SCSI_TX_DMA__TERMOUT0_SEL 1u
#define SCSI_TX_DMA__TERMOUT1_EN 0u
#define SCSI_TX_DMA__TERMOUT1_SEL 0u
/* SD_Data_Clk */
#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
@ -1014,16 +1170,16 @@
#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define SD_Data_Clk__PM_STBY_MSK 0x01u
/* SD_Init_Clk */
#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG1_CFG0
#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG1_CFG1
#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG1_CFG2
#define SD_Init_Clk__CFG2_SRC_SEL_MASK 0x07u
#define SD_Init_Clk__INDEX 0x01u
#define SD_Init_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define SD_Init_Clk__PM_ACT_MSK 0x02u
#define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define SD_Init_Clk__PM_STBY_MSK 0x02u
/* timer_clock */
#define timer_clock__CFG0 CYREG_CLKDIST_DCFG1_CFG0
#define timer_clock__CFG1 CYREG_CLKDIST_DCFG1_CFG1
#define timer_clock__CFG2 CYREG_CLKDIST_DCFG1_CFG2
#define timer_clock__CFG2_SRC_SEL_MASK 0x07u
#define timer_clock__INDEX 0x01u
#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define timer_clock__PM_ACT_MSK 0x02u
#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define timer_clock__PM_STBY_MSK 0x02u
/* scsiTarget */
#define scsiTarget_StatusReg__0__MASK 0x01u
@ -1036,77 +1192,57 @@
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
#define scsiTarget_StatusReg__3__POS 3
#define scsiTarget_StatusReg__MASK 0x0Fu
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB13_MSK
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB13_ST
#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST
#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB10_MSK
#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB10_ST_CTL
#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB10_ST_CTL
#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB10_ST
#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB10_CTL
#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB10_CTL
#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB10_MSK
#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB10_11_A0
#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB10_11_A1
#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB10_11_D0
#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB10_11_D1
#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB10_11_F0
#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB10_11_F1
#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB10_A0_A1
#define scsiTarget_datapath__A0_REG CYREG_B0_UDB10_A0
#define scsiTarget_datapath__A1_REG CYREG_B0_UDB10_A1
#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB10_D0_D1
#define scsiTarget_datapath__D0_REG CYREG_B0_UDB10_D0
#define scsiTarget_datapath__D1_REG CYREG_B0_UDB10_D1
#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB10_F0_F1
#define scsiTarget_datapath__F0_REG CYREG_B0_UDB10_F0
#define scsiTarget_datapath__F1_REG CYREG_B0_UDB10_F1
#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
/* SD_Clk_Ctl */
#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST
#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB14_MSK
#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL
#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB14_ST_CTL
#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB14_ST_CTL
#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB14_ST
#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB14_CTL
#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB14_CTL
#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB14_MSK
#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB14_15_A0
#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB14_15_A1
#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB14_15_D0
#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB14_15_D1
#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB14_15_F0
#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB14_15_F1
#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB14_A0_A1
#define scsiTarget_datapath__A0_REG CYREG_B0_UDB14_A0
#define scsiTarget_datapath__A1_REG CYREG_B0_UDB14_A1
#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB14_D0_D1
#define scsiTarget_datapath__D0_REG CYREG_B0_UDB14_D0
#define scsiTarget_datapath__D1_REG CYREG_B0_UDB14_D1
#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB14_ACTL
#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB14_F0_F1
#define scsiTarget_datapath__F0_REG CYREG_B0_UDB14_F0
#define scsiTarget_datapath__F1_REG CYREG_B0_UDB14_F1
#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
/* USBFS_ep_0 */
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -1121,23 +1257,67 @@
/* USBFS_ep_1 */
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ep_1__INTC_MASK 0x01u
#define USBFS_ep_1__INTC_NUMBER 0u
#define USBFS_ep_1__INTC_MASK 0x20u
#define USBFS_ep_1__INTC_NUMBER 5u
#define USBFS_ep_1__INTC_PRIOR_NUM 7u
#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0
#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_5
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_ep_2 */
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ep_2__INTC_MASK 0x02u
#define USBFS_ep_2__INTC_NUMBER 1u
#define USBFS_ep_2__INTC_MASK 0x40u
#define USBFS_ep_2__INTC_NUMBER 6u
#define USBFS_ep_2__INTC_PRIOR_NUM 7u
#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1
#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_6
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_ep_3 */
#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ep_3__INTC_MASK 0x80u
#define USBFS_ep_3__INTC_NUMBER 7u
#define USBFS_ep_3__INTC_PRIOR_NUM 7u
#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_7
#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_ep_4 */
#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_ep_4__INTC_MASK 0x200u
#define USBFS_ep_4__INTC_NUMBER 9u
#define USBFS_ep_4__INTC_PRIOR_NUM 7u
#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9
#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SD_RX_DMA */
#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
#define SD_RX_DMA__DRQ_NUMBER 2u
#define SD_RX_DMA__NUMBEROF_TDS 0u
#define SD_RX_DMA__PRIORITY 1u
#define SD_RX_DMA__TERMIN_EN 0u
#define SD_RX_DMA__TERMIN_SEL 0u
#define SD_RX_DMA__TERMOUT0_EN 1u
#define SD_RX_DMA__TERMOUT0_SEL 2u
#define SD_RX_DMA__TERMOUT1_EN 0u
#define SD_RX_DMA__TERMOUT1_SEL 0u
/* SD_TX_DMA */
#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
#define SD_TX_DMA__DRQ_NUMBER 3u
#define SD_TX_DMA__NUMBEROF_TDS 0u
#define SD_TX_DMA__PRIORITY 2u
#define SD_TX_DMA__TERMIN_EN 0u
#define SD_TX_DMA__TERMIN_SEL 0u
#define SD_TX_DMA__TERMOUT0_EN 1u
#define SD_TX_DMA__TERMOUT0_SEL 3u
#define SD_TX_DMA__TERMOUT1_EN 0u
#define SD_TX_DMA__TERMOUT1_SEL 0u
/* USBFS_USB */
#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
@ -1652,33 +1832,33 @@
#define SCSI_Out__BSY__PS CYREG_PRT6_PS
#define SCSI_Out__BSY__SHIFT 1
#define SCSI_Out__BSY__SLW CYREG_PRT6_SLW
#define SCSI_Out__CD__AG CYREG_PRT0_AG
#define SCSI_Out__CD__AMUX CYREG_PRT0_AMUX
#define SCSI_Out__CD__BIE CYREG_PRT0_BIE
#define SCSI_Out__CD__BIT_MASK CYREG_PRT0_BIT_MASK
#define SCSI_Out__CD__BYP CYREG_PRT0_BYP
#define SCSI_Out__CD__CTL CYREG_PRT0_CTL
#define SCSI_Out__CD__DM0 CYREG_PRT0_DM0
#define SCSI_Out__CD__DM1 CYREG_PRT0_DM1
#define SCSI_Out__CD__DM2 CYREG_PRT0_DM2
#define SCSI_Out__CD__DR CYREG_PRT0_DR
#define SCSI_Out__CD__INP_DIS CYREG_PRT0_INP_DIS
#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__CD__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__CD__MASK 0x40u
#define SCSI_Out__CD__PC CYREG_PRT0_PC6
#define SCSI_Out__CD__PORT 0u
#define SCSI_Out__CD__PRT CYREG_PRT0_PRT
#define SCSI_Out__CD__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define SCSI_Out__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define SCSI_Out__CD__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define SCSI_Out__CD__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define SCSI_Out__CD__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define SCSI_Out__CD__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define SCSI_Out__CD__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define SCSI_Out__CD__PS CYREG_PRT0_PS
#define SCSI_Out__CD__SHIFT 6
#define SCSI_Out__CD__SLW CYREG_PRT0_SLW
#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG
#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX
#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE
#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK
#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP
#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL
#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0
#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1
#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2
#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR
#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS
#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__CD_raw__MASK 0x40u
#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC6
#define SCSI_Out__CD_raw__PORT 0u
#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT
#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS
#define SCSI_Out__CD_raw__SHIFT 6
#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW
#define SCSI_Out__DBP_raw__AG CYREG_PRT15_AG
#define SCSI_Out__DBP_raw__AMUX CYREG_PRT15_AMUX
#define SCSI_Out__DBP_raw__BIE CYREG_PRT15_BIE
@ -1733,33 +1913,33 @@
#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS
#define SCSI_Out__IO_raw__SHIFT 2
#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW
#define SCSI_Out__MSG__AG CYREG_PRT4_AG
#define SCSI_Out__MSG__AMUX CYREG_PRT4_AMUX
#define SCSI_Out__MSG__BIE CYREG_PRT4_BIE
#define SCSI_Out__MSG__BIT_MASK CYREG_PRT4_BIT_MASK
#define SCSI_Out__MSG__BYP CYREG_PRT4_BYP
#define SCSI_Out__MSG__CTL CYREG_PRT4_CTL
#define SCSI_Out__MSG__DM0 CYREG_PRT4_DM0
#define SCSI_Out__MSG__DM1 CYREG_PRT4_DM1
#define SCSI_Out__MSG__DM2 CYREG_PRT4_DM2
#define SCSI_Out__MSG__DR CYREG_PRT4_DR
#define SCSI_Out__MSG__INP_DIS CYREG_PRT4_INP_DIS
#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define SCSI_Out__MSG__LCD_EN CYREG_PRT4_LCD_EN
#define SCSI_Out__MSG__MASK 0x10u
#define SCSI_Out__MSG__PC CYREG_PRT4_PC4
#define SCSI_Out__MSG__PORT 4u
#define SCSI_Out__MSG__PRT CYREG_PRT4_PRT
#define SCSI_Out__MSG__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
#define SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
#define SCSI_Out__MSG__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
#define SCSI_Out__MSG__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
#define SCSI_Out__MSG__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
#define SCSI_Out__MSG__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
#define SCSI_Out__MSG__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
#define SCSI_Out__MSG__PS CYREG_PRT4_PS
#define SCSI_Out__MSG__SHIFT 4
#define SCSI_Out__MSG__SLW CYREG_PRT4_SLW
#define SCSI_Out__MSG_raw__AG CYREG_PRT4_AG
#define SCSI_Out__MSG_raw__AMUX CYREG_PRT4_AMUX
#define SCSI_Out__MSG_raw__BIE CYREG_PRT4_BIE
#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT4_BIT_MASK
#define SCSI_Out__MSG_raw__BYP CYREG_PRT4_BYP
#define SCSI_Out__MSG_raw__CTL CYREG_PRT4_CTL
#define SCSI_Out__MSG_raw__DM0 CYREG_PRT4_DM0
#define SCSI_Out__MSG_raw__DM1 CYREG_PRT4_DM1
#define SCSI_Out__MSG_raw__DM2 CYREG_PRT4_DM2
#define SCSI_Out__MSG_raw__DR CYREG_PRT4_DR
#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT4_INP_DIS
#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT4_LCD_EN
#define SCSI_Out__MSG_raw__MASK 0x10u
#define SCSI_Out__MSG_raw__PC CYREG_PRT4_PC4
#define SCSI_Out__MSG_raw__PORT 4u
#define SCSI_Out__MSG_raw__PRT CYREG_PRT4_PRT
#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
#define SCSI_Out__MSG_raw__PS CYREG_PRT4_PS
#define SCSI_Out__MSG_raw__SHIFT 4
#define SCSI_Out__MSG_raw__SLW CYREG_PRT4_SLW
#define SCSI_Out__REQ__AG CYREG_PRT0_AG
#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX
#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE
@ -2584,9 +2764,9 @@
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_DIE_PSOC5LP 4u
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP
#define BCLK__BUS_CLK__HZ 60000000U
#define BCLK__BUS_CLK__KHZ 60000U
#define BCLK__BUS_CLK__MHZ 60U
#define BCLK__BUS_CLK__HZ 50000000U
#define BCLK__BUS_CLK__KHZ 50000U
#define BCLK__BUS_CLK__MHZ 50U
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PANTHER 3u
@ -2647,7 +2827,7 @@
#define CYDEV_ECC_ENABLE 0
#define CYDEV_HEAP_SIZE 0x1000
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
#define CYDEV_INTR_RISING 0x00000000u
#define CYDEV_INTR_RISING 0x0000001Eu
#define CYDEV_PROJ_TYPE 2
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LOADABLE 2
@ -2678,7 +2858,7 @@
#define CYDEV_VIO2_MV 5000
#define CYDEV_VIO3 3.3
#define CYDEV_VIO3_MV 3300
#define DMA_CHANNELS_USED__MASK0 0x00000000u
#define DMA_CHANNELS_USED__MASK0 0x0000000Fu
#define CYDEV_BOOTLOADER_ENABLE 0
#endif /* INCLUDED_CYFITTER_H */

1897
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c Executable file → Normal file
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File diff suppressed because it is too large Load Diff

598
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfittergnu.inc Executable file → Normal file
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@ -3,6 +3,74 @@
.include "cydevicegnu.inc"
.include "cydevicegnu_trm.inc"
/* Debug_Timer_Interrupt */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set Debug_Timer_Interrupt__INTC_MASK, 0x02
.set Debug_Timer_Interrupt__INTC_NUMBER, 1
.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7
.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_RX_DMA_COMPLETE */
.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01
.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0
.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_TX_DMA_COMPLETE */
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x04
.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 2
.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* Debug_Timer_TimerHW */
.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0
.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1
.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0
.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1
.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2
.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0
.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1
.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0
.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1
.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3
.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01
.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3
.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01
.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0
.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1
.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0
/* SD_RX_DMA_COMPLETE */
.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x08
.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 3
.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SD_TX_DMA_COMPLETE */
.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x10
.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 4
.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_bus_reset */
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
@ -13,6 +81,68 @@
.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
/* SCSI_Out_Bits */
.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3
.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10
.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4
.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20
.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5
.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
/* USBFS_arb_int */
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
@ -33,6 +163,28 @@
.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB08_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB08_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB08_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB08_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB08_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX
@ -478,34 +630,23 @@
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB11_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB11_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB11_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB11_ST
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB11_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB11_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB11_MSK
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@ -513,13 +654,13 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB10_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB10_ST
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
@ -529,26 +670,30 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1
.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1
.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB06_A0
.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB06_A1
.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1
.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB06_D0
.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB06_D1
.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB06_F0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB06_F1
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB08_MSK
.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB08_ST_CTL
.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB08_ST_CTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB08_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB08_09_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB08_09_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB08_09_D0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB08_09_D1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB08_09_F0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB08_09_F1
.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB08_A0_A1
.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB08_A0
.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB08_A1
.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB08_D0_D1
.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB08_D0
.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB08_D1
.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB08_F0_F1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB08_F0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB08_F1
/* USBFS_dp_int */
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -560,19 +705,6 @@
.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_CTL_IO */
.set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL
.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL
.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL
.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL
.set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01
.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK
.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
/* SCSI_In_DBx */
.set SCSI_In_DBx__0__AG, CYREG_PRT5_AG
.set SCSI_In_DBx__0__AMUX, CYREG_PRT5_AMUX
@ -1003,6 +1135,30 @@
.set SCSI_In_DBx__DB7__SHIFT, 4
.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW
/* SCSI_RX_DMA */
.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
.set SCSI_RX_DMA__DRQ_NUMBER, 0
.set SCSI_RX_DMA__NUMBEROF_TDS, 0
.set SCSI_RX_DMA__PRIORITY, 2
.set SCSI_RX_DMA__TERMIN_EN, 0
.set SCSI_RX_DMA__TERMIN_SEL, 0
.set SCSI_RX_DMA__TERMOUT0_EN, 1
.set SCSI_RX_DMA__TERMOUT0_SEL, 0
.set SCSI_RX_DMA__TERMOUT1_EN, 0
.set SCSI_RX_DMA__TERMOUT1_SEL, 0
/* SCSI_TX_DMA */
.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
.set SCSI_TX_DMA__DRQ_NUMBER, 1
.set SCSI_TX_DMA__NUMBEROF_TDS, 0
.set SCSI_TX_DMA__PRIORITY, 2
.set SCSI_TX_DMA__TERMIN_EN, 0
.set SCSI_TX_DMA__TERMIN_SEL, 0
.set SCSI_TX_DMA__TERMOUT0_EN, 1
.set SCSI_TX_DMA__TERMOUT0_SEL, 1
.set SCSI_TX_DMA__TERMOUT1_EN, 0
.set SCSI_TX_DMA__TERMOUT1_SEL, 0
/* SD_Data_Clk */
.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0
.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1
@ -1014,16 +1170,16 @@
.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
.set SD_Data_Clk__PM_STBY_MSK, 0x01
/* SD_Init_Clk */
.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG1_CFG0
.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG1_CFG1
.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG1_CFG2
.set SD_Init_Clk__CFG2_SRC_SEL_MASK, 0x07
.set SD_Init_Clk__INDEX, 0x01
.set SD_Init_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
.set SD_Init_Clk__PM_ACT_MSK, 0x02
.set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
.set SD_Init_Clk__PM_STBY_MSK, 0x02
/* timer_clock */
.set timer_clock__CFG0, CYREG_CLKDIST_DCFG1_CFG0
.set timer_clock__CFG1, CYREG_CLKDIST_DCFG1_CFG1
.set timer_clock__CFG2, CYREG_CLKDIST_DCFG1_CFG2
.set timer_clock__CFG2_SRC_SEL_MASK, 0x07
.set timer_clock__INDEX, 0x01
.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
.set timer_clock__PM_ACT_MSK, 0x02
.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
.set timer_clock__PM_STBY_MSK, 0x02
/* scsiTarget */
.set scsiTarget_StatusReg__0__MASK, 0x01
@ -1036,77 +1192,57 @@
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
.set scsiTarget_StatusReg__3__POS, 3
.set scsiTarget_StatusReg__MASK, 0x0F
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB13_MSK
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB13_ST
.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB10_11_ST
.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB10_MSK
.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB10_ST_CTL
.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB10_ST_CTL
.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB10_ST
.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB10_CTL
.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB10_CTL
.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB10_MSK
.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB10_11_A0
.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB10_11_A1
.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB10_11_D0
.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB10_11_D1
.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB10_11_F0
.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB10_11_F1
.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB10_A0_A1
.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB10_A0
.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB10_A1
.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB10_D0_D1
.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB10_D0
.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB10_D1
.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB10_F0_F1
.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB10_F0
.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB10_F1
.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
/* SD_Clk_Ctl */
.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST
.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB14_MSK
.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB14_ST_CTL
.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB14_ST_CTL
.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB14_ST
.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL
.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL
.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL
.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL
.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK
.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK
.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK
.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK
.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB14_CTL
.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL
.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB14_CTL
.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL
.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB14_MSK
.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB14_15_A0
.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB14_15_A1
.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB14_15_D0
.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB14_15_D1
.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB14_15_F0
.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB14_15_F1
.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB14_A0_A1
.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB14_A0
.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB14_A1
.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB14_D0_D1
.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB14_D0
.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB14_D1
.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB14_F0_F1
.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB14_F0
.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB14_F1
.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
/* USBFS_ep_0 */
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -1121,23 +1257,67 @@
/* USBFS_ep_1 */
.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set USBFS_ep_1__INTC_MASK, 0x01
.set USBFS_ep_1__INTC_NUMBER, 0
.set USBFS_ep_1__INTC_MASK, 0x20
.set USBFS_ep_1__INTC_NUMBER, 5
.set USBFS_ep_1__INTC_PRIOR_NUM, 7
.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_ep_2 */
.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set USBFS_ep_2__INTC_MASK, 0x02
.set USBFS_ep_2__INTC_NUMBER, 1
.set USBFS_ep_2__INTC_MASK, 0x40
.set USBFS_ep_2__INTC_NUMBER, 6
.set USBFS_ep_2__INTC_PRIOR_NUM, 7
.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_ep_3 */
.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set USBFS_ep_3__INTC_MASK, 0x80
.set USBFS_ep_3__INTC_NUMBER, 7
.set USBFS_ep_3__INTC_PRIOR_NUM, 7
.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_ep_4 */
.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set USBFS_ep_4__INTC_MASK, 0x200
.set USBFS_ep_4__INTC_NUMBER, 9
.set USBFS_ep_4__INTC_PRIOR_NUM, 7
.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SD_RX_DMA */
.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
.set SD_RX_DMA__DRQ_NUMBER, 2
.set SD_RX_DMA__NUMBEROF_TDS, 0
.set SD_RX_DMA__PRIORITY, 1
.set SD_RX_DMA__TERMIN_EN, 0
.set SD_RX_DMA__TERMIN_SEL, 0
.set SD_RX_DMA__TERMOUT0_EN, 1
.set SD_RX_DMA__TERMOUT0_SEL, 2
.set SD_RX_DMA__TERMOUT1_EN, 0
.set SD_RX_DMA__TERMOUT1_SEL, 0
/* SD_TX_DMA */
.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
.set SD_TX_DMA__DRQ_NUMBER, 3
.set SD_TX_DMA__NUMBEROF_TDS, 0
.set SD_TX_DMA__PRIORITY, 2
.set SD_TX_DMA__TERMIN_EN, 0
.set SD_TX_DMA__TERMIN_SEL, 0
.set SD_TX_DMA__TERMOUT0_EN, 1
.set SD_TX_DMA__TERMOUT0_SEL, 3
.set SD_TX_DMA__TERMOUT1_EN, 0
.set SD_TX_DMA__TERMOUT1_SEL, 0
/* USBFS_USB */
.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG
.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
@ -1652,33 +1832,33 @@
.set SCSI_Out__BSY__PS, CYREG_PRT6_PS
.set SCSI_Out__BSY__SHIFT, 1
.set SCSI_Out__BSY__SLW, CYREG_PRT6_SLW
.set SCSI_Out__CD__AG, CYREG_PRT0_AG
.set SCSI_Out__CD__AMUX, CYREG_PRT0_AMUX
.set SCSI_Out__CD__BIE, CYREG_PRT0_BIE
.set SCSI_Out__CD__BIT_MASK, CYREG_PRT0_BIT_MASK
.set SCSI_Out__CD__BYP, CYREG_PRT0_BYP
.set SCSI_Out__CD__CTL, CYREG_PRT0_CTL
.set SCSI_Out__CD__DM0, CYREG_PRT0_DM0
.set SCSI_Out__CD__DM1, CYREG_PRT0_DM1
.set SCSI_Out__CD__DM2, CYREG_PRT0_DM2
.set SCSI_Out__CD__DR, CYREG_PRT0_DR
.set SCSI_Out__CD__INP_DIS, CYREG_PRT0_INP_DIS
.set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__CD__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__CD__MASK, 0x40
.set SCSI_Out__CD__PC, CYREG_PRT0_PC6
.set SCSI_Out__CD__PORT, 0
.set SCSI_Out__CD__PRT, CYREG_PRT0_PRT
.set SCSI_Out__CD__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
.set SCSI_Out__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
.set SCSI_Out__CD__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
.set SCSI_Out__CD__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
.set SCSI_Out__CD__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
.set SCSI_Out__CD__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
.set SCSI_Out__CD__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
.set SCSI_Out__CD__PS, CYREG_PRT0_PS
.set SCSI_Out__CD__SHIFT, 6
.set SCSI_Out__CD__SLW, CYREG_PRT0_SLW
.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG
.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX
.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE
.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP
.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL
.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0
.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1
.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2
.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR
.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS
.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__CD_raw__MASK, 0x40
.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC6
.set SCSI_Out__CD_raw__PORT, 0
.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT
.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS
.set SCSI_Out__CD_raw__SHIFT, 6
.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW
.set SCSI_Out__DBP_raw__AG, CYREG_PRT15_AG
.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT15_AMUX
.set SCSI_Out__DBP_raw__BIE, CYREG_PRT15_BIE
@ -1733,33 +1913,33 @@
.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS
.set SCSI_Out__IO_raw__SHIFT, 2
.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW
.set SCSI_Out__MSG__AG, CYREG_PRT4_AG
.set SCSI_Out__MSG__AMUX, CYREG_PRT4_AMUX
.set SCSI_Out__MSG__BIE, CYREG_PRT4_BIE
.set SCSI_Out__MSG__BIT_MASK, CYREG_PRT4_BIT_MASK
.set SCSI_Out__MSG__BYP, CYREG_PRT4_BYP
.set SCSI_Out__MSG__CTL, CYREG_PRT4_CTL
.set SCSI_Out__MSG__DM0, CYREG_PRT4_DM0
.set SCSI_Out__MSG__DM1, CYREG_PRT4_DM1
.set SCSI_Out__MSG__DM2, CYREG_PRT4_DM2
.set SCSI_Out__MSG__DR, CYREG_PRT4_DR
.set SCSI_Out__MSG__INP_DIS, CYREG_PRT4_INP_DIS
.set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
.set SCSI_Out__MSG__LCD_EN, CYREG_PRT4_LCD_EN
.set SCSI_Out__MSG__MASK, 0x10
.set SCSI_Out__MSG__PC, CYREG_PRT4_PC4
.set SCSI_Out__MSG__PORT, 4
.set SCSI_Out__MSG__PRT, CYREG_PRT4_PRT
.set SCSI_Out__MSG__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
.set SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
.set SCSI_Out__MSG__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
.set SCSI_Out__MSG__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
.set SCSI_Out__MSG__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
.set SCSI_Out__MSG__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
.set SCSI_Out__MSG__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
.set SCSI_Out__MSG__PS, CYREG_PRT4_PS
.set SCSI_Out__MSG__SHIFT, 4
.set SCSI_Out__MSG__SLW, CYREG_PRT4_SLW
.set SCSI_Out__MSG_raw__AG, CYREG_PRT4_AG
.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT4_AMUX
.set SCSI_Out__MSG_raw__BIE, CYREG_PRT4_BIE
.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT4_BIT_MASK
.set SCSI_Out__MSG_raw__BYP, CYREG_PRT4_BYP
.set SCSI_Out__MSG_raw__CTL, CYREG_PRT4_CTL
.set SCSI_Out__MSG_raw__DM0, CYREG_PRT4_DM0
.set SCSI_Out__MSG_raw__DM1, CYREG_PRT4_DM1
.set SCSI_Out__MSG_raw__DM2, CYREG_PRT4_DM2
.set SCSI_Out__MSG_raw__DR, CYREG_PRT4_DR
.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT4_INP_DIS
.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT4_LCD_EN
.set SCSI_Out__MSG_raw__MASK, 0x10
.set SCSI_Out__MSG_raw__PC, CYREG_PRT4_PC4
.set SCSI_Out__MSG_raw__PORT, 4
.set SCSI_Out__MSG_raw__PRT, CYREG_PRT4_PRT
.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
.set SCSI_Out__MSG_raw__PS, CYREG_PRT4_PS
.set SCSI_Out__MSG_raw__SHIFT, 4
.set SCSI_Out__MSG_raw__SLW, CYREG_PRT4_SLW
.set SCSI_Out__REQ__AG, CYREG_PRT0_AG
.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX
.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE
@ -2584,9 +2764,9 @@
.set CYDEV_CHIP_FAMILY_PSOC5, 3
.set CYDEV_CHIP_DIE_PSOC5LP, 4
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP
.set BCLK__BUS_CLK__HZ, 60000000
.set BCLK__BUS_CLK__KHZ, 60000
.set BCLK__BUS_CLK__MHZ, 60
.set BCLK__BUS_CLK__HZ, 50000000
.set BCLK__BUS_CLK__KHZ, 50000
.set BCLK__BUS_CLK__MHZ, 50
.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
.set CYDEV_CHIP_DIE_LEOPARD, 1
.set CYDEV_CHIP_DIE_PANTHER, 3
@ -2647,7 +2827,7 @@
.set CYDEV_ECC_ENABLE, 0
.set CYDEV_HEAP_SIZE, 0x1000
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1
.set CYDEV_INTR_RISING, 0x00000000
.set CYDEV_INTR_RISING, 0x0000001E
.set CYDEV_PROJ_TYPE, 2
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
.set CYDEV_PROJ_TYPE_LOADABLE, 2
@ -2671,6 +2851,6 @@
.set CYDEV_VIO2, 5
.set CYDEV_VIO2_MV, 5000
.set CYDEV_VIO3_MV, 3300
.set DMA_CHANNELS_USED__MASK0, 0x00000000
.set DMA_CHANNELS_USED__MASK0, 0x0000000F
.set CYDEV_BOOTLOADER_ENABLE, 0
.endif

598
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitteriar.inc Executable file → Normal file
View File

@ -3,6 +3,74 @@
INCLUDE cydeviceiar.inc
INCLUDE cydeviceiar_trm.inc
/* Debug_Timer_Interrupt */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
Debug_Timer_Interrupt__INTC_MASK EQU 0x02
Debug_Timer_Interrupt__INTC_NUMBER EQU 1
Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_RX_DMA_COMPLETE */
SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_TX_DMA_COMPLETE */
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04
SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* Debug_Timer_TimerHW */
Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
/* SD_RX_DMA_COMPLETE */
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08
SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SD_TX_DMA_COMPLETE */
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_bus_reset */
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@ -13,6 +81,68 @@ USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
/* SCSI_Out_Bits */
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
/* USBFS_arb_int */
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@ -33,6 +163,28 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
@ -478,34 +630,23 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB11_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB11_ST
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB11_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB11_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB11_MSK
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -513,13 +654,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
@ -529,26 +670,30 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB08_09_D0
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB08_09_D1
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB08_09_F0
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB08_09_F1
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB08_A0_A1
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB08_A0
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB08_A1
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB08_D0_D1
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB08_D0
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB08_D1
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB08_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB08_F1
/* USBFS_dp_int */
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -560,19 +705,6 @@ USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_CTL_IO */
SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01
SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
/* SCSI_In_DBx */
SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG
SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX
@ -1003,6 +1135,30 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
SCSI_In_DBx__DB7__SHIFT EQU 4
SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
/* SCSI_RX_DMA */
SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
SCSI_RX_DMA__DRQ_NUMBER EQU 0
SCSI_RX_DMA__NUMBEROF_TDS EQU 0
SCSI_RX_DMA__PRIORITY EQU 2
SCSI_RX_DMA__TERMIN_EN EQU 0
SCSI_RX_DMA__TERMIN_SEL EQU 0
SCSI_RX_DMA__TERMOUT0_EN EQU 1
SCSI_RX_DMA__TERMOUT0_SEL EQU 0
SCSI_RX_DMA__TERMOUT1_EN EQU 0
SCSI_RX_DMA__TERMOUT1_SEL EQU 0
/* SCSI_TX_DMA */
SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
SCSI_TX_DMA__DRQ_NUMBER EQU 1
SCSI_TX_DMA__NUMBEROF_TDS EQU 0
SCSI_TX_DMA__PRIORITY EQU 2
SCSI_TX_DMA__TERMIN_EN EQU 0
SCSI_TX_DMA__TERMIN_SEL EQU 0
SCSI_TX_DMA__TERMOUT0_EN EQU 1
SCSI_TX_DMA__TERMOUT0_SEL EQU 1
SCSI_TX_DMA__TERMOUT1_EN EQU 0
SCSI_TX_DMA__TERMOUT1_SEL EQU 0
/* SD_Data_Clk */
SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
@ -1014,16 +1170,16 @@ SD_Data_Clk__PM_ACT_MSK EQU 0x01
SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SD_Data_Clk__PM_STBY_MSK EQU 0x01
/* SD_Init_Clk */
SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07
SD_Init_Clk__INDEX EQU 0x01
SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
SD_Init_Clk__PM_ACT_MSK EQU 0x02
SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SD_Init_Clk__PM_STBY_MSK EQU 0x02
/* timer_clock */
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
timer_clock__INDEX EQU 0x01
timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
timer_clock__PM_ACT_MSK EQU 0x02
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
timer_clock__PM_STBY_MSK EQU 0x02
/* scsiTarget */
scsiTarget_StatusReg__0__MASK EQU 0x01
@ -1036,77 +1192,57 @@ scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__MASK EQU 0x0F
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB10_MSK
scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB10_ST_CTL
scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB10_ST_CTL
scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB10_ST
scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB10_CTL
scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB10_CTL
scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB10_MSK
scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB10_11_A0
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB10_11_A1
scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB10_11_D0
scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB10_11_D1
scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB10_11_F0
scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB10_11_F1
scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB10_A0_A1
scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB10_A0
scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB10_A1
scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB10_D0_D1
scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB10_D0
scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB10_D1
scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB10_F0_F1
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB10_F0
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB10_F1
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
/* SD_Clk_Ctl */
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB14_MSK
scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB14_ST_CTL
scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB14_ST_CTL
scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB14_ST
scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB14_CTL
scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB14_CTL
scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB14_MSK
scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB14_15_A0
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB14_15_A1
scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB14_15_D0
scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB14_15_D1
scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB14_15_F0
scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB14_15_F1
scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB14_A0_A1
scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB14_A0
scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB14_A1
scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB14_D0_D1
scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB14_D0
scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB14_D1
scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB14_F0_F1
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB14_F0
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB14_F1
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
/* USBFS_ep_0 */
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -1121,23 +1257,67 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_ep_1 */
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_1__INTC_MASK EQU 0x01
USBFS_ep_1__INTC_NUMBER EQU 0
USBFS_ep_1__INTC_MASK EQU 0x20
USBFS_ep_1__INTC_NUMBER EQU 5
USBFS_ep_1__INTC_PRIOR_NUM EQU 7
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_ep_2 */
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_2__INTC_MASK EQU 0x02
USBFS_ep_2__INTC_NUMBER EQU 1
USBFS_ep_2__INTC_MASK EQU 0x40
USBFS_ep_2__INTC_NUMBER EQU 6
USBFS_ep_2__INTC_PRIOR_NUM EQU 7
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_ep_3 */
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_3__INTC_MASK EQU 0x80
USBFS_ep_3__INTC_NUMBER EQU 7
USBFS_ep_3__INTC_PRIOR_NUM EQU 7
USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_ep_4 */
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_4__INTC_MASK EQU 0x200
USBFS_ep_4__INTC_NUMBER EQU 9
USBFS_ep_4__INTC_PRIOR_NUM EQU 7
USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SD_RX_DMA */
SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
SD_RX_DMA__DRQ_NUMBER EQU 2
SD_RX_DMA__NUMBEROF_TDS EQU 0
SD_RX_DMA__PRIORITY EQU 1
SD_RX_DMA__TERMIN_EN EQU 0
SD_RX_DMA__TERMIN_SEL EQU 0
SD_RX_DMA__TERMOUT0_EN EQU 1
SD_RX_DMA__TERMOUT0_SEL EQU 2
SD_RX_DMA__TERMOUT1_EN EQU 0
SD_RX_DMA__TERMOUT1_SEL EQU 0
/* SD_TX_DMA */
SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
SD_TX_DMA__DRQ_NUMBER EQU 3
SD_TX_DMA__NUMBEROF_TDS EQU 0
SD_TX_DMA__PRIORITY EQU 2
SD_TX_DMA__TERMIN_EN EQU 0
SD_TX_DMA__TERMIN_SEL EQU 0
SD_TX_DMA__TERMOUT0_EN EQU 1
SD_TX_DMA__TERMOUT0_SEL EQU 3
SD_TX_DMA__TERMOUT1_EN EQU 0
SD_TX_DMA__TERMOUT1_SEL EQU 0
/* USBFS_USB */
USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
@ -1652,33 +1832,33 @@ SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
SCSI_Out__BSY__PS EQU CYREG_PRT6_PS
SCSI_Out__BSY__SHIFT EQU 1
SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW
SCSI_Out__CD__AG EQU CYREG_PRT0_AG
SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX
SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE
SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK
SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP
SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL
SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0
SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__CD__DR EQU CYREG_PRT0_DR
SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__CD__MASK EQU 0x40
SCSI_Out__CD__PC EQU CYREG_PRT0_PC6
SCSI_Out__CD__PORT EQU 0
SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT
SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
SCSI_Out__CD__PS EQU CYREG_PRT0_PS
SCSI_Out__CD__SHIFT EQU 6
SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW
SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__CD_raw__MASK EQU 0x40
SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6
SCSI_Out__CD_raw__PORT EQU 0
SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
SCSI_Out__CD_raw__SHIFT EQU 6
SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG
SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX
SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE
@ -1733,33 +1913,33 @@ SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
SCSI_Out__IO_raw__SHIFT EQU 2
SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
SCSI_Out__MSG__AG EQU CYREG_PRT4_AG
SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX
SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE
SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK
SCSI_Out__MSG__BYP EQU CYREG_PRT4_BYP
SCSI_Out__MSG__CTL EQU CYREG_PRT4_CTL
SCSI_Out__MSG__DM0 EQU CYREG_PRT4_DM0
SCSI_Out__MSG__DM1 EQU CYREG_PRT4_DM1
SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__MSG__DR EQU CYREG_PRT4_DR
SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS
SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__MSG__MASK EQU 0x10
SCSI_Out__MSG__PC EQU CYREG_PRT4_PC4
SCSI_Out__MSG__PORT EQU 4
SCSI_Out__MSG__PRT EQU CYREG_PRT4_PRT
SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
SCSI_Out__MSG__PS EQU CYREG_PRT4_PS
SCSI_Out__MSG__SHIFT EQU 4
SCSI_Out__MSG__SLW EQU CYREG_PRT4_SLW
SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG
SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX
SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE
SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP
SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL
SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0
SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1
SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR
SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__MSG_raw__MASK EQU 0x10
SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4
SCSI_Out__MSG_raw__PORT EQU 4
SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT
SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS
SCSI_Out__MSG_raw__SHIFT EQU 4
SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW
SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
@ -2584,9 +2764,9 @@ CYDEV_CHIP_MEMBER_5B EQU 4
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_DIE_PSOC5LP EQU 4
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
BCLK__BUS_CLK__HZ EQU 60000000
BCLK__BUS_CLK__KHZ EQU 60000
BCLK__BUS_CLK__MHZ EQU 60
BCLK__BUS_CLK__HZ EQU 50000000
BCLK__BUS_CLK__KHZ EQU 50000
BCLK__BUS_CLK__MHZ EQU 50
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PANTHER EQU 3
@ -2647,7 +2827,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x1000
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x00000000
CYDEV_INTR_RISING EQU 0x0000001E
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
@ -2671,7 +2851,7 @@ CYDEV_VIO1_MV EQU 5000
CYDEV_VIO2 EQU 5
CYDEV_VIO2_MV EQU 5000
CYDEV_VIO3_MV EQU 3300
DMA_CHANNELS_USED__MASK0 EQU 0x00000000
DMA_CHANNELS_USED__MASK0 EQU 0x0000000F
CYDEV_BOOTLOADER_ENABLE EQU 0
#endif /* INCLUDED_CYFITTERIAR_INC */

598
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitterrv.inc Executable file → Normal file
View File

@ -3,6 +3,74 @@ INCLUDED_CYFITTERRV_INC EQU 1
GET cydevicerv.inc
GET cydevicerv_trm.inc
; Debug_Timer_Interrupt
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
Debug_Timer_Interrupt__INTC_MASK EQU 0x02
Debug_Timer_Interrupt__INTC_NUMBER EQU 1
Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_RX_DMA_COMPLETE
SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_TX_DMA_COMPLETE
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04
SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; Debug_Timer_TimerHW
Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
; SD_RX_DMA_COMPLETE
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08
SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SD_TX_DMA_COMPLETE
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_bus_reset
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@ -13,6 +81,68 @@ USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
; SCSI_Out_Bits
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
; USBFS_arb_int
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@ -33,6 +163,28 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
@ -478,34 +630,23 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SDCard_BSPIM
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB11_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB11_ST
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB11_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB11_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB11_MSK
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -513,13 +654,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
@ -529,26 +670,30 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB08_09_D0
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB08_09_D1
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB08_09_F0
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB08_09_F1
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB08_A0_A1
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB08_A0
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB08_A1
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB08_D0_D1
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB08_D0
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB08_D1
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB08_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB08_F1
; USBFS_dp_int
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -560,19 +705,6 @@ USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_CTL_IO
SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01
SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
; SCSI_In_DBx
SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG
SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX
@ -1003,6 +1135,30 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
SCSI_In_DBx__DB7__SHIFT EQU 4
SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
; SCSI_RX_DMA
SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
SCSI_RX_DMA__DRQ_NUMBER EQU 0
SCSI_RX_DMA__NUMBEROF_TDS EQU 0
SCSI_RX_DMA__PRIORITY EQU 2
SCSI_RX_DMA__TERMIN_EN EQU 0
SCSI_RX_DMA__TERMIN_SEL EQU 0
SCSI_RX_DMA__TERMOUT0_EN EQU 1
SCSI_RX_DMA__TERMOUT0_SEL EQU 0
SCSI_RX_DMA__TERMOUT1_EN EQU 0
SCSI_RX_DMA__TERMOUT1_SEL EQU 0
; SCSI_TX_DMA
SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
SCSI_TX_DMA__DRQ_NUMBER EQU 1
SCSI_TX_DMA__NUMBEROF_TDS EQU 0
SCSI_TX_DMA__PRIORITY EQU 2
SCSI_TX_DMA__TERMIN_EN EQU 0
SCSI_TX_DMA__TERMIN_SEL EQU 0
SCSI_TX_DMA__TERMOUT0_EN EQU 1
SCSI_TX_DMA__TERMOUT0_SEL EQU 1
SCSI_TX_DMA__TERMOUT1_EN EQU 0
SCSI_TX_DMA__TERMOUT1_SEL EQU 0
; SD_Data_Clk
SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
@ -1014,16 +1170,16 @@ SD_Data_Clk__PM_ACT_MSK EQU 0x01
SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SD_Data_Clk__PM_STBY_MSK EQU 0x01
; SD_Init_Clk
SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07
SD_Init_Clk__INDEX EQU 0x01
SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
SD_Init_Clk__PM_ACT_MSK EQU 0x02
SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SD_Init_Clk__PM_STBY_MSK EQU 0x02
; timer_clock
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
timer_clock__INDEX EQU 0x01
timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
timer_clock__PM_ACT_MSK EQU 0x02
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
timer_clock__PM_STBY_MSK EQU 0x02
; scsiTarget
scsiTarget_StatusReg__0__MASK EQU 0x01
@ -1036,77 +1192,57 @@ scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__MASK EQU 0x0F
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB10_MSK
scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB10_ST_CTL
scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB10_ST_CTL
scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB10_ST
scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB10_CTL
scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB10_CTL
scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB10_MSK
scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB10_11_A0
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB10_11_A1
scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB10_11_D0
scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB10_11_D1
scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB10_11_F0
scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB10_11_F1
scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB10_A0_A1
scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB10_A0
scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB10_A1
scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB10_D0_D1
scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB10_D0
scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB10_D1
scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB10_F0_F1
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB10_F0
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB10_F1
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
; SD_Clk_Ctl
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB14_MSK
scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB14_ST_CTL
scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB14_ST_CTL
scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB14_ST
scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB14_CTL
scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB14_CTL
scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB14_MSK
scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB14_15_A0
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB14_15_A1
scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB14_15_D0
scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB14_15_D1
scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB14_15_F0
scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB14_15_F1
scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB14_A0_A1
scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB14_A0
scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB14_A1
scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB14_D0_D1
scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB14_D0
scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB14_D1
scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB14_F0_F1
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB14_F0
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB14_F1
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
; USBFS_ep_0
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -1121,23 +1257,67 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_ep_1
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_1__INTC_MASK EQU 0x01
USBFS_ep_1__INTC_NUMBER EQU 0
USBFS_ep_1__INTC_MASK EQU 0x20
USBFS_ep_1__INTC_NUMBER EQU 5
USBFS_ep_1__INTC_PRIOR_NUM EQU 7
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_ep_2
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_2__INTC_MASK EQU 0x02
USBFS_ep_2__INTC_NUMBER EQU 1
USBFS_ep_2__INTC_MASK EQU 0x40
USBFS_ep_2__INTC_NUMBER EQU 6
USBFS_ep_2__INTC_PRIOR_NUM EQU 7
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_ep_3
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_3__INTC_MASK EQU 0x80
USBFS_ep_3__INTC_NUMBER EQU 7
USBFS_ep_3__INTC_PRIOR_NUM EQU 7
USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_ep_4
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_4__INTC_MASK EQU 0x200
USBFS_ep_4__INTC_NUMBER EQU 9
USBFS_ep_4__INTC_PRIOR_NUM EQU 7
USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SD_RX_DMA
SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
SD_RX_DMA__DRQ_NUMBER EQU 2
SD_RX_DMA__NUMBEROF_TDS EQU 0
SD_RX_DMA__PRIORITY EQU 1
SD_RX_DMA__TERMIN_EN EQU 0
SD_RX_DMA__TERMIN_SEL EQU 0
SD_RX_DMA__TERMOUT0_EN EQU 1
SD_RX_DMA__TERMOUT0_SEL EQU 2
SD_RX_DMA__TERMOUT1_EN EQU 0
SD_RX_DMA__TERMOUT1_SEL EQU 0
; SD_TX_DMA
SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
SD_TX_DMA__DRQ_NUMBER EQU 3
SD_TX_DMA__NUMBEROF_TDS EQU 0
SD_TX_DMA__PRIORITY EQU 2
SD_TX_DMA__TERMIN_EN EQU 0
SD_TX_DMA__TERMIN_SEL EQU 0
SD_TX_DMA__TERMOUT0_EN EQU 1
SD_TX_DMA__TERMOUT0_SEL EQU 3
SD_TX_DMA__TERMOUT1_EN EQU 0
SD_TX_DMA__TERMOUT1_SEL EQU 0
; USBFS_USB
USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
@ -1652,33 +1832,33 @@ SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
SCSI_Out__BSY__PS EQU CYREG_PRT6_PS
SCSI_Out__BSY__SHIFT EQU 1
SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW
SCSI_Out__CD__AG EQU CYREG_PRT0_AG
SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX
SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE
SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK
SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP
SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL
SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0
SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__CD__DR EQU CYREG_PRT0_DR
SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__CD__MASK EQU 0x40
SCSI_Out__CD__PC EQU CYREG_PRT0_PC6
SCSI_Out__CD__PORT EQU 0
SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT
SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
SCSI_Out__CD__PS EQU CYREG_PRT0_PS
SCSI_Out__CD__SHIFT EQU 6
SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW
SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__CD_raw__MASK EQU 0x40
SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6
SCSI_Out__CD_raw__PORT EQU 0
SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
SCSI_Out__CD_raw__SHIFT EQU 6
SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG
SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX
SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE
@ -1733,33 +1913,33 @@ SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
SCSI_Out__IO_raw__SHIFT EQU 2
SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
SCSI_Out__MSG__AG EQU CYREG_PRT4_AG
SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX
SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE
SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK
SCSI_Out__MSG__BYP EQU CYREG_PRT4_BYP
SCSI_Out__MSG__CTL EQU CYREG_PRT4_CTL
SCSI_Out__MSG__DM0 EQU CYREG_PRT4_DM0
SCSI_Out__MSG__DM1 EQU CYREG_PRT4_DM1
SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__MSG__DR EQU CYREG_PRT4_DR
SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS
SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__MSG__MASK EQU 0x10
SCSI_Out__MSG__PC EQU CYREG_PRT4_PC4
SCSI_Out__MSG__PORT EQU 4
SCSI_Out__MSG__PRT EQU CYREG_PRT4_PRT
SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
SCSI_Out__MSG__PS EQU CYREG_PRT4_PS
SCSI_Out__MSG__SHIFT EQU 4
SCSI_Out__MSG__SLW EQU CYREG_PRT4_SLW
SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG
SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX
SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE
SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP
SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL
SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0
SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1
SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR
SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__MSG_raw__MASK EQU 0x10
SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4
SCSI_Out__MSG_raw__PORT EQU 4
SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT
SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS
SCSI_Out__MSG_raw__SHIFT EQU 4
SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW
SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
@ -2584,9 +2764,9 @@ CYDEV_CHIP_MEMBER_5B EQU 4
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_DIE_PSOC5LP EQU 4
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
BCLK__BUS_CLK__HZ EQU 60000000
BCLK__BUS_CLK__KHZ EQU 60000
BCLK__BUS_CLK__MHZ EQU 60
BCLK__BUS_CLK__HZ EQU 50000000
BCLK__BUS_CLK__KHZ EQU 50000
BCLK__BUS_CLK__MHZ EQU 50
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PANTHER EQU 3
@ -2647,7 +2827,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x1000
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x00000000
CYDEV_INTR_RISING EQU 0x0000001E
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
@ -2671,7 +2851,7 @@ CYDEV_VIO1_MV EQU 5000
CYDEV_VIO2 EQU 5
CYDEV_VIO2_MV EQU 5000
CYDEV_VIO3_MV EQU 3300
DMA_CHANNELS_USED__MASK0 EQU 0x00000000
DMA_CHANNELS_USED__MASK0 EQU 0x0000000F
CYDEV_BOOTLOADER_ENABLE EQU 0
ENDIF
END

17
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/project.h Executable file → Normal file
View File

@ -21,12 +21,13 @@
#include <cydisabledsheets.h>
#include <SCSI_In_DBx_aliases.h>
#include <SCSI_Out_DBx_aliases.h>
#include <SD_Clk_Ctl.h>
#include <SD_TX_DMA_dma.h>
#include <SD_RX_DMA_COMPLETE.h>
#include <SD_Data_Clk.h>
#include <SD_Init_Clk.h>
#include <SD_RX_DMA_dma.h>
#include <SD_CD_aliases.h>
#include <SD_CD.h>
#include <SCSI_CTL_IO.h>
#include <SCSI_CTL_PHASE.h>
#include <SCSI_In_aliases.h>
#include <SCSI_Out_aliases.h>
#include <CFG_EEPROM.h>
@ -54,6 +55,16 @@
#include <USBFS_midi.h>
#include <USBFS_pvt.h>
#include <Bootloadable_1.h>
#include <SD_TX_DMA_COMPLETE.h>
#include <SCSI_TX_DMA_dma.h>
#include <SCSI_RX_DMA_dma.h>
#include <SCSI_TX_DMA_COMPLETE.h>
#include <SCSI_RX_DMA_COMPLETE.h>
#include <SCSI_Out_Bits.h>
#include <SCSI_Out_Ctl.h>
#include <Debug_Timer.h>
#include <timer_clock.h>
#include <Debug_Timer_Interrupt.h>
#include <USBFS_Dm_aliases.h>
#include <USBFS_Dm.h>
#include <USBFS_Dp_aliases.h>

521
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/timer_clock.c Normal file
View File

@ -0,0 +1,521 @@
/*******************************************************************************
* File Name: timer_clock.c
* Version 2.10
*
* Description:
* This file provides the source code to the API for the clock component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include "timer_clock.h"
/* Clock Distribution registers. */
#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)
#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)
#define BCFG2_MASK (0x80u)
#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)
#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)
#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)
/*******************************************************************************
* Function Name: timer_clock_Start
********************************************************************************
*
* Summary:
* Starts the clock. Note that on startup, clocks may be already running if the
* "Start on Reset" option is enabled in the DWR.
*
* Parameters:
* None
*
* Returns:
* None
*
*******************************************************************************/
void timer_clock_Start(void)
{
/* Set the bit to enable the clock. */
timer_clock_CLKEN |= timer_clock_CLKEN_MASK;
timer_clock_CLKSTBY |= timer_clock_CLKSTBY_MASK;
}
/*******************************************************************************
* Function Name: timer_clock_Stop
********************************************************************************
*
* Summary:
* Stops the clock and returns immediately. This API does not require the
* source clock to be running but may return before the hardware is actually
* disabled. If the settings of the clock are changed after calling this
* function, the clock may glitch when it is started. To avoid the clock
* glitch, use the StopBlock function.
*
* Parameters:
* None
*
* Returns:
* None
*
*******************************************************************************/
void timer_clock_Stop(void)
{
/* Clear the bit to disable the clock. */
timer_clock_CLKEN &= (uint8)(~timer_clock_CLKEN_MASK);
timer_clock_CLKSTBY &= (uint8)(~timer_clock_CLKSTBY_MASK);
}
#if(CY_PSOC3 || CY_PSOC5LP)
/*******************************************************************************
* Function Name: timer_clock_StopBlock
********************************************************************************
*
* Summary:
* Stops the clock and waits for the hardware to actually be disabled before
* returning. This ensures that the clock is never truncated (high part of the
* cycle will terminate before the clock is disabled and the API returns).
* Note that the source clock must be running or this API will never return as
* a stopped clock cannot be disabled.
*
* Parameters:
* None
*
* Returns:
* None
*
*******************************************************************************/
void timer_clock_StopBlock(void)
{
if ((timer_clock_CLKEN & timer_clock_CLKEN_MASK) != 0u)
{
#if HAS_CLKDIST_LD_DISABLE
uint16 oldDivider;
CLK_DIST_LD = 0u;
/* Clear all the mask bits except ours. */
#if defined(timer_clock__CFG3)
CLK_DIST_AMASK = timer_clock_CLKEN_MASK;
CLK_DIST_DMASK = 0x00u;
#else
CLK_DIST_DMASK = timer_clock_CLKEN_MASK;
CLK_DIST_AMASK = 0x00u;
#endif /* timer_clock__CFG3 */
/* Clear mask of bus clock. */
CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
oldDivider = CY_GET_REG16(timer_clock_DIV_PTR);
CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
/* Wait for clock to be disabled */
while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
#endif /* HAS_CLKDIST_LD_DISABLE */
/* Clear the bit to disable the clock. */
timer_clock_CLKEN &= (uint8)(~timer_clock_CLKEN_MASK);
timer_clock_CLKSTBY &= (uint8)(~timer_clock_CLKSTBY_MASK);
#if HAS_CLKDIST_LD_DISABLE
/* Clear the disable bit */
CLK_DIST_LD = 0x00u;
CY_SET_REG16(timer_clock_DIV_PTR, oldDivider);
#endif /* HAS_CLKDIST_LD_DISABLE */
}
}
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/*******************************************************************************
* Function Name: timer_clock_StandbyPower
********************************************************************************
*
* Summary:
* Sets whether the clock is active in standby mode.
*
* Parameters:
* state: 0 to disable clock during standby, nonzero to enable.
*
* Returns:
* None
*
*******************************************************************************/
void timer_clock_StandbyPower(uint8 state)
{
if(state == 0u)
{
timer_clock_CLKSTBY &= (uint8)(~timer_clock_CLKSTBY_MASK);
}
else
{
timer_clock_CLKSTBY |= timer_clock_CLKSTBY_MASK;
}
}
/*******************************************************************************
* Function Name: timer_clock_SetDividerRegister
********************************************************************************
*
* Summary:
* Modifies the clock divider and, thus, the frequency. When the clock divider
* register is set to zero or changed from zero, the clock will be temporarily
* disabled in order to change the SSS mode bit. If the clock is enabled when
* SetDividerRegister is called, then the source clock must be running.
*
* Parameters:
* clkDivider: Divider register value (0-65,535). This value is NOT the
* divider; the clock hardware divides by clkDivider plus one. For example,
* to divide the clock by 2, this parameter should be set to 1.
* restart: If nonzero, restarts the clock divider: the current clock cycle
* will be truncated and the new divide value will take effect immediately. If
* zero, the new divide value will take effect at the end of the current clock
* cycle.
*
* Returns:
* None
*
*******************************************************************************/
void timer_clock_SetDividerRegister(uint16 clkDivider, uint8 restart)
{
uint8 enabled;
uint8 currSrc = timer_clock_GetSourceRegister();
uint16 oldDivider = timer_clock_GetDividerRegister();
if (clkDivider != oldDivider)
{
enabled = timer_clock_CLKEN & timer_clock_CLKEN_MASK;
if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
{
/* Moving to/from SSS requires correct ordering to prevent halting the clock */
if (oldDivider == 0u)
{
/* Moving away from SSS, set the divider first so when SSS is cleared we */
/* don't halt the clock. Using the shadow load isn't required as the */
/* divider is ignored while SSS is set. */
CY_SET_REG16(timer_clock_DIV_PTR, clkDivider);
timer_clock_MOD_SRC &= (uint8)(~CYCLK_SSS);
}
else
{
/* Moving to SSS, set SSS which then ignores the divider and we can set */
/* it without bothering with the shadow load. */
timer_clock_MOD_SRC |= CYCLK_SSS;
CY_SET_REG16(timer_clock_DIV_PTR, clkDivider);
}
}
else
{
if (enabled != 0u)
{
CLK_DIST_LD = 0x00u;
/* Clear all the mask bits except ours. */
#if defined(timer_clock__CFG3)
CLK_DIST_AMASK = timer_clock_CLKEN_MASK;
CLK_DIST_DMASK = 0x00u;
#else
CLK_DIST_DMASK = timer_clock_CLKEN_MASK;
CLK_DIST_AMASK = 0x00u;
#endif /* timer_clock__CFG3 */
/* Clear mask of bus clock. */
CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
/* If clock is currently enabled, disable it if async or going from N-to-1*/
if (((timer_clock_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
{
#if HAS_CLKDIST_LD_DISABLE
CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
/* Wait for clock to be disabled */
while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
#endif /* HAS_CLKDIST_LD_DISABLE */
timer_clock_CLKEN &= (uint8)(~timer_clock_CLKEN_MASK);
#if HAS_CLKDIST_LD_DISABLE
/* Clear the disable bit */
CLK_DIST_LD = 0x00u;
#endif /* HAS_CLKDIST_LD_DISABLE */
}
}
/* Load divide value. */
if ((timer_clock_CLKEN & timer_clock_CLKEN_MASK) != 0u)
{
/* If the clock is still enabled, use the shadow registers */
CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
}
else
{
/* If the clock is disabled, set the divider directly */
CY_SET_REG16(timer_clock_DIV_PTR, clkDivider);
timer_clock_CLKEN |= enabled;
}
}
}
}
/*******************************************************************************
* Function Name: timer_clock_GetDividerRegister
********************************************************************************
*
* Summary:
* Gets the clock divider register value.
*
* Parameters:
* None
*
* Returns:
* Divide value of the clock minus 1. For example, if the clock is set to
* divide by 2, the return value will be 1.
*
*******************************************************************************/
uint16 timer_clock_GetDividerRegister(void)
{
return CY_GET_REG16(timer_clock_DIV_PTR);
}
/*******************************************************************************
* Function Name: timer_clock_SetModeRegister
********************************************************************************
*
* Summary:
* Sets flags that control the operating mode of the clock. This function only
* changes flags from 0 to 1; flags that are already 1 will remain unchanged.
* To clear flags, use the ClearModeRegister function. The clock must be
* disabled before changing the mode.
*
* Parameters:
* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
* clkMode should be a set of the following optional bits or'ed together.
* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
* occur when the divider count reaches half of the divide
* value.
* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
* is asserted for approximately half of its period. When
* disabled, the output clock is asserted for one period of the
* source clock.
* - CYCLK_SYNC Enable output synchronization to master clock. This should
* be enabled for all synchronous clocks.
* See the Technical Reference Manual for details about setting the mode of
* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
*
* Returns:
* None
*
*******************************************************************************/
void timer_clock_SetModeRegister(uint8 modeBitMask)
{
timer_clock_MOD_SRC |= modeBitMask & (uint8)timer_clock_MODE_MASK;
}
/*******************************************************************************
* Function Name: timer_clock_ClearModeRegister
********************************************************************************
*
* Summary:
* Clears flags that control the operating mode of the clock. This function
* only changes flags from 1 to 0; flags that are already 0 will remain
* unchanged. To set flags, use the SetModeRegister function. The clock must be
* disabled before changing the mode.
*
* Parameters:
* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
* clkMode should be a set of the following optional bits or'ed together.
* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
* occur when the divider count reaches half of the divide
* value.
* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
* is asserted for approximately half of its period. When
* disabled, the output clock is asserted for one period of the
* source clock.
* - CYCLK_SYNC Enable output synchronization to master clock. This should
* be enabled for all synchronous clocks.
* See the Technical Reference Manual for details about setting the mode of
* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
*
* Returns:
* None
*
*******************************************************************************/
void timer_clock_ClearModeRegister(uint8 modeBitMask)
{
timer_clock_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(timer_clock_MODE_MASK));
}
/*******************************************************************************
* Function Name: timer_clock_GetModeRegister
********************************************************************************
*
* Summary:
* Gets the clock mode register value.
*
* Parameters:
* None
*
* Returns:
* Bit mask representing the enabled mode bits. See the SetModeRegister and
* ClearModeRegister descriptions for details about the mode bits.
*
*******************************************************************************/
uint8 timer_clock_GetModeRegister(void)
{
return timer_clock_MOD_SRC & (uint8)(timer_clock_MODE_MASK);
}
/*******************************************************************************
* Function Name: timer_clock_SetSourceRegister
********************************************************************************
*
* Summary:
* Sets the input source of the clock. The clock must be disabled before
* changing the source. The old and new clock sources must be running.
*
* Parameters:
* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the
* following input sources:
* - CYCLK_SRC_SEL_SYNC_DIG
* - CYCLK_SRC_SEL_IMO
* - CYCLK_SRC_SEL_XTALM
* - CYCLK_SRC_SEL_ILO
* - CYCLK_SRC_SEL_PLL
* - CYCLK_SRC_SEL_XTALK
* - CYCLK_SRC_SEL_DSI_G
* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
* See the Technical Reference Manual for details on clock sources.
*
* Returns:
* None
*
*******************************************************************************/
void timer_clock_SetSourceRegister(uint8 clkSource)
{
uint16 currDiv = timer_clock_GetDividerRegister();
uint8 oldSrc = timer_clock_GetSourceRegister();
if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
(clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
{
/* Switching to Master and divider is 1, set SSS, which will output master, */
/* then set the source so we are consistent. */
timer_clock_MOD_SRC |= CYCLK_SSS;
timer_clock_MOD_SRC =
(timer_clock_MOD_SRC & (uint8)(~timer_clock_SRC_SEL_MSK)) | clkSource;
}
else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
(clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
{
/* Switching from Master to not and divider is 1, set source, so we don't */
/* lock when we clear SSS. */
timer_clock_MOD_SRC =
(timer_clock_MOD_SRC & (uint8)(~timer_clock_SRC_SEL_MSK)) | clkSource;
timer_clock_MOD_SRC &= (uint8)(~CYCLK_SSS);
}
else
{
timer_clock_MOD_SRC =
(timer_clock_MOD_SRC & (uint8)(~timer_clock_SRC_SEL_MSK)) | clkSource;
}
}
/*******************************************************************************
* Function Name: timer_clock_GetSourceRegister
********************************************************************************
*
* Summary:
* Gets the input source of the clock.
*
* Parameters:
* None
*
* Returns:
* The input source of the clock. See SetSourceRegister for details.
*
*******************************************************************************/
uint8 timer_clock_GetSourceRegister(void)
{
return timer_clock_MOD_SRC & timer_clock_SRC_SEL_MSK;
}
#if defined(timer_clock__CFG3)
/*******************************************************************************
* Function Name: timer_clock_SetPhaseRegister
********************************************************************************
*
* Summary:
* Sets the phase delay of the analog clock. This function is only available
* for analog clocks. The clock must be disabled before changing the phase
* delay to avoid glitches.
*
* Parameters:
* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
* clkPhase must be from 1 to 11 inclusive. Other values, including 0,
* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11
* produces a 10ns delay.
*
* Returns:
* None
*
*******************************************************************************/
void timer_clock_SetPhaseRegister(uint8 clkPhase)
{
timer_clock_PHASE = clkPhase & timer_clock_PHASE_MASK;
}
/*******************************************************************************
* Function Name: timer_clock_GetPhase
********************************************************************************
*
* Summary:
* Gets the phase delay of the analog clock. This function is only available
* for analog clocks.
*
* Parameters:
* None
*
* Returns:
* Phase of the analog clock. See SetPhaseRegister for details.
*
*******************************************************************************/
uint8 timer_clock_GetPhaseRegister(void)
{
return timer_clock_PHASE & timer_clock_PHASE_MASK;
}
#endif /* timer_clock__CFG3 */
/* [] END OF FILE */

124
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/timer_clock.h Normal file
View File

@ -0,0 +1,124 @@
/*******************************************************************************
* File Name: timer_clock.h
* Version 2.10
*
* Description:
* Provides the function and constant definitions for the clock component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CLOCK_timer_clock_H)
#define CY_CLOCK_timer_clock_H
#include <cytypes.h>
#include <cyfitter.h>
/***************************************
* Conditional Compilation Parameters
***************************************/
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
#error Component cy_clock_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
/***************************************
* Function Prototypes
***************************************/
void timer_clock_Start(void) ;
void timer_clock_Stop(void) ;
#if(CY_PSOC3 || CY_PSOC5LP)
void timer_clock_StopBlock(void) ;
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
void timer_clock_StandbyPower(uint8 state) ;
void timer_clock_SetDividerRegister(uint16 clkDivider, uint8 restart)
;
uint16 timer_clock_GetDividerRegister(void) ;
void timer_clock_SetModeRegister(uint8 modeBitMask) ;
void timer_clock_ClearModeRegister(uint8 modeBitMask) ;
uint8 timer_clock_GetModeRegister(void) ;
void timer_clock_SetSourceRegister(uint8 clkSource) ;
uint8 timer_clock_GetSourceRegister(void) ;
#if defined(timer_clock__CFG3)
void timer_clock_SetPhaseRegister(uint8 clkPhase) ;
uint8 timer_clock_GetPhaseRegister(void) ;
#endif /* defined(timer_clock__CFG3) */
#define timer_clock_Enable() timer_clock_Start()
#define timer_clock_Disable() timer_clock_Stop()
#define timer_clock_SetDivider(clkDivider) timer_clock_SetDividerRegister(clkDivider, 1u)
#define timer_clock_SetDividerValue(clkDivider) timer_clock_SetDividerRegister((clkDivider) - 1u, 1u)
#define timer_clock_SetMode(clkMode) timer_clock_SetModeRegister(clkMode)
#define timer_clock_SetSource(clkSource) timer_clock_SetSourceRegister(clkSource)
#if defined(timer_clock__CFG3)
#define timer_clock_SetPhase(clkPhase) timer_clock_SetPhaseRegister(clkPhase)
#define timer_clock_SetPhaseValue(clkPhase) timer_clock_SetPhaseRegister((clkPhase) + 1u)
#endif /* defined(timer_clock__CFG3) */
/***************************************
* Registers
***************************************/
/* Register to enable or disable the clock */
#define timer_clock_CLKEN (* (reg8 *) timer_clock__PM_ACT_CFG)
#define timer_clock_CLKEN_PTR ((reg8 *) timer_clock__PM_ACT_CFG)
/* Register to enable or disable the clock */
#define timer_clock_CLKSTBY (* (reg8 *) timer_clock__PM_STBY_CFG)
#define timer_clock_CLKSTBY_PTR ((reg8 *) timer_clock__PM_STBY_CFG)
/* Clock LSB divider configuration register. */
#define timer_clock_DIV_LSB (* (reg8 *) timer_clock__CFG0)
#define timer_clock_DIV_LSB_PTR ((reg8 *) timer_clock__CFG0)
#define timer_clock_DIV_PTR ((reg16 *) timer_clock__CFG0)
/* Clock MSB divider configuration register. */
#define timer_clock_DIV_MSB (* (reg8 *) timer_clock__CFG1)
#define timer_clock_DIV_MSB_PTR ((reg8 *) timer_clock__CFG1)
/* Mode and source configuration register */
#define timer_clock_MOD_SRC (* (reg8 *) timer_clock__CFG2)
#define timer_clock_MOD_SRC_PTR ((reg8 *) timer_clock__CFG2)
#if defined(timer_clock__CFG3)
/* Analog clock phase configuration register */
#define timer_clock_PHASE (* (reg8 *) timer_clock__CFG3)
#define timer_clock_PHASE_PTR ((reg8 *) timer_clock__CFG3)
#endif /* defined(timer_clock__CFG3) */
/**************************************
* Register Constants
**************************************/
/* Power manager register masks */
#define timer_clock_CLKEN_MASK timer_clock__PM_ACT_MSK
#define timer_clock_CLKSTBY_MASK timer_clock__PM_STBY_MSK
/* CFG2 field masks */
#define timer_clock_SRC_SEL_MSK timer_clock__CFG2_SRC_SEL_MASK
#define timer_clock_MODE_MASK (~(timer_clock_SRC_SEL_MSK))
#if defined(timer_clock__CFG3)
/* CFG3 phase mask */
#define timer_clock_PHASE_MASK timer_clock__CFG3_PHASE_DLY_MASK
#endif /* defined(timer_clock__CFG3) */
#endif /* CY_CLOCK_timer_clock_H */
/* [] END OF FILE */

242
software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoCCreatorExportIDE.xml Executable file
View File

@ -0,0 +1,242 @@
<?xml version="1.0" encoding="utf-8"?>
<!--DO NOT EDIT. This document is generated by PSoC Creator design builds.-->
<PSoCCreatorIdeExport Version="1">
<Device Part="CY8C5267AXI-LP051" Processor="CortexM3" DeviceID="2E133069" />
<Toolchains>
<Toolchain Name="ARM GCC" Selected="True">
<Tool Name="prebuild" Command="" Options="" />
<Tool Name="assembler" Command="arm-none-eabi-as.exe" Options="-I. -I./Generated_Source/PSoC5 -mcpu=cortex-m3 -mthumb -g -alh=${OutputDir}/${CompileFile}.lst " />
<Tool Name="compiler" Command="arm-none-eabi-gcc.exe" Options="-I. -I./Generated_Source/PSoC5 -Wno-main -mcpu=cortex-m3 -mthumb -Wall -g -D DEBUG -Wa,-alh=${OutputDir}\${CompileFile}.lst -ffunction-sections " />
<Tool Name="linker" Command="arm-none-eabi-gcc.exe" Options="-mthumb -march=armv7-m -mfix-cortex-m3-ldrd -T .\Generated_Source\PSoC5\cm3gcc.ld -g -Wl,-Map,${OutputDir}\${ProjectShortName}.map -specs=nano.specs -Wl,--gc-sections " />
<Tool Name="postbuild" Command="" Options="" />
</Toolchain>
<Toolchain Name="ARM Keil MDK" Selected="False">
<Tool Name="prebuild" Command="" Options="" />
<Tool Name="assembler" Command="armasm.exe" Options="-i. -iGenerated_Source/PSoC5 --diag_style=gnu --thumb --cpu=Cortex-M3 -g --list=${OutputDir}/${CompileFile}.lst " />
<Tool Name="compiler" Command="armcc.exe" Options="-I. -I./Generated_Source/PSoC5 --diag_suppress=951 --diag_style=gnu --cpu=Cortex-M3 -g -D DEBUG --signed_chars --list -O0 --split_sections " />
<Tool Name="linker" Command="armlink.exe" Options="--diag_style=gnu --no_startup --cpu=Cortex-M3 --scatter .\Generated_Source\PSoC5\Cm3RealView.scat --map --list ${OutputDir}\${ProjectShortName}.map " />
<Tool Name="postbuild" Command="" Options="" />
</Toolchain>
</Toolchains>
<Project Name="pbook" Path="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn" Version="4.0" Type="Bootloadable">
<CMSIS_SVD_File>pbook.svd</CMSIS_SVD_File>
<Datasheet />
<LinkerFiles>
<LinkerFile Toolchain="ARM GCC">.\Generated_Source\PSoC5\cm3gcc.ld</LinkerFile>
<LinkerFile Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\Cm3RealView.scat</LinkerFile>
<LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
</LinkerFiles>
<Folders>
<Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\src">
<Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn">
<File BuildType="BUILD" Toolchain="">..\..\src\main.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\disk.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\geometry.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\inquiry.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\mode.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\scsi.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\scsiPhy.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\bits.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\sd.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\config.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\disk.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\geometry.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\inquiry.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\led.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\mode.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\scsi.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\scsiPhy.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\sense.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\bits.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\sd.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\config.h</File>
</Files>
</Folder>
<Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn">
<Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn">
<File BuildType="BUILD" Toolchain="">.\device.h</File>
</Files>
</Folder>
<Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn\Generated_Source\PSoC5">
<Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn">
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cybootloader.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cymetadata.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevice.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicegnu.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicerv.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydeviceiar.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevice_trm.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicegnu_trm.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicerv_trm.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydeviceiar_trm.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfittergnu.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitterrv.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitteriar.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydisabledsheets.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_DBx_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_DBx_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Data_Clk.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Data_Clk.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CFG_EEPROM.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CFG_EEPROM.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_SCK_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_SCK.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_SCK.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_ISR.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_ISR.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_PM.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_INT.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_PVT.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO_aliases.h</File>
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<Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">
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<Folder BuildType="EXCLUDE" Path=".\CortexM0">
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<Folder BuildType="EXCLUDE" Path=".\CortexM3">
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BIN
software/SCSI2SD/pbook/pbook.cydsn/TopDesign/TopDesign.cysch
View File

Binary file not shown.

126
software/SCSI2SD/pbook/pbook.cydsn/pbook.cycdx Executable file → Normal file
View File

@ -1,23 +1,22 @@
<?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
<block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">
<field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />
@ -85,9 +84,9 @@
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
</block>
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@ -95,21 +94,94 @@
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
</block>
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SD_Clk_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" />
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">
<field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
</register>
<register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">
<field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
<field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
<value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
<value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
</field>
<field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
<field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
<field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
<field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
<value name="Timer" value="0" desc="CMP and TC are output." />
<value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
</field>
<field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
</register>
<register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">
<field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
<field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
<value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
<value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
</field>
<field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
<field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
<field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
<field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
</register>
<register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">
<field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
<value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
<value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
<value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
<value name="Irq" value="11" desc="Timer runs until IRQ." />
</field>
<field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
<field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
<field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
<value name="Equal" value="0" desc="Compare Equal " />
<value name="Less than" value="1" desc="Compare Less Than " />
<value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
<value name="Greater" value="11" desc="Compare Greater Than ." />
<value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
</field>
<field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
</register>
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
</block>
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<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
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<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006578" bitWidth="8" desc="" />
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<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />
</block>
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<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_CTL_IO" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SCSI_CTL_IO_CONTROL_REG" address="0x4000647F" bitWidth="8" desc="" />
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BIN
software/SCSI2SD/pbook/pbook.cydsn/pbook.cydwr
View File

Binary file not shown.

BIN
software/SCSI2SD/pbook/pbook.cydsn/pbook.cyfit Executable file → Normal file
View File

Binary file not shown.

449
software/SCSI2SD/pbook/pbook.cydsn/pbook.cyprj
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</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<filters />
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="timer_clock" persistent="">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
<dependencies>
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="timer_clock.c" persistent=".\Generated_Source\PSoC5\timer_clock.c">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<build_action v="ARM_C_FILE" />
<PropertyDeltas />
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="timer_clock.h" persistent=".\Generated_Source\PSoC5\timer_clock.h">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<build_action v="NONE" />
<PropertyDeltas />
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<filters />
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="Debug_Timer_Interrupt" persistent="">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
<dependencies>
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="Debug_Timer_Interrupt.c" persistent=".\Generated_Source\PSoC5\Debug_Timer_Interrupt.c">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<build_action v="ARM_C_FILE" />
<PropertyDeltas />
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="Debug_Timer_Interrupt.h" persistent=".\Generated_Source\PSoC5\Debug_Timer_Interrupt.h">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<build_action v="NONE" />
<PropertyDeltas />
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<filters />
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@ -2213,4 +2642,4 @@
<BootloaderTag hexFile="" elfFile="" />
<current_generation v="2" />
</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
</CyXmlSerializer>
</CyXmlSerializer>

325
software/SCSI2SD/pbook/pbook.cydsn/pbook.svd Executable file → Normal file
View File

@ -491,9 +491,301 @@
</registers>
</peripheral>
<peripheral>
<name>SD_Clk_Ctl</name>
<name>Debug_Timer</name>
<description>No description available</description>
<baseAddress>0x40006474</baseAddress>
<baseAddress>0x400043A3</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xB64</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>Debug_Timer_GLOBAL_ENABLE</name>
<description>PM.ACT.CFG</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>en_timer</name>
<description>Enable timer/counters.</description>
<lsb>0</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL</name>
<description>TMRx.CFG0</description>
<addressOffset>0xB5D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>EN</name>
<description>Enables timer/comparator.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>MODE</name>
<description>Mode. (0 = Timer; 1 = Comparator)</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Timer</name>
<description>Timer mode. CNT/CMP register holds timer count value.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Comparator</name>
<description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONESHOT</name>
<description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>CMP_BUFF</name>
<description>Buffer compare register. Compare register updates only on timer terminal count.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>INV</name>
<description>Invert sense of TIMEREN signal</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DB</name>
<description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Timer</name>
<description>CMP and TC are output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Deadband</name>
<description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEADBAND_PERIOD</name>
<description>Deadband Period</description>
<lsb>6</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL2</name>
<description>TMRx.CFG1</description>
<addressOffset>0xB5E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IRQ_SEL</name>
<description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>FTC</name>
<description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Disable_FTC</name>
<description>Disable the single cycle pulse, which signifies the timer is starting.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable_FTC</name>
<description>Enable the single cycle pulse, which signifies the timer is starting.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCOR</name>
<description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>DBMODE</name>
<description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>CLK_BUS_EN_SEL</name>
<description>Digital Global Clock selection.</description>
<lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>BUS_CLK_SEL</name>
<description>Bus Clock selection.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL3_</name>
<description>TMRx.CFG2</description>
<addressOffset>0xB5F</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>TMR_CFG</name>
<description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
<lsb>0</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Continuous</name>
<description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Pulsewidth</name>
<description>Timer runs from positive to negative edge of TIMEREN.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Period</name>
<description>Timer runs from positive to positive edge of TIMEREN.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>Irq</name>
<description>Timer runs until IRQ.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COD</name>
<description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>ROD</name>
<description>Reset On Disable (ROD). Resets internal state of output logic</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>CMP_CFG</name>
<description>Comparator configurations</description>
<lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Equal</name>
<description>Compare Equal </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Less_than</name>
<description>Compare Less Than </description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Less_than_or_equal</name>
<description>Compare Less Than or Equal .</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>Greater</name>
<description>Compare Greater Than .</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>Greater_than_or_equal</name>
<description>Compare Greater Than or Equal </description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HW_EN</name>
<description>When set Timer Enable controls counting.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_PERIOD</name>
<description>TMRx.PER0 - Assigned Period</description>
<addressOffset>0xB61</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>Debug_Timer_COUNTER</name>
<description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
<addressOffset>0xB63</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
<baseAddress>0x40006578</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
@ -501,7 +793,7 @@
</addressBlock>
<registers>
<register>
<name>SD_Clk_Ctl_CONTROL_REG</name>
<name>SCSI_Out_Ctl_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
@ -512,9 +804,9 @@
</registers>
</peripheral>
<peripheral>
<name>SCSI_CTL_IO</name>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x4000647F</baseAddress>
<baseAddress>0x4000647A</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
@ -522,7 +814,28 @@
</addressBlock>
<registers>
<register>
<name>SCSI_CTL_IO_CONTROL_REG</name>
<name>SCSI_Out_Bits_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
<baseAddress>0x4000647C</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_CTL_PHASE_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>

2
software/SCSI2SD/src/config.c
View File

@ -35,7 +35,7 @@ static Config shadow =
0, // SCSI ID
" codesrc", // vendor (68k Apple Drive Setup: Set to " SEAGATE")
" SCSI2SD", //prodId (68k Apple Drive Setup: Set to " ST225N")
" 3.4", // revision (68k Apple Drive Setup: Set to "1.0 ")
" 3.5", // revision (68k Apple Drive Setup: Set to "1.0 ")
1, // enable parity
1, // enable unit attention,
0, // RESERVED

1
software/SCSI2SD/src/disk.c
View File

@ -562,6 +562,7 @@ void scsiDiskPoll()
scsiActive = 1;
}
}
if (scsiDev.phase == DATA_OUT)
{
scsiDev.phase = STATUS;

6
software/SCSI2SD/src/main.c
View File

@ -41,6 +41,12 @@ int main()
scsiInit();
scsiDiskInit();
if (!(blockDev.state & DISK_INITIALISED))
{
while (1) { ledOn();CyDelay(200); ledOff();CyDelay(200); }
}
while (1)
{
#ifdef MM_DEBUG

48
software/SCSI2SD/src/sd.c
View File

@ -35,8 +35,8 @@ static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL;
static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL;
// DMA descriptors
static uint8 sdDMARxTd[1] = { CY_DMA_INVALID_TD };
static uint8 sdDMATxTd[1] = { CY_DMA_INVALID_TD };
static uint8 sdDMARxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
static uint8 sdDMATxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
// Dummy location for DMA to send unchecked CRC bytes to
static uint8 discardBuffer;
@ -212,9 +212,13 @@ dmaReadSector(uint8_t* outputBuffer)
return;
}
CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE, CY_DMA_DISABLE_TD, TD_INC_DST_ADR | SD_RX_DMA__TD_TERMOUT_EN);
// Receive 512 bytes of data and then 2 bytes CRC.
CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE, sdDMARxTd[1], TD_INC_DST_ADR);
CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)outputBuffer));
CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
CyDmaTdSetConfiguration(sdDMARxTd[1], 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
CyDmaTdSetAddress(sdDMARxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
dmaInProgress = 1;
@ -246,10 +250,6 @@ sdReadSectorDMAPoll()
{
// DMA transfer is complete
dmaInProgress = 0;
sdSpiByte(0xFF); // CRC
sdSpiByte(0xFF); // CRC
return 1;
}
else
@ -352,10 +352,15 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer)
{
sdSpiByte(0xFC); // MULTIPLE byte start token
CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE, CY_DMA_DISABLE_TD, TD_INC_SRC_ADR | SD_TX_DMA__TD_TERMOUT_EN);
// Transmit 512 bytes of data and then 2 bytes CRC.
CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE, sdDMATxTd[1], TD_INC_SRC_ADR);
CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));
CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
CyDmaTdSetConfiguration(sdDMATxTd[1], 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
CyDmaTdSetAddress(sdDMATxTd[1], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
dmaInProgress = 1;
// The DMA controller is a bit trigger-happy. It will retain
@ -384,23 +389,12 @@ sdWriteSectorDMAPoll()
{
if (rxDMAComplete && txDMAComplete)
{
// DMA transfer is complete
dmaInProgress = 0;
sdSpiByte(0x00); // CRC
sdSpiByte(0x00); // CRC
// Don't wait more than 1s.
// My 2g Kingston micro-sd card doesn't respond immediately.
// My 16Gb card does.
int maxWait = 1000000;
uint8_t dataToken = sdSpiByte(0xFF); // Response
while (dataToken == 0xFF && maxWait-- > 0)
if (dataToken == 0x0FF)
{
CyDelayUs(1);
dataToken = sdSpiByte(0xFF);
return 0; // Write has not completed.
}
if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted.
else if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted.
{
uint8 r1b, busy;
@ -431,7 +425,9 @@ sdWriteSectorDMAPoll()
else
{
sdWaitWriteBusy();
}
}
// DMA transfer is complete and the SD card has accepted the write.
dmaInProgress = 0;
return 1;
}
@ -624,7 +620,9 @@ static void sdInitDMA()
CyDmaChDisable(sdDMARxChan);
sdDMARxTd[0] = CyDmaTdAllocate();
sdDMARxTd[1] = CyDmaTdAllocate();
sdDMATxTd[0] = CyDmaTdAllocate();
sdDMATxTd[1] = CyDmaTdAllocate();
SD_RX_DMA_COMPLETE_StartEx(sdRxISR);
SD_TX_DMA_COMPLETE_StartEx(sdTxISR);

4
software/bootloaderhost/main.c
View File

@ -170,7 +170,7 @@ int main(int argc, char* argv[])
case 0x3001:
printf(" Release: 3.5\" SCSI2SD\n");
expectedName = "SCSI2SD.cyacd";
if (!strstr(filename, expectedName))
if (strncasecmp(filename, expectedName, 13))
{
fileMismatch = 1;
}
@ -178,7 +178,7 @@ int main(int argc, char* argv[])
case 0x3002:
printf(" Release: 2.5\" SCSI2SD for Apple Powerbook\n");
expectedName = "pbook.cyacd";
if (!strstr(filename, expectedName))
if (strncasecmp(filename, expectedName, 11))
{
fileMismatch = 1;
}

5
software/scsi2sd-config/main.c
View File

@ -196,6 +196,11 @@ int main(int argc, char* argv[])
// Enumerate and print the HID devices on the system
struct hid_device_info *dev = hid_enumerate(vendorId, productId);
while (dev && dev->interface_number != 0)
{
dev = dev->next;
}
if (!dev)
{
fprintf(stderr, "ERROR: SCSI2SD USB device not found.\n");

10
software/scsi2sd-debug/main.c
View File

@ -96,18 +96,22 @@ int main(int argc, char* argv[])
// Enumerate and print the HID devices on the system
struct hid_device_info *dev = hid_enumerate(vendorId, productId);
// We need the SECOND interface for debug data
if (!dev)
{
fprintf(stderr, "ERROR: SCSI2SD USB device not found.\n");
exit(1);
}
else if (!dev->next)
// We need the SECOND interface for debug data
while (dev && dev->interface_number != 1)
{
dev = dev->next;
}
if (!dev)
{
fprintf(stderr, "ERROR: SCSI2SD Debug firmware not enabled.\n");
exit(1);
}
dev = dev->next;
printf("USB Device Found\n type: %04hx %04hx\n path: %s\n serial_number: %ls",
dev->vendor_id, dev->product_id, dev->path, dev->serial_number);