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Final tweaks for v4.5

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This commit is contained in:
Michael McMaster 2015-11-05 21:43:36 +10:00
parent 0b558479a6
commit e13a6e2678
24 changed files with 4957 additions and 4791 deletions
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2
CHANGELOG
View File

@ -1,4 +1,4 @@
20150x0x 4.5
20151105 4.5
- Fix bug in SCSI MODE SENSE that returned the wrong mode type
- Fixes CDROM emulation
- Added selection delay parameter. This should be set to 1ms for older

7
readme.txt
View File

@ -111,6 +111,10 @@ Compatibility
1 spare sector per cylinder
2051459 usable sectors on volume
Apollo 400/425s running DOMAIN/OS
Motorola System V/68 R3V7 and R3V8.
Since the installation have information about limited number of drives(most of them with custom commands) it requires a pre-installed disk image to be dd-ed on it. Works with MVME167 and MVME177
Motorola System V/88 R40V4.0 through R40V4.4
It requires to describe the disk into a configuration file. The process is described here - http://m88k.com/howto-001.html
Samplers
@ -134,6 +138,9 @@ Samplers
May require scsi2sd-config --apple flag
Yamaha A5000, A3000, EX5, EX5R
EMU ESI4000
Synclavier 9600.
Disable Parity. Max size == 9GB.
Other

10
software/SCSI2SD/src/main.c
View File

@ -50,14 +50,20 @@ int main()
// Optional bootup delay
int delaySeconds = 0;
while (delaySeconds < scsiDev.boardCfg.startupDelay) {
CyDelay(1000);
// Keep the USB connection working, otherwise it's very hard to revert
// silly extra-long startup delay settings.
int i;
for (i = 0; i < 200; i++) {
CyDelay(5);
scsiDev.watchdogTick++;
configPoll();
}
++delaySeconds;
}
uint32_t lastSDPoll = getTime_ms();
sdCheckPresent();
while (1)
{
scsiDev.watchdogTick++;

238
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
View File

@ -391,34 +391,34 @@
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
/* SDCard_BSPIM */
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB07_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB07_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB07_MSK
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB07_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB07_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@ -426,9 +426,9 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
@ -450,8 +450,8 @@
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
@ -459,9 +459,9 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB08_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB08_ST
/* SD_SCK */
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2
@ -1941,15 +1941,15 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@ -1962,37 +1962,37 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB05_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB05_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB05_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
@ -2818,8 +2818,8 @@
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
@ -2827,9 +2827,9 @@
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB02_MSK
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST
/* Debug_Timer_Interrupt */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -2950,8 +2950,8 @@
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@ -2959,67 +2959,67 @@
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB04_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB04_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U

3305
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
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File diff suppressed because it is too large Load Diff

238
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
View File

@ -391,34 +391,34 @@
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
/* SDCard_BSPIM */
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB07_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB07_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB07_MSK
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB07_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB07_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@ -426,9 +426,9 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
@ -450,8 +450,8 @@
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
@ -459,9 +459,9 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB08_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB08_ST
/* SD_SCK */
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2
@ -1941,15 +1941,15 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@ -1962,37 +1962,37 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB05_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB05_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB05_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
@ -2818,8 +2818,8 @@
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
@ -2827,9 +2827,9 @@
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB02_MSK
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB02_ST
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST
/* Debug_Timer_Interrupt */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -2950,8 +2950,8 @@
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@ -2959,67 +2959,67 @@
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB04_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB04_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000

238
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
View File

@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
/* SDCard_BSPIM */
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -426,9 +426,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -450,8 +450,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -459,9 +459,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST
/* SD_SCK */
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@ -1941,15 +1941,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1962,37 +1962,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB05_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB05_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB05_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@ -2818,8 +2818,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2827,9 +2827,9 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
/* Debug_Timer_Interrupt */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2950,8 +2950,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2959,67 +2959,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000

238
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
View File

@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
; SDCard_BSPIM
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -426,9 +426,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -450,8 +450,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -459,9 +459,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST
; SD_SCK
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@ -1941,15 +1941,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1962,37 +1962,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB05_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB05_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB05_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@ -2818,8 +2818,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2827,9 +2827,9 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
; Debug_Timer_Interrupt
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2950,8 +2950,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2959,67 +2959,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
; SCSI_Glitch_Ctl
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000

118
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
View File

@ -1,42 +1,12 @@
<?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006464" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006484" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006494" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
<field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
<value name="ENABLED" value="1" desc="Interrupt enabled" />
<value name="DISABLED" value="0" desc="Interrupt disabled" />
</field>
<field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
<field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
</register>
</block>
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -95,13 +65,26 @@
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
</block>
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />
</block>
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x40006461" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x40006481" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006491" bitWidth="8" desc="" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x40006462" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x40006482" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006492" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
@ -128,18 +111,36 @@
</field>
</register>
</block>
<block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" hidden="false" />
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006469" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006489" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006499" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
<field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
<value name="ENABLED" value="1" desc="Interrupt enabled" />
<value name="DISABLED" value="0" desc="Interrupt disabled" />
</field>
<field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
<field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
</register>
</block>
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -150,7 +151,7 @@
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -158,8 +159,6 @@
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">
<block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -257,13 +256,6 @@
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" hidden="false" />
</block>
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006575" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -271,10 +263,16 @@
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
</block>
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
</blockRegMap>

BIN
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit
View File

Binary file not shown.

364
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
View File

@ -6,161 +6,6 @@
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<peripherals>
<peripheral>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
<baseAddress>0x40006464</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Parity_Error_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Parity_Error_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x20</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x30</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>FIFO0</name>
<description>FIFO0 clear</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable counter</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable counter</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTRENBL</name>
<description>Enables or disables the Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Interrupt enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Interrupt disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1LEVEL</name>
<description>FIFO level</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0LEVEL</name>
<description>FIFO level</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1CLEAR</name>
<description>FIFO clear</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0CLEAR</name>
<description>FIFO clear</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>Debug_Timer</name>
<description>No description available</description>
@ -453,10 +298,52 @@
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
<baseAddress>0x4000647E</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Out_Ctl_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Glitch_Ctl</name>
<description>No description available</description>
<baseAddress>0x40006474</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Glitch_Ctl_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Filtered</name>
<description>No description available</description>
<baseAddress>0x40006461</baseAddress>
<baseAddress>0x40006462</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -609,9 +496,9 @@
</registers>
</peripheral>
<peripheral>
<name>SCSI_Glitch_Ctl</name>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
<baseAddress>0x4000647A</baseAddress>
<baseAddress>0x40006469</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -619,7 +506,7 @@
</addressBlock>
<registers>
<register>
<name>SCSI_Glitch_Ctl_CONTROL_REG</name>
<name>SCSI_Parity_Error_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
@ -627,12 +514,146 @@
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Parity_Error_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x20</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x30</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>FIFO0</name>
<description>FIFO0 clear</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable counter</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable counter</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTRENBL</name>
<description>Enables or disables the Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Interrupt enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Interrupt disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1LEVEL</name>
<description>FIFO level</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0LEVEL</name>
<description>FIFO level</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1CLEAR</name>
<description>FIFO clear</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0CLEAR</name>
<description>FIFO clear</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
<baseAddress>0x4000647B</baseAddress>
<baseAddress>0x40006475</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -1134,31 +1155,10 @@
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
<baseAddress>0x40006475</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Out_Ctl_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x40006575</baseAddress>
<baseAddress>0x4000647A</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>

BIN
software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
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180
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
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@ -426,34 +426,34 @@
#define EXTLED__SLW CYREG_PRT0_SLW
/* SDCard_BSPIM */
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@ -461,9 +461,9 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
@ -481,12 +481,14 @@
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
@ -494,9 +496,9 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB04_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB04_ST
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
/* SD_SCK */
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2
@ -1906,15 +1908,15 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@ -1927,37 +1929,37 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
@ -2785,8 +2787,8 @@
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
@ -2794,9 +2796,13 @@
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK
#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL
#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST
/* Debug_Timer_Interrupt */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -2917,8 +2923,8 @@
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@ -2926,13 +2932,9 @@
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK
#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
@ -2985,12 +2987,12 @@
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U

3037
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
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File diff suppressed because it is too large Load Diff

180
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
View File

@ -426,34 +426,34 @@
.set EXTLED__SLW, CYREG_PRT0_SLW
/* SDCard_BSPIM */
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@ -461,9 +461,9 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
@ -481,12 +481,14 @@
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
@ -494,9 +496,9 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB04_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB04_ST
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
/* SD_SCK */
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2
@ -1906,15 +1908,15 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@ -1927,37 +1929,37 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
@ -2785,8 +2787,8 @@
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
@ -2794,9 +2796,13 @@
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK
.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL
.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST
/* Debug_Timer_Interrupt */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -2917,8 +2923,8 @@
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@ -2926,13 +2932,9 @@
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK
.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
@ -2985,12 +2987,12 @@
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000

180
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
View File

@ -426,34 +426,34 @@ EXTLED__SHIFT EQU 0
EXTLED__SLW EQU CYREG_PRT0_SLW
/* SDCard_BSPIM */
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -461,9 +461,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -481,12 +481,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -494,9 +496,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
/* SD_SCK */
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@ -1906,15 +1908,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1927,37 +1929,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
@ -2785,8 +2787,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2794,9 +2796,13 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
/* Debug_Timer_Interrupt */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2917,8 +2923,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2926,13 +2932,9 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
@ -2985,12 +2987,12 @@ SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000

180
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
View File

@ -426,34 +426,34 @@ EXTLED__SHIFT EQU 0
EXTLED__SLW EQU CYREG_PRT0_SLW
; SDCard_BSPIM
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -461,9 +461,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -481,12 +481,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -494,9 +496,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
; SD_SCK
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@ -1906,15 +1908,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1927,37 +1929,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
@ -2785,8 +2787,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2794,9 +2796,13 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
; Debug_Timer_Interrupt
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2917,8 +2923,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2926,13 +2932,9 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
@ -2985,12 +2987,12 @@ SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000

266
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx
View File

@ -1,76 +1,76 @@
<?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
<field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
<value name="ENABLED" value="1" desc="Interrupt enabled" />
<value name="DISABLED" value="0" desc="Interrupt disabled" />
</field>
<field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
<field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
</register>
</block>
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x40006462" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x40006482" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006492" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
<field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
<value name="ENABLED" value="1" desc="Interrupt enabled" />
<value name="DISABLED" value="0" desc="Interrupt disabled" />
</field>
<field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
<field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
</register>
</block>
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
<field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
<value name="ENABLED" value="1" desc="Interrupt enabled" />
<value name="DISABLED" value="0" desc="Interrupt disabled" />
</field>
<field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
<field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
</register>
</block>
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
<field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
<value name="ENABLED" value="1" desc="Interrupt enabled" />
<value name="DISABLED" value="0" desc="Interrupt disabled" />
</field>
<field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
<field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
</register>
</block>
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -79,21 +79,75 @@
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" hidden="false" />
</block>
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">
<field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
</register>
<register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">
<field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
<field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
<value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
<value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
</field>
<field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
<field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
<field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
<field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
<value name="Timer" value="0" desc="CMP and TC are output." />
<value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
</field>
<field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
</register>
<register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">
<field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
<field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
<value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
<value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
</field>
<field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
<field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
<field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
<field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
</register>
<register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">
<field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
<value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
<value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
<value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
<value name="Irq" value="11" desc="Timer runs until IRQ." />
</field>
<field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
<field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
<field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
<value name="Equal" value="0" desc="Compare Equal " />
<value name="Less than" value="1" desc="Compare Less Than " />
<value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
<value name="Greater" value="11" desc="Compare Greater Than ." />
<value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
</field>
<field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
</register>
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
</block>
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -102,7 +156,7 @@
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">
<block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -200,70 +254,14 @@
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" hidden="false" />
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" hidden="false" />
</block>
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">
<field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
</register>
<register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">
<field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
<field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
<value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
<value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
</field>
<field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
<field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
<field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
<field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
<value name="Timer" value="0" desc="CMP and TC are output." />
<value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
</field>
<field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
</register>
<register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">
<field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
<field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
<value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
<value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
</field>
<field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
<field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
<field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
<field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
</register>
<register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">
<field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
<value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
<value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
<value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
<value name="Irq" value="11" desc="Timer runs until IRQ." />
</field>
<field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
<field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
<field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
<value name="Equal" value="0" desc="Compare Equal " />
<value name="Less than" value="1" desc="Compare Less Than " />
<value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
<value name="Greater" value="11" desc="Compare Greater Than ." />
<value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
</field>
<field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
</register>
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
</block>
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />

BIN
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit
View File

Binary file not shown.

900
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
View File

@ -6,165 +6,10 @@
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<peripherals>
<peripheral>
<name>SCSI_Filtered</name>
<description>No description available</description>
<baseAddress>0x40006462</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Filtered_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Filtered_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x20</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x30</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>FIFO0</name>
<description>FIFO0 clear</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable counter</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable counter</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTRENBL</name>
<description>Enables or disables the Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Interrupt enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Interrupt disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1LEVEL</name>
<description>FIFO level</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0LEVEL</name>
<description>FIFO level</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1CLEAR</name>
<description>FIFO clear</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0CLEAR</name>
<description>FIFO clear</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
<baseAddress>0x4000646B</baseAddress>
<baseAddress>0x40006465</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -316,6 +161,161 @@
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Filtered</name>
<description>No description available</description>
<baseAddress>0x40006468</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Filtered_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Filtered_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x20</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x30</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>FIFO0</name>
<description>FIFO0 clear</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable counter</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable counter</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTRENBL</name>
<description>Enables or disables the Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Interrupt enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Interrupt disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1LEVEL</name>
<description>FIFO level</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0LEVEL</name>
<description>FIFO level</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1CLEAR</name>
<description>FIFO clear</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0CLEAR</name>
<description>FIFO clear</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Glitch_Ctl</name>
<description>No description available</description>
@ -337,6 +337,298 @@
</register>
</registers>
</peripheral>
<peripheral>
<name>Debug_Timer</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>Debug_Timer_GLOBAL_ENABLE</name>
<description>PM.ACT.CFG</description>
<addressOffset>0x400043A3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>en_timer</name>
<description>Enable timer/counters.</description>
<lsb>0</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL</name>
<description>TMRx.CFG0</description>
<addressOffset>0x40004F00</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>EN</name>
<description>Enables timer/comparator.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>MODE</name>
<description>Mode. (0 = Timer; 1 = Comparator)</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Timer</name>
<description>Timer mode. CNT/CMP register holds timer count value.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Comparator</name>
<description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONESHOT</name>
<description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>CMP_BUFF</name>
<description>Buffer compare register. Compare register updates only on timer terminal count.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>INV</name>
<description>Invert sense of TIMEREN signal</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DB</name>
<description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Timer</name>
<description>CMP and TC are output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Deadband</name>
<description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEADBAND_PERIOD</name>
<description>Deadband Period</description>
<lsb>6</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL2</name>
<description>TMRx.CFG1</description>
<addressOffset>0x40004F01</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IRQ_SEL</name>
<description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>FTC</name>
<description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Disable_FTC</name>
<description>Disable the single cycle pulse, which signifies the timer is starting.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable_FTC</name>
<description>Enable the single cycle pulse, which signifies the timer is starting.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCOR</name>
<description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>DBMODE</name>
<description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>CLK_BUS_EN_SEL</name>
<description>Digital Global Clock selection.</description>
<lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>BUS_CLK_SEL</name>
<description>Bus Clock selection.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL3_</name>
<description>TMRx.CFG2</description>
<addressOffset>0x40004F02</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>TMR_CFG</name>
<description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
<lsb>0</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Continuous</name>
<description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Pulsewidth</name>
<description>Timer runs from positive to negative edge of TIMEREN.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Period</name>
<description>Timer runs from positive to positive edge of TIMEREN.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>Irq</name>
<description>Timer runs until IRQ.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COD</name>
<description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>ROD</name>
<description>Reset On Disable (ROD). Resets internal state of output logic</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>CMP_CFG</name>
<description>Comparator configurations</description>
<lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Equal</name>
<description>Compare Equal </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Less_than</name>
<description>Compare Less Than </description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Less_than_or_equal</name>
<description>Compare Less Than or Equal .</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>Greater</name>
<description>Compare Greater Than .</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>Greater_than_or_equal</name>
<description>Compare Greater Than or Equal </description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HW_EN</name>
<description>When set Timer Enable controls counting.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_PERIOD</name>
<description>TMRx.PER0 - Assigned Period</description>
<addressOffset>0x40004F04</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>Debug_Timer_COUNTER</name>
<description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
<addressOffset>0x40004F06</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
@ -842,302 +1134,10 @@
</register>
</registers>
</peripheral>
<peripheral>
<name>Debug_Timer</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>Debug_Timer_GLOBAL_ENABLE</name>
<description>PM.ACT.CFG</description>
<addressOffset>0x400043A3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>en_timer</name>
<description>Enable timer/counters.</description>
<lsb>0</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL</name>
<description>TMRx.CFG0</description>
<addressOffset>0x40004F00</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>EN</name>
<description>Enables timer/comparator.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>MODE</name>
<description>Mode. (0 = Timer; 1 = Comparator)</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Timer</name>
<description>Timer mode. CNT/CMP register holds timer count value.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Comparator</name>
<description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONESHOT</name>
<description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>CMP_BUFF</name>
<description>Buffer compare register. Compare register updates only on timer terminal count.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>INV</name>
<description>Invert sense of TIMEREN signal</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DB</name>
<description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Timer</name>
<description>CMP and TC are output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Deadband</name>
<description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEADBAND_PERIOD</name>
<description>Deadband Period</description>
<lsb>6</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL2</name>
<description>TMRx.CFG1</description>
<addressOffset>0x40004F01</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IRQ_SEL</name>
<description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>FTC</name>
<description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Disable_FTC</name>
<description>Disable the single cycle pulse, which signifies the timer is starting.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable_FTC</name>
<description>Enable the single cycle pulse, which signifies the timer is starting.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCOR</name>
<description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>DBMODE</name>
<description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>CLK_BUS_EN_SEL</name>
<description>Digital Global Clock selection.</description>
<lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>BUS_CLK_SEL</name>
<description>Bus Clock selection.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL3_</name>
<description>TMRx.CFG2</description>
<addressOffset>0x40004F02</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>TMR_CFG</name>
<description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
<lsb>0</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Continuous</name>
<description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Pulsewidth</name>
<description>Timer runs from positive to negative edge of TIMEREN.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Period</name>
<description>Timer runs from positive to positive edge of TIMEREN.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>Irq</name>
<description>Timer runs until IRQ.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COD</name>
<description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>ROD</name>
<description>Reset On Disable (ROD). Resets internal state of output logic</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>CMP_CFG</name>
<description>Comparator configurations</description>
<lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Equal</name>
<description>Compare Equal </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Less_than</name>
<description>Compare Less Than </description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Less_than_or_equal</name>
<description>Compare Less Than or Equal .</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>Greater</name>
<description>Compare Greater Than .</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>Greater_than_or_equal</name>
<description>Compare Greater Than or Equal </description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HW_EN</name>
<description>When set Timer Enable controls counting.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_PERIOD</name>
<description>TMRx.PER0 - Assigned Period</description>
<addressOffset>0x40004F04</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>Debug_Timer_COUNTER</name>
<description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
<addressOffset>0x40004F06</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
<baseAddress>0x40006471</baseAddress>
<baseAddress>0x40006474</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -1158,7 +1158,7 @@
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x40006472</baseAddress>
<baseAddress>0x40006473</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>

BIN
software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
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58
software/scsi2sd-util/BoardPanel.cc
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@ -46,26 +46,41 @@ namespace
return std::make_pair(value, static_cast<bool>(conv));
}
void CtrlGetFixedString(wxTextEntry* ctrl, char* dest, size_t len)
{
memset(dest, ' ', len);
std::string str(ctrl->GetValue().ToAscii());
// Don't use strncpy - we need to avoid NULL's
memcpy(dest, str.c_str(), std::min(len, str.size()));
}
bool CtrlIsAscii(wxTextEntry* ctrl)
{
return ctrl->GetValue().IsAscii();
}
}
BoardPanel::BoardPanel(wxWindow* parent, const BoardConfig& initialConfig) :
wxPanel(parent),
myParent(parent)
myParent(parent),
myDelayValidator(new wxIntegerValidator<uint8_t>)
{
wxFlexGridSizer *fgs = new wxFlexGridSizer(6, 2, 9, 25);
wxFlexGridSizer *fgs = new wxFlexGridSizer(8, 2, 9, 25);
fgs->Add(new wxStaticText(this, wxID_ANY, _("Startup Delay (seconds)")));
myStartDelayCtrl =
new wxTextCtrl(
this,
ID_startDelayCtrl,
"0",
wxDefaultPosition,
wxDefaultSize,
0,
*myDelayValidator);
myStartDelayCtrl->SetToolTip(_("Extra delay on power on, normally set to 0"));
fgs->Add(myStartDelayCtrl);
fgs->Add(new wxStaticText(this, wxID_ANY, _("SCSI Selection Delay (ms, 255 = auto)")));
mySelDelayCtrl =
new wxTextCtrl(
this,
ID_selDelayCtrl,
"255",
wxDefaultPosition,
wxDefaultSize,
0,
*myDelayValidator);
mySelDelayCtrl->SetToolTip(_("Delay before responding to SCSI selection. SCSI1 hosts usually require 1ms delay, however some require no delay"));
fgs->Add(mySelDelayCtrl);
fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
myParityCtrl =
@ -147,6 +162,8 @@ BoardPanel::getConfig() const
(myCacheCtrl->IsChecked() ? CONFIG_ENABLE_CACHE: 0) |
(myDisconnectCtrl->IsChecked() ? CONFIG_ENABLE_DISCONNECT: 0);
config.startupDelay = CtrlGetValue<unsigned int>(myStartDelayCtrl).first;
config.selectionDelay = CtrlGetValue<unsigned int>(mySelDelayCtrl).first;
return config;
}
@ -161,6 +178,17 @@ BoardPanel::setConfig(const BoardConfig& config)
myGlitchCtrl->SetValue(config.flags & CONFIG_DISABLE_GLITCH);
myCacheCtrl->SetValue(config.flags & CONFIG_ENABLE_CACHE);
myDisconnectCtrl->SetValue(config.flags & CONFIG_ENABLE_DISCONNECT);
{
std::stringstream conv;
conv << static_cast<unsigned int>(config.startupDelay);
myStartDelayCtrl->ChangeValue(conv.str());
}
{
std::stringstream conv;
conv << static_cast<unsigned int>(config.selectionDelay);
mySelDelayCtrl->ChangeValue(conv.str());
}
}

8
software/scsi2sd-util/BoardPanel.hh
View File

@ -57,7 +57,9 @@ private:
ID_scsi2Ctrl,
ID_glitchCtrl,
ID_cacheCtrl,
ID_disconnectCtrl
ID_disconnectCtrl,
ID_startDelayCtrl,
ID_selDelayCtrl
};
wxWindow* myParent;
@ -70,6 +72,10 @@ private:
wxCheckBox* myGlitchCtrl;
wxCheckBox* myCacheCtrl;
wxCheckBox* myDisconnectCtrl;
wxIntegerValidator<uint8_t>* myDelayValidator;
wxTextCtrl* myStartDelayCtrl;
wxTextCtrl* mySelDelayCtrl;
};
} // namespace SCSI2SD

1
software/scsi2sd-util/scsi2sd-util.cc
View File

@ -378,6 +378,7 @@ private:
void OnID_ConfigDefaults(wxCommandEvent& event)
{
myBoardPanel->setConfig(ConfigUtil::DefaultBoardConfig());
for (size_t i = 0; i < myTargets.size(); ++i)
{
myTargets[i]->setConfig(ConfigUtil::Default(i));