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52828268ae
SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
Michael McMaster 52828268ae Prepare for release
2019-06-10 19:52:37 +10:00

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<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
<name>CY8C5267AXI_LP051</name>
<version>0.1</version>
<description>CY8C52LP</description>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<peripherals>
<peripheral>
<name>SCSI_Filtered</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Filtered_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x4000646B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Filtered_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x4000648B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x4000649B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>FIFO0</name>
<description>FIFO0 clear</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable counter</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable counter</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTRENBL</name>
<description>Enables or disables the Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Interrupt enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Interrupt disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1LEVEL</name>
<description>FIFO level</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0LEVEL</name>
<description>FIFO level</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1CLEAR</name>
<description>FIFO clear</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0CLEAR</name>
<description>FIFO clear</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Parity_Error_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x40006465</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Parity_Error_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x40006485</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x40006495</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>FIFO0</name>
<description>FIFO0 clear</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable counter</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable counter</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTRENBL</name>
<description>Enables or disables the Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Interrupt enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Interrupt disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1LEVEL</name>
<description>FIFO level</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0LEVEL</name>
<description>FIFO level</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1CLEAR</name>
<description>FIFO clear</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0CLEAR</name>
<description>FIFO clear</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Glitch_Ctl</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Glitch_Ctl_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x40006474</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_CTL_PHASE_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x40006476</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>USBFS</name>
<description>USBFS</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR0</name>
<description>USB Control 0 Register</description>
<addressOffset>0x40006008</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DEVICE_ADDRESS</name>
<description>These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware.</description>
<lsb>0</lsb>
<msb>6</msb>
<access>read-only</access>
</field>
<field>
<name>USB_ENABLE</name>
<description>This bit enables the device to respond to USB traffic.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Disabled</name>
<description>Block responds to USB traffic.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Block does not respond to USB traffic.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<description>USB Control 1 Register</description>
<addressOffset>0x40006009</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>REG_ENABLE</name>
<description>This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Disabled</name>
<description>Regulator for 5V is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Regulator for 5V is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENABLE_LOCK</name>
<description>This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>BUS_ACTIVITY</name>
<description>The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>TRIM_OFFSET_MSB</name>
<description>This bit enables trim bit[7].</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP_INT_EN</name>
<description>USB SIE Data Endpoints Interrupt Enable Register</description>
<addressOffset>0x4000600A</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>EP1_INTR_EN</name>
<description>Enables interrupt for EP1.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>EP2_INTR_EN</name>
<description>Enables interrupt for EP2.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>EP3_INTR_EN</name>
<description>Enables interrupt for EP3.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>EP4_INTR_EN</name>
<description>Enables interrupt for EP4.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>EP5_INTR_EN</name>
<description>Enables interrupt for EP5.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>EP6_INTR_EN</name>
<description>Enables interrupt for EP6.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
<field>
<name>EP7_INTR_EN</name>
<description>Enables interrupt for EP7.</description>
<lsb>6</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>EP8_INTR_EN</name>
<description>Enables interrupt for EP8.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP_INT_SR</name>
<description>SIE Data Endpoint Interrupt Status Register</description>
<addressOffset>0x4000600B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>EP1_INTR</name>
<description>Interrupt status for EP1.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>EP2_INTR</name>
<description>Interrupt status for EP2.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>EP3_INTR</name>
<description>Interrupt status for EP3.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>EP4_INTR</name>
<description>Interrupt status for EP4.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>EP5_INTR</name>
<description>Interrupt status for EP5.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>EP6_INTR</name>
<description>Interrupt status for EP6.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
<field>
<name>EP7_INTR</name>
<description>Interrupt status for EP7.</description>
<lsb>6</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>EP8_INTR</name>
<description>Interrupt status for EP8.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP1_CNT0</name>
<description>SIE Endpoint 1 Count0 Register</description>
<addressOffset>0x4000600C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DATA_COUNT_MSB</name>
<description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<lsb>0</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>DATA_ERROR - 0, DATA_VALID - 1.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP1_CNT1</name>
<description>SIE Endpoint 1 Count1 Register</description>
<addressOffset>0x4000600D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DATA_COUNT</name>
<description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
<lsb>0</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP1_CR0</name>
<description>SIE Endpoint 1 Control Register</description>
<addressOffset>0x4000600E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<lsb>0</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept, IN: NAK, OUT: NAK.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept, IN: STALL, OUT: STALL.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>ACKED_NO - 0, ACKED_YES - 1.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected.</description>
<lsb>6</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USBIO_CR0</name>
<description>USBIO Control 0 Register</description>
<addressOffset>0x40006010</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RD</name>
<description>Received Data. This read only bit gives the state of the USB differential receiver.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DIFF_LOW</name>
<description>D+ less than D- (K state), or D+=D-=0 (SE0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIFF_HIGH</name>
<description>D+ greater than D- (J state).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TD</name>
<description>Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DIFF_K</name>
<description>Force USB K state (D+ is low D- is high).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIFF_J</name>
<description>Force USB J state (D+ is high D- is low).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSE0</name>
<description>Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0.</description>
<lsb>6</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>TEN</name>
<description>USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting is to force a resume state on the bus.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USBIO_CR1</name>
<description>USBIO Control 1 Register</description>
<addressOffset>0x40006012</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DMO</name>
<description>This read only bit gives the state of the D- pin.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-only</access>
</field>
<field>
<name>DPO</name>
<description>This read only bit gives the state of the D+ pin.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-only</access>
</field>
<field>
<name>USBPUEN</name>
<description>This bit enables the connection of the internal 1.5 k pull up resistor on the D+ pin.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>IOMODE</name>
<description>This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Bit_banged</name>
<description>Bit-banged mode for Dm and Dp.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>USB</name>
<description>USB block controls Dm and Dp.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SIE_EP2_CNT0</name>
<description>SIE Endpoint 1 Count0 Register</description>
<addressOffset>0x4000601C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DATA_COUNT_MSB</name>
<description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<lsb>0</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>DATA_ERROR - 0, DATA_VALID - 1.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP2_CNT1</name>
<description>SIE Endpoint 1 Count1 Register</description>
<addressOffset>0x4000601D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DATA_COUNT</name>
<description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
<lsb>0</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP2_CR0</name>
<description>SIE Endpoint 1 Control Register</description>
<addressOffset>0x4000601E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<lsb>0</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept, IN: NAK, OUT: NAK.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept, IN: STALL, OUT: STALL.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>ACKED_NO - 0, ACKED_YES - 1.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected.</description>
<lsb>6</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EP0_CR</name>
<description>Endpoint0 control Register</description>
<addressOffset>0x40006028</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<lsb>0</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept, IN: NAK, OUT: NAK.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept, IN: STALL, OUT: STALL.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>ACKED_NO - 0, ACKED_YES - 1.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected.</description>
<lsb>6</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EP0_CNT</name>
<description>Endpoint0 control Register</description>
<addressOffset>0x40006029</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>BYTE_COUNT</name>
<description>These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10.</description>
<lsb>0</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DATA_ERROR</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_VALID</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP3_CNT0</name>
<description>SIE Endpoint 1 Count0 Register</description>
<addressOffset>0x4000602C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DATA_COUNT_MSB</name>
<description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<lsb>0</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>DATA_ERROR - 0, DATA_VALID - 1.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP3_CNT1</name>
<description>SIE Endpoint 1 Count1 Register</description>
<addressOffset>0x4000602D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DATA_COUNT</name>
<description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
<lsb>0</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP3_CR0</name>
<description>SIE Endpoint 1 Control Register</description>
<addressOffset>0x4000602E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<lsb>0</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept, IN: NAK, OUT: NAK.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept, IN: STALL, OUT: STALL.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>ACKED_NO - 0, ACKED_YES - 1.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected.</description>
<lsb>6</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP4_CNT0</name>
<description>SIE Endpoint 1 Count0 Register</description>
<addressOffset>0x4000603C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DATA_COUNT_MSB</name>
<description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<lsb>0</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>DATA_ERROR - 0, DATA_VALID - 1.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP4_CNT1</name>
<description>SIE Endpoint 1 Count1 Register</description>
<addressOffset>0x4000603D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DATA_COUNT</name>
<description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
<lsb>0</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP4_CR0</name>
<description>SIE Endpoint 1 Control Register</description>
<addressOffset>0x4000603E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<lsb>0</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept, IN: NAK, OUT: NAK.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept, IN: STALL, OUT: STALL.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>ACKED_NO - 0, ACKED_YES - 1.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected.</description>
<lsb>6</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP1_CFG</name>
<description>Arbiter Endpoint 1 Configuration Register</description>
<addressOffset>0x40006080</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IN_DATA_RDY</name>
<description>Indication that Endpoint Packet Data is Ready in Main memory</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_REQ</name>
<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>CRC_BYPASS</name>
<description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>RESET_PTR</name>
<description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP1_INT_EN</name>
<description>Arbiter Endpoint 1 Interrupt Enable Register</description>
<addressOffset>0x40006081</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP1_INT_SR</name>
<description>Arbiter Endpoint 1 Interrupt Status Register</description>
<addressOffset>0x40006082</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW1_WA</name>
<description>Arbiter Endpoint 1 Write Address LSB Register</description>
<addressOffset>0x40006084</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>WA8</name>
<description>Write Address for EP.</description>
<lsb>0</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW1_WA_MSB</name>
<description>Arbiter Endpoint 1 Write Address MSB Register</description>
<addressOffset>0x40006085</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>WA9</name>
<description>Write Address for EP MSB.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW1_RA</name>
<description>Arbiter Endpoint 1 Read Address LSB Register</description>
<addressOffset>0x40006086</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RA8</name>
<description>Read Address for EP MSB.</description>
<lsb>0</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW1_RA_MSB</name>
<description>Arbiter Endpoint 1 Read Address MSB Register</description>
<addressOffset>0x40006087</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RA9</name>
<description>Read Address for EP MSB.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP2_CFG</name>
<description>Arbiter Endpoint 1 Configuration Register</description>
<addressOffset>0x40006090</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IN_DATA_RDY</name>
<description>Indication that Endpoint Packet Data is Ready in Main memory</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_REQ</name>
<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>CRC_BYPASS</name>
<description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>RESET_PTR</name>
<description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP2_INT_EN</name>
<description>Arbiter Endpoint 1 Interrupt Enable Register</description>
<addressOffset>0x40006091</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP2_INT_SR</name>
<description>Arbiter Endpoint 1 Interrupt Status Register</description>
<addressOffset>0x40006092</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW2_WA</name>
<description>Arbiter Endpoint 1 Write Address LSB Register</description>
<addressOffset>0x40006094</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>WA8</name>
<description>Write Address for EP.</description>
<lsb>0</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW2_WA_MSB</name>
<description>Arbiter Endpoint 1 Write Address MSB Register</description>
<addressOffset>0x40006095</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>WA9</name>
<description>Write Address for EP MSB.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW2_RA</name>
<description>Arbiter Endpoint 1 Read Address LSB Register</description>
<addressOffset>0x40006096</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RA8</name>
<description>Read Address for EP MSB.</description>
<lsb>0</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW2_RA_MSB</name>
<description>Arbiter Endpoint 1 Read Address MSB Register</description>
<addressOffset>0x40006097</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RA9</name>
<description>Read Address for EP MSB.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_CFG</name>
<description>Arbiter configuration register</description>
<addressOffset>0x4000609C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>AUTO_MEM</name>
<description>Enables Auto Memory Configuration. Manual memory configuration by default.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_CFG</name>
<description>DMA Access Configuration.</description>
<lsb>5</lsb>
<msb>6</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DMA_NONE</name>
<description>No DMA.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA_MANUAL</name>
<description>Manual DMA.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA_AUTO</name>
<description>Auto DMA.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG_CMP</name>
<description>Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USB_CLK_EN</name>
<description>USB Control 0 Register</description>
<addressOffset>0x4000609D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>CSR_CLK_EN</name>
<description>Clock Enable for Core Logic clocked by AHB bus clock.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Disabled</name>
<description>Disables clock to UBS block.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Enables clock to UBS block.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ARB_INT_EN</name>
<description>Arbiter Interrupt Enable Register</description>
<addressOffset>0x4000609E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>EP1_INTR_EN</name>
<description>Enables interrupt for EP1.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>EP2_INTR_EN</name>
<description>Enables interrupt for EP2.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>EP3_INTR_EN</name>
<description>Enables interrupt for EP3.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>EP4_INTR_EN</name>
<description>Enables interrupt for EP4.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>EP5_INTR_EN</name>
<description>Enables interrupt for EP5.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>EP6_INTR_EN</name>
<description>Enables interrupt for EP6.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
<field>
<name>EP7_INTR_EN</name>
<description>Enables interrupt for EP7.</description>
<lsb>6</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>EP8_INTR_EN</name>
<description>Enables interrupt for EP8.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_INT_SR</name>
<description>Arbiter Interrupt Status</description>
<addressOffset>0x4000609F</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>EP1_INTR</name>
<description>Interrupt status for EP1.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-only</access>
</field>
<field>
<name>EP2_INTR</name>
<description>Interrupt status for EP2.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-only</access>
</field>
<field>
<name>EP3_INTR</name>
<description>Interrupt status for EP3.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-only</access>
</field>
<field>
<name>EP4_INTR</name>
<description>Interrupt status for EP4.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-only</access>
</field>
<field>
<name>EP5_INTR</name>
<description>Interrupt status for EP5.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-only</access>
</field>
<field>
<name>EP6_INTR</name>
<description>Interrupt status for EP6.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-only</access>
</field>
<field>
<name>EP7_INTR</name>
<description>Interrupt status for EP7.</description>
<lsb>6</lsb>
<msb>6</msb>
<access>read-only</access>
</field>
<field>
<name>EP8_INTR</name>
<description>Interrupt status for EP8.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP3_CFG</name>
<description>Arbiter Endpoint 1 Configuration Register</description>
<addressOffset>0x400060A0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IN_DATA_RDY</name>
<description>Indication that Endpoint Packet Data is Ready in Main memory</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_REQ</name>
<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>CRC_BYPASS</name>
<description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>RESET_PTR</name>
<description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP3_INT_EN</name>
<description>Arbiter Endpoint 1 Interrupt Enable Register</description>
<addressOffset>0x400060A1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP3_INT_SR</name>
<description>Arbiter Endpoint 1 Interrupt Status Register</description>
<addressOffset>0x400060A2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW3_WA</name>
<description>Arbiter Endpoint 1 Write Address LSB Register</description>
<addressOffset>0x400060A4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>WA8</name>
<description>Write Address for EP.</description>
<lsb>0</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW3_WA_MSB</name>
<description>Arbiter Endpoint 1 Write Address MSB Register</description>
<addressOffset>0x400060A5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>WA9</name>
<description>Write Address for EP MSB.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW3_RA</name>
<description>Arbiter Endpoint 1 Read Address LSB Register</description>
<addressOffset>0x400060A6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RA8</name>
<description>Read Address for EP MSB.</description>
<lsb>0</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW3_RA_MSB</name>
<description>Arbiter Endpoint 1 Read Address MSB Register</description>
<addressOffset>0x400060A7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RA9</name>
<description>Read Address for EP MSB.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP4_CFG</name>
<description>Arbiter Endpoint 1 Configuration Register</description>
<addressOffset>0x400060B0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IN_DATA_RDY</name>
<description>Indication that Endpoint Packet Data is Ready in Main memory</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_REQ</name>
<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>CRC_BYPASS</name>
<description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>RESET_PTR</name>
<description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP4_INT_EN</name>
<description>Arbiter Endpoint 1 Interrupt Enable Register</description>
<addressOffset>0x400060B1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP4_INT_SR</name>
<description>Arbiter Endpoint 1 Interrupt Status Register</description>
<addressOffset>0x400060B2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW4_WA</name>
<description>Arbiter Endpoint 1 Write Address LSB Register</description>
<addressOffset>0x400060B4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>WA8</name>
<description>Write Address for EP.</description>
<lsb>0</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW4_WA_MSB</name>
<description>Arbiter Endpoint 1 Write Address MSB Register</description>
<addressOffset>0x400060B5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>WA9</name>
<description>Write Address for EP MSB.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW4_RA</name>
<description>Arbiter Endpoint 1 Read Address LSB Register</description>
<addressOffset>0x400060B6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RA8</name>
<description>Read Address for EP MSB.</description>
<lsb>0</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW4_RA_MSB</name>
<description>Arbiter Endpoint 1 Read Address MSB Register</description>
<addressOffset>0x400060B7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RA9</name>
<description>Read Address for EP MSB.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>Debug_Timer</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>Debug_Timer_GLOBAL_ENABLE</name>
<description>PM.ACT.CFG</description>
<addressOffset>0x400043A3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>en_timer</name>
<description>Enable timer/counters.</description>
<lsb>0</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL</name>
<description>TMRx.CFG0</description>
<addressOffset>0x40004F00</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>EN</name>
<description>Enables timer/comparator.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>MODE</name>
<description>Mode. (0 = Timer; 1 = Comparator)</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Timer</name>
<description>Timer mode. CNT/CMP register holds timer count value.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Comparator</name>
<description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONESHOT</name>
<description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>CMP_BUFF</name>
<description>Buffer compare register. Compare register updates only on timer terminal count.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>INV</name>
<description>Invert sense of TIMEREN signal</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DB</name>
<description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Timer</name>
<description>CMP and TC are output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Deadband</name>
<description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEADBAND_PERIOD</name>
<description>Deadband Period</description>
<lsb>6</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL2</name>
<description>TMRx.CFG1</description>
<addressOffset>0x40004F01</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IRQ_SEL</name>
<description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>FTC</name>
<description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Disable_FTC</name>
<description>Disable the single cycle pulse, which signifies the timer is starting.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable_FTC</name>
<description>Enable the single cycle pulse, which signifies the timer is starting.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCOR</name>
<description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>DBMODE</name>
<description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>CLK_BUS_EN_SEL</name>
<description>Digital Global Clock selection.</description>
<lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>BUS_CLK_SEL</name>
<description>Bus Clock selection.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL3_</name>
<description>TMRx.CFG2</description>
<addressOffset>0x40004F02</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>TMR_CFG</name>
<description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
<lsb>0</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Continuous</name>
<description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Pulsewidth</name>
<description>Timer runs from positive to negative edge of TIMEREN.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Period</name>
<description>Timer runs from positive to positive edge of TIMEREN.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>Irq</name>
<description>Timer runs until IRQ.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COD</name>
<description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>ROD</name>
<description>Reset On Disable (ROD). Resets internal state of output logic</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>CMP_CFG</name>
<description>Comparator configurations</description>
<lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Equal</name>
<description>Compare Equal </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Less_than</name>
<description>Compare Less Than </description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Less_than_or_equal</name>
<description>Compare Less Than or Equal .</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>Greater</name>
<description>Compare Greater Than .</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>Greater_than_or_equal</name>
<description>Compare Greater Than or Equal </description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HW_EN</name>
<description>When set Timer Enable controls counting.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_PERIOD</name>
<description>TMRx.PER0 - Assigned Period</description>
<addressOffset>0x40004F04</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>Debug_Timer_COUNTER</name>
<description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
<addressOffset>0x40004F06</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Out_Ctl_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x4000647C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Out_Bits_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x4000647E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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