Prepare for release
This commit is contained in:
Michael McMaster
parent
38597c1f25
commit
52828268ae
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@ -1,6 +1,9 @@
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2019XXXX 4.9.X
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20190610 4.8.3
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- Improve XEBEC controller support
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- Add Flexible Disk Drive Geometry SCSI MODE page
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- Fix SD card hotswap bug
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- Add scsi mode page 0 support
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- Fix regression for EMU EMAX
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20180926 4.8.1
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- Fix bug when writing with multiple SCSI devices on the chain
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@ -31,7 +31,7 @@
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#include <string.h>
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static const uint16_t FIRMWARE_VERSION = 0x0482;
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static const uint16_t FIRMWARE_VERSION = 0x0483;
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// 1 flash row
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static const uint8_t DEFAULT_CONFIG[256] =
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,556 @@
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/*******************************************************************************
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* \file cy_em_eeprom.h
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* \version 2.0
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*
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* \brief
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* This file provides the function prototypes and constants for the Emulated
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* EEPROM middleware library.
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*
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********************************************************************************
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* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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/**
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* \mainpage Cypress Em_EEPROM Middleware Library
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*
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* The Emulated EEPROM provides an API that allows creating an emulated
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* EEPROM in flash that has the ability to do wear leveling and restore
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* corrupted data from a redundant copy. The Emulated EEPROM library is designed
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* to be used with the Em_EEPROM component.
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*
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* The Cy_Em_EEPROM API is described in the following sections:
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* - \ref group_em_eeprom_macros
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* - \ref group_em_eeprom_data_structures
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* - \ref group_em_eeprom_enums
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* - \ref group_em_eeprom_functions
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*
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* <b>Features:</b>
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* * EEPROM-Like Non-Volatile Storage
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* * Easy to use Read and Write API
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* * Optional Wear Leveling
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* * Optional Redundant Data storage
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*
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* \section group_em_eeprom_configuration Configuration Considerations
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*
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* The Em_EEPROM operates on the top of the flash driver. The flash driver has
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* some prerequisites for proper operation. Refer to the "Flash System
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* Routine (Flash)" section of the PDL API Reference Manual.
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*
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* <b>Initializing Emulated EEPROM in User flash</b>
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*
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* To initialize an Emulated EEPROM in the User flash, the EEPROM storage should
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* be declared by the user. For the proper operation, the EEPROM storage should
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* be aligned to the size of the flash row. An example of the EEPROM storage
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* declaration is below (applicable for GCC and MDK compilers):
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*
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* CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW)
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* const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u};
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*
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* The same declaration for the IAR compiler:
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*
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* #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW
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* const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u};
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*
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* Note that the name "emEeprom" is shown for reference. Any other name can be
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* used instead. Also, note that the Em_EEPROM_PHYSICAL_SIZE constant is
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* generated by the PSoC Creator Em_EEPROM component and so it is instance name
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* dependent and its prefix should be changed when the name of the component
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* changes. If the The Cy_Em_EEPROM middleware library is used without the
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* Em_EEPROM component, the user has to provide a proper size for the EEPROM
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* storage instead of Em_EEPROM_PHYSICAL_SIZE. The size of the EEPROM storage
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* can be calculated using the following equation:
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*
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* Physical size = EEPROM data size * 2 * wear leveling * (1 + redundant copy)
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*
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* where,
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* "EEPROM data size" - the size of data the user wants to store in the
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* EEPROM. The data size must divide evenly to the half of the flash row size.
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* "wear leveling" - the wear leveling factor (1-10).
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* "redundant copy" - "zero" if a redundant copy is not used, and "one"
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* otherwise.
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*
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* The start address of the storage should be filled to the Emulated EEPROM
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* configuration structure and then passed to the Cy_Em_EEPROM_Init().
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* If the Em_EEPROM component is used, the config (Em_EEPROM_config) and
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* context structures (Em_EEPROM_context) are defined by the component, so the
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* user may just use that structures otherwise both of the structures need to
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* be provided by the user. Note that if the "Config Data in Flash"
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* option is selected in the component, then the configuration structure should
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* be copied to RAM to allow EEPROM storage start address update. The following
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* code demonstrates utilization of "Em_EEPROM_config" and "Em_EEPROM_context"
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* Em_EEPROM component structures for Cy_Em_EEPROM middleware library
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* initialization:
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*
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* cy_en_em_eeprom_status_t retValue;
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* cy_stc_eeprom_config_t config;
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*
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* memcpy((void *)&config,
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(void *)&Em_EEPROM_config,
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sizeof(cy_stc_eeprom_config_t));
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* config.userFlashStartAddr = (uint32)emEeprom;
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* retValue = Cy_Em_EEPROM_Init(&config, &Em_EEPROM_context);
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*
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* <b>Initializing EEPROM in Emulated EEPROM flash area</b>
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*
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* Initializing of the EEPROM storage in the Emulated EEPROM flash area is
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* identical to initializing of the EEPROM storage in the User flash with one
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* difference. The location of the Emulated EEPROM storage should be specified
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* somewhere in the EmulatedEEPROM flash area. If the Em_EEPROM component is
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* utilized in the project, then the respective storage
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* (Em_EEPROM_em_EepromStorage[]) is automatically declared by the component
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* if the "Use Emulated EEPROM" option is set to "Yes". The user just needs to
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* fill the start address of the storage to the config structure. If the
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* Em_EEPROM component is not used, the user needs to declare the storage
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* in the Emulated EEPROM flash area. An example of such declaration is
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* following (applicable for GCC and MDK compilers):
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*
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* CY_SECTION(".cy_em_eeprom") CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW)
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* const uint8_t emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u};
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*
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* The same declaration for the IAR compiler:
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*
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* #pragma location = ".cy_em_eeprom"
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* #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW
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* const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u};
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*
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* where,
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* Em_EEPROM_PHYSICAL_SIZE - is a constant that is generated by the Em_EEPROM
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* component when the component is utilized in the project or it should be
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* provided by the user. The equation for the calculation of the constant is
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* shown above.
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*
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* Note that the size of the Emulated EEPROM flash area is limited. Refer to the
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* specific device datasheet for the value of the available EEPROM Emulation
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* area.
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*
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* \section group_em_eeprom_more_information More Information
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* See the Em_EEPROM Component datasheet.
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*
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*
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* \section group_em_eeprom_MISRA MISRA-C Compliance
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*
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* The Cy_Em_EEPROM library has the following specific deviations:
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*
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* <table class="doxtable">
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* <tr>
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* <th>MISRA Rule</th>
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* <th>Rule Class (Required/Advisory)</th>
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* <th>Rule Description</th>
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* <th>Description of Deviation(s)</th>
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* </tr>
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* <tr>
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* <td>11.4</td>
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* <td>A</td>
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* <td>The cast should not be performed between a pointer to the object type
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* and a different pointer to the object type.</td>
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* <td>The cast from the object type and a different pointer to the object
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* was used intentionally because of the performance reasons.</td>
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* </tr>
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* <tr>
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* <td>14.2</td>
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* <td>R</td>
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* <td>All non-null statements shall either have at least one side-effect,
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* however executed, or cause control flow to change.</td>
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* <td>To maintain common codebase, some variables, unused for a specific
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* device, are casted to void to prevent generation of an unused variable
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* compiler warning.</td>
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* </tr>
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* <tr>
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* <td>16.7</td>
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* <td>A</td>
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* <td>The object addressed by the pointer parameter is not modified and so
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* the pointer could be of type 'pointer to const'.</td>
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* <td>The warning is generated because of the pointer dereferencing to
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* address which makes the MISRA checker think the data is not
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* modified.</td>
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* </tr>
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* <tr>
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* <td>17.4</td>
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* <td>R</td>
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* <td>The array indexing shall be the only allowed form of pointer
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* arithmetic.</td>
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* <td>The pointer arithmetic used in several places on the Cy_Em_EEPROM
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* implementation is safe and preferred because it increases the code
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* flexibility.</td>
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* </tr>
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* <tr>
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* <td>19.7</td>
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* <td>A</td>
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* <td>A function shall be used in preference to a function-like macro.</td>
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* <td>Macro is used because of performance reasons.</td>
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* </tr>
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* </table>
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*
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* \section group_em_eeprom_changelog Changelog
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* <table class="doxtable">
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* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
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* <tr>
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* <td>1.0</td>
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* <td>Initial Version</td>
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* <td></td>
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* </tr>
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* </table>
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*
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* \defgroup group_em_eeprom_macros Macros
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* \brief
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* This section describes the Emulated EEPROM Macros.
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*
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* \defgroup group_em_eeprom_functions Functions
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* \brief
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* This section describes the Emulated EEPROM Function Prototypes.
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*
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* \defgroup group_em_eeprom_data_structures Data Structures
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* \brief
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* Describes the data structures defined by the Emulated EEPROM.
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*
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* \defgroup group_em_eeprom_enums Enumerated types
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* \brief
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* Describes the enumeration types defined by the Emulated EEPROM.
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*
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*/
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#if !defined(CY_EM_EEPROM_H)
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#define CY_EM_EEPROM_H
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#include "cytypes.h"
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#include <stddef.h>
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#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6)
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#include <cy_device_headers.h>
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#include "syslib/cy_syslib.h"
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#include "flash/cy_flash.h"
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#else
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#include "CyFlash.h"
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#include <cyfitter.h>
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#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */
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/* The C binding of definitions if building with the C++ compiler */
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/***************************************
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* Conditional Compilation Parameters
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***************************************/
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#define CY_PSOC6 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6)
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/***************************************
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* Data Structure definitions
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***************************************/
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/**
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* \addtogroup group_em_eeprom_data_structures
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* \{
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*/
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/** EEPROM configuration structure */
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typedef struct
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{
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/** The number of bytes to store in EEPROM */
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uint32 eepromSize;
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/** The amount of wear leveling from 1 to 10. 1 means no wear leveling
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* is used.
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*/
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uint32 wearLevelingFactor;
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/** If not zero, a redundant copy of the Em_EEPROM is included. */
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uint8 redundantCopy;
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/** If not zero, a blocking write to flash is used. Otherwise non-blocking
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* write is used. This parameter is used only for PSoC 6.
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*/
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uint8 blockingWrite;
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/** The start address for the EEPROM memory in the user's flash. */
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uint32 userFlashStartAddr;
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} cy_stc_eeprom_config_t;
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/** \} group_em_eeprom_data_structures */
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/** The EEPROM context data structure. It is used to store the specific
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* EEPROM context data.
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*/
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typedef struct
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{
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/** The pointer to the end address of EEPROM including wear leveling overhead
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* and excluding redundant copy overhead.
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*/
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uint32 wlEndAddr;
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/** The number of flash rows allocated for the EEPROM excluding the number of
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* rows allocated for wear leveling and redundant copy overhead.
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*/
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uint32 numberOfRows;
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/** The address of the last written EEPROM row */
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uint32 lastWrRowAddr;
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/** The number of bytes to store in EEPROM */
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uint32 eepromSize;
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/** The amount of wear leveling from 1 to 10. 1 means no wear leveling
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* is used.
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*/
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uint32 wearLevelingFactor;
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/** If not zero, a redundant copy of the Em_EEPROM is included. */
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uint8 redundantCopy;
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/** If not zero, a blocking write to flash is used. Otherwise non-blocking
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* write is used. This parameter is used only for PSoC 6.
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*/
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uint8 blockingWrite;
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/** The start address for the EEPROM memory in the user's flash. */
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uint32 userFlashStartAddr;
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} cy_stc_eeprom_context_t;
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#if (CY_PSOC6)
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#define CY_EM_EEPROM_ID (CY_PDL_DRV_ID(0x1BuL)) /**< Em_EEPROM PDL ID */
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/**
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* \addtogroup group_em_eeprom_enums
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* \{
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* Specifies return values meaning.
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*/
|
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/** A prefix for EEPROM function error return-values */
|
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#define CY_EM_EEPROM_ID_ERROR (uint32_t)(CY_EM_EEPROM_ID | CY_PDL_STATUS_ERROR)
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||||
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||||
#else
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||||
|
||||
/** A prefix for EEPROM function status codes. For non-PSoC6 devices,
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* prefix is zero.
|
||||
*/
|
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#define CY_EM_EEPROM_ID_ERROR (0uL)
|
||||
|
||||
#endif /* (CY_PSOC6) */
|
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|
||||
|
||||
/***************************************
|
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* Enumerated Types and Parameters
|
||||
***************************************/
|
||||
|
||||
/** EEPROM return enumeration type */
|
||||
typedef enum
|
||||
{
|
||||
CY_EM_EEPROM_SUCCESS = 0x00uL, /**< The function executed successfully */
|
||||
CY_EM_EEPROM_BAD_PARAM = (CY_EM_EEPROM_ID_ERROR + 1uL), /**< The input parameter is invalid */
|
||||
CY_EM_EEPROM_BAD_CHECKSUM = (CY_EM_EEPROM_ID_ERROR + 2uL), /**< The data in EEPROM is corrupted */
|
||||
CY_EM_EEPROM_BAD_DATA = (CY_EM_EEPROM_ID_ERROR + 3uL), /**< Failed to place the EEPROM in flash */
|
||||
CY_EM_EEPROM_WRITE_FAIL = (CY_EM_EEPROM_ID_ERROR + 4uL) /**< Write to EEPROM failed */
|
||||
} cy_en_em_eeprom_status_t;
|
||||
|
||||
/** \} group_em_eeprom_enums */
|
||||
|
||||
|
||||
/***************************************
|
||||
* Function Prototypes
|
||||
***************************************/
|
||||
|
||||
/**
|
||||
* \addtogroup group_em_eeprom_functions
|
||||
* \{
|
||||
*/
|
||||
cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context);
|
||||
cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr,
|
||||
void * eepromData,
|
||||
uint32 size,
|
||||
cy_stc_eeprom_context_t * context);
|
||||
cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr,
|
||||
void * eepromData,
|
||||
uint32 size,
|
||||
cy_stc_eeprom_context_t * context);
|
||||
cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context);
|
||||
uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context);
|
||||
/** \} group_em_eeprom_functions */
|
||||
|
||||
|
||||
/***************************************
|
||||
* API Constants
|
||||
***************************************/
|
||||
/**
|
||||
* \addtogroup group_em_eeprom_macros
|
||||
* \{
|
||||
*/
|
||||
/** Library major version */
|
||||
#define CY_EM_EEPROM_VERSION_MAJOR (2)
|
||||
|
||||
/** Library minor version */
|
||||
#define CY_EM_EEPROM_VERSION_MINOR (0)
|
||||
|
||||
/** Defines the maximum data length that can be stored in one flash row */
|
||||
#define CY_EM_EEPROM_EEPROM_DATA_LEN (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u)
|
||||
|
||||
/** \} group_em_eeprom_macros */
|
||||
|
||||
|
||||
/***************************************
|
||||
* Macro definitions
|
||||
***************************************/
|
||||
/** \cond INTERNAL */
|
||||
|
||||
/* Defines the size of flash row */
|
||||
#define CY_EM_EEPROM_FLASH_SIZEOF_ROW (CY_FLASH_SIZEOF_ROW)
|
||||
|
||||
/* Device specific flash constants */
|
||||
#if (!CY_PSOC6)
|
||||
#define CY_EM_EEPROM_FLASH_BASE_ADDR (CYDEV_FLASH_BASE)
|
||||
#define CY_EM_EEPROM_FLASH_SIZE (CYDEV_FLASH_SIZE)
|
||||
#define CY_EM_EEPROM_ROWS_IN_ARRAY (CY_FLASH_SIZEOF_ARRAY / CY_EM_EEPROM_FLASH_SIZEOF_ROW)
|
||||
#if (CY_PSOC3)
|
||||
#define CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX (0xff0000uL)
|
||||
#define CY_EM_EEPROM_CODE_ADDR_END \
|
||||
(CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX + (CY_EM_EEPROM_FLASH_SIZE - 1u))
|
||||
#define CY_EM_EEPROM_CODE_ADDR_MASK (0xffffu)
|
||||
/* Checks if the EEPROM is in flash range */
|
||||
#define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \
|
||||
(((startAddr) > CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX) && \
|
||||
((endAddr) <= CY_EM_EEPROM_CODE_ADDR_END))
|
||||
#else
|
||||
/* Checks is the EEPROM is in flash range */
|
||||
#define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \
|
||||
(((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR))
|
||||
#endif /* (CY_PSOC3) */
|
||||
#else
|
||||
#define CY_EM_EEPROM_FLASH_BASE_ADDR (CY_FLASH_BASE)
|
||||
#define CY_EM_EEPROM_FLASH_SIZE (CY_FLASH_SIZE)
|
||||
#define CY_EM_EEPROM_EM_EEPROM_BASE_ADDR (CY_EM_EEPROM_BASE)
|
||||
#define CY_EM_EEPROM_EM_EEPROM_SIZE (CY_EM_EEPROM_SIZE)
|
||||
#define CY_EM_EEPROM_EM_EEPROM_END_ADDR (CY_EM_EEPROM_EM_EEPROM_BASE_ADDR + CY_EM_EEPROM_EM_EEPROM_SIZE)
|
||||
/* Checks is the EEPROM is in flash range */
|
||||
#define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \
|
||||
(((((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) || \
|
||||
(((startAddr) >= CY_EM_EEPROM_EM_EEPROM_BASE_ADDR) && \
|
||||
((endAddr) <= CY_EM_EEPROM_EM_EEPROM_END_ADDR))))
|
||||
#endif /* (!CY_PSOC6) */
|
||||
|
||||
#define CY_EM_EEPROM_FLASH_END_ADDR (CY_EM_EEPROM_FLASH_BASE_ADDR + CY_EM_EEPROM_FLASH_SIZE)
|
||||
|
||||
/* Defines the length of EEPROM data that can be stored in Em_EEPROM header */
|
||||
#define CY_EM_EEPROM_HEADER_DATA_LEN ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) - 16u)
|
||||
|
||||
#define CY_EM_EEPROM_ADDR_IN_RANGE (1u)
|
||||
|
||||
/* Return CY_EM_EEPROM_ADDR_IN_RANGE if addr exceeded the upper range of
|
||||
* EEPROM. The wear leveling overhead is included in the range but redundant copy
|
||||
* is excluded.
|
||||
*/
|
||||
#define CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(addr, endEepromAddr) \
|
||||
(((addr) >= (endEepromAddr)) ? (0u) : (CY_EM_EEPROM_ADDR_IN_RANGE))
|
||||
|
||||
/* Check to see if the specified address is present in the EEPROM */
|
||||
#define CY_EM_EEPROM_IS_ADDR_IN_RANGE(addr, startEepromAddr, endEepromAddr) \
|
||||
(((addr) > (startEepromAddr)) ? \
|
||||
(((addr) < (endEepromAddr)) ? (CY_EM_EEPROM_ADDR_IN_RANGE) : (0u)) : (0u))
|
||||
|
||||
/* Check if the EEPROM address locations from startAddr1 to endAddr1
|
||||
* are crossed with EEPROM address locations from startAddr2 to endAddr2.
|
||||
*/
|
||||
#define CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr1, endAddr1 , startAddr2, endAddr2) \
|
||||
(((startAddr1) > (startAddr2)) ? (((startAddr1) >= (endAddr2)) ? (0u) : (1u) ) : \
|
||||
(((startAddr2) >= (endAddr1)) ? (0u) : (1u)))
|
||||
|
||||
/* Return the pointer to the start of the redundant copy of the EEPROM */
|
||||
#define CY_EM_EEPROM_GET_REDNT_COPY_ADDR_BASE(numRows, wearLeveling, eepromStartAddr) \
|
||||
((((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) * (wearLeveling)) + (eepromStartAddr))
|
||||
|
||||
/* Return the number of the row in EM_EEPROM which contains an address defined by
|
||||
* rowAddr.
|
||||
*/
|
||||
#define CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(rowAddr, maxRows, eepromStartAddr) \
|
||||
((((rowAddr) - (eepromStartAddr)) / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % (maxRows))
|
||||
|
||||
|
||||
/** Returns the size allocated for the EEPROM excluding wear leveling and
|
||||
* redundant copy overhead.
|
||||
*/
|
||||
#define CY_EM_EEPROM_GET_EEPROM_SIZE(numRows) ((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW)
|
||||
|
||||
/* Check if the given address belongs to the EEPROM address of the row
|
||||
* specified by rowNum.
|
||||
*/
|
||||
#define CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum) \
|
||||
(((addr) < ((rowNum) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u))) ? (0u) : \
|
||||
(((addr) > ((((rowNum) + 1u) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u)) - 1u)) ? \
|
||||
(0u) : (1u)))
|
||||
|
||||
/* CRC-8 constants */
|
||||
#define CY_EM_EEPROM_CRC8_POLYNOM ((uint8)(0x31u))
|
||||
#define CY_EM_EEPROM_CRC8_POLYNOM_LEN (8u)
|
||||
#define CY_EM_EEPROM_CRC8_SEED (0xFFu)
|
||||
#define CY_EM_EEPROM_CRC8_XOR_VAL ((uint8) (0x80u))
|
||||
|
||||
#define CY_EM_EEPROM_CALCULATE_CRC8(crc) \
|
||||
((CY_EM_EEPROM_CRC8_XOR_VAL == ((crc) & CY_EM_EEPROM_CRC8_XOR_VAL)) ? \
|
||||
((uint8)(((uint8)((uint8)((crc) << 1u))) ^ CY_EM_EEPROM_CRC8_POLYNOM)) : ((uint8)((crc) << 1u)))
|
||||
|
||||
#define CY_EM_EEPROM_GET_SEQ_NUM(addr) (*(uint32*)(addr))
|
||||
|
||||
/** \endcond */
|
||||
|
||||
/**
|
||||
* \addtogroup group_em_eeprom_macros
|
||||
* \{
|
||||
*/
|
||||
|
||||
/** Calculate the number of flash rows required to create an Em_EEPROM of
|
||||
* dataSize.
|
||||
*/
|
||||
#define CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) \
|
||||
(((dataSize) / (CY_EM_EEPROM_EEPROM_DATA_LEN)) + \
|
||||
((((dataSize) % (CY_EM_EEPROM_EEPROM_DATA_LEN)) != 0u) ? 1U : 0U))
|
||||
|
||||
/** Returns the size of flash allocated for EEPROM including wear leveling and
|
||||
* redundant copy overhead.
|
||||
*/
|
||||
#define CY_EM_EEPROM_GET_PHYSICAL_SIZE(dataSize, wearLeveling, redundantCopy) \
|
||||
(((CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) * \
|
||||
CY_EM_EEPROM_FLASH_SIZEOF_ROW) * \
|
||||
(wearLeveling)) * (1uL + (redundantCopy)))
|
||||
|
||||
/** \} group_em_eeprom_macros */
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Local definitions
|
||||
*******************************************************************************/
|
||||
/** \cond INTERNAL */
|
||||
|
||||
/* Offsets for 32-bit RAM buffer addressing */
|
||||
#define CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) / 4u)
|
||||
#define CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32 (0u)
|
||||
#define CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32 (1u)
|
||||
#define CY_EM_EEPROM_HEADER_LEN_OFFSET_U32 (2u)
|
||||
#define CY_EM_EEPROM_HEADER_DATA_OFFSET_U32 (3u)
|
||||
#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32 (CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 - 1u)
|
||||
|
||||
/* The same offsets as above used for direct memory addressing */
|
||||
#define CY_EM_EEPROM_EEPROM_DATA_OFFSET (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u)
|
||||
#define CY_EM_EEPROM_HEADER_ADDR_OFFSET (4u)
|
||||
#define CY_EM_EEPROM_HEADER_LEN_OFFSET (8u)
|
||||
#define CY_EM_EEPROM_HEADER_DATA_OFFSET (12u)
|
||||
#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET (CY_EM_EEPROM_EEPROM_DATA_OFFSET - 4u)
|
||||
|
||||
#define CY_EM_EEPROM_U32_DIV (4u)
|
||||
|
||||
/* Maximum wear leveling value */
|
||||
#define CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR (10u)
|
||||
|
||||
/* Maximum allowed flash row write/erase operation duration */
|
||||
#define CY_EM_EEPROM_MAX_WRITE_DURATION_MS (50u)
|
||||
|
||||
/** \endcond */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* CY_EM_EEPROM_H */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,14 +1,14 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cydevice.h
|
||||
* OBSOLETE: Do not use this file. Use the _trm version instead.
|
||||
* PSoC Creator 4.1
|
||||
* PSoC Creator 4.2
|
||||
*
|
||||
* Description:
|
||||
* This file provides all of the address values for the entire PSoC device.
|
||||
* This file is automatically generated by PSoC Creator.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
|
||||
* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cydevice_trm.h
|
||||
*
|
||||
* PSoC Creator 4.1
|
||||
* PSoC Creator 4.2
|
||||
*
|
||||
* Description:
|
||||
* This file provides all of the address values for the entire PSoC device.
|
||||
* This file is automatically generated by PSoC Creator.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
|
||||
* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cydevicegnu.inc
|
||||
* OBSOLETE: Do not use this file. Use the _trm version instead.
|
||||
* PSoC Creator 4.1
|
||||
* PSoC Creator 4.2
|
||||
*
|
||||
* Description:
|
||||
* This file provides all of the address values for the entire PSoC device.
|
||||
* This file is automatically generated by PSoC Creator.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
|
||||
* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cydevicegnu_trm.inc
|
||||
*
|
||||
* PSoC Creator 4.1
|
||||
* PSoC Creator 4.2
|
||||
*
|
||||
* Description:
|
||||
* This file provides all of the address values for the entire PSoC device.
|
||||
* This file is automatically generated by PSoC Creator.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
|
||||
* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
;
|
||||
; File Name: cydeviceiar.inc
|
||||
; OBSOLETE: Do not use this file. Use the _trm version instead.
|
||||
; PSoC Creator 4.1
|
||||
; PSoC Creator 4.2
|
||||
;
|
||||
; Description:
|
||||
; This file provides all of the address values for the entire PSoC device.
|
||||
;
|
||||
;-------------------------------------------------------------------------------
|
||||
; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
|
||||
; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
|
||||
; You may use this file only in accordance with the license, terms, conditions,
|
||||
; disclaimers, and limitations in the end user license agreement accompanying
|
||||
; the software package with which this file was provided.
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
;
|
||||
; File Name: cydeviceiar_trm.inc
|
||||
;
|
||||
; PSoC Creator 4.1
|
||||
; PSoC Creator 4.2
|
||||
;
|
||||
; Description:
|
||||
; This file provides all of the address values for the entire PSoC device.
|
||||
;
|
||||
;-------------------------------------------------------------------------------
|
||||
; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
|
||||
; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
|
||||
; You may use this file only in accordance with the license, terms, conditions,
|
||||
; disclaimers, and limitations in the end user license agreement accompanying
|
||||
; the software package with which this file was provided.
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
;
|
||||
; File Name: cydevicerv.inc
|
||||
; OBSOLETE: Do not use this file. Use the _trm version instead.
|
||||
; PSoC Creator 4.1
|
||||
; PSoC Creator 4.2
|
||||
;
|
||||
; Description:
|
||||
; This file provides all of the address values for the entire PSoC device.
|
||||
;
|
||||
;-------------------------------------------------------------------------------
|
||||
; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
|
||||
; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
|
||||
; You may use this file only in accordance with the license, terms, conditions,
|
||||
; disclaimers, and limitations in the end user license agreement accompanying
|
||||
; the software package with which this file was provided.
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
;
|
||||
; File Name: cydevicerv_trm.inc
|
||||
;
|
||||
; PSoC Creator 4.1
|
||||
; PSoC Creator 4.2
|
||||
;
|
||||
; Description:
|
||||
; This file provides all of the address values for the entire PSoC device.
|
||||
;
|
||||
;-------------------------------------------------------------------------------
|
||||
; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
|
||||
; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
|
||||
; You may use this file only in accordance with the license, terms, conditions,
|
||||
; disclaimers, and limitations in the end user license agreement accompanying
|
||||
; the software package with which this file was provided.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -2,7 +2,7 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cyfitter_cfg.c
|
||||
*
|
||||
* PSoC Creator 4.1
|
||||
* PSoC Creator 4.2
|
||||
*
|
||||
* Description:
|
||||
* This file contains device initialization code.
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
* This file is automatically generated by PSoC Creator.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
|
||||
* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
|
|
@ -101,6 +101,7 @@ static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
|
|||
#define CYCLOCKSTART_32KHZ_ERROR 2u
|
||||
#define CYCLOCKSTART_PLL_ERROR 3u
|
||||
#define CYCLOCKSTART_FLL_ERROR 4u
|
||||
#define CYCLOCKSTART_WCO_ERROR 5u
|
||||
|
||||
|
||||
#ifdef CY_NEED_CYCLOCKSTARTUPERROR
|
||||
|
|
@ -124,12 +125,8 @@ static void CyClockStartupError(uint8 errorCode);
|
|||
CY_CFG_UNUSED
|
||||
static void CyClockStartupError(uint8 errorCode)
|
||||
{
|
||||
/* To remove the compiler warning if errorCode not used. */
|
||||
#if defined(CY_PSOC3) && (CY_PSOC3)
|
||||
/* To remove the compiler warning if errorCode not used. */
|
||||
errorCode = errorCode;
|
||||
#else
|
||||
(void)errorCode;
|
||||
#endif /* CY_PSOC3 */
|
||||
|
||||
/* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */
|
||||
/* we will end up here to allow the customer to implement something to */
|
||||
|
|
@ -403,7 +400,7 @@ void cyfitter_cfg(void)
|
|||
|
||||
|
||||
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
|
||||
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));
|
||||
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x61u : 0x60u));
|
||||
/* Setup clocks based on selections from Clock DWR */
|
||||
ClockSetup();
|
||||
/* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cyfitter_cfg.h
|
||||
*
|
||||
* PSoC Creator 4.1
|
||||
* PSoC Creator 4.2
|
||||
*
|
||||
* Description:
|
||||
* This file provides basic startup and mux configuration settings
|
||||
* This file is automatically generated by PSoC Creator.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
|
||||
* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,14 +1,14 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cymetadata.c
|
||||
*
|
||||
* PSoC Creator 4.1
|
||||
* PSoC Creator 4.2
|
||||
*
|
||||
* Description:
|
||||
* This file defines all extra memory spaces that need to be included.
|
||||
* This file is automatically generated by PSoC Creator.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
|
||||
* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
/*******************************************************************************
|
||||
* File Name: project.h
|
||||
*
|
||||
* PSoC Creator 4.1
|
||||
* PSoC Creator 4.2
|
||||
*
|
||||
* Description:
|
||||
* It contains references to all generated header files and should not be modified.
|
||||
* This file is automatically generated by PSoC Creator.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
|
||||
* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
|
|
@ -85,6 +85,7 @@
|
|||
#include "cyPm.h"
|
||||
#include "CySpc.h"
|
||||
#include "cytypes.h"
|
||||
#include "cy_em_eeprom.h"
|
||||
|
||||
/*[]*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,42 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
|
||||
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006461" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006481" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006491" bitWidth="8" desc="" hidden="false">
|
||||
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="Enable counter" />
|
||||
<value name="DISABLED" value="0" desc="Disable counter" />
|
||||
</field>
|
||||
<field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="Interrupt enabled" />
|
||||
<value name="DISABLED" value="0" desc="Interrupt disabled" />
|
||||
</field>
|
||||
<field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
|
||||
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
|
||||
</field>
|
||||
<field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
|
||||
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
|
||||
</field>
|
||||
<field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="Clear FIFO state" />
|
||||
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
|
||||
</field>
|
||||
<field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="Clear FIFO state" />
|
||||
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
|
||||
</field>
|
||||
</register>
|
||||
</block>
|
||||
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
|
|
@ -65,21 +95,19 @@
|
|||
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
|
||||
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
|
||||
</block>
|
||||
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006477" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Filtered_STATUS_REG" address="0x40006462" bitWidth="8" desc="" hidden="false" />
|
||||
|
|
@ -111,39 +139,12 @@
|
|||
</field>
|
||||
</register>
|
||||
</block>
|
||||
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006461" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006481" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006491" bitWidth="8" desc="" hidden="false">
|
||||
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="Enable counter" />
|
||||
<value name="DISABLED" value="0" desc="Disable counter" />
|
||||
</field>
|
||||
<field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="Interrupt enabled" />
|
||||
<value name="DISABLED" value="0" desc="Interrupt disabled" />
|
||||
</field>
|
||||
<field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
|
||||
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
|
||||
</field>
|
||||
<field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
|
||||
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
|
||||
</field>
|
||||
<field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="Clear FIFO state" />
|
||||
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
|
||||
</field>
|
||||
<field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="Clear FIFO state" />
|
||||
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
|
||||
</field>
|
||||
</register>
|
||||
</block>
|
||||
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
|
|
|
|||
|
|
@ -450,6 +450,7 @@
|
|||
<Group key="Component">
|
||||
<Group key="v1">
|
||||
<Data key="cy_boot" value="cy_boot_v5_50" />
|
||||
<Data key="Em_EEPROM_Dynamic" value="Em_EEPROM_Dynamic_v2_0" />
|
||||
<Data key="LIN_Dynamic" value="LIN_Dynamic_v3_40" />
|
||||
</Group>
|
||||
</Group>
|
||||
|
|
@ -3603,8 +3604,20 @@
|
|||
</Group>
|
||||
</Group>
|
||||
<Group key="Interrupt">
|
||||
<Data key="4abaf846-60a1-4cfc-b1e0-6eb532fa6a05" value="0" />
|
||||
<Data key="791071b3-a348-49c4-b578-64e66d701d0f/d91ea660-bc91-4817-b29b-2fe86c305500" value="6" />
|
||||
<Group key="4abaf846-60a1-4cfc-b1e0-6eb532fa6a05">
|
||||
<Group key="CortexM3">
|
||||
<Data key="Assigned" value="True" />
|
||||
<Data key="Priority" value="0" />
|
||||
<Data key="Vector" value="-1" />
|
||||
</Group>
|
||||
</Group>
|
||||
<Group key="791071b3-a348-49c4-b578-64e66d701d0f/d91ea660-bc91-4817-b29b-2fe86c305500">
|
||||
<Group key="CortexM3">
|
||||
<Data key="Assigned" value="True" />
|
||||
<Data key="Priority" value="6" />
|
||||
<Data key="Vector" value="-1" />
|
||||
</Group>
|
||||
</Group>
|
||||
</Group>
|
||||
<Group key="Pin2">
|
||||
<Group key="1bd12db2-da87-4f00-90d1-0a734e846c58">
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -2848,6 +2848,32 @@
|
|||
<build_action v="OTHER;;;;" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">
|
||||
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="Em_EEPROM_Dynamic" persistent="">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemListSerialize" version="2">
|
||||
<dependencies>
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="cy_em_eeprom.c" persistent="Generated_Source\PSoC5\cy_em_eeprom.c">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="SOURCE_C;CortexM3;;;" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="cy_em_eeprom.h" persistent="Generated_Source\PSoC5\cy_em_eeprom.h">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="HEADER;;;;" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
</dependencies>
|
||||
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
|
||||
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
|
||||
<filters />
|
||||
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
|
||||
</dependencies>
|
||||
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
|
||||
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
|
||||
|
|
@ -3456,8 +3482,8 @@
|
|||
</platforms>
|
||||
<project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />
|
||||
<last_selected_tab v="Cypress" />
|
||||
<WriteAppVersionLastSavedWith v="4.1.0.2686" />
|
||||
<WriteAppMarketingVersionLastSavedWith v=" 4.1" />
|
||||
<WriteAppVersionLastSavedWith v="4.2.0.641" />
|
||||
<WriteAppMarketingVersionLastSavedWith v=" 4.2" />
|
||||
<project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" />
|
||||
<GenerateDescriptionFiles v="False" />
|
||||
</CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
|
||||
|
|
|
|||
|
|
@ -6,6 +6,161 @@
|
|||
<addressUnitBits>8</addressUnitBits>
|
||||
<width>32</width>
|
||||
<peripherals>
|
||||
<peripheral>
|
||||
<name>SCSI_Parity_Error</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x0</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>SCSI_Parity_Error_STATUS_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x40006461</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
<register>
|
||||
<name>SCSI_Parity_Error_MASK_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x40006481</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
<register>
|
||||
<name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x40006491</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>FIFO0</name>
|
||||
<description>FIFO0 clear</description>
|
||||
<lsb>5</lsb>
|
||||
<msb>5</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>ENABLED</name>
|
||||
<description>Enable counter</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>DISABLED</name>
|
||||
<description>Disable counter</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>INTRENBL</name>
|
||||
<description>Enables or disables the Interrupt</description>
|
||||
<lsb>4</lsb>
|
||||
<msb>4</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>ENABLED</name>
|
||||
<description>Interrupt enabled</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>DISABLED</name>
|
||||
<description>Interrupt disabled</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>FIFO1LEVEL</name>
|
||||
<description>FIFO level</description>
|
||||
<lsb>3</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>ENABLED</name>
|
||||
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>DISABLED</name>
|
||||
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>FIFO0LEVEL</name>
|
||||
<description>FIFO level</description>
|
||||
<lsb>2</lsb>
|
||||
<msb>2</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>ENABLED</name>
|
||||
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>DISABLED</name>
|
||||
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>FIFO1CLEAR</name>
|
||||
<description>FIFO clear</description>
|
||||
<lsb>1</lsb>
|
||||
<msb>1</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>ENABLED</name>
|
||||
<description>Clear FIFO state</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>DISABLED</name>
|
||||
<description>Normal FIFO operation</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>FIFO0CLEAR</name>
|
||||
<description>FIFO clear</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>0</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>ENABLED</name>
|
||||
<description>Clear FIFO state</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>DISABLED</name>
|
||||
<description>Normal FIFO operation</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>Debug_Timer</name>
|
||||
<description>No description available</description>
|
||||
|
|
@ -298,31 +453,10 @@
|
|||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_Out_Ctl</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006478</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>SCSI_Out_Ctl_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_Glitch_Ctl</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006477</baseAddress>
|
||||
<baseAddress>0x0</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
|
|
@ -332,7 +466,7 @@
|
|||
<register>
|
||||
<name>SCSI_Glitch_Ctl_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<addressOffset>0x40006477</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -343,7 +477,7 @@
|
|||
<peripheral>
|
||||
<name>SCSI_Filtered</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006462</baseAddress>
|
||||
<baseAddress>0x0</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
|
|
@ -353,7 +487,7 @@
|
|||
<register>
|
||||
<name>SCSI_Filtered_STATUS_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<addressOffset>0x40006462</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -362,7 +496,7 @@
|
|||
<register>
|
||||
<name>SCSI_Filtered_MASK_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x20</addressOffset>
|
||||
<addressOffset>0x40006482</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -371,7 +505,7 @@
|
|||
<register>
|
||||
<name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x30</addressOffset>
|
||||
<addressOffset>0x40006492</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -496,9 +630,9 @@
|
|||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_Parity_Error</name>
|
||||
<name>SCSI_Out_Ctl</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006461</baseAddress>
|
||||
<baseAddress>0x0</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
|
|
@ -506,154 +640,20 @@
|
|||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>SCSI_Parity_Error_STATUS_REG</name>
|
||||
<name>SCSI_Out_Ctl_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<addressOffset>0x40006478</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
<register>
|
||||
<name>SCSI_Parity_Error_MASK_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x20</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
<register>
|
||||
<name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x30</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>FIFO0</name>
|
||||
<description>FIFO0 clear</description>
|
||||
<lsb>5</lsb>
|
||||
<msb>5</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>ENABLED</name>
|
||||
<description>Enable counter</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>DISABLED</name>
|
||||
<description>Disable counter</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>INTRENBL</name>
|
||||
<description>Enables or disables the Interrupt</description>
|
||||
<lsb>4</lsb>
|
||||
<msb>4</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>ENABLED</name>
|
||||
<description>Interrupt enabled</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>DISABLED</name>
|
||||
<description>Interrupt disabled</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>FIFO1LEVEL</name>
|
||||
<description>FIFO level</description>
|
||||
<lsb>3</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>ENABLED</name>
|
||||
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>DISABLED</name>
|
||||
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>FIFO0LEVEL</name>
|
||||
<description>FIFO level</description>
|
||||
<lsb>2</lsb>
|
||||
<msb>2</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>ENABLED</name>
|
||||
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>DISABLED</name>
|
||||
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>FIFO1CLEAR</name>
|
||||
<description>FIFO clear</description>
|
||||
<lsb>1</lsb>
|
||||
<msb>1</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>ENABLED</name>
|
||||
<description>Clear FIFO state</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>DISABLED</name>
|
||||
<description>Normal FIFO operation</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>FIFO0CLEAR</name>
|
||||
<description>FIFO clear</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>0</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>ENABLED</name>
|
||||
<description>Clear FIFO state</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>DISABLED</name>
|
||||
<description>Normal FIFO operation</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_CTL_PHASE</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006475</baseAddress>
|
||||
<baseAddress>0x0</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
|
|
@ -663,7 +663,7 @@
|
|||
<register>
|
||||
<name>SCSI_CTL_PHASE_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<addressOffset>0x40006475</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -2912,7 +2912,7 @@
|
|||
<peripheral>
|
||||
<name>SCSI_Out_Bits</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006578</baseAddress>
|
||||
<baseAddress>0x0</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
|
|
@ -2922,7 +2922,7 @@
|
|||
<register>
|
||||
<name>SCSI_Out_Bits_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<addressOffset>0x40006578</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
|
|||
|
|
@ -420,34 +420,34 @@
|
|||
#define EXTLED__SLW CYREG_PRT0_SLW
|
||||
|
||||
/* SDCard */
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL
|
||||
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK
|
||||
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
|
||||
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK
|
||||
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL
|
||||
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK
|
||||
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
|
||||
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK
|
||||
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
|
||||
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
|
||||
#define SDCard_BSPIM_RxStsReg__4__POS 4
|
||||
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
|
||||
|
|
@ -455,9 +455,9 @@
|
|||
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
|
||||
#define SDCard_BSPIM_RxStsReg__6__POS 6
|
||||
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
|
||||
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST
|
||||
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
|
||||
|
|
@ -1896,15 +1896,15 @@
|
|||
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
|
||||
|
|
@ -1917,35 +1917,35 @@
|
|||
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
|
||||
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
|
||||
#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX
|
||||
#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE
|
||||
|
|
@ -2767,8 +2767,8 @@
|
|||
#define scsiTarget_StatusReg__0__POS 0
|
||||
#define scsiTarget_StatusReg__1__MASK 0x02u
|
||||
#define scsiTarget_StatusReg__1__POS 1
|
||||
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
|
||||
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
|
||||
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
|
||||
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
|
||||
#define scsiTarget_StatusReg__2__MASK 0x04u
|
||||
#define scsiTarget_StatusReg__2__POS 2
|
||||
#define scsiTarget_StatusReg__3__MASK 0x08u
|
||||
|
|
@ -2776,13 +2776,9 @@
|
|||
#define scsiTarget_StatusReg__4__MASK 0x10u
|
||||
#define scsiTarget_StatusReg__4__POS 4
|
||||
#define scsiTarget_StatusReg__MASK 0x1Fu
|
||||
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB07_MSK
|
||||
#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
|
||||
#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
|
||||
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
|
||||
#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL
|
||||
#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL
|
||||
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST
|
||||
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB02_MSK
|
||||
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
|
||||
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST
|
||||
|
||||
/* Debug_Timer */
|
||||
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
||||
|
|
@ -2897,8 +2893,8 @@
|
|||
#define SCSI_Filtered_sts_sts_reg__0__POS 0
|
||||
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
|
||||
#define SCSI_Filtered_sts_sts_reg__1__POS 1
|
||||
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
|
||||
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST
|
||||
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
|
||||
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
|
||||
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
|
||||
#define SCSI_Filtered_sts_sts_reg__2__POS 2
|
||||
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
|
||||
|
|
@ -2906,67 +2902,67 @@
|
|||
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
|
||||
#define SCSI_Filtered_sts_sts_reg__4__POS 4
|
||||
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
|
||||
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK
|
||||
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL
|
||||
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST
|
||||
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
|
||||
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
|
||||
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
|
||||
|
||||
/* SCSI_CTL_PHASE */
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK
|
||||
|
||||
/* SCSI_Glitch_Ctl */
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
|
||||
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
|
||||
|
||||
/* SCSI_Parity_Error */
|
||||
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
|
||||
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
|
||||
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
|
||||
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
|
||||
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
|
||||
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
|
||||
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
|
||||
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
|
||||
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
|
||||
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
|
||||
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK
|
||||
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
|
||||
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST
|
||||
|
||||
/* Miscellaneous */
|
||||
#define BCLK__BUS_CLK__HZ 50000000U
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -420,34 +420,34 @@
|
|||
.set EXTLED__SLW, CYREG_PRT0_SLW
|
||||
|
||||
/* SDCard */
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
|
||||
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
|
||||
.set SDCard_BSPIM_RxStsReg__4__POS, 4
|
||||
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
|
||||
|
|
@ -455,9 +455,9 @@
|
|||
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
|
||||
.set SDCard_BSPIM_RxStsReg__6__POS, 6
|
||||
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
|
||||
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
|
||||
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
|
||||
|
|
@ -1896,15 +1896,15 @@
|
|||
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
|
||||
|
|
@ -1917,35 +1917,35 @@
|
|||
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
|
||||
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
|
||||
.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX
|
||||
.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE
|
||||
|
|
@ -2767,8 +2767,8 @@
|
|||
.set scsiTarget_StatusReg__0__POS, 0
|
||||
.set scsiTarget_StatusReg__1__MASK, 0x02
|
||||
.set scsiTarget_StatusReg__1__POS, 1
|
||||
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
|
||||
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
|
||||
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
|
||||
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
|
||||
.set scsiTarget_StatusReg__2__MASK, 0x04
|
||||
.set scsiTarget_StatusReg__2__POS, 2
|
||||
.set scsiTarget_StatusReg__3__MASK, 0x08
|
||||
|
|
@ -2776,13 +2776,9 @@
|
|||
.set scsiTarget_StatusReg__4__MASK, 0x10
|
||||
.set scsiTarget_StatusReg__4__POS, 4
|
||||
.set scsiTarget_StatusReg__MASK, 0x1F
|
||||
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB07_MSK
|
||||
.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
|
||||
.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
|
||||
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
|
||||
.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL
|
||||
.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL
|
||||
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB07_ST
|
||||
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB02_MSK
|
||||
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
|
||||
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB02_ST
|
||||
|
||||
/* Debug_Timer */
|
||||
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
|
|
@ -2897,8 +2893,8 @@
|
|||
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
|
||||
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
|
||||
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
|
||||
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
|
||||
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST
|
||||
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
|
||||
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
|
||||
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
|
||||
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
|
||||
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
|
||||
|
|
@ -2906,67 +2902,67 @@
|
|||
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
|
||||
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
|
||||
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
|
||||
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB13_MSK
|
||||
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
|
||||
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB13_ST
|
||||
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
|
||||
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
|
||||
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
|
||||
|
||||
/* SCSI_CTL_PHASE */
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK
|
||||
|
||||
/* SCSI_Glitch_Ctl */
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
|
||||
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
|
||||
|
||||
/* SCSI_Parity_Error */
|
||||
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
|
||||
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
|
||||
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
|
||||
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
|
||||
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
|
||||
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
|
||||
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
|
||||
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
|
||||
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
|
||||
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
|
||||
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK
|
||||
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
|
||||
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST
|
||||
|
||||
/* Miscellaneous */
|
||||
.set BCLK__BUS_CLK__HZ, 50000000
|
||||
|
|
|
|||
|
|
@ -419,34 +419,34 @@ EXTLED__SHIFT EQU 0
|
|||
EXTLED__SLW EQU CYREG_PRT0_SLW
|
||||
|
||||
/* SDCard */
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
|
||||
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_RxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
|
||||
|
|
@ -454,9 +454,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
|
|||
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
|
||||
SDCard_BSPIM_RxStsReg__6__POS EQU 6
|
||||
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
|
||||
|
|
@ -1895,15 +1895,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
|
|||
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
|
||||
|
|
@ -1916,35 +1916,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
|
|||
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
|
||||
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
|
||||
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
|
||||
SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
|
||||
|
|
@ -2766,8 +2766,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
|
|||
scsiTarget_StatusReg__0__POS EQU 0
|
||||
scsiTarget_StatusReg__1__MASK EQU 0x02
|
||||
scsiTarget_StatusReg__1__POS EQU 1
|
||||
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
|
||||
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
|
||||
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
|
||||
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
|
||||
scsiTarget_StatusReg__2__MASK EQU 0x04
|
||||
scsiTarget_StatusReg__2__POS EQU 2
|
||||
scsiTarget_StatusReg__3__MASK EQU 0x08
|
||||
|
|
@ -2775,13 +2775,9 @@ scsiTarget_StatusReg__3__POS EQU 3
|
|||
scsiTarget_StatusReg__4__MASK EQU 0x10
|
||||
scsiTarget_StatusReg__4__POS EQU 4
|
||||
scsiTarget_StatusReg__MASK EQU 0x1F
|
||||
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK
|
||||
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
|
||||
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
|
||||
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
|
||||
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
|
||||
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
|
||||
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST
|
||||
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK
|
||||
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
|
||||
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST
|
||||
|
||||
/* Debug_Timer */
|
||||
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
|
|
@ -2896,8 +2892,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
|
|||
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
|
||||
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
|
||||
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
|
||||
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
|
||||
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
|
||||
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
|
||||
|
|
@ -2905,67 +2901,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
|
|||
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
|
||||
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
|
||||
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
|
||||
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST
|
||||
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
|
||||
|
||||
/* SCSI_CTL_PHASE */
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
|
||||
|
||||
/* SCSI_Glitch_Ctl */
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
|
||||
|
||||
/* SCSI_Parity_Error */
|
||||
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
|
||||
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
|
||||
|
||||
/* Miscellaneous */
|
||||
BCLK__BUS_CLK__HZ EQU 50000000
|
||||
|
|
|
|||
|
|
@ -419,34 +419,34 @@ EXTLED__SHIFT EQU 0
|
|||
EXTLED__SLW EQU CYREG_PRT0_SLW
|
||||
|
||||
; SDCard
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
|
||||
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_RxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
|
||||
|
|
@ -454,9 +454,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
|
|||
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
|
||||
SDCard_BSPIM_RxStsReg__6__POS EQU 6
|
||||
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
|
||||
|
|
@ -1895,15 +1895,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
|
|||
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
|
||||
|
|
@ -1916,35 +1916,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
|
|||
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
|
||||
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
|
||||
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
|
||||
SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
|
||||
|
|
@ -2766,8 +2766,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
|
|||
scsiTarget_StatusReg__0__POS EQU 0
|
||||
scsiTarget_StatusReg__1__MASK EQU 0x02
|
||||
scsiTarget_StatusReg__1__POS EQU 1
|
||||
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
|
||||
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
|
||||
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
|
||||
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
|
||||
scsiTarget_StatusReg__2__MASK EQU 0x04
|
||||
scsiTarget_StatusReg__2__POS EQU 2
|
||||
scsiTarget_StatusReg__3__MASK EQU 0x08
|
||||
|
|
@ -2775,13 +2775,9 @@ scsiTarget_StatusReg__3__POS EQU 3
|
|||
scsiTarget_StatusReg__4__MASK EQU 0x10
|
||||
scsiTarget_StatusReg__4__POS EQU 4
|
||||
scsiTarget_StatusReg__MASK EQU 0x1F
|
||||
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK
|
||||
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
|
||||
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
|
||||
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
|
||||
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
|
||||
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
|
||||
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST
|
||||
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK
|
||||
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
|
||||
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST
|
||||
|
||||
; Debug_Timer
|
||||
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
|
|
@ -2896,8 +2892,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
|
|||
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
|
||||
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
|
||||
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
|
||||
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
|
||||
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
|
||||
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
|
||||
|
|
@ -2905,67 +2901,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
|
|||
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
|
||||
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
|
||||
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
|
||||
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST
|
||||
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
|
||||
|
||||
; SCSI_CTL_PHASE
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
|
||||
|
||||
; SCSI_Glitch_Ctl
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
|
||||
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
|
||||
|
||||
; SCSI_Parity_Error
|
||||
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
|
||||
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
|
||||
|
||||
; Miscellaneous
|
||||
BCLK__BUS_CLK__HZ EQU 50000000
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@
|
|||
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Filtered_STATUS_REG" address="0x4000646D" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Filtered_MASK_REG" address="0x4000648D" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649D" bitWidth="8" desc="" hidden="false">
|
||||
<register name="SCSI_Filtered_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Filtered_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">
|
||||
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="Enable counter" />
|
||||
<value name="DISABLED" value="0" desc="Disable counter" />
|
||||
|
|
@ -34,9 +34,9 @@
|
|||
</register>
|
||||
</block>
|
||||
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Parity_Error_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">
|
||||
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="" hidden="false">
|
||||
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
|
||||
<value name="ENABLED" value="1" desc="Enable counter" />
|
||||
<value name="DISABLED" value="0" desc="Disable counter" />
|
||||
|
|
@ -77,7 +77,7 @@
|
|||
<block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
|
|
@ -98,7 +98,7 @@
|
|||
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006476" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
|
|
@ -1019,10 +1019,10 @@
|
|||
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
|
||||
</block>
|
||||
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006477" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
|
||||
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" hidden="false" />
|
||||
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" hidden="false" />
|
||||
</block>
|
||||
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -19,7 +19,7 @@
|
|||
<register>
|
||||
<name>SCSI_Filtered_STATUS_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x4000646D</addressOffset>
|
||||
<addressOffset>0x4000646B</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
<register>
|
||||
<name>SCSI_Filtered_MASK_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x4000648D</addressOffset>
|
||||
<addressOffset>0x4000648B</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
<register>
|
||||
<name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x4000649D</addressOffset>
|
||||
<addressOffset>0x4000649B</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -174,7 +174,7 @@
|
|||
<register>
|
||||
<name>SCSI_Parity_Error_STATUS_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x4000646B</addressOffset>
|
||||
<addressOffset>0x40006465</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -183,7 +183,7 @@
|
|||
<register>
|
||||
<name>SCSI_Parity_Error_MASK_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x4000648B</addressOffset>
|
||||
<addressOffset>0x40006485</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -192,7 +192,7 @@
|
|||
<register>
|
||||
<name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x4000649B</addressOffset>
|
||||
<addressOffset>0x40006495</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -329,7 +329,7 @@
|
|||
<register>
|
||||
<name>SCSI_Glitch_Ctl_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x40006473</addressOffset>
|
||||
<addressOffset>0x40006474</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -350,7 +350,7 @@
|
|||
<register>
|
||||
<name>SCSI_CTL_PHASE_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x40006472</addressOffset>
|
||||
<addressOffset>0x40006476</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -2901,7 +2901,7 @@
|
|||
<register>
|
||||
<name>SCSI_Out_Ctl_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x40006477</addressOffset>
|
||||
<addressOffset>0x4000647C</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
@ -2922,7 +2922,7 @@
|
|||
<register>
|
||||
<name>SCSI_Out_Bits_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x4000647A</addressOffset>
|
||||
<addressOffset>0x4000647E</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
|
|
|
|||
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Loading…
Reference in New Issue