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166 lines
6.1 KiB
C
166 lines
6.1 KiB
C
/*******************************************************************************
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* File Name: nNOR_WP.h
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* Version 2.20
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*
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* Description:
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* This file contains Pin function prototypes and register defines
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*
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* Note:
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*
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********************************************************************************
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* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#if !defined(CY_PINS_nNOR_WP_H) /* Pins nNOR_WP_H */
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#define CY_PINS_nNOR_WP_H
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#include "cytypes.h"
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#include "cyfitter.h"
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#include "cypins.h"
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#include "nNOR_WP_aliases.h"
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/* APIs are not generated for P15[7:6] */
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#if !(CY_PSOC5A &&\
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nNOR_WP__PORT == 15 && ((nNOR_WP__MASK & 0xC0) != 0))
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/***************************************
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* Function Prototypes
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***************************************/
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/**
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* \addtogroup group_general
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* @{
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*/
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void nNOR_WP_Write(uint8 value);
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void nNOR_WP_SetDriveMode(uint8 mode);
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uint8 nNOR_WP_ReadDataReg(void);
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uint8 nNOR_WP_Read(void);
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void nNOR_WP_SetInterruptMode(uint16 position, uint16 mode);
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uint8 nNOR_WP_ClearInterrupt(void);
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/** @} general */
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/***************************************
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* API Constants
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***************************************/
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/**
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* \addtogroup group_constants
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* @{
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*/
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/** \addtogroup driveMode Drive mode constants
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* \brief Constants to be passed as "mode" parameter in the nNOR_WP_SetDriveMode() function.
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* @{
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*/
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#define nNOR_WP_DM_ALG_HIZ PIN_DM_ALG_HIZ
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#define nNOR_WP_DM_DIG_HIZ PIN_DM_DIG_HIZ
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#define nNOR_WP_DM_RES_UP PIN_DM_RES_UP
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#define nNOR_WP_DM_RES_DWN PIN_DM_RES_DWN
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#define nNOR_WP_DM_OD_LO PIN_DM_OD_LO
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#define nNOR_WP_DM_OD_HI PIN_DM_OD_HI
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#define nNOR_WP_DM_STRONG PIN_DM_STRONG
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#define nNOR_WP_DM_RES_UPDWN PIN_DM_RES_UPDWN
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/** @} driveMode */
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/** @} group_constants */
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/* Digital Port Constants */
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#define nNOR_WP_MASK nNOR_WP__MASK
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#define nNOR_WP_SHIFT nNOR_WP__SHIFT
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#define nNOR_WP_WIDTH 1u
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/* Interrupt constants */
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#if defined(nNOR_WP__INTSTAT)
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/**
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* \addtogroup group_constants
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* @{
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*/
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/** \addtogroup intrMode Interrupt constants
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* \brief Constants to be passed as "mode" parameter in nNOR_WP_SetInterruptMode() function.
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* @{
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*/
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#define nNOR_WP_INTR_NONE (uint16)(0x0000u)
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#define nNOR_WP_INTR_RISING (uint16)(0x0001u)
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#define nNOR_WP_INTR_FALLING (uint16)(0x0002u)
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#define nNOR_WP_INTR_BOTH (uint16)(0x0003u)
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/** @} intrMode */
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/** @} group_constants */
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#define nNOR_WP_INTR_MASK (0x01u)
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#endif /* (nNOR_WP__INTSTAT) */
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/***************************************
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* Registers
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***************************************/
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/* Main Port Registers */
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/* Pin State */
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#define nNOR_WP_PS (* (reg8 *) nNOR_WP__PS)
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/* Data Register */
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#define nNOR_WP_DR (* (reg8 *) nNOR_WP__DR)
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/* Port Number */
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#define nNOR_WP_PRT_NUM (* (reg8 *) nNOR_WP__PRT)
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/* Connect to Analog Globals */
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#define nNOR_WP_AG (* (reg8 *) nNOR_WP__AG)
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/* Analog MUX bux enable */
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#define nNOR_WP_AMUX (* (reg8 *) nNOR_WP__AMUX)
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/* Bidirectional Enable */
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#define nNOR_WP_BIE (* (reg8 *) nNOR_WP__BIE)
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/* Bit-mask for Aliased Register Access */
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#define nNOR_WP_BIT_MASK (* (reg8 *) nNOR_WP__BIT_MASK)
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/* Bypass Enable */
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#define nNOR_WP_BYP (* (reg8 *) nNOR_WP__BYP)
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/* Port wide control signals */
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#define nNOR_WP_CTL (* (reg8 *) nNOR_WP__CTL)
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/* Drive Modes */
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#define nNOR_WP_DM0 (* (reg8 *) nNOR_WP__DM0)
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#define nNOR_WP_DM1 (* (reg8 *) nNOR_WP__DM1)
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#define nNOR_WP_DM2 (* (reg8 *) nNOR_WP__DM2)
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/* Input Buffer Disable Override */
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#define nNOR_WP_INP_DIS (* (reg8 *) nNOR_WP__INP_DIS)
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/* LCD Common or Segment Drive */
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#define nNOR_WP_LCD_COM_SEG (* (reg8 *) nNOR_WP__LCD_COM_SEG)
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/* Enable Segment LCD */
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#define nNOR_WP_LCD_EN (* (reg8 *) nNOR_WP__LCD_EN)
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/* Slew Rate Control */
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#define nNOR_WP_SLW (* (reg8 *) nNOR_WP__SLW)
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/* DSI Port Registers */
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/* Global DSI Select Register */
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#define nNOR_WP_PRTDSI__CAPS_SEL (* (reg8 *) nNOR_WP__PRTDSI__CAPS_SEL)
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/* Double Sync Enable */
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#define nNOR_WP_PRTDSI__DBL_SYNC_IN (* (reg8 *) nNOR_WP__PRTDSI__DBL_SYNC_IN)
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/* Output Enable Select Drive Strength */
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#define nNOR_WP_PRTDSI__OE_SEL0 (* (reg8 *) nNOR_WP__PRTDSI__OE_SEL0)
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#define nNOR_WP_PRTDSI__OE_SEL1 (* (reg8 *) nNOR_WP__PRTDSI__OE_SEL1)
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/* Port Pin Output Select Registers */
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#define nNOR_WP_PRTDSI__OUT_SEL0 (* (reg8 *) nNOR_WP__PRTDSI__OUT_SEL0)
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#define nNOR_WP_PRTDSI__OUT_SEL1 (* (reg8 *) nNOR_WP__PRTDSI__OUT_SEL1)
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/* Sync Output Enable Registers */
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#define nNOR_WP_PRTDSI__SYNC_OUT (* (reg8 *) nNOR_WP__PRTDSI__SYNC_OUT)
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/* SIO registers */
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#if defined(nNOR_WP__SIO_CFG)
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#define nNOR_WP_SIO_HYST_EN (* (reg8 *) nNOR_WP__SIO_HYST_EN)
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#define nNOR_WP_SIO_REG_HIFREQ (* (reg8 *) nNOR_WP__SIO_REG_HIFREQ)
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#define nNOR_WP_SIO_CFG (* (reg8 *) nNOR_WP__SIO_CFG)
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#define nNOR_WP_SIO_DIFF (* (reg8 *) nNOR_WP__SIO_DIFF)
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#endif /* (nNOR_WP__SIO_CFG) */
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/* Interrupt Registers */
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#if defined(nNOR_WP__INTSTAT)
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#define nNOR_WP_INTSTAT (* (reg8 *) nNOR_WP__INTSTAT)
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#define nNOR_WP_SNAP (* (reg8 *) nNOR_WP__SNAP)
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#define nNOR_WP_0_INTTYPE_REG (* (reg8 *) nNOR_WP__0__INTTYPE)
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#endif /* (nNOR_WP__INTSTAT) */
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#endif /* CY_PSOC5A... */
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#endif /* CY_PINS_nNOR_WP_H */
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/* [] END OF FILE */
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