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Add second SPI master for 5.2 board

This commit is contained in:
Michael McMaster 2020-12-14 21:44:09 +10:00
parent 5567b3540f
commit c59a94a16b
40 changed files with 10054 additions and 2990 deletions
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65
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_CTL.c Normal file
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/*******************************************************************************
* File Name: NOR_CTL.c
* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "NOR_CTL.h"
/* Check for removal by optimization */
#if !defined(NOR_CTL_Sync_ctrl_reg__REMOVED)
/*******************************************************************************
* Function Name: NOR_CTL_Write
********************************************************************************
*
* Summary:
* Write a byte to the Control Register.
*
* Parameters:
* control: The value to be assigned to the Control Register.
*
* Return:
* None.
*
*******************************************************************************/
void NOR_CTL_Write(uint8 control)
{
NOR_CTL_Control = control;
}
/*******************************************************************************
* Function Name: NOR_CTL_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Control Register.
*
* Parameters:
* None.
*
* Return:
* Returns the current value in the Control Register.
*
*******************************************************************************/
uint8 NOR_CTL_Read(void)
{
return NOR_CTL_Control;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

67
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_CTL.h Normal file
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/*******************************************************************************
* File Name: NOR_CTL.h
* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CONTROL_REG_NOR_CTL_H) /* CY_CONTROL_REG_NOR_CTL_H */
#define CY_CONTROL_REG_NOR_CTL_H
#include "cyfitter.h"
#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
(CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
(CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
#include "cytypes.h"
#else
#include "syslib/cy_syslib.h"
#endif
/***************************************
* Data Struct Definitions
***************************************/
/* Sleep Mode API Support */
typedef struct
{
uint8 controlState;
} NOR_CTL_BACKUP_STRUCT;
/***************************************
* Function Prototypes
***************************************/
void NOR_CTL_Write(uint8 control) ;
uint8 NOR_CTL_Read(void) ;
void NOR_CTL_SaveConfig(void) ;
void NOR_CTL_RestoreConfig(void) ;
void NOR_CTL_Sleep(void) ;
void NOR_CTL_Wakeup(void) ;
/***************************************
* Registers
***************************************/
/* Control Register */
#define NOR_CTL_Control (* (reg8 *) NOR_CTL_Sync_ctrl_reg__CONTROL_REG )
#define NOR_CTL_Control_PTR ( (reg8 *) NOR_CTL_Sync_ctrl_reg__CONTROL_REG )
#endif /* End CY_CONTROL_REG_NOR_CTL_H */
/* [] END OF FILE */

109
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_CTL_PM.c Normal file
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/*******************************************************************************
* File Name: NOR_CTL_PM.c
* Version 1.80
*
* Description:
* This file contains the setup, control, and status commands to support
* the component operation in the low power mode.
*
* Note:
*
********************************************************************************
* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "NOR_CTL.h"
/* Check for removal by optimization */
#if !defined(NOR_CTL_Sync_ctrl_reg__REMOVED)
static NOR_CTL_BACKUP_STRUCT NOR_CTL_backup = {0u};
/*******************************************************************************
* Function Name: NOR_CTL_SaveConfig
********************************************************************************
*
* Summary:
* Saves the control register value.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void NOR_CTL_SaveConfig(void)
{
NOR_CTL_backup.controlState = NOR_CTL_Control;
}
/*******************************************************************************
* Function Name: NOR_CTL_RestoreConfig
********************************************************************************
*
* Summary:
* Restores the control register value.
*
* Parameters:
* None
*
* Return:
* None
*
*
*******************************************************************************/
void NOR_CTL_RestoreConfig(void)
{
NOR_CTL_Control = NOR_CTL_backup.controlState;
}
/*******************************************************************************
* Function Name: NOR_CTL_Sleep
********************************************************************************
*
* Summary:
* Prepares the component for entering the low power mode.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void NOR_CTL_Sleep(void)
{
NOR_CTL_SaveConfig();
}
/*******************************************************************************
* Function Name: NOR_CTL_Wakeup
********************************************************************************
*
* Summary:
* Restores the component after waking up from the low power mode.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void NOR_CTL_Wakeup(void)
{
NOR_CTL_RestoreConfig();
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

521
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_Clock.c Normal file
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/*******************************************************************************
* File Name: NOR_Clock.c
* Version 2.20
*
* Description:
* This file provides the source code to the API for the clock component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include "NOR_Clock.h"
/* Clock Distribution registers. */
#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)
#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)
#define BCFG2_MASK (0x80u)
#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)
#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)
#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)
/*******************************************************************************
* Function Name: NOR_Clock_Start
********************************************************************************
*
* Summary:
* Starts the clock. Note that on startup, clocks may be already running if the
* "Start on Reset" option is enabled in the DWR.
*
* Parameters:
* None
*
* Returns:
* None
*
*******************************************************************************/
void NOR_Clock_Start(void)
{
/* Set the bit to enable the clock. */
NOR_Clock_CLKEN |= NOR_Clock_CLKEN_MASK;
NOR_Clock_CLKSTBY |= NOR_Clock_CLKSTBY_MASK;
}
/*******************************************************************************
* Function Name: NOR_Clock_Stop
********************************************************************************
*
* Summary:
* Stops the clock and returns immediately. This API does not require the
* source clock to be running but may return before the hardware is actually
* disabled. If the settings of the clock are changed after calling this
* function, the clock may glitch when it is started. To avoid the clock
* glitch, use the StopBlock function.
*
* Parameters:
* None
*
* Returns:
* None
*
*******************************************************************************/
void NOR_Clock_Stop(void)
{
/* Clear the bit to disable the clock. */
NOR_Clock_CLKEN &= (uint8)(~NOR_Clock_CLKEN_MASK);
NOR_Clock_CLKSTBY &= (uint8)(~NOR_Clock_CLKSTBY_MASK);
}
#if(CY_PSOC3 || CY_PSOC5LP)
/*******************************************************************************
* Function Name: NOR_Clock_StopBlock
********************************************************************************
*
* Summary:
* Stops the clock and waits for the hardware to actually be disabled before
* returning. This ensures that the clock is never truncated (high part of the
* cycle will terminate before the clock is disabled and the API returns).
* Note that the source clock must be running or this API will never return as
* a stopped clock cannot be disabled.
*
* Parameters:
* None
*
* Returns:
* None
*
*******************************************************************************/
void NOR_Clock_StopBlock(void)
{
if ((NOR_Clock_CLKEN & NOR_Clock_CLKEN_MASK) != 0u)
{
#if HAS_CLKDIST_LD_DISABLE
uint16 oldDivider;
CLK_DIST_LD = 0u;
/* Clear all the mask bits except ours. */
#if defined(NOR_Clock__CFG3)
CLK_DIST_AMASK = NOR_Clock_CLKEN_MASK;
CLK_DIST_DMASK = 0x00u;
#else
CLK_DIST_DMASK = NOR_Clock_CLKEN_MASK;
CLK_DIST_AMASK = 0x00u;
#endif /* NOR_Clock__CFG3 */
/* Clear mask of bus clock. */
CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
oldDivider = CY_GET_REG16(NOR_Clock_DIV_PTR);
CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
/* Wait for clock to be disabled */
while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
#endif /* HAS_CLKDIST_LD_DISABLE */
/* Clear the bit to disable the clock. */
NOR_Clock_CLKEN &= (uint8)(~NOR_Clock_CLKEN_MASK);
NOR_Clock_CLKSTBY &= (uint8)(~NOR_Clock_CLKSTBY_MASK);
#if HAS_CLKDIST_LD_DISABLE
/* Clear the disable bit */
CLK_DIST_LD = 0x00u;
CY_SET_REG16(NOR_Clock_DIV_PTR, oldDivider);
#endif /* HAS_CLKDIST_LD_DISABLE */
}
}
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/*******************************************************************************
* Function Name: NOR_Clock_StandbyPower
********************************************************************************
*
* Summary:
* Sets whether the clock is active in standby mode.
*
* Parameters:
* state: 0 to disable clock during standby, nonzero to enable.
*
* Returns:
* None
*
*******************************************************************************/
void NOR_Clock_StandbyPower(uint8 state)
{
if(state == 0u)
{
NOR_Clock_CLKSTBY &= (uint8)(~NOR_Clock_CLKSTBY_MASK);
}
else
{
NOR_Clock_CLKSTBY |= NOR_Clock_CLKSTBY_MASK;
}
}
/*******************************************************************************
* Function Name: NOR_Clock_SetDividerRegister
********************************************************************************
*
* Summary:
* Modifies the clock divider and, thus, the frequency. When the clock divider
* register is set to zero or changed from zero, the clock will be temporarily
* disabled in order to change the SSS mode bit. If the clock is enabled when
* SetDividerRegister is called, then the source clock must be running.
*
* Parameters:
* clkDivider: Divider register value (0-65,535). This value is NOT the
* divider; the clock hardware divides by clkDivider plus one. For example,
* to divide the clock by 2, this parameter should be set to 1.
* restart: If nonzero, restarts the clock divider: the current clock cycle
* will be truncated and the new divide value will take effect immediately. If
* zero, the new divide value will take effect at the end of the current clock
* cycle.
*
* Returns:
* None
*
*******************************************************************************/
void NOR_Clock_SetDividerRegister(uint16 clkDivider, uint8 restart)
{
uint8 enabled;
uint8 currSrc = NOR_Clock_GetSourceRegister();
uint16 oldDivider = NOR_Clock_GetDividerRegister();
if (clkDivider != oldDivider)
{
enabled = NOR_Clock_CLKEN & NOR_Clock_CLKEN_MASK;
if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
{
/* Moving to/from SSS requires correct ordering to prevent halting the clock */
if (oldDivider == 0u)
{
/* Moving away from SSS, set the divider first so when SSS is cleared we */
/* don't halt the clock. Using the shadow load isn't required as the */
/* divider is ignored while SSS is set. */
CY_SET_REG16(NOR_Clock_DIV_PTR, clkDivider);
NOR_Clock_MOD_SRC &= (uint8)(~CYCLK_SSS);
}
else
{
/* Moving to SSS, set SSS which then ignores the divider and we can set */
/* it without bothering with the shadow load. */
NOR_Clock_MOD_SRC |= CYCLK_SSS;
CY_SET_REG16(NOR_Clock_DIV_PTR, clkDivider);
}
}
else
{
if (enabled != 0u)
{
CLK_DIST_LD = 0x00u;
/* Clear all the mask bits except ours. */
#if defined(NOR_Clock__CFG3)
CLK_DIST_AMASK = NOR_Clock_CLKEN_MASK;
CLK_DIST_DMASK = 0x00u;
#else
CLK_DIST_DMASK = NOR_Clock_CLKEN_MASK;
CLK_DIST_AMASK = 0x00u;
#endif /* NOR_Clock__CFG3 */
/* Clear mask of bus clock. */
CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
/* If clock is currently enabled, disable it if async or going from N-to-1*/
if (((NOR_Clock_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
{
#if HAS_CLKDIST_LD_DISABLE
CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
/* Wait for clock to be disabled */
while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
#endif /* HAS_CLKDIST_LD_DISABLE */
NOR_Clock_CLKEN &= (uint8)(~NOR_Clock_CLKEN_MASK);
#if HAS_CLKDIST_LD_DISABLE
/* Clear the disable bit */
CLK_DIST_LD = 0x00u;
#endif /* HAS_CLKDIST_LD_DISABLE */
}
}
/* Load divide value. */
if ((NOR_Clock_CLKEN & NOR_Clock_CLKEN_MASK) != 0u)
{
/* If the clock is still enabled, use the shadow registers */
CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
}
else
{
/* If the clock is disabled, set the divider directly */
CY_SET_REG16(NOR_Clock_DIV_PTR, clkDivider);
NOR_Clock_CLKEN |= enabled;
}
}
}
}
/*******************************************************************************
* Function Name: NOR_Clock_GetDividerRegister
********************************************************************************
*
* Summary:
* Gets the clock divider register value.
*
* Parameters:
* None
*
* Returns:
* Divide value of the clock minus 1. For example, if the clock is set to
* divide by 2, the return value will be 1.
*
*******************************************************************************/
uint16 NOR_Clock_GetDividerRegister(void)
{
return CY_GET_REG16(NOR_Clock_DIV_PTR);
}
/*******************************************************************************
* Function Name: NOR_Clock_SetModeRegister
********************************************************************************
*
* Summary:
* Sets flags that control the operating mode of the clock. This function only
* changes flags from 0 to 1; flags that are already 1 will remain unchanged.
* To clear flags, use the ClearModeRegister function. The clock must be
* disabled before changing the mode.
*
* Parameters:
* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
* clkMode should be a set of the following optional bits or'ed together.
* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
* occur when the divider count reaches half of the divide
* value.
* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
* is asserted for approximately half of its period. When
* disabled, the output clock is asserted for one period of the
* source clock.
* - CYCLK_SYNC Enable output synchronization to master clock. This should
* be enabled for all synchronous clocks.
* See the Technical Reference Manual for details about setting the mode of
* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
*
* Returns:
* None
*
*******************************************************************************/
void NOR_Clock_SetModeRegister(uint8 modeBitMask)
{
NOR_Clock_MOD_SRC |= modeBitMask & (uint8)NOR_Clock_MODE_MASK;
}
/*******************************************************************************
* Function Name: NOR_Clock_ClearModeRegister
********************************************************************************
*
* Summary:
* Clears flags that control the operating mode of the clock. This function
* only changes flags from 1 to 0; flags that are already 0 will remain
* unchanged. To set flags, use the SetModeRegister function. The clock must be
* disabled before changing the mode.
*
* Parameters:
* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
* clkMode should be a set of the following optional bits or'ed together.
* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
* occur when the divider count reaches half of the divide
* value.
* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
* is asserted for approximately half of its period. When
* disabled, the output clock is asserted for one period of the
* source clock.
* - CYCLK_SYNC Enable output synchronization to master clock. This should
* be enabled for all synchronous clocks.
* See the Technical Reference Manual for details about setting the mode of
* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
*
* Returns:
* None
*
*******************************************************************************/
void NOR_Clock_ClearModeRegister(uint8 modeBitMask)
{
NOR_Clock_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(NOR_Clock_MODE_MASK));
}
/*******************************************************************************
* Function Name: NOR_Clock_GetModeRegister
********************************************************************************
*
* Summary:
* Gets the clock mode register value.
*
* Parameters:
* None
*
* Returns:
* Bit mask representing the enabled mode bits. See the SetModeRegister and
* ClearModeRegister descriptions for details about the mode bits.
*
*******************************************************************************/
uint8 NOR_Clock_GetModeRegister(void)
{
return NOR_Clock_MOD_SRC & (uint8)(NOR_Clock_MODE_MASK);
}
/*******************************************************************************
* Function Name: NOR_Clock_SetSourceRegister
********************************************************************************
*
* Summary:
* Sets the input source of the clock. The clock must be disabled before
* changing the source. The old and new clock sources must be running.
*
* Parameters:
* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the
* following input sources:
* - CYCLK_SRC_SEL_SYNC_DIG
* - CYCLK_SRC_SEL_IMO
* - CYCLK_SRC_SEL_XTALM
* - CYCLK_SRC_SEL_ILO
* - CYCLK_SRC_SEL_PLL
* - CYCLK_SRC_SEL_XTALK
* - CYCLK_SRC_SEL_DSI_G
* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
* See the Technical Reference Manual for details on clock sources.
*
* Returns:
* None
*
*******************************************************************************/
void NOR_Clock_SetSourceRegister(uint8 clkSource)
{
uint16 currDiv = NOR_Clock_GetDividerRegister();
uint8 oldSrc = NOR_Clock_GetSourceRegister();
if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
(clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
{
/* Switching to Master and divider is 1, set SSS, which will output master, */
/* then set the source so we are consistent. */
NOR_Clock_MOD_SRC |= CYCLK_SSS;
NOR_Clock_MOD_SRC =
(NOR_Clock_MOD_SRC & (uint8)(~NOR_Clock_SRC_SEL_MSK)) | clkSource;
}
else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
(clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
{
/* Switching from Master to not and divider is 1, set source, so we don't */
/* lock when we clear SSS. */
NOR_Clock_MOD_SRC =
(NOR_Clock_MOD_SRC & (uint8)(~NOR_Clock_SRC_SEL_MSK)) | clkSource;
NOR_Clock_MOD_SRC &= (uint8)(~CYCLK_SSS);
}
else
{
NOR_Clock_MOD_SRC =
(NOR_Clock_MOD_SRC & (uint8)(~NOR_Clock_SRC_SEL_MSK)) | clkSource;
}
}
/*******************************************************************************
* Function Name: NOR_Clock_GetSourceRegister
********************************************************************************
*
* Summary:
* Gets the input source of the clock.
*
* Parameters:
* None
*
* Returns:
* The input source of the clock. See SetSourceRegister for details.
*
*******************************************************************************/
uint8 NOR_Clock_GetSourceRegister(void)
{
return NOR_Clock_MOD_SRC & NOR_Clock_SRC_SEL_MSK;
}
#if defined(NOR_Clock__CFG3)
/*******************************************************************************
* Function Name: NOR_Clock_SetPhaseRegister
********************************************************************************
*
* Summary:
* Sets the phase delay of the analog clock. This function is only available
* for analog clocks. The clock must be disabled before changing the phase
* delay to avoid glitches.
*
* Parameters:
* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
* clkPhase must be from 1 to 11 inclusive. Other values, including 0,
* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11
* produces a 10ns delay.
*
* Returns:
* None
*
*******************************************************************************/
void NOR_Clock_SetPhaseRegister(uint8 clkPhase)
{
NOR_Clock_PHASE = clkPhase & NOR_Clock_PHASE_MASK;
}
/*******************************************************************************
* Function Name: NOR_Clock_GetPhase
********************************************************************************
*
* Summary:
* Gets the phase delay of the analog clock. This function is only available
* for analog clocks.
*
* Parameters:
* None
*
* Returns:
* Phase of the analog clock. See SetPhaseRegister for details.
*
*******************************************************************************/
uint8 NOR_Clock_GetPhaseRegister(void)
{
return NOR_Clock_PHASE & NOR_Clock_PHASE_MASK;
}
#endif /* NOR_Clock__CFG3 */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: NOR_Clock.h
* Version 2.20
*
* Description:
* Provides the function and constant definitions for the clock component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CLOCK_NOR_Clock_H)
#define CY_CLOCK_NOR_Clock_H
#include <cytypes.h>
#include <cyfitter.h>
/***************************************
* Conditional Compilation Parameters
***************************************/
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
#error Component cy_clock_v2_20 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
/***************************************
* Function Prototypes
***************************************/
void NOR_Clock_Start(void) ;
void NOR_Clock_Stop(void) ;
#if(CY_PSOC3 || CY_PSOC5LP)
void NOR_Clock_StopBlock(void) ;
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
void NOR_Clock_StandbyPower(uint8 state) ;
void NOR_Clock_SetDividerRegister(uint16 clkDivider, uint8 restart)
;
uint16 NOR_Clock_GetDividerRegister(void) ;
void NOR_Clock_SetModeRegister(uint8 modeBitMask) ;
void NOR_Clock_ClearModeRegister(uint8 modeBitMask) ;
uint8 NOR_Clock_GetModeRegister(void) ;
void NOR_Clock_SetSourceRegister(uint8 clkSource) ;
uint8 NOR_Clock_GetSourceRegister(void) ;
#if defined(NOR_Clock__CFG3)
void NOR_Clock_SetPhaseRegister(uint8 clkPhase) ;
uint8 NOR_Clock_GetPhaseRegister(void) ;
#endif /* defined(NOR_Clock__CFG3) */
#define NOR_Clock_Enable() NOR_Clock_Start()
#define NOR_Clock_Disable() NOR_Clock_Stop()
#define NOR_Clock_SetDivider(clkDivider) NOR_Clock_SetDividerRegister(clkDivider, 1u)
#define NOR_Clock_SetDividerValue(clkDivider) NOR_Clock_SetDividerRegister((clkDivider) - 1u, 1u)
#define NOR_Clock_SetMode(clkMode) NOR_Clock_SetModeRegister(clkMode)
#define NOR_Clock_SetSource(clkSource) NOR_Clock_SetSourceRegister(clkSource)
#if defined(NOR_Clock__CFG3)
#define NOR_Clock_SetPhase(clkPhase) NOR_Clock_SetPhaseRegister(clkPhase)
#define NOR_Clock_SetPhaseValue(clkPhase) NOR_Clock_SetPhaseRegister((clkPhase) + 1u)
#endif /* defined(NOR_Clock__CFG3) */
/***************************************
* Registers
***************************************/
/* Register to enable or disable the clock */
#define NOR_Clock_CLKEN (* (reg8 *) NOR_Clock__PM_ACT_CFG)
#define NOR_Clock_CLKEN_PTR ((reg8 *) NOR_Clock__PM_ACT_CFG)
/* Register to enable or disable the clock */
#define NOR_Clock_CLKSTBY (* (reg8 *) NOR_Clock__PM_STBY_CFG)
#define NOR_Clock_CLKSTBY_PTR ((reg8 *) NOR_Clock__PM_STBY_CFG)
/* Clock LSB divider configuration register. */
#define NOR_Clock_DIV_LSB (* (reg8 *) NOR_Clock__CFG0)
#define NOR_Clock_DIV_LSB_PTR ((reg8 *) NOR_Clock__CFG0)
#define NOR_Clock_DIV_PTR ((reg16 *) NOR_Clock__CFG0)
/* Clock MSB divider configuration register. */
#define NOR_Clock_DIV_MSB (* (reg8 *) NOR_Clock__CFG1)
#define NOR_Clock_DIV_MSB_PTR ((reg8 *) NOR_Clock__CFG1)
/* Mode and source configuration register */
#define NOR_Clock_MOD_SRC (* (reg8 *) NOR_Clock__CFG2)
#define NOR_Clock_MOD_SRC_PTR ((reg8 *) NOR_Clock__CFG2)
#if defined(NOR_Clock__CFG3)
/* Analog clock phase configuration register */
#define NOR_Clock_PHASE (* (reg8 *) NOR_Clock__CFG3)
#define NOR_Clock_PHASE_PTR ((reg8 *) NOR_Clock__CFG3)
#endif /* defined(NOR_Clock__CFG3) */
/**************************************
* Register Constants
**************************************/
/* Power manager register masks */
#define NOR_Clock_CLKEN_MASK NOR_Clock__PM_ACT_MSK
#define NOR_Clock_CLKSTBY_MASK NOR_Clock__PM_STBY_MSK
/* CFG2 field masks */
#define NOR_Clock_SRC_SEL_MSK NOR_Clock__CFG2_SRC_SEL_MASK
#define NOR_Clock_MODE_MASK (~(NOR_Clock_SRC_SEL_MSK))
#if defined(NOR_Clock__CFG3)
/* CFG3 phase mask */
#define NOR_Clock_PHASE_MASK NOR_Clock__CFG3_PHASE_DLY_MASK
#endif /* defined(NOR_Clock__CFG3) */
#endif /* CY_CLOCK_NOR_Clock_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: NOR_SCK.c
* Version 2.20
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "NOR_SCK.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
NOR_SCK__PORT == 15 && ((NOR_SCK__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: NOR_SCK_Write
****************************************************************************//**
*
* \brief Writes the value to the physical port (data output register), masking
* and shifting the bits appropriately.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This function avoids changing
* other bits in the port by using the appropriate method (read-modify-write or
* bit banding).
*
* <b>Note</b> This function should not be used on a hardware digital output pin
* as it is driven by the hardware signal attached to it.
*
* \param value
* Value to write to the component instance.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic; the Interrupt
* Service Routines (ISR) can cause corruption of this function. An ISR that
* interrupts this function and performs writes to the Pins component data
* register can cause corrupted port data. To avoid this issue, you should
* either use the Per-Pin APIs (primary method) or disable interrupts around
* this function.
*
* \funcusage
* \snippet NOR_SCK_SUT.c usage_NOR_SCK_Write
*******************************************************************************/
void NOR_SCK_Write(uint8 value)
{
uint8 staticBits = (NOR_SCK_DR & (uint8)(~NOR_SCK_MASK));
NOR_SCK_DR = staticBits | ((uint8)(value << NOR_SCK_SHIFT) & NOR_SCK_MASK);
}
/*******************************************************************************
* Function Name: NOR_SCK_SetDriveMode
****************************************************************************//**
*
* \brief Sets the drive mode for each of the Pins component's pins.
*
* <b>Note</b> This affects all pins in the Pins component instance. Use the
* Per-Pin APIs if you wish to control individual pin's drive modes.
*
* \param mode
* Mode for the selected signals. Valid options are documented in
* \ref driveMode.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic, the ISR can
* cause corruption of this function. An ISR that interrupts this function
* and performs writes to the Pins component Drive Mode registers can cause
* corrupted port data. To avoid this issue, you should either use the Per-Pin
* APIs (primary method) or disable interrupts around this function.
*
* \funcusage
* \snippet NOR_SCK_SUT.c usage_NOR_SCK_SetDriveMode
*******************************************************************************/
void NOR_SCK_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(NOR_SCK_0, mode);
}
/*******************************************************************************
* Function Name: NOR_SCK_Read
****************************************************************************//**
*
* \brief Reads the associated physical port (pin status register) and masks
* the required bits according to the width and bit position of the component
* instance.
*
* The pin's status register returns the current logic level present on the
* physical pin.
*
* \return
* The current value for the pins in the component as a right justified number.
*
* \funcusage
* \snippet NOR_SCK_SUT.c usage_NOR_SCK_Read
*******************************************************************************/
uint8 NOR_SCK_Read(void)
{
return (NOR_SCK_PS & NOR_SCK_MASK) >> NOR_SCK_SHIFT;
}
/*******************************************************************************
* Function Name: NOR_SCK_ReadDataReg
****************************************************************************//**
*
* \brief Reads the associated physical port's data output register and masks
* the correct bits according to the width and bit position of the component
* instance.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This is not the same as the
* preferred NOR_SCK_Read() API because the
* NOR_SCK_ReadDataReg() reads the data register instead of the status
* register. For output pins this is a useful function to determine the value
* just written to the pin.
*
* \return
* The current value of the data register masked and shifted into a right
* justified number for the component instance.
*
* \funcusage
* \snippet NOR_SCK_SUT.c usage_NOR_SCK_ReadDataReg
*******************************************************************************/
uint8 NOR_SCK_ReadDataReg(void)
{
return (NOR_SCK_DR & NOR_SCK_MASK) >> NOR_SCK_SHIFT;
}
/* If interrupt is connected for this Pins component */
#if defined(NOR_SCK_INTSTAT)
/*******************************************************************************
* Function Name: NOR_SCK_SetInterruptMode
****************************************************************************//**
*
* \brief Configures the interrupt mode for each of the Pins component's
* pins. Alternatively you may set the interrupt mode for all the pins
* specified in the Pins component.
*
* <b>Note</b> The interrupt is port-wide and therefore any enabled pin
* interrupt may trigger it.
*
* \param position
* The pin position as listed in the Pins component. You may OR these to be
* able to configure the interrupt mode of multiple pins within a Pins
* component. Or you may use NOR_SCK_INTR_ALL to configure the
* interrupt mode of all the pins in the Pins component.
* - NOR_SCK_0_INTR (First pin in the list)
* - NOR_SCK_1_INTR (Second pin in the list)
* - ...
* - NOR_SCK_INTR_ALL (All pins in Pins component)
*
* \param mode
* Interrupt mode for the selected pins. Valid options are documented in
* \ref intrMode.
*
* \return
* None
*
* \sideeffect
* It is recommended that the interrupt be disabled before calling this
* function to avoid unintended interrupt requests. Note that the interrupt
* type is port wide, and therefore will trigger for any enabled pin on the
* port.
*
* \funcusage
* \snippet NOR_SCK_SUT.c usage_NOR_SCK_SetInterruptMode
*******************************************************************************/
void NOR_SCK_SetInterruptMode(uint16 position, uint16 mode)
{
if((position & NOR_SCK_0_INTR) != 0u)
{
NOR_SCK_0_INTTYPE_REG = (uint8)mode;
}
}
/*******************************************************************************
* Function Name: NOR_SCK_ClearInterrupt
****************************************************************************//**
*
* \brief Clears any active interrupts attached with the component and returns
* the value of the interrupt status register allowing determination of which
* pins generated an interrupt event.
*
* \return
* The right-shifted current value of the interrupt status register. Each pin
* has one bit set if it generated an interrupt event. For example, bit 0 is
* for pin 0 and bit 1 is for pin 1 of the Pins component.
*
* \sideeffect
* Clears all bits of the physical port's interrupt status register, not just
* those associated with the Pins component.
*
* \funcusage
* \snippet NOR_SCK_SUT.c usage_NOR_SCK_ClearInterrupt
*******************************************************************************/
uint8 NOR_SCK_ClearInterrupt(void)
{
return (NOR_SCK_INTSTAT & NOR_SCK_MASK) >> NOR_SCK_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: NOR_SCK.h
* Version 2.20
*
* Description:
* This file contains Pin function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_NOR_SCK_H) /* Pins NOR_SCK_H */
#define CY_PINS_NOR_SCK_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "NOR_SCK_aliases.h"
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
NOR_SCK__PORT == 15 && ((NOR_SCK__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_general
* @{
*/
void NOR_SCK_Write(uint8 value);
void NOR_SCK_SetDriveMode(uint8 mode);
uint8 NOR_SCK_ReadDataReg(void);
uint8 NOR_SCK_Read(void);
void NOR_SCK_SetInterruptMode(uint16 position, uint16 mode);
uint8 NOR_SCK_ClearInterrupt(void);
/** @} general */
/***************************************
* API Constants
***************************************/
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup driveMode Drive mode constants
* \brief Constants to be passed as "mode" parameter in the NOR_SCK_SetDriveMode() function.
* @{
*/
#define NOR_SCK_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define NOR_SCK_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define NOR_SCK_DM_RES_UP PIN_DM_RES_UP
#define NOR_SCK_DM_RES_DWN PIN_DM_RES_DWN
#define NOR_SCK_DM_OD_LO PIN_DM_OD_LO
#define NOR_SCK_DM_OD_HI PIN_DM_OD_HI
#define NOR_SCK_DM_STRONG PIN_DM_STRONG
#define NOR_SCK_DM_RES_UPDWN PIN_DM_RES_UPDWN
/** @} driveMode */
/** @} group_constants */
/* Digital Port Constants */
#define NOR_SCK_MASK NOR_SCK__MASK
#define NOR_SCK_SHIFT NOR_SCK__SHIFT
#define NOR_SCK_WIDTH 1u
/* Interrupt constants */
#if defined(NOR_SCK__INTSTAT)
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup intrMode Interrupt constants
* \brief Constants to be passed as "mode" parameter in NOR_SCK_SetInterruptMode() function.
* @{
*/
#define NOR_SCK_INTR_NONE (uint16)(0x0000u)
#define NOR_SCK_INTR_RISING (uint16)(0x0001u)
#define NOR_SCK_INTR_FALLING (uint16)(0x0002u)
#define NOR_SCK_INTR_BOTH (uint16)(0x0003u)
/** @} intrMode */
/** @} group_constants */
#define NOR_SCK_INTR_MASK (0x01u)
#endif /* (NOR_SCK__INTSTAT) */
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define NOR_SCK_PS (* (reg8 *) NOR_SCK__PS)
/* Data Register */
#define NOR_SCK_DR (* (reg8 *) NOR_SCK__DR)
/* Port Number */
#define NOR_SCK_PRT_NUM (* (reg8 *) NOR_SCK__PRT)
/* Connect to Analog Globals */
#define NOR_SCK_AG (* (reg8 *) NOR_SCK__AG)
/* Analog MUX bux enable */
#define NOR_SCK_AMUX (* (reg8 *) NOR_SCK__AMUX)
/* Bidirectional Enable */
#define NOR_SCK_BIE (* (reg8 *) NOR_SCK__BIE)
/* Bit-mask for Aliased Register Access */
#define NOR_SCK_BIT_MASK (* (reg8 *) NOR_SCK__BIT_MASK)
/* Bypass Enable */
#define NOR_SCK_BYP (* (reg8 *) NOR_SCK__BYP)
/* Port wide control signals */
#define NOR_SCK_CTL (* (reg8 *) NOR_SCK__CTL)
/* Drive Modes */
#define NOR_SCK_DM0 (* (reg8 *) NOR_SCK__DM0)
#define NOR_SCK_DM1 (* (reg8 *) NOR_SCK__DM1)
#define NOR_SCK_DM2 (* (reg8 *) NOR_SCK__DM2)
/* Input Buffer Disable Override */
#define NOR_SCK_INP_DIS (* (reg8 *) NOR_SCK__INP_DIS)
/* LCD Common or Segment Drive */
#define NOR_SCK_LCD_COM_SEG (* (reg8 *) NOR_SCK__LCD_COM_SEG)
/* Enable Segment LCD */
#define NOR_SCK_LCD_EN (* (reg8 *) NOR_SCK__LCD_EN)
/* Slew Rate Control */
#define NOR_SCK_SLW (* (reg8 *) NOR_SCK__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define NOR_SCK_PRTDSI__CAPS_SEL (* (reg8 *) NOR_SCK__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define NOR_SCK_PRTDSI__DBL_SYNC_IN (* (reg8 *) NOR_SCK__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define NOR_SCK_PRTDSI__OE_SEL0 (* (reg8 *) NOR_SCK__PRTDSI__OE_SEL0)
#define NOR_SCK_PRTDSI__OE_SEL1 (* (reg8 *) NOR_SCK__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define NOR_SCK_PRTDSI__OUT_SEL0 (* (reg8 *) NOR_SCK__PRTDSI__OUT_SEL0)
#define NOR_SCK_PRTDSI__OUT_SEL1 (* (reg8 *) NOR_SCK__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define NOR_SCK_PRTDSI__SYNC_OUT (* (reg8 *) NOR_SCK__PRTDSI__SYNC_OUT)
/* SIO registers */
#if defined(NOR_SCK__SIO_CFG)
#define NOR_SCK_SIO_HYST_EN (* (reg8 *) NOR_SCK__SIO_HYST_EN)
#define NOR_SCK_SIO_REG_HIFREQ (* (reg8 *) NOR_SCK__SIO_REG_HIFREQ)
#define NOR_SCK_SIO_CFG (* (reg8 *) NOR_SCK__SIO_CFG)
#define NOR_SCK_SIO_DIFF (* (reg8 *) NOR_SCK__SIO_DIFF)
#endif /* (NOR_SCK__SIO_CFG) */
/* Interrupt Registers */
#if defined(NOR_SCK__INTSTAT)
#define NOR_SCK_INTSTAT (* (reg8 *) NOR_SCK__INTSTAT)
#define NOR_SCK_SNAP (* (reg8 *) NOR_SCK__SNAP)
#define NOR_SCK_0_INTTYPE_REG (* (reg8 *) NOR_SCK__0__INTTYPE)
#endif /* (NOR_SCK__INTSTAT) */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_NOR_SCK_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: NOR_SCK.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_NOR_SCK_ALIASES_H) /* Pins NOR_SCK_ALIASES_H */
#define CY_PINS_NOR_SCK_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define NOR_SCK_0 (NOR_SCK__0__PC)
#define NOR_SCK_0_INTR ((uint16)((uint16)0x0001u << NOR_SCK__0__SHIFT))
#define NOR_SCK_INTR_ALL ((uint16)(NOR_SCK_0_INTR))
#endif /* End Pins NOR_SCK_ALIASES_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: NOR_SI.c
* Version 2.20
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "NOR_SI.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
NOR_SI__PORT == 15 && ((NOR_SI__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: NOR_SI_Write
****************************************************************************//**
*
* \brief Writes the value to the physical port (data output register), masking
* and shifting the bits appropriately.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This function avoids changing
* other bits in the port by using the appropriate method (read-modify-write or
* bit banding).
*
* <b>Note</b> This function should not be used on a hardware digital output pin
* as it is driven by the hardware signal attached to it.
*
* \param value
* Value to write to the component instance.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic; the Interrupt
* Service Routines (ISR) can cause corruption of this function. An ISR that
* interrupts this function and performs writes to the Pins component data
* register can cause corrupted port data. To avoid this issue, you should
* either use the Per-Pin APIs (primary method) or disable interrupts around
* this function.
*
* \funcusage
* \snippet NOR_SI_SUT.c usage_NOR_SI_Write
*******************************************************************************/
void NOR_SI_Write(uint8 value)
{
uint8 staticBits = (NOR_SI_DR & (uint8)(~NOR_SI_MASK));
NOR_SI_DR = staticBits | ((uint8)(value << NOR_SI_SHIFT) & NOR_SI_MASK);
}
/*******************************************************************************
* Function Name: NOR_SI_SetDriveMode
****************************************************************************//**
*
* \brief Sets the drive mode for each of the Pins component's pins.
*
* <b>Note</b> This affects all pins in the Pins component instance. Use the
* Per-Pin APIs if you wish to control individual pin's drive modes.
*
* \param mode
* Mode for the selected signals. Valid options are documented in
* \ref driveMode.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic, the ISR can
* cause corruption of this function. An ISR that interrupts this function
* and performs writes to the Pins component Drive Mode registers can cause
* corrupted port data. To avoid this issue, you should either use the Per-Pin
* APIs (primary method) or disable interrupts around this function.
*
* \funcusage
* \snippet NOR_SI_SUT.c usage_NOR_SI_SetDriveMode
*******************************************************************************/
void NOR_SI_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(NOR_SI_0, mode);
}
/*******************************************************************************
* Function Name: NOR_SI_Read
****************************************************************************//**
*
* \brief Reads the associated physical port (pin status register) and masks
* the required bits according to the width and bit position of the component
* instance.
*
* The pin's status register returns the current logic level present on the
* physical pin.
*
* \return
* The current value for the pins in the component as a right justified number.
*
* \funcusage
* \snippet NOR_SI_SUT.c usage_NOR_SI_Read
*******************************************************************************/
uint8 NOR_SI_Read(void)
{
return (NOR_SI_PS & NOR_SI_MASK) >> NOR_SI_SHIFT;
}
/*******************************************************************************
* Function Name: NOR_SI_ReadDataReg
****************************************************************************//**
*
* \brief Reads the associated physical port's data output register and masks
* the correct bits according to the width and bit position of the component
* instance.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This is not the same as the
* preferred NOR_SI_Read() API because the
* NOR_SI_ReadDataReg() reads the data register instead of the status
* register. For output pins this is a useful function to determine the value
* just written to the pin.
*
* \return
* The current value of the data register masked and shifted into a right
* justified number for the component instance.
*
* \funcusage
* \snippet NOR_SI_SUT.c usage_NOR_SI_ReadDataReg
*******************************************************************************/
uint8 NOR_SI_ReadDataReg(void)
{
return (NOR_SI_DR & NOR_SI_MASK) >> NOR_SI_SHIFT;
}
/* If interrupt is connected for this Pins component */
#if defined(NOR_SI_INTSTAT)
/*******************************************************************************
* Function Name: NOR_SI_SetInterruptMode
****************************************************************************//**
*
* \brief Configures the interrupt mode for each of the Pins component's
* pins. Alternatively you may set the interrupt mode for all the pins
* specified in the Pins component.
*
* <b>Note</b> The interrupt is port-wide and therefore any enabled pin
* interrupt may trigger it.
*
* \param position
* The pin position as listed in the Pins component. You may OR these to be
* able to configure the interrupt mode of multiple pins within a Pins
* component. Or you may use NOR_SI_INTR_ALL to configure the
* interrupt mode of all the pins in the Pins component.
* - NOR_SI_0_INTR (First pin in the list)
* - NOR_SI_1_INTR (Second pin in the list)
* - ...
* - NOR_SI_INTR_ALL (All pins in Pins component)
*
* \param mode
* Interrupt mode for the selected pins. Valid options are documented in
* \ref intrMode.
*
* \return
* None
*
* \sideeffect
* It is recommended that the interrupt be disabled before calling this
* function to avoid unintended interrupt requests. Note that the interrupt
* type is port wide, and therefore will trigger for any enabled pin on the
* port.
*
* \funcusage
* \snippet NOR_SI_SUT.c usage_NOR_SI_SetInterruptMode
*******************************************************************************/
void NOR_SI_SetInterruptMode(uint16 position, uint16 mode)
{
if((position & NOR_SI_0_INTR) != 0u)
{
NOR_SI_0_INTTYPE_REG = (uint8)mode;
}
}
/*******************************************************************************
* Function Name: NOR_SI_ClearInterrupt
****************************************************************************//**
*
* \brief Clears any active interrupts attached with the component and returns
* the value of the interrupt status register allowing determination of which
* pins generated an interrupt event.
*
* \return
* The right-shifted current value of the interrupt status register. Each pin
* has one bit set if it generated an interrupt event. For example, bit 0 is
* for pin 0 and bit 1 is for pin 1 of the Pins component.
*
* \sideeffect
* Clears all bits of the physical port's interrupt status register, not just
* those associated with the Pins component.
*
* \funcusage
* \snippet NOR_SI_SUT.c usage_NOR_SI_ClearInterrupt
*******************************************************************************/
uint8 NOR_SI_ClearInterrupt(void)
{
return (NOR_SI_INTSTAT & NOR_SI_MASK) >> NOR_SI_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: NOR_SI.h
* Version 2.20
*
* Description:
* This file contains Pin function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_NOR_SI_H) /* Pins NOR_SI_H */
#define CY_PINS_NOR_SI_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "NOR_SI_aliases.h"
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
NOR_SI__PORT == 15 && ((NOR_SI__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_general
* @{
*/
void NOR_SI_Write(uint8 value);
void NOR_SI_SetDriveMode(uint8 mode);
uint8 NOR_SI_ReadDataReg(void);
uint8 NOR_SI_Read(void);
void NOR_SI_SetInterruptMode(uint16 position, uint16 mode);
uint8 NOR_SI_ClearInterrupt(void);
/** @} general */
/***************************************
* API Constants
***************************************/
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup driveMode Drive mode constants
* \brief Constants to be passed as "mode" parameter in the NOR_SI_SetDriveMode() function.
* @{
*/
#define NOR_SI_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define NOR_SI_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define NOR_SI_DM_RES_UP PIN_DM_RES_UP
#define NOR_SI_DM_RES_DWN PIN_DM_RES_DWN
#define NOR_SI_DM_OD_LO PIN_DM_OD_LO
#define NOR_SI_DM_OD_HI PIN_DM_OD_HI
#define NOR_SI_DM_STRONG PIN_DM_STRONG
#define NOR_SI_DM_RES_UPDWN PIN_DM_RES_UPDWN
/** @} driveMode */
/** @} group_constants */
/* Digital Port Constants */
#define NOR_SI_MASK NOR_SI__MASK
#define NOR_SI_SHIFT NOR_SI__SHIFT
#define NOR_SI_WIDTH 1u
/* Interrupt constants */
#if defined(NOR_SI__INTSTAT)
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup intrMode Interrupt constants
* \brief Constants to be passed as "mode" parameter in NOR_SI_SetInterruptMode() function.
* @{
*/
#define NOR_SI_INTR_NONE (uint16)(0x0000u)
#define NOR_SI_INTR_RISING (uint16)(0x0001u)
#define NOR_SI_INTR_FALLING (uint16)(0x0002u)
#define NOR_SI_INTR_BOTH (uint16)(0x0003u)
/** @} intrMode */
/** @} group_constants */
#define NOR_SI_INTR_MASK (0x01u)
#endif /* (NOR_SI__INTSTAT) */
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define NOR_SI_PS (* (reg8 *) NOR_SI__PS)
/* Data Register */
#define NOR_SI_DR (* (reg8 *) NOR_SI__DR)
/* Port Number */
#define NOR_SI_PRT_NUM (* (reg8 *) NOR_SI__PRT)
/* Connect to Analog Globals */
#define NOR_SI_AG (* (reg8 *) NOR_SI__AG)
/* Analog MUX bux enable */
#define NOR_SI_AMUX (* (reg8 *) NOR_SI__AMUX)
/* Bidirectional Enable */
#define NOR_SI_BIE (* (reg8 *) NOR_SI__BIE)
/* Bit-mask for Aliased Register Access */
#define NOR_SI_BIT_MASK (* (reg8 *) NOR_SI__BIT_MASK)
/* Bypass Enable */
#define NOR_SI_BYP (* (reg8 *) NOR_SI__BYP)
/* Port wide control signals */
#define NOR_SI_CTL (* (reg8 *) NOR_SI__CTL)
/* Drive Modes */
#define NOR_SI_DM0 (* (reg8 *) NOR_SI__DM0)
#define NOR_SI_DM1 (* (reg8 *) NOR_SI__DM1)
#define NOR_SI_DM2 (* (reg8 *) NOR_SI__DM2)
/* Input Buffer Disable Override */
#define NOR_SI_INP_DIS (* (reg8 *) NOR_SI__INP_DIS)
/* LCD Common or Segment Drive */
#define NOR_SI_LCD_COM_SEG (* (reg8 *) NOR_SI__LCD_COM_SEG)
/* Enable Segment LCD */
#define NOR_SI_LCD_EN (* (reg8 *) NOR_SI__LCD_EN)
/* Slew Rate Control */
#define NOR_SI_SLW (* (reg8 *) NOR_SI__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define NOR_SI_PRTDSI__CAPS_SEL (* (reg8 *) NOR_SI__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define NOR_SI_PRTDSI__DBL_SYNC_IN (* (reg8 *) NOR_SI__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define NOR_SI_PRTDSI__OE_SEL0 (* (reg8 *) NOR_SI__PRTDSI__OE_SEL0)
#define NOR_SI_PRTDSI__OE_SEL1 (* (reg8 *) NOR_SI__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define NOR_SI_PRTDSI__OUT_SEL0 (* (reg8 *) NOR_SI__PRTDSI__OUT_SEL0)
#define NOR_SI_PRTDSI__OUT_SEL1 (* (reg8 *) NOR_SI__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define NOR_SI_PRTDSI__SYNC_OUT (* (reg8 *) NOR_SI__PRTDSI__SYNC_OUT)
/* SIO registers */
#if defined(NOR_SI__SIO_CFG)
#define NOR_SI_SIO_HYST_EN (* (reg8 *) NOR_SI__SIO_HYST_EN)
#define NOR_SI_SIO_REG_HIFREQ (* (reg8 *) NOR_SI__SIO_REG_HIFREQ)
#define NOR_SI_SIO_CFG (* (reg8 *) NOR_SI__SIO_CFG)
#define NOR_SI_SIO_DIFF (* (reg8 *) NOR_SI__SIO_DIFF)
#endif /* (NOR_SI__SIO_CFG) */
/* Interrupt Registers */
#if defined(NOR_SI__INTSTAT)
#define NOR_SI_INTSTAT (* (reg8 *) NOR_SI__INTSTAT)
#define NOR_SI_SNAP (* (reg8 *) NOR_SI__SNAP)
#define NOR_SI_0_INTTYPE_REG (* (reg8 *) NOR_SI__0__INTTYPE)
#endif /* (NOR_SI__INTSTAT) */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_NOR_SI_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: NOR_SI.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_NOR_SI_ALIASES_H) /* Pins NOR_SI_ALIASES_H */
#define CY_PINS_NOR_SI_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define NOR_SI_0 (NOR_SI__0__PC)
#define NOR_SI_0_INTR ((uint16)((uint16)0x0001u << NOR_SI__0__SHIFT))
#define NOR_SI_INTR_ALL ((uint16)(NOR_SI_0_INTR))
#endif /* End Pins NOR_SI_ALIASES_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: NOR_SO.c
* Version 2.20
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "NOR_SO.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
NOR_SO__PORT == 15 && ((NOR_SO__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: NOR_SO_Write
****************************************************************************//**
*
* \brief Writes the value to the physical port (data output register), masking
* and shifting the bits appropriately.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This function avoids changing
* other bits in the port by using the appropriate method (read-modify-write or
* bit banding).
*
* <b>Note</b> This function should not be used on a hardware digital output pin
* as it is driven by the hardware signal attached to it.
*
* \param value
* Value to write to the component instance.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic; the Interrupt
* Service Routines (ISR) can cause corruption of this function. An ISR that
* interrupts this function and performs writes to the Pins component data
* register can cause corrupted port data. To avoid this issue, you should
* either use the Per-Pin APIs (primary method) or disable interrupts around
* this function.
*
* \funcusage
* \snippet NOR_SO_SUT.c usage_NOR_SO_Write
*******************************************************************************/
void NOR_SO_Write(uint8 value)
{
uint8 staticBits = (NOR_SO_DR & (uint8)(~NOR_SO_MASK));
NOR_SO_DR = staticBits | ((uint8)(value << NOR_SO_SHIFT) & NOR_SO_MASK);
}
/*******************************************************************************
* Function Name: NOR_SO_SetDriveMode
****************************************************************************//**
*
* \brief Sets the drive mode for each of the Pins component's pins.
*
* <b>Note</b> This affects all pins in the Pins component instance. Use the
* Per-Pin APIs if you wish to control individual pin's drive modes.
*
* \param mode
* Mode for the selected signals. Valid options are documented in
* \ref driveMode.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic, the ISR can
* cause corruption of this function. An ISR that interrupts this function
* and performs writes to the Pins component Drive Mode registers can cause
* corrupted port data. To avoid this issue, you should either use the Per-Pin
* APIs (primary method) or disable interrupts around this function.
*
* \funcusage
* \snippet NOR_SO_SUT.c usage_NOR_SO_SetDriveMode
*******************************************************************************/
void NOR_SO_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(NOR_SO_0, mode);
}
/*******************************************************************************
* Function Name: NOR_SO_Read
****************************************************************************//**
*
* \brief Reads the associated physical port (pin status register) and masks
* the required bits according to the width and bit position of the component
* instance.
*
* The pin's status register returns the current logic level present on the
* physical pin.
*
* \return
* The current value for the pins in the component as a right justified number.
*
* \funcusage
* \snippet NOR_SO_SUT.c usage_NOR_SO_Read
*******************************************************************************/
uint8 NOR_SO_Read(void)
{
return (NOR_SO_PS & NOR_SO_MASK) >> NOR_SO_SHIFT;
}
/*******************************************************************************
* Function Name: NOR_SO_ReadDataReg
****************************************************************************//**
*
* \brief Reads the associated physical port's data output register and masks
* the correct bits according to the width and bit position of the component
* instance.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This is not the same as the
* preferred NOR_SO_Read() API because the
* NOR_SO_ReadDataReg() reads the data register instead of the status
* register. For output pins this is a useful function to determine the value
* just written to the pin.
*
* \return
* The current value of the data register masked and shifted into a right
* justified number for the component instance.
*
* \funcusage
* \snippet NOR_SO_SUT.c usage_NOR_SO_ReadDataReg
*******************************************************************************/
uint8 NOR_SO_ReadDataReg(void)
{
return (NOR_SO_DR & NOR_SO_MASK) >> NOR_SO_SHIFT;
}
/* If interrupt is connected for this Pins component */
#if defined(NOR_SO_INTSTAT)
/*******************************************************************************
* Function Name: NOR_SO_SetInterruptMode
****************************************************************************//**
*
* \brief Configures the interrupt mode for each of the Pins component's
* pins. Alternatively you may set the interrupt mode for all the pins
* specified in the Pins component.
*
* <b>Note</b> The interrupt is port-wide and therefore any enabled pin
* interrupt may trigger it.
*
* \param position
* The pin position as listed in the Pins component. You may OR these to be
* able to configure the interrupt mode of multiple pins within a Pins
* component. Or you may use NOR_SO_INTR_ALL to configure the
* interrupt mode of all the pins in the Pins component.
* - NOR_SO_0_INTR (First pin in the list)
* - NOR_SO_1_INTR (Second pin in the list)
* - ...
* - NOR_SO_INTR_ALL (All pins in Pins component)
*
* \param mode
* Interrupt mode for the selected pins. Valid options are documented in
* \ref intrMode.
*
* \return
* None
*
* \sideeffect
* It is recommended that the interrupt be disabled before calling this
* function to avoid unintended interrupt requests. Note that the interrupt
* type is port wide, and therefore will trigger for any enabled pin on the
* port.
*
* \funcusage
* \snippet NOR_SO_SUT.c usage_NOR_SO_SetInterruptMode
*******************************************************************************/
void NOR_SO_SetInterruptMode(uint16 position, uint16 mode)
{
if((position & NOR_SO_0_INTR) != 0u)
{
NOR_SO_0_INTTYPE_REG = (uint8)mode;
}
}
/*******************************************************************************
* Function Name: NOR_SO_ClearInterrupt
****************************************************************************//**
*
* \brief Clears any active interrupts attached with the component and returns
* the value of the interrupt status register allowing determination of which
* pins generated an interrupt event.
*
* \return
* The right-shifted current value of the interrupt status register. Each pin
* has one bit set if it generated an interrupt event. For example, bit 0 is
* for pin 0 and bit 1 is for pin 1 of the Pins component.
*
* \sideeffect
* Clears all bits of the physical port's interrupt status register, not just
* those associated with the Pins component.
*
* \funcusage
* \snippet NOR_SO_SUT.c usage_NOR_SO_ClearInterrupt
*******************************************************************************/
uint8 NOR_SO_ClearInterrupt(void)
{
return (NOR_SO_INTSTAT & NOR_SO_MASK) >> NOR_SO_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: NOR_SO.h
* Version 2.20
*
* Description:
* This file contains Pin function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_NOR_SO_H) /* Pins NOR_SO_H */
#define CY_PINS_NOR_SO_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "NOR_SO_aliases.h"
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
NOR_SO__PORT == 15 && ((NOR_SO__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_general
* @{
*/
void NOR_SO_Write(uint8 value);
void NOR_SO_SetDriveMode(uint8 mode);
uint8 NOR_SO_ReadDataReg(void);
uint8 NOR_SO_Read(void);
void NOR_SO_SetInterruptMode(uint16 position, uint16 mode);
uint8 NOR_SO_ClearInterrupt(void);
/** @} general */
/***************************************
* API Constants
***************************************/
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup driveMode Drive mode constants
* \brief Constants to be passed as "mode" parameter in the NOR_SO_SetDriveMode() function.
* @{
*/
#define NOR_SO_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define NOR_SO_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define NOR_SO_DM_RES_UP PIN_DM_RES_UP
#define NOR_SO_DM_RES_DWN PIN_DM_RES_DWN
#define NOR_SO_DM_OD_LO PIN_DM_OD_LO
#define NOR_SO_DM_OD_HI PIN_DM_OD_HI
#define NOR_SO_DM_STRONG PIN_DM_STRONG
#define NOR_SO_DM_RES_UPDWN PIN_DM_RES_UPDWN
/** @} driveMode */
/** @} group_constants */
/* Digital Port Constants */
#define NOR_SO_MASK NOR_SO__MASK
#define NOR_SO_SHIFT NOR_SO__SHIFT
#define NOR_SO_WIDTH 1u
/* Interrupt constants */
#if defined(NOR_SO__INTSTAT)
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup intrMode Interrupt constants
* \brief Constants to be passed as "mode" parameter in NOR_SO_SetInterruptMode() function.
* @{
*/
#define NOR_SO_INTR_NONE (uint16)(0x0000u)
#define NOR_SO_INTR_RISING (uint16)(0x0001u)
#define NOR_SO_INTR_FALLING (uint16)(0x0002u)
#define NOR_SO_INTR_BOTH (uint16)(0x0003u)
/** @} intrMode */
/** @} group_constants */
#define NOR_SO_INTR_MASK (0x01u)
#endif /* (NOR_SO__INTSTAT) */
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define NOR_SO_PS (* (reg8 *) NOR_SO__PS)
/* Data Register */
#define NOR_SO_DR (* (reg8 *) NOR_SO__DR)
/* Port Number */
#define NOR_SO_PRT_NUM (* (reg8 *) NOR_SO__PRT)
/* Connect to Analog Globals */
#define NOR_SO_AG (* (reg8 *) NOR_SO__AG)
/* Analog MUX bux enable */
#define NOR_SO_AMUX (* (reg8 *) NOR_SO__AMUX)
/* Bidirectional Enable */
#define NOR_SO_BIE (* (reg8 *) NOR_SO__BIE)
/* Bit-mask for Aliased Register Access */
#define NOR_SO_BIT_MASK (* (reg8 *) NOR_SO__BIT_MASK)
/* Bypass Enable */
#define NOR_SO_BYP (* (reg8 *) NOR_SO__BYP)
/* Port wide control signals */
#define NOR_SO_CTL (* (reg8 *) NOR_SO__CTL)
/* Drive Modes */
#define NOR_SO_DM0 (* (reg8 *) NOR_SO__DM0)
#define NOR_SO_DM1 (* (reg8 *) NOR_SO__DM1)
#define NOR_SO_DM2 (* (reg8 *) NOR_SO__DM2)
/* Input Buffer Disable Override */
#define NOR_SO_INP_DIS (* (reg8 *) NOR_SO__INP_DIS)
/* LCD Common or Segment Drive */
#define NOR_SO_LCD_COM_SEG (* (reg8 *) NOR_SO__LCD_COM_SEG)
/* Enable Segment LCD */
#define NOR_SO_LCD_EN (* (reg8 *) NOR_SO__LCD_EN)
/* Slew Rate Control */
#define NOR_SO_SLW (* (reg8 *) NOR_SO__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define NOR_SO_PRTDSI__CAPS_SEL (* (reg8 *) NOR_SO__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define NOR_SO_PRTDSI__DBL_SYNC_IN (* (reg8 *) NOR_SO__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define NOR_SO_PRTDSI__OE_SEL0 (* (reg8 *) NOR_SO__PRTDSI__OE_SEL0)
#define NOR_SO_PRTDSI__OE_SEL1 (* (reg8 *) NOR_SO__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define NOR_SO_PRTDSI__OUT_SEL0 (* (reg8 *) NOR_SO__PRTDSI__OUT_SEL0)
#define NOR_SO_PRTDSI__OUT_SEL1 (* (reg8 *) NOR_SO__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define NOR_SO_PRTDSI__SYNC_OUT (* (reg8 *) NOR_SO__PRTDSI__SYNC_OUT)
/* SIO registers */
#if defined(NOR_SO__SIO_CFG)
#define NOR_SO_SIO_HYST_EN (* (reg8 *) NOR_SO__SIO_HYST_EN)
#define NOR_SO_SIO_REG_HIFREQ (* (reg8 *) NOR_SO__SIO_REG_HIFREQ)
#define NOR_SO_SIO_CFG (* (reg8 *) NOR_SO__SIO_CFG)
#define NOR_SO_SIO_DIFF (* (reg8 *) NOR_SO__SIO_DIFF)
#endif /* (NOR_SO__SIO_CFG) */
/* Interrupt Registers */
#if defined(NOR_SO__INTSTAT)
#define NOR_SO_INTSTAT (* (reg8 *) NOR_SO__INTSTAT)
#define NOR_SO_SNAP (* (reg8 *) NOR_SO__SNAP)
#define NOR_SO_0_INTTYPE_REG (* (reg8 *) NOR_SO__0__INTTYPE)
#endif /* (NOR_SO__INTSTAT) */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_NOR_SO_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: NOR_SO.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_NOR_SO_ALIASES_H) /* Pins NOR_SO_ALIASES_H */
#define CY_PINS_NOR_SO_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define NOR_SO_0 (NOR_SO__0__PC)
#define NOR_SO_0_INTR ((uint16)((uint16)0x0001u << NOR_SO__0__SHIFT))
#define NOR_SO_INTR_ALL ((uint16)(NOR_SO_0_INTR))
#endif /* End Pins NOR_SO_ALIASES_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: NOR_SPI.h
* Version 2.50
*
* Description:
* Contains the function prototypes, constants and register definition
* of the SPI Master Component.
*
* Note:
* None
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_SPIM_NOR_SPI_H)
#define CY_SPIM_NOR_SPI_H
#include "cyfitter.h"
#include "cytypes.h"
#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */
/***************************************
* Conditional Compilation Parameters
***************************************/
#define NOR_SPI_INTERNAL_CLOCK (0u)
#if(0u != NOR_SPI_INTERNAL_CLOCK)
#include "NOR_SPI_IntClock.h"
#endif /* (0u != NOR_SPI_INTERNAL_CLOCK) */
#define NOR_SPI_MODE (1u)
#define NOR_SPI_DATA_WIDTH (8u)
#define NOR_SPI_MODE_USE_ZERO (1u)
#define NOR_SPI_BIDIRECTIONAL_MODE (0u)
/* Internal interrupt handling */
#define NOR_SPI_TX_BUFFER_SIZE (4u)
#define NOR_SPI_RX_BUFFER_SIZE (4u)
#define NOR_SPI_INTERNAL_TX_INT_ENABLED (0u)
#define NOR_SPI_INTERNAL_RX_INT_ENABLED (0u)
#define NOR_SPI_SINGLE_REG_SIZE (8u)
#define NOR_SPI_USE_SECOND_DATAPATH (NOR_SPI_DATA_WIDTH > NOR_SPI_SINGLE_REG_SIZE)
#define NOR_SPI_FIFO_SIZE (4u)
#define NOR_SPI_TX_SOFTWARE_BUF_ENABLED ((0u != NOR_SPI_INTERNAL_TX_INT_ENABLED) && \
(NOR_SPI_TX_BUFFER_SIZE > NOR_SPI_FIFO_SIZE))
#define NOR_SPI_RX_SOFTWARE_BUF_ENABLED ((0u != NOR_SPI_INTERNAL_RX_INT_ENABLED) && \
(NOR_SPI_RX_BUFFER_SIZE > NOR_SPI_FIFO_SIZE))
/***************************************
* Data Struct Definition
***************************************/
/* Sleep Mode API Support */
typedef struct
{
uint8 enableState;
uint8 cntrPeriod;
} NOR_SPI_BACKUP_STRUCT;
/***************************************
* Function Prototypes
***************************************/
void NOR_SPI_Init(void) ;
void NOR_SPI_Enable(void) ;
void NOR_SPI_Start(void) ;
void NOR_SPI_Stop(void) ;
void NOR_SPI_EnableTxInt(void) ;
void NOR_SPI_EnableRxInt(void) ;
void NOR_SPI_DisableTxInt(void) ;
void NOR_SPI_DisableRxInt(void) ;
void NOR_SPI_Sleep(void) ;
void NOR_SPI_Wakeup(void) ;
void NOR_SPI_SaveConfig(void) ;
void NOR_SPI_RestoreConfig(void) ;
void NOR_SPI_SetTxInterruptMode(uint8 intSrc) ;
void NOR_SPI_SetRxInterruptMode(uint8 intSrc) ;
uint8 NOR_SPI_ReadTxStatus(void) ;
uint8 NOR_SPI_ReadRxStatus(void) ;
void NOR_SPI_WriteTxData(uint8 txData) \
;
uint8 NOR_SPI_ReadRxData(void) \
;
uint8 NOR_SPI_GetRxBufferSize(void) ;
uint8 NOR_SPI_GetTxBufferSize(void) ;
void NOR_SPI_ClearRxBuffer(void) ;
void NOR_SPI_ClearTxBuffer(void) ;
void NOR_SPI_ClearFIFO(void) ;
void NOR_SPI_PutArray(const uint8 buffer[], uint8 byteCount) \
;
#if(0u != NOR_SPI_BIDIRECTIONAL_MODE)
void NOR_SPI_TxEnable(void) ;
void NOR_SPI_TxDisable(void) ;
#endif /* (0u != NOR_SPI_BIDIRECTIONAL_MODE) */
CY_ISR_PROTO(NOR_SPI_TX_ISR);
CY_ISR_PROTO(NOR_SPI_RX_ISR);
/***************************************
* Variable with external linkage
***************************************/
extern uint8 NOR_SPI_initVar;
/***************************************
* API Constants
***************************************/
#define NOR_SPI_TX_ISR_NUMBER ((uint8) (NOR_SPI_TxInternalInterrupt__INTC_NUMBER))
#define NOR_SPI_RX_ISR_NUMBER ((uint8) (NOR_SPI_RxInternalInterrupt__INTC_NUMBER))
#define NOR_SPI_TX_ISR_PRIORITY ((uint8) (NOR_SPI_TxInternalInterrupt__INTC_PRIOR_NUM))
#define NOR_SPI_RX_ISR_PRIORITY ((uint8) (NOR_SPI_RxInternalInterrupt__INTC_PRIOR_NUM))
/***************************************
* Initial Parameter Constants
***************************************/
#define NOR_SPI_INT_ON_SPI_DONE ((uint8) (0u << NOR_SPI_STS_SPI_DONE_SHIFT))
#define NOR_SPI_INT_ON_TX_EMPTY ((uint8) (0u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT))
#define NOR_SPI_INT_ON_TX_NOT_FULL ((uint8) (0u << \
NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT))
#define NOR_SPI_INT_ON_BYTE_COMP ((uint8) (0u << NOR_SPI_STS_BYTE_COMPLETE_SHIFT))
#define NOR_SPI_INT_ON_SPI_IDLE ((uint8) (0u << NOR_SPI_STS_SPI_IDLE_SHIFT))
/* Disable TX_NOT_FULL if software buffer is used */
#define NOR_SPI_INT_ON_TX_NOT_FULL_DEF ((NOR_SPI_TX_SOFTWARE_BUF_ENABLED) ? \
(0u) : (NOR_SPI_INT_ON_TX_NOT_FULL))
/* TX interrupt mask */
#define NOR_SPI_TX_INIT_INTERRUPTS_MASK (NOR_SPI_INT_ON_SPI_DONE | \
NOR_SPI_INT_ON_TX_EMPTY | \
NOR_SPI_INT_ON_TX_NOT_FULL_DEF | \
NOR_SPI_INT_ON_BYTE_COMP | \
NOR_SPI_INT_ON_SPI_IDLE)
#define NOR_SPI_INT_ON_RX_FULL ((uint8) (0u << \
NOR_SPI_STS_RX_FIFO_FULL_SHIFT))
#define NOR_SPI_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \
NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT))
#define NOR_SPI_INT_ON_RX_OVER ((uint8) (0u << \
NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT))
/* RX interrupt mask */
#define NOR_SPI_RX_INIT_INTERRUPTS_MASK (NOR_SPI_INT_ON_RX_FULL | \
NOR_SPI_INT_ON_RX_NOT_EMPTY | \
NOR_SPI_INT_ON_RX_OVER)
/* Nubmer of bits to receive/transmit */
#define NOR_SPI_BITCTR_INIT (((uint8) (NOR_SPI_DATA_WIDTH << 1u)) - 1u)
/***************************************
* Registers
***************************************/
#if(CY_PSOC3 || CY_PSOC5)
#define NOR_SPI_TXDATA_REG (* (reg8 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG)
#define NOR_SPI_TXDATA_PTR ( (reg8 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG)
#define NOR_SPI_RXDATA_REG (* (reg8 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG)
#define NOR_SPI_RXDATA_PTR ( (reg8 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG)
#else /* PSOC4 */
#if(NOR_SPI_USE_SECOND_DATAPATH)
#define NOR_SPI_TXDATA_REG (* (reg16 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
#define NOR_SPI_TXDATA_PTR ( (reg16 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
#define NOR_SPI_RXDATA_REG (* (reg16 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
#define NOR_SPI_RXDATA_PTR ( (reg16 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
#else
#define NOR_SPI_TXDATA_REG (* (reg8 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG)
#define NOR_SPI_TXDATA_PTR ( (reg8 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG)
#define NOR_SPI_RXDATA_REG (* (reg8 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG)
#define NOR_SPI_RXDATA_PTR ( (reg8 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG)
#endif /* (NOR_SPI_USE_SECOND_DATAPATH) */
#endif /* (CY_PSOC3 || CY_PSOC5) */
#define NOR_SPI_AUX_CONTROL_DP0_REG (* (reg8 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
#define NOR_SPI_AUX_CONTROL_DP0_PTR ( (reg8 *) \
NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
#if(NOR_SPI_USE_SECOND_DATAPATH)
#define NOR_SPI_AUX_CONTROL_DP1_REG (* (reg8 *) \
NOR_SPI_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
#define NOR_SPI_AUX_CONTROL_DP1_PTR ( (reg8 *) \
NOR_SPI_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
#endif /* (NOR_SPI_USE_SECOND_DATAPATH) */
#define NOR_SPI_COUNTER_PERIOD_REG (* (reg8 *) NOR_SPI_BSPIM_BitCounter__PERIOD_REG)
#define NOR_SPI_COUNTER_PERIOD_PTR ( (reg8 *) NOR_SPI_BSPIM_BitCounter__PERIOD_REG)
#define NOR_SPI_COUNTER_CONTROL_REG (* (reg8 *) NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
#define NOR_SPI_COUNTER_CONTROL_PTR ( (reg8 *) NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
#define NOR_SPI_TX_STATUS_REG (* (reg8 *) NOR_SPI_BSPIM_TxStsReg__STATUS_REG)
#define NOR_SPI_TX_STATUS_PTR ( (reg8 *) NOR_SPI_BSPIM_TxStsReg__STATUS_REG)
#define NOR_SPI_RX_STATUS_REG (* (reg8 *) NOR_SPI_BSPIM_RxStsReg__STATUS_REG)
#define NOR_SPI_RX_STATUS_PTR ( (reg8 *) NOR_SPI_BSPIM_RxStsReg__STATUS_REG)
#define NOR_SPI_CONTROL_REG (* (reg8 *) \
NOR_SPI_BSPIM_BidirMode_CtrlReg__CONTROL_REG)
#define NOR_SPI_CONTROL_PTR ( (reg8 *) \
NOR_SPI_BSPIM_BidirMode_CtrlReg__CONTROL_REG)
#define NOR_SPI_TX_STATUS_MASK_REG (* (reg8 *) NOR_SPI_BSPIM_TxStsReg__MASK_REG)
#define NOR_SPI_TX_STATUS_MASK_PTR ( (reg8 *) NOR_SPI_BSPIM_TxStsReg__MASK_REG)
#define NOR_SPI_RX_STATUS_MASK_REG (* (reg8 *) NOR_SPI_BSPIM_RxStsReg__MASK_REG)
#define NOR_SPI_RX_STATUS_MASK_PTR ( (reg8 *) NOR_SPI_BSPIM_RxStsReg__MASK_REG)
#define NOR_SPI_TX_STATUS_ACTL_REG (* (reg8 *) NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
#define NOR_SPI_TX_STATUS_ACTL_PTR ( (reg8 *) NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
#define NOR_SPI_RX_STATUS_ACTL_REG (* (reg8 *) NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
#define NOR_SPI_RX_STATUS_ACTL_PTR ( (reg8 *) NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
#if(NOR_SPI_USE_SECOND_DATAPATH)
#define NOR_SPI_AUX_CONTROLDP1 (NOR_SPI_AUX_CONTROL_DP1_REG)
#endif /* (NOR_SPI_USE_SECOND_DATAPATH) */
/***************************************
* Register Constants
***************************************/
/* Status Register Definitions */
#define NOR_SPI_STS_SPI_DONE_SHIFT (0x00u)
#define NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT (0x01u)
#define NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT (0x02u)
#define NOR_SPI_STS_BYTE_COMPLETE_SHIFT (0x03u)
#define NOR_SPI_STS_SPI_IDLE_SHIFT (0x04u)
#define NOR_SPI_STS_RX_FIFO_FULL_SHIFT (0x04u)
#define NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT (0x05u)
#define NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT (0x06u)
#define NOR_SPI_STS_SPI_DONE ((uint8) (0x01u << NOR_SPI_STS_SPI_DONE_SHIFT))
#define NOR_SPI_STS_TX_FIFO_EMPTY ((uint8) (0x01u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT))
#define NOR_SPI_STS_TX_FIFO_NOT_FULL ((uint8) (0x01u << NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT))
#define NOR_SPI_STS_BYTE_COMPLETE ((uint8) (0x01u << NOR_SPI_STS_BYTE_COMPLETE_SHIFT))
#define NOR_SPI_STS_SPI_IDLE ((uint8) (0x01u << NOR_SPI_STS_SPI_IDLE_SHIFT))
#define NOR_SPI_STS_RX_FIFO_FULL ((uint8) (0x01u << NOR_SPI_STS_RX_FIFO_FULL_SHIFT))
#define NOR_SPI_STS_RX_FIFO_NOT_EMPTY ((uint8) (0x01u << NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT))
#define NOR_SPI_STS_RX_FIFO_OVERRUN ((uint8) (0x01u << NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT))
/* TX and RX masks for clear on read bits */
#define NOR_SPI_TX_STS_CLR_ON_RD_BYTES_MASK (0x09u)
#define NOR_SPI_RX_STS_CLR_ON_RD_BYTES_MASK (0x40u)
/* StatusI Register Interrupt Enable Control Bits */
/* As defined by the Register map for the AUX Control Register */
#define NOR_SPI_INT_ENABLE (0x10u) /* Enable interrupt from statusi */
#define NOR_SPI_TX_FIFO_CLR (0x01u) /* F0 - TX FIFO */
#define NOR_SPI_RX_FIFO_CLR (0x02u) /* F1 - RX FIFO */
#define NOR_SPI_FIFO_CLR (NOR_SPI_TX_FIFO_CLR | NOR_SPI_RX_FIFO_CLR)
/* Bit Counter (7-bit) Control Register Bit Definitions */
/* As defined by the Register map for the AUX Control Register */
#define NOR_SPI_CNTR_ENABLE (0x20u) /* Enable CNT7 */
/* Bi-Directional mode control bit */
#define NOR_SPI_CTRL_TX_SIGNAL_EN (0x01u)
/* Datapath Auxillary Control Register definitions */
#define NOR_SPI_AUX_CTRL_FIFO0_CLR (0x01u)
#define NOR_SPI_AUX_CTRL_FIFO1_CLR (0x02u)
#define NOR_SPI_AUX_CTRL_FIFO0_LVL (0x04u)
#define NOR_SPI_AUX_CTRL_FIFO1_LVL (0x08u)
#define NOR_SPI_STATUS_ACTL_INT_EN_MASK (0x10u)
/* Component disabled */
#define NOR_SPI_DISABLED (0u)
/***************************************
* Macros
***************************************/
/* Returns true if componentn enabled */
#define NOR_SPI_IS_ENABLED (0u != (NOR_SPI_TX_STATUS_ACTL_REG & NOR_SPI_INT_ENABLE))
/* Retuns TX status register */
#define NOR_SPI_GET_STATUS_TX(swTxSts) ( (uint8)(NOR_SPI_TX_STATUS_REG | \
((swTxSts) & NOR_SPI_TX_STS_CLR_ON_RD_BYTES_MASK)) )
/* Retuns RX status register */
#define NOR_SPI_GET_STATUS_RX(swRxSts) ( (uint8)(NOR_SPI_RX_STATUS_REG | \
((swRxSts) & NOR_SPI_RX_STS_CLR_ON_RD_BYTES_MASK)) )
/***************************************
* The following code is DEPRECATED and
* should not be used in new projects.
***************************************/
#define NOR_SPI_WriteByte NOR_SPI_WriteTxData
#define NOR_SPI_ReadByte NOR_SPI_ReadRxData
void NOR_SPI_SetInterruptMode(uint8 intSrc) ;
uint8 NOR_SPI_ReadStatus(void) ;
void NOR_SPI_EnableInt(void) ;
void NOR_SPI_DisableInt(void) ;
#define NOR_SPI_TXDATA (NOR_SPI_TXDATA_REG)
#define NOR_SPI_RXDATA (NOR_SPI_RXDATA_REG)
#define NOR_SPI_AUX_CONTROLDP0 (NOR_SPI_AUX_CONTROL_DP0_REG)
#define NOR_SPI_TXBUFFERREAD (NOR_SPI_txBufferRead)
#define NOR_SPI_TXBUFFERWRITE (NOR_SPI_txBufferWrite)
#define NOR_SPI_RXBUFFERREAD (NOR_SPI_rxBufferRead)
#define NOR_SPI_RXBUFFERWRITE (NOR_SPI_rxBufferWrite)
#define NOR_SPI_COUNTER_PERIOD (NOR_SPI_COUNTER_PERIOD_REG)
#define NOR_SPI_COUNTER_CONTROL (NOR_SPI_COUNTER_CONTROL_REG)
#define NOR_SPI_STATUS (NOR_SPI_TX_STATUS_REG)
#define NOR_SPI_CONTROL (NOR_SPI_CONTROL_REG)
#define NOR_SPI_STATUS_MASK (NOR_SPI_TX_STATUS_MASK_REG)
#define NOR_SPI_STATUS_ACTL (NOR_SPI_TX_STATUS_ACTL_REG)
#define NOR_SPI_INIT_INTERRUPTS_MASK (NOR_SPI_INT_ON_SPI_DONE | \
NOR_SPI_INT_ON_TX_EMPTY | \
NOR_SPI_INT_ON_TX_NOT_FULL_DEF | \
NOR_SPI_INT_ON_RX_FULL | \
NOR_SPI_INT_ON_RX_NOT_EMPTY | \
NOR_SPI_INT_ON_RX_OVER | \
NOR_SPI_INT_ON_BYTE_COMP)
#define NOR_SPI_DataWidth (NOR_SPI_DATA_WIDTH)
#define NOR_SPI_InternalClockUsed (NOR_SPI_INTERNAL_CLOCK)
#define NOR_SPI_InternalTxInterruptEnabled (NOR_SPI_INTERNAL_TX_INT_ENABLED)
#define NOR_SPI_InternalRxInterruptEnabled (NOR_SPI_INTERNAL_RX_INT_ENABLED)
#define NOR_SPI_ModeUseZero (NOR_SPI_MODE_USE_ZERO)
#define NOR_SPI_BidirectionalMode (NOR_SPI_BIDIRECTIONAL_MODE)
#define NOR_SPI_Mode (NOR_SPI_MODE)
#define NOR_SPI_DATAWIDHT (NOR_SPI_DATA_WIDTH)
#define NOR_SPI_InternalInterruptEnabled (0u)
#define NOR_SPI_TXBUFFERSIZE (NOR_SPI_TX_BUFFER_SIZE)
#define NOR_SPI_RXBUFFERSIZE (NOR_SPI_RX_BUFFER_SIZE)
#define NOR_SPI_TXBUFFER NOR_SPI_txBuffer
#define NOR_SPI_RXBUFFER NOR_SPI_rxBuffer
#endif /* (CY_SPIM_NOR_SPI_H) */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: NOR_SPI_INT.c
* Version 2.50
*
* Description:
* This file provides all Interrupt Service Routine (ISR) for the SPI Master
* component.
*
* Note:
* None.
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "NOR_SPI_PVT.h"
/* User code required at start of ISR */
/* `#START NOR_SPI_ISR_START_DEF` */
/* `#END` */
/*******************************************************************************
* Function Name: NOR_SPI_TX_ISR
********************************************************************************
*
* Summary:
* Interrupt Service Routine for TX portion of the SPI Master.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* NOR_SPI_txBufferWrite - used for the account of the bytes which
* have been written down in the TX software buffer.
* NOR_SPI_txBufferRead - used for the account of the bytes which
* have been read from the TX software buffer, modified when exist data to
* sending and FIFO Not Full.
* NOR_SPI_txBuffer[NOR_SPI_TX_BUFFER_SIZE] - used to store
* data to sending.
* All described above Global variables are used when Software Buffer is used.
*
*******************************************************************************/
CY_ISR(NOR_SPI_TX_ISR)
{
#if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED)
uint8 tmpStatus;
#endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */
#ifdef NOR_SPI_TX_ISR_ENTRY_CALLBACK
NOR_SPI_TX_ISR_EntryCallback();
#endif /* NOR_SPI_TX_ISR_ENTRY_CALLBACK */
/* User code required at start of ISR */
/* `#START NOR_SPI_TX_ISR_START` */
/* `#END` */
#if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED)
/* Check if TX data buffer is not empty and there is space in TX FIFO */
while(NOR_SPI_txBufferRead != NOR_SPI_txBufferWrite)
{
tmpStatus = NOR_SPI_GET_STATUS_TX(NOR_SPI_swStatusTx);
NOR_SPI_swStatusTx = tmpStatus;
if(0u != (NOR_SPI_swStatusTx & NOR_SPI_STS_TX_FIFO_NOT_FULL))
{
if(0u == NOR_SPI_txBufferFull)
{
NOR_SPI_txBufferRead++;
if(NOR_SPI_txBufferRead >= NOR_SPI_TX_BUFFER_SIZE)
{
NOR_SPI_txBufferRead = 0u;
}
}
else
{
NOR_SPI_txBufferFull = 0u;
}
/* Put data element into the TX FIFO */
CY_SET_REG8(NOR_SPI_TXDATA_PTR,
NOR_SPI_txBuffer[NOR_SPI_txBufferRead]);
}
else
{
break;
}
}
if(NOR_SPI_txBufferRead == NOR_SPI_txBufferWrite)
{
/* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */
NOR_SPI_TX_STATUS_MASK_REG &= ((uint8) ~NOR_SPI_STS_TX_FIFO_NOT_FULL);
}
#endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */
/* User code required at end of ISR (Optional) */
/* `#START NOR_SPI_TX_ISR_END` */
/* `#END` */
#ifdef NOR_SPI_TX_ISR_EXIT_CALLBACK
NOR_SPI_TX_ISR_ExitCallback();
#endif /* NOR_SPI_TX_ISR_EXIT_CALLBACK */
}
/*******************************************************************************
* Function Name: NOR_SPI_RX_ISR
********************************************************************************
*
* Summary:
* Interrupt Service Routine for RX portion of the SPI Master.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* NOR_SPI_rxBufferWrite - used for the account of the bytes which
* have been written down in the RX software buffer modified when FIFO contains
* new data.
* NOR_SPI_rxBufferRead - used for the account of the bytes which
* have been read from the RX software buffer, modified when overflow occurred.
* NOR_SPI_rxBuffer[NOR_SPI_RX_BUFFER_SIZE] - used to store
* received data, modified when FIFO contains new data.
* All described above Global variables are used when Software Buffer is used.
*
*******************************************************************************/
CY_ISR(NOR_SPI_RX_ISR)
{
#if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED)
uint8 tmpStatus;
uint8 rxData;
#endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */
#ifdef NOR_SPI_RX_ISR_ENTRY_CALLBACK
NOR_SPI_RX_ISR_EntryCallback();
#endif /* NOR_SPI_RX_ISR_ENTRY_CALLBACK */
/* User code required at start of ISR */
/* `#START NOR_SPI_RX_ISR_START` */
/* `#END` */
#if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED)
tmpStatus = NOR_SPI_GET_STATUS_RX(NOR_SPI_swStatusRx);
NOR_SPI_swStatusRx = tmpStatus;
/* Check if RX data FIFO has some data to be moved into the RX Buffer */
while(0u != (NOR_SPI_swStatusRx & NOR_SPI_STS_RX_FIFO_NOT_EMPTY))
{
rxData = CY_GET_REG8(NOR_SPI_RXDATA_PTR);
/* Set next pointer. */
NOR_SPI_rxBufferWrite++;
if(NOR_SPI_rxBufferWrite >= NOR_SPI_RX_BUFFER_SIZE)
{
NOR_SPI_rxBufferWrite = 0u;
}
if(NOR_SPI_rxBufferWrite == NOR_SPI_rxBufferRead)
{
NOR_SPI_rxBufferRead++;
if(NOR_SPI_rxBufferRead >= NOR_SPI_RX_BUFFER_SIZE)
{
NOR_SPI_rxBufferRead = 0u;
}
NOR_SPI_rxBufferFull = 1u;
}
/* Move data from the FIFO to the Buffer */
NOR_SPI_rxBuffer[NOR_SPI_rxBufferWrite] = rxData;
tmpStatus = NOR_SPI_GET_STATUS_RX(NOR_SPI_swStatusRx);
NOR_SPI_swStatusRx = tmpStatus;
}
#endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */
/* User code required at end of ISR (Optional) */
/* `#START NOR_SPI_RX_ISR_END` */
/* `#END` */
#ifdef NOR_SPI_RX_ISR_EXIT_CALLBACK
NOR_SPI_RX_ISR_ExitCallback();
#endif /* NOR_SPI_RX_ISR_EXIT_CALLBACK */
}
/* [] END OF FILE */

149
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/*******************************************************************************
* File Name: NOR_SPI_PM.c
* Version 2.50
*
* Description:
* This file contains the setup, control and status commands to support
* component operations in low power mode.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "NOR_SPI_PVT.h"
static NOR_SPI_BACKUP_STRUCT NOR_SPI_backup =
{
NOR_SPI_DISABLED,
NOR_SPI_BITCTR_INIT,
};
/*******************************************************************************
* Function Name: NOR_SPI_SaveConfig
********************************************************************************
*
* Summary:
* Empty function. Included for consistency with other components.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void NOR_SPI_SaveConfig(void)
{
}
/*******************************************************************************
* Function Name: NOR_SPI_RestoreConfig
********************************************************************************
*
* Summary:
* Empty function. Included for consistency with other components.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void NOR_SPI_RestoreConfig(void)
{
}
/*******************************************************************************
* Function Name: NOR_SPI_Sleep
********************************************************************************
*
* Summary:
* Prepare SPIM Component goes to sleep.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global Variables:
* NOR_SPI_backup - modified when non-retention registers are saved.
*
* Reentrant:
* No.
*
*******************************************************************************/
void NOR_SPI_Sleep(void)
{
/* Save components enable state */
NOR_SPI_backup.enableState = ((uint8) NOR_SPI_IS_ENABLED);
NOR_SPI_Stop();
}
/*******************************************************************************
* Function Name: NOR_SPI_Wakeup
********************************************************************************
*
* Summary:
* Prepare SPIM Component to wake up.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global Variables:
* NOR_SPI_backup - used when non-retention registers are restored.
* NOR_SPI_txBufferWrite - modified every function call - resets to
* zero.
* NOR_SPI_txBufferRead - modified every function call - resets to
* zero.
* NOR_SPI_rxBufferWrite - modified every function call - resets to
* zero.
* NOR_SPI_rxBufferRead - modified every function call - resets to
* zero.
*
* Reentrant:
* No.
*
*******************************************************************************/
void NOR_SPI_Wakeup(void)
{
#if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED)
NOR_SPI_rxBufferFull = 0u;
NOR_SPI_rxBufferRead = 0u;
NOR_SPI_rxBufferWrite = 0u;
#endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */
#if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED)
NOR_SPI_txBufferFull = 0u;
NOR_SPI_txBufferRead = 0u;
NOR_SPI_txBufferWrite = 0u;
#endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */
/* Clear any data from the RX and TX FIFO */
NOR_SPI_ClearFIFO();
/* Restore components block enable state */
if(0u != NOR_SPI_backup.enableState)
{
NOR_SPI_Enable();
}
}
/* [] END OF FILE */

53
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@ -0,0 +1,53 @@
/*******************************************************************************
* File Name: .h
* Version 2.50
*
* Description:
* This private header file contains internal definitions for the SPIM
* component. Do not use these definitions directly in your application.
*
* Note:
*
********************************************************************************
* Copyright 2012-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_SPIM_PVT_NOR_SPI_H)
#define CY_SPIM_PVT_NOR_SPI_H
#include "NOR_SPI.h"
/**********************************
* Functions with external linkage
**********************************/
/**********************************
* Variables with external linkage
**********************************/
extern volatile uint8 NOR_SPI_swStatusTx;
extern volatile uint8 NOR_SPI_swStatusRx;
#if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED)
extern volatile uint8 NOR_SPI_txBuffer[NOR_SPI_TX_BUFFER_SIZE];
extern volatile uint8 NOR_SPI_txBufferRead;
extern volatile uint8 NOR_SPI_txBufferWrite;
extern volatile uint8 NOR_SPI_txBufferFull;
#endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */
#if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED)
extern volatile uint8 NOR_SPI_rxBuffer[NOR_SPI_RX_BUFFER_SIZE];
extern volatile uint8 NOR_SPI_rxBufferRead;
extern volatile uint8 NOR_SPI_rxBufferWrite;
extern volatile uint8 NOR_SPI_rxBufferFull;
#endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */
#endif /* CY_SPIM_PVT_NOR_SPI_H */
/* [] END OF FILE */

661
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
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@ -355,33 +355,101 @@
#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
/* NOR_SI */
#define NOR_SI__0__INTTYPE CYREG_PICU3_INTTYPE6
#define NOR_SI__0__MASK 0x40u
#define NOR_SI__0__PC CYREG_PRT3_PC6
#define NOR_SI__0__PORT 3u
#define NOR_SI__0__SHIFT 6u
#define NOR_SI__AG CYREG_PRT3_AG
#define NOR_SI__AMUX CYREG_PRT3_AMUX
#define NOR_SI__BIE CYREG_PRT3_BIE
#define NOR_SI__BIT_MASK CYREG_PRT3_BIT_MASK
#define NOR_SI__BYP CYREG_PRT3_BYP
#define NOR_SI__CTL CYREG_PRT3_CTL
#define NOR_SI__DM0 CYREG_PRT3_DM0
#define NOR_SI__DM1 CYREG_PRT3_DM1
#define NOR_SI__DM2 CYREG_PRT3_DM2
#define NOR_SI__DR CYREG_PRT3_DR
#define NOR_SI__INP_DIS CYREG_PRT3_INP_DIS
#define NOR_SI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
#define NOR_SI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
#define NOR_SI__LCD_EN CYREG_PRT3_LCD_EN
#define NOR_SI__MASK 0x40u
#define NOR_SI__PORT 3u
#define NOR_SI__PRT CYREG_PRT3_PRT
#define NOR_SI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
#define NOR_SI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
#define NOR_SI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
#define NOR_SI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
#define NOR_SI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
#define NOR_SI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
#define NOR_SI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
#define NOR_SI__PS CYREG_PRT3_PS
#define NOR_SI__SHIFT 6u
#define NOR_SI__SLW CYREG_PRT3_SLW
/* NOR_SO */
#define NOR_SO__0__INTTYPE CYREG_PICU15_INTTYPE2
#define NOR_SO__0__MASK 0x04u
#define NOR_SO__0__PC CYREG_IO_PC_PRT15_PC2
#define NOR_SO__0__PORT 15u
#define NOR_SO__0__SHIFT 2u
#define NOR_SO__AG CYREG_PRT15_AG
#define NOR_SO__AMUX CYREG_PRT15_AMUX
#define NOR_SO__BIE CYREG_PRT15_BIE
#define NOR_SO__BIT_MASK CYREG_PRT15_BIT_MASK
#define NOR_SO__BYP CYREG_PRT15_BYP
#define NOR_SO__CTL CYREG_PRT15_CTL
#define NOR_SO__DM0 CYREG_PRT15_DM0
#define NOR_SO__DM1 CYREG_PRT15_DM1
#define NOR_SO__DM2 CYREG_PRT15_DM2
#define NOR_SO__DR CYREG_PRT15_DR
#define NOR_SO__INP_DIS CYREG_PRT15_INP_DIS
#define NOR_SO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define NOR_SO__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define NOR_SO__LCD_EN CYREG_PRT15_LCD_EN
#define NOR_SO__MASK 0x04u
#define NOR_SO__PORT 15u
#define NOR_SO__PRT CYREG_PRT15_PRT
#define NOR_SO__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define NOR_SO__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define NOR_SO__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define NOR_SO__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define NOR_SO__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define NOR_SO__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define NOR_SO__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define NOR_SO__PS CYREG_PRT15_PS
#define NOR_SO__SHIFT 2u
#define NOR_SO__SLW CYREG_PRT15_SLW
/* SDCard */
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
@ -392,7 +460,11 @@
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
@ -411,14 +483,12 @@
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
@ -426,9 +496,9 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB06_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB06_ST
/* SD_SCK */
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1
@ -464,6 +534,137 @@
#define SD_SCK__SHIFT 1u
#define SD_SCK__SLW CYREG_PRT3_SLW
/* NOR_CTL */
#define NOR_CTL_Sync_ctrl_reg__0__MASK 0x01u
#define NOR_CTL_Sync_ctrl_reg__0__POS 0
#define NOR_CTL_Sync_ctrl_reg__1__MASK 0x02u
#define NOR_CTL_Sync_ctrl_reg__1__POS 1
#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
#define NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define NOR_CTL_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB06_CTL
#define NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
#define NOR_CTL_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB06_CTL
#define NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
#define NOR_CTL_Sync_ctrl_reg__MASK 0x03u
#define NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define NOR_CTL_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB06_MSK
/* NOR_SCK */
#define NOR_SCK__0__INTTYPE CYREG_PICU3_INTTYPE7
#define NOR_SCK__0__MASK 0x80u
#define NOR_SCK__0__PC CYREG_PRT3_PC7
#define NOR_SCK__0__PORT 3u
#define NOR_SCK__0__SHIFT 7u
#define NOR_SCK__AG CYREG_PRT3_AG
#define NOR_SCK__AMUX CYREG_PRT3_AMUX
#define NOR_SCK__BIE CYREG_PRT3_BIE
#define NOR_SCK__BIT_MASK CYREG_PRT3_BIT_MASK
#define NOR_SCK__BYP CYREG_PRT3_BYP
#define NOR_SCK__CTL CYREG_PRT3_CTL
#define NOR_SCK__DM0 CYREG_PRT3_DM0
#define NOR_SCK__DM1 CYREG_PRT3_DM1
#define NOR_SCK__DM2 CYREG_PRT3_DM2
#define NOR_SCK__DR CYREG_PRT3_DR
#define NOR_SCK__INP_DIS CYREG_PRT3_INP_DIS
#define NOR_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
#define NOR_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
#define NOR_SCK__LCD_EN CYREG_PRT3_LCD_EN
#define NOR_SCK__MASK 0x80u
#define NOR_SCK__PORT 3u
#define NOR_SCK__PRT CYREG_PRT3_PRT
#define NOR_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
#define NOR_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
#define NOR_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
#define NOR_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
#define NOR_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
#define NOR_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
#define NOR_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
#define NOR_SCK__PS CYREG_PRT3_PS
#define NOR_SCK__SHIFT 7u
#define NOR_SCK__SLW CYREG_PRT3_SLW
/* NOR_SPI */
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB08_CTL
#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB08_CTL
#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB08_MSK
#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB08_MSK
#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB08_ST
#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
#define NOR_SPI_BSPIM_RxStsReg__4__MASK 0x10u
#define NOR_SPI_BSPIM_RxStsReg__4__POS 4
#define NOR_SPI_BSPIM_RxStsReg__5__MASK 0x20u
#define NOR_SPI_BSPIM_RxStsReg__5__POS 5
#define NOR_SPI_BSPIM_RxStsReg__6__MASK 0x40u
#define NOR_SPI_BSPIM_RxStsReg__6__POS 6
#define NOR_SPI_BSPIM_RxStsReg__MASK 0x70u
#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK
#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1
#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1
#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0
#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1
#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1
#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0
#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1
#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1
#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0
#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1
#define NOR_SPI_BSPIM_TxStsReg__0__MASK 0x01u
#define NOR_SPI_BSPIM_TxStsReg__0__POS 0
#define NOR_SPI_BSPIM_TxStsReg__1__MASK 0x02u
#define NOR_SPI_BSPIM_TxStsReg__1__POS 1
#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define NOR_SPI_BSPIM_TxStsReg__2__MASK 0x04u
#define NOR_SPI_BSPIM_TxStsReg__2__POS 2
#define NOR_SPI_BSPIM_TxStsReg__3__MASK 0x08u
#define NOR_SPI_BSPIM_TxStsReg__3__POS 3
#define NOR_SPI_BSPIM_TxStsReg__4__MASK 0x10u
#define NOR_SPI_BSPIM_TxStsReg__4__POS 4
#define NOR_SPI_BSPIM_TxStsReg__MASK 0x1Fu
#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
/* SCSI_In */
#define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1
#define SCSI_In__0__MASK 0x02u
@ -1051,16 +1252,84 @@
#define TERM_EN__SHIFT 3u
#define TERM_EN__SLW CYREG_PRT15_SLW
/* nNOR_CS */
#define nNOR_CS__0__INTTYPE CYREG_PICU3_INTTYPE4
#define nNOR_CS__0__MASK 0x10u
#define nNOR_CS__0__PC CYREG_PRT3_PC4
#define nNOR_CS__0__PORT 3u
#define nNOR_CS__0__SHIFT 4u
#define nNOR_CS__AG CYREG_PRT3_AG
#define nNOR_CS__AMUX CYREG_PRT3_AMUX
#define nNOR_CS__BIE CYREG_PRT3_BIE
#define nNOR_CS__BIT_MASK CYREG_PRT3_BIT_MASK
#define nNOR_CS__BYP CYREG_PRT3_BYP
#define nNOR_CS__CTL CYREG_PRT3_CTL
#define nNOR_CS__DM0 CYREG_PRT3_DM0
#define nNOR_CS__DM1 CYREG_PRT3_DM1
#define nNOR_CS__DM2 CYREG_PRT3_DM2
#define nNOR_CS__DR CYREG_PRT3_DR
#define nNOR_CS__INP_DIS CYREG_PRT3_INP_DIS
#define nNOR_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
#define nNOR_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
#define nNOR_CS__LCD_EN CYREG_PRT3_LCD_EN
#define nNOR_CS__MASK 0x10u
#define nNOR_CS__PORT 3u
#define nNOR_CS__PRT CYREG_PRT3_PRT
#define nNOR_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
#define nNOR_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
#define nNOR_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
#define nNOR_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
#define nNOR_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
#define nNOR_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
#define nNOR_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
#define nNOR_CS__PS CYREG_PRT3_PS
#define nNOR_CS__SHIFT 4u
#define nNOR_CS__SLW CYREG_PRT3_SLW
/* nNOR_WP */
#define nNOR_WP__0__INTTYPE CYREG_PICU3_INTTYPE5
#define nNOR_WP__0__MASK 0x20u
#define nNOR_WP__0__PC CYREG_PRT3_PC5
#define nNOR_WP__0__PORT 3u
#define nNOR_WP__0__SHIFT 5u
#define nNOR_WP__AG CYREG_PRT3_AG
#define nNOR_WP__AMUX CYREG_PRT3_AMUX
#define nNOR_WP__BIE CYREG_PRT3_BIE
#define nNOR_WP__BIT_MASK CYREG_PRT3_BIT_MASK
#define nNOR_WP__BYP CYREG_PRT3_BYP
#define nNOR_WP__CTL CYREG_PRT3_CTL
#define nNOR_WP__DM0 CYREG_PRT3_DM0
#define nNOR_WP__DM1 CYREG_PRT3_DM1
#define nNOR_WP__DM2 CYREG_PRT3_DM2
#define nNOR_WP__DR CYREG_PRT3_DR
#define nNOR_WP__INP_DIS CYREG_PRT3_INP_DIS
#define nNOR_WP__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
#define nNOR_WP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
#define nNOR_WP__LCD_EN CYREG_PRT3_LCD_EN
#define nNOR_WP__MASK 0x20u
#define nNOR_WP__PORT 3u
#define nNOR_WP__PRT CYREG_PRT3_PRT
#define nNOR_WP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
#define nNOR_WP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
#define nNOR_WP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
#define nNOR_WP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
#define nNOR_WP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
#define nNOR_WP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
#define nNOR_WP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
#define nNOR_WP__PS CYREG_PRT3_PS
#define nNOR_WP__SHIFT 5u
#define nNOR_WP__SLW CYREG_PRT3_SLW
/* SCSI_CLK */
#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG2_CFG0
#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG2_CFG1
#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG2_CFG2
#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
#define SCSI_CLK__INDEX 0x01u
#define SCSI_CLK__INDEX 0x02u
#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define SCSI_CLK__PM_ACT_MSK 0x02u
#define SCSI_CLK__PM_ACT_MSK 0x04u
#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define SCSI_CLK__PM_STBY_MSK 0x02u
#define SCSI_CLK__PM_STBY_MSK 0x04u
/* SCSI_Out */
#define SCSI_Out__0__AG CYREG_PRT6_AG
@ -1515,15 +1784,15 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@ -1536,35 +1805,35 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
@ -2012,6 +2281,17 @@
#define SCSI_Out_DBx__DB7__SHIFT 5u
#define SCSI_Out_DBx__DB7__SLW CYREG_PRT15_SLW
/* NOR_Clock */
#define NOR_Clock__CFG0 CYREG_CLKDIST_DCFG0_CFG0
#define NOR_Clock__CFG1 CYREG_CLKDIST_DCFG0_CFG1
#define NOR_Clock__CFG2 CYREG_CLKDIST_DCFG0_CFG2
#define NOR_Clock__CFG2_SRC_SEL_MASK 0x07u
#define NOR_Clock__INDEX 0x00u
#define NOR_Clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define NOR_Clock__PM_ACT_MSK 0x01u
#define NOR_Clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define NOR_Clock__PM_STBY_MSK 0x01u
/* SD_RX_DMA */
#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
#define SD_RX_DMA__DRQ_NUMBER 2u
@ -2052,6 +2332,39 @@
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* nNOR_HOLD */
#define nNOR_HOLD__0__INTTYPE CYREG_PICU12_INTTYPE1
#define nNOR_HOLD__0__MASK 0x02u
#define nNOR_HOLD__0__PC CYREG_PRT12_PC1
#define nNOR_HOLD__0__PORT 12u
#define nNOR_HOLD__0__SHIFT 1u
#define nNOR_HOLD__AG CYREG_PRT12_AG
#define nNOR_HOLD__BIE CYREG_PRT12_BIE
#define nNOR_HOLD__BIT_MASK CYREG_PRT12_BIT_MASK
#define nNOR_HOLD__BYP CYREG_PRT12_BYP
#define nNOR_HOLD__DM0 CYREG_PRT12_DM0
#define nNOR_HOLD__DM1 CYREG_PRT12_DM1
#define nNOR_HOLD__DM2 CYREG_PRT12_DM2
#define nNOR_HOLD__DR CYREG_PRT12_DR
#define nNOR_HOLD__INP_DIS CYREG_PRT12_INP_DIS
#define nNOR_HOLD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define nNOR_HOLD__MASK 0x02u
#define nNOR_HOLD__PORT 12u
#define nNOR_HOLD__PRT CYREG_PRT12_PRT
#define nNOR_HOLD__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define nNOR_HOLD__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define nNOR_HOLD__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define nNOR_HOLD__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define nNOR_HOLD__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define nNOR_HOLD__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define nNOR_HOLD__PS CYREG_PRT12_PS
#define nNOR_HOLD__SHIFT 1u
#define nNOR_HOLD__SIO_CFG CYREG_PRT12_SIO_CFG
#define nNOR_HOLD__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define nNOR_HOLD__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define nNOR_HOLD__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define nNOR_HOLD__SLW CYREG_PRT12_SLW
/* SCSI_Noise */
#define SCSI_Noise__0__AG CYREG_PRT4_AG
#define SCSI_Noise__0__AMUX CYREG_PRT4_AMUX
@ -2384,6 +2697,8 @@
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
@ -2391,13 +2706,13 @@
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK
#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB15_ST_CTL
#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB15_ST_CTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK
#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL
#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST
/* Debug_Timer */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -2466,111 +2781,26 @@
#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SD_Data_Clk */
#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2
#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG1_CFG0
#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG1_CFG1
#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG1_CFG2
#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u
#define SD_Data_Clk__INDEX 0x00u
#define SD_Data_Clk__INDEX 0x01u
#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define SD_Data_Clk__PM_ACT_MSK 0x01u
#define SD_Data_Clk__PM_ACT_MSK 0x02u
#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define SD_Data_Clk__PM_STBY_MSK 0x01u
/* SPI_Pullups */
#define SPI_Pullups__0__INTTYPE CYREG_PICU3_INTTYPE4
#define SPI_Pullups__0__MASK 0x10u
#define SPI_Pullups__0__PC CYREG_PRT3_PC4
#define SPI_Pullups__0__PORT 3u
#define SPI_Pullups__0__SHIFT 4u
#define SPI_Pullups__1__INTTYPE CYREG_PICU3_INTTYPE5
#define SPI_Pullups__1__MASK 0x20u
#define SPI_Pullups__1__PC CYREG_PRT3_PC5
#define SPI_Pullups__1__PORT 3u
#define SPI_Pullups__1__SHIFT 5u
#define SPI_Pullups__2__INTTYPE CYREG_PICU3_INTTYPE6
#define SPI_Pullups__2__MASK 0x40u
#define SPI_Pullups__2__PC CYREG_PRT3_PC6
#define SPI_Pullups__2__PORT 3u
#define SPI_Pullups__2__SHIFT 6u
#define SPI_Pullups__3__INTTYPE CYREG_PICU3_INTTYPE7
#define SPI_Pullups__3__MASK 0x80u
#define SPI_Pullups__3__PC CYREG_PRT3_PC7
#define SPI_Pullups__3__PORT 3u
#define SPI_Pullups__3__SHIFT 7u
#define SPI_Pullups__AG CYREG_PRT3_AG
#define SPI_Pullups__AMUX CYREG_PRT3_AMUX
#define SPI_Pullups__BIE CYREG_PRT3_BIE
#define SPI_Pullups__BIT_MASK CYREG_PRT3_BIT_MASK
#define SPI_Pullups__BYP CYREG_PRT3_BYP
#define SPI_Pullups__CTL CYREG_PRT3_CTL
#define SPI_Pullups__DM0 CYREG_PRT3_DM0
#define SPI_Pullups__DM1 CYREG_PRT3_DM1
#define SPI_Pullups__DM2 CYREG_PRT3_DM2
#define SPI_Pullups__DR CYREG_PRT3_DR
#define SPI_Pullups__INP_DIS CYREG_PRT3_INP_DIS
#define SPI_Pullups__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
#define SPI_Pullups__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
#define SPI_Pullups__LCD_EN CYREG_PRT3_LCD_EN
#define SPI_Pullups__MASK 0xF0u
#define SPI_Pullups__PORT 3u
#define SPI_Pullups__PRT CYREG_PRT3_PRT
#define SPI_Pullups__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
#define SPI_Pullups__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
#define SPI_Pullups__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
#define SPI_Pullups__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
#define SPI_Pullups__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
#define SPI_Pullups__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
#define SPI_Pullups__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
#define SPI_Pullups__PS CYREG_PRT3_PS
#define SPI_Pullups__SHIFT 4u
#define SPI_Pullups__SLW CYREG_PRT3_SLW
#define SPI_Pullups_1__0__INTTYPE CYREG_PICU12_INTTYPE0
#define SPI_Pullups_1__0__MASK 0x01u
#define SPI_Pullups_1__0__PC CYREG_PRT12_PC0
#define SPI_Pullups_1__0__PORT 12u
#define SPI_Pullups_1__0__SHIFT 0u
#define SPI_Pullups_1__1__INTTYPE CYREG_PICU12_INTTYPE1
#define SPI_Pullups_1__1__MASK 0x02u
#define SPI_Pullups_1__1__PC CYREG_PRT12_PC1
#define SPI_Pullups_1__1__PORT 12u
#define SPI_Pullups_1__1__SHIFT 1u
#define SPI_Pullups_1__AG CYREG_PRT12_AG
#define SPI_Pullups_1__BIE CYREG_PRT12_BIE
#define SPI_Pullups_1__BIT_MASK CYREG_PRT12_BIT_MASK
#define SPI_Pullups_1__BYP CYREG_PRT12_BYP
#define SPI_Pullups_1__DM0 CYREG_PRT12_DM0
#define SPI_Pullups_1__DM1 CYREG_PRT12_DM1
#define SPI_Pullups_1__DM2 CYREG_PRT12_DM2
#define SPI_Pullups_1__DR CYREG_PRT12_DR
#define SPI_Pullups_1__INP_DIS CYREG_PRT12_INP_DIS
#define SPI_Pullups_1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define SPI_Pullups_1__MASK 0x03u
#define SPI_Pullups_1__PORT 12u
#define SPI_Pullups_1__PRT CYREG_PRT12_PRT
#define SPI_Pullups_1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define SPI_Pullups_1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define SPI_Pullups_1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define SPI_Pullups_1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define SPI_Pullups_1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define SPI_Pullups_1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define SPI_Pullups_1__PS CYREG_PRT12_PS
#define SPI_Pullups_1__SHIFT 0u
#define SPI_Pullups_1__SIO_CFG CYREG_PRT12_SIO_CFG
#define SPI_Pullups_1__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define SPI_Pullups_1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define SPI_Pullups_1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define SPI_Pullups_1__SLW CYREG_PRT12_SLW
#define SD_Data_Clk__PM_STBY_MSK 0x02u
/* timer_clock */
#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2
#define timer_clock__CFG0 CYREG_CLKDIST_DCFG3_CFG0
#define timer_clock__CFG1 CYREG_CLKDIST_DCFG3_CFG1
#define timer_clock__CFG2 CYREG_CLKDIST_DCFG3_CFG2
#define timer_clock__CFG2_SRC_SEL_MASK 0x07u
#define timer_clock__INDEX 0x02u
#define timer_clock__INDEX 0x03u
#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define timer_clock__PM_ACT_MSK 0x04u
#define timer_clock__PM_ACT_MSK 0x08u
#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define timer_clock__PM_STBY_MSK 0x04u
#define timer_clock__PM_STBY_MSK 0x08u
/* SCSI_RST_ISR */
#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -2597,8 +2827,6 @@
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@ -2606,58 +2834,67 @@
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB15_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB15_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
/* SCSI_Glitch_Ctl */
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB14_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB14_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U

3367
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
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File diff suppressed because it is too large Load Diff

661
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
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@ -355,33 +355,101 @@
.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
/* NOR_SI */
.set NOR_SI__0__INTTYPE, CYREG_PICU3_INTTYPE6
.set NOR_SI__0__MASK, 0x40
.set NOR_SI__0__PC, CYREG_PRT3_PC6
.set NOR_SI__0__PORT, 3
.set NOR_SI__0__SHIFT, 6
.set NOR_SI__AG, CYREG_PRT3_AG
.set NOR_SI__AMUX, CYREG_PRT3_AMUX
.set NOR_SI__BIE, CYREG_PRT3_BIE
.set NOR_SI__BIT_MASK, CYREG_PRT3_BIT_MASK
.set NOR_SI__BYP, CYREG_PRT3_BYP
.set NOR_SI__CTL, CYREG_PRT3_CTL
.set NOR_SI__DM0, CYREG_PRT3_DM0
.set NOR_SI__DM1, CYREG_PRT3_DM1
.set NOR_SI__DM2, CYREG_PRT3_DM2
.set NOR_SI__DR, CYREG_PRT3_DR
.set NOR_SI__INP_DIS, CYREG_PRT3_INP_DIS
.set NOR_SI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
.set NOR_SI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
.set NOR_SI__LCD_EN, CYREG_PRT3_LCD_EN
.set NOR_SI__MASK, 0x40
.set NOR_SI__PORT, 3
.set NOR_SI__PRT, CYREG_PRT3_PRT
.set NOR_SI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
.set NOR_SI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
.set NOR_SI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
.set NOR_SI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
.set NOR_SI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
.set NOR_SI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
.set NOR_SI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
.set NOR_SI__PS, CYREG_PRT3_PS
.set NOR_SI__SHIFT, 6
.set NOR_SI__SLW, CYREG_PRT3_SLW
/* NOR_SO */
.set NOR_SO__0__INTTYPE, CYREG_PICU15_INTTYPE2
.set NOR_SO__0__MASK, 0x04
.set NOR_SO__0__PC, CYREG_IO_PC_PRT15_PC2
.set NOR_SO__0__PORT, 15
.set NOR_SO__0__SHIFT, 2
.set NOR_SO__AG, CYREG_PRT15_AG
.set NOR_SO__AMUX, CYREG_PRT15_AMUX
.set NOR_SO__BIE, CYREG_PRT15_BIE
.set NOR_SO__BIT_MASK, CYREG_PRT15_BIT_MASK
.set NOR_SO__BYP, CYREG_PRT15_BYP
.set NOR_SO__CTL, CYREG_PRT15_CTL
.set NOR_SO__DM0, CYREG_PRT15_DM0
.set NOR_SO__DM1, CYREG_PRT15_DM1
.set NOR_SO__DM2, CYREG_PRT15_DM2
.set NOR_SO__DR, CYREG_PRT15_DR
.set NOR_SO__INP_DIS, CYREG_PRT15_INP_DIS
.set NOR_SO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
.set NOR_SO__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set NOR_SO__LCD_EN, CYREG_PRT15_LCD_EN
.set NOR_SO__MASK, 0x04
.set NOR_SO__PORT, 15
.set NOR_SO__PRT, CYREG_PRT15_PRT
.set NOR_SO__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
.set NOR_SO__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
.set NOR_SO__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
.set NOR_SO__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
.set NOR_SO__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
.set NOR_SO__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
.set NOR_SO__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
.set NOR_SO__PS, CYREG_PRT15_PS
.set NOR_SO__SHIFT, 2
.set NOR_SO__SLW, CYREG_PRT15_SLW
/* SDCard */
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
@ -392,7 +460,11 @@
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
@ -411,14 +483,12 @@
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
@ -426,9 +496,9 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB06_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB06_ST
/* SD_SCK */
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE1
@ -464,6 +534,137 @@
.set SD_SCK__SHIFT, 1
.set SD_SCK__SLW, CYREG_PRT3_SLW
/* NOR_CTL */
.set NOR_CTL_Sync_ctrl_reg__0__MASK, 0x01
.set NOR_CTL_Sync_ctrl_reg__0__POS, 0
.set NOR_CTL_Sync_ctrl_reg__1__MASK, 0x02
.set NOR_CTL_Sync_ctrl_reg__1__POS, 1
.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
.set NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
.set NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
.set NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
.set NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
.set NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
.set NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
.set NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set NOR_CTL_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB06_CTL
.set NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
.set NOR_CTL_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB06_CTL
.set NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
.set NOR_CTL_Sync_ctrl_reg__MASK, 0x03
.set NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set NOR_CTL_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB06_MSK
/* NOR_SCK */
.set NOR_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE7
.set NOR_SCK__0__MASK, 0x80
.set NOR_SCK__0__PC, CYREG_PRT3_PC7
.set NOR_SCK__0__PORT, 3
.set NOR_SCK__0__SHIFT, 7
.set NOR_SCK__AG, CYREG_PRT3_AG
.set NOR_SCK__AMUX, CYREG_PRT3_AMUX
.set NOR_SCK__BIE, CYREG_PRT3_BIE
.set NOR_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK
.set NOR_SCK__BYP, CYREG_PRT3_BYP
.set NOR_SCK__CTL, CYREG_PRT3_CTL
.set NOR_SCK__DM0, CYREG_PRT3_DM0
.set NOR_SCK__DM1, CYREG_PRT3_DM1
.set NOR_SCK__DM2, CYREG_PRT3_DM2
.set NOR_SCK__DR, CYREG_PRT3_DR
.set NOR_SCK__INP_DIS, CYREG_PRT3_INP_DIS
.set NOR_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
.set NOR_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
.set NOR_SCK__LCD_EN, CYREG_PRT3_LCD_EN
.set NOR_SCK__MASK, 0x80
.set NOR_SCK__PORT, 3
.set NOR_SCK__PRT, CYREG_PRT3_PRT
.set NOR_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
.set NOR_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
.set NOR_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
.set NOR_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
.set NOR_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
.set NOR_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
.set NOR_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
.set NOR_SCK__PS, CYREG_PRT3_PS
.set NOR_SCK__SHIFT, 7
.set NOR_SCK__SLW, CYREG_PRT3_SLW
/* NOR_SPI */
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB08_CTL
.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB08_CTL
.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB08_MSK
.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB08_MSK
.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB08_ST
.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
.set NOR_SPI_BSPIM_RxStsReg__4__MASK, 0x10
.set NOR_SPI_BSPIM_RxStsReg__4__POS, 4
.set NOR_SPI_BSPIM_RxStsReg__5__MASK, 0x20
.set NOR_SPI_BSPIM_RxStsReg__5__POS, 5
.set NOR_SPI_BSPIM_RxStsReg__6__MASK, 0x40
.set NOR_SPI_BSPIM_RxStsReg__6__POS, 6
.set NOR_SPI_BSPIM_RxStsReg__MASK, 0x70
.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK
.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1
.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1
.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0
.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1
.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1
.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0
.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1
.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1
.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0
.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1
.set NOR_SPI_BSPIM_TxStsReg__0__MASK, 0x01
.set NOR_SPI_BSPIM_TxStsReg__0__POS, 0
.set NOR_SPI_BSPIM_TxStsReg__1__MASK, 0x02
.set NOR_SPI_BSPIM_TxStsReg__1__POS, 1
.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set NOR_SPI_BSPIM_TxStsReg__2__MASK, 0x04
.set NOR_SPI_BSPIM_TxStsReg__2__POS, 2
.set NOR_SPI_BSPIM_TxStsReg__3__MASK, 0x08
.set NOR_SPI_BSPIM_TxStsReg__3__POS, 3
.set NOR_SPI_BSPIM_TxStsReg__4__MASK, 0x10
.set NOR_SPI_BSPIM_TxStsReg__4__POS, 4
.set NOR_SPI_BSPIM_TxStsReg__MASK, 0x1F
.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
/* SCSI_In */
.set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1
.set SCSI_In__0__MASK, 0x02
@ -1051,16 +1252,84 @@
.set TERM_EN__SHIFT, 3
.set TERM_EN__SLW, CYREG_PRT15_SLW
/* nNOR_CS */
.set nNOR_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4
.set nNOR_CS__0__MASK, 0x10
.set nNOR_CS__0__PC, CYREG_PRT3_PC4
.set nNOR_CS__0__PORT, 3
.set nNOR_CS__0__SHIFT, 4
.set nNOR_CS__AG, CYREG_PRT3_AG
.set nNOR_CS__AMUX, CYREG_PRT3_AMUX
.set nNOR_CS__BIE, CYREG_PRT3_BIE
.set nNOR_CS__BIT_MASK, CYREG_PRT3_BIT_MASK
.set nNOR_CS__BYP, CYREG_PRT3_BYP
.set nNOR_CS__CTL, CYREG_PRT3_CTL
.set nNOR_CS__DM0, CYREG_PRT3_DM0
.set nNOR_CS__DM1, CYREG_PRT3_DM1
.set nNOR_CS__DM2, CYREG_PRT3_DM2
.set nNOR_CS__DR, CYREG_PRT3_DR
.set nNOR_CS__INP_DIS, CYREG_PRT3_INP_DIS
.set nNOR_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
.set nNOR_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
.set nNOR_CS__LCD_EN, CYREG_PRT3_LCD_EN
.set nNOR_CS__MASK, 0x10
.set nNOR_CS__PORT, 3
.set nNOR_CS__PRT, CYREG_PRT3_PRT
.set nNOR_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
.set nNOR_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
.set nNOR_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
.set nNOR_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
.set nNOR_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
.set nNOR_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
.set nNOR_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
.set nNOR_CS__PS, CYREG_PRT3_PS
.set nNOR_CS__SHIFT, 4
.set nNOR_CS__SLW, CYREG_PRT3_SLW
/* nNOR_WP */
.set nNOR_WP__0__INTTYPE, CYREG_PICU3_INTTYPE5
.set nNOR_WP__0__MASK, 0x20
.set nNOR_WP__0__PC, CYREG_PRT3_PC5
.set nNOR_WP__0__PORT, 3
.set nNOR_WP__0__SHIFT, 5
.set nNOR_WP__AG, CYREG_PRT3_AG
.set nNOR_WP__AMUX, CYREG_PRT3_AMUX
.set nNOR_WP__BIE, CYREG_PRT3_BIE
.set nNOR_WP__BIT_MASK, CYREG_PRT3_BIT_MASK
.set nNOR_WP__BYP, CYREG_PRT3_BYP
.set nNOR_WP__CTL, CYREG_PRT3_CTL
.set nNOR_WP__DM0, CYREG_PRT3_DM0
.set nNOR_WP__DM1, CYREG_PRT3_DM1
.set nNOR_WP__DM2, CYREG_PRT3_DM2
.set nNOR_WP__DR, CYREG_PRT3_DR
.set nNOR_WP__INP_DIS, CYREG_PRT3_INP_DIS
.set nNOR_WP__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
.set nNOR_WP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
.set nNOR_WP__LCD_EN, CYREG_PRT3_LCD_EN
.set nNOR_WP__MASK, 0x20
.set nNOR_WP__PORT, 3
.set nNOR_WP__PRT, CYREG_PRT3_PRT
.set nNOR_WP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
.set nNOR_WP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
.set nNOR_WP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
.set nNOR_WP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
.set nNOR_WP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
.set nNOR_WP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
.set nNOR_WP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
.set nNOR_WP__PS, CYREG_PRT3_PS
.set nNOR_WP__SHIFT, 5
.set nNOR_WP__SLW, CYREG_PRT3_SLW
/* SCSI_CLK */
.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG2_CFG0
.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG2_CFG1
.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG2_CFG2
.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
.set SCSI_CLK__INDEX, 0x01
.set SCSI_CLK__INDEX, 0x02
.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
.set SCSI_CLK__PM_ACT_MSK, 0x02
.set SCSI_CLK__PM_ACT_MSK, 0x04
.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
.set SCSI_CLK__PM_STBY_MSK, 0x02
.set SCSI_CLK__PM_STBY_MSK, 0x04
/* SCSI_Out */
.set SCSI_Out__0__AG, CYREG_PRT6_AG
@ -1515,15 +1784,15 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@ -1536,35 +1805,35 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB09_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB09_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX
.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE
@ -2012,6 +2281,17 @@
.set SCSI_Out_DBx__DB7__SHIFT, 5
.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT15_SLW
/* NOR_Clock */
.set NOR_Clock__CFG0, CYREG_CLKDIST_DCFG0_CFG0
.set NOR_Clock__CFG1, CYREG_CLKDIST_DCFG0_CFG1
.set NOR_Clock__CFG2, CYREG_CLKDIST_DCFG0_CFG2
.set NOR_Clock__CFG2_SRC_SEL_MASK, 0x07
.set NOR_Clock__INDEX, 0x00
.set NOR_Clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
.set NOR_Clock__PM_ACT_MSK, 0x01
.set NOR_Clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
.set NOR_Clock__PM_STBY_MSK, 0x01
/* SD_RX_DMA */
.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
.set SD_RX_DMA__DRQ_NUMBER, 2
@ -2052,6 +2332,39 @@
.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* nNOR_HOLD */
.set nNOR_HOLD__0__INTTYPE, CYREG_PICU12_INTTYPE1
.set nNOR_HOLD__0__MASK, 0x02
.set nNOR_HOLD__0__PC, CYREG_PRT12_PC1
.set nNOR_HOLD__0__PORT, 12
.set nNOR_HOLD__0__SHIFT, 1
.set nNOR_HOLD__AG, CYREG_PRT12_AG
.set nNOR_HOLD__BIE, CYREG_PRT12_BIE
.set nNOR_HOLD__BIT_MASK, CYREG_PRT12_BIT_MASK
.set nNOR_HOLD__BYP, CYREG_PRT12_BYP
.set nNOR_HOLD__DM0, CYREG_PRT12_DM0
.set nNOR_HOLD__DM1, CYREG_PRT12_DM1
.set nNOR_HOLD__DM2, CYREG_PRT12_DM2
.set nNOR_HOLD__DR, CYREG_PRT12_DR
.set nNOR_HOLD__INP_DIS, CYREG_PRT12_INP_DIS
.set nNOR_HOLD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU12_BASE
.set nNOR_HOLD__MASK, 0x02
.set nNOR_HOLD__PORT, 12
.set nNOR_HOLD__PRT, CYREG_PRT12_PRT
.set nNOR_HOLD__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
.set nNOR_HOLD__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
.set nNOR_HOLD__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
.set nNOR_HOLD__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
.set nNOR_HOLD__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
.set nNOR_HOLD__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
.set nNOR_HOLD__PS, CYREG_PRT12_PS
.set nNOR_HOLD__SHIFT, 1
.set nNOR_HOLD__SIO_CFG, CYREG_PRT12_SIO_CFG
.set nNOR_HOLD__SIO_DIFF, CYREG_PRT12_SIO_DIFF
.set nNOR_HOLD__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
.set nNOR_HOLD__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
.set nNOR_HOLD__SLW, CYREG_PRT12_SLW
/* SCSI_Noise */
.set SCSI_Noise__0__AG, CYREG_PRT4_AG
.set SCSI_Noise__0__AMUX, CYREG_PRT4_AMUX
@ -2384,6 +2697,8 @@
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
@ -2391,13 +2706,13 @@
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK
.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB15_ST_CTL
.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB15_ST_CTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK
.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL
.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST
/* Debug_Timer */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -2466,111 +2781,26 @@
.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SD_Data_Clk */
.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0
.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1
.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2
.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG1_CFG0
.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG1_CFG1
.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG1_CFG2
.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07
.set SD_Data_Clk__INDEX, 0x00
.set SD_Data_Clk__INDEX, 0x01
.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
.set SD_Data_Clk__PM_ACT_MSK, 0x01
.set SD_Data_Clk__PM_ACT_MSK, 0x02
.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
.set SD_Data_Clk__PM_STBY_MSK, 0x01
/* SPI_Pullups */
.set SPI_Pullups__0__INTTYPE, CYREG_PICU3_INTTYPE4
.set SPI_Pullups__0__MASK, 0x10
.set SPI_Pullups__0__PC, CYREG_PRT3_PC4
.set SPI_Pullups__0__PORT, 3
.set SPI_Pullups__0__SHIFT, 4
.set SPI_Pullups__1__INTTYPE, CYREG_PICU3_INTTYPE5
.set SPI_Pullups__1__MASK, 0x20
.set SPI_Pullups__1__PC, CYREG_PRT3_PC5
.set SPI_Pullups__1__PORT, 3
.set SPI_Pullups__1__SHIFT, 5
.set SPI_Pullups__2__INTTYPE, CYREG_PICU3_INTTYPE6
.set SPI_Pullups__2__MASK, 0x40
.set SPI_Pullups__2__PC, CYREG_PRT3_PC6
.set SPI_Pullups__2__PORT, 3
.set SPI_Pullups__2__SHIFT, 6
.set SPI_Pullups__3__INTTYPE, CYREG_PICU3_INTTYPE7
.set SPI_Pullups__3__MASK, 0x80
.set SPI_Pullups__3__PC, CYREG_PRT3_PC7
.set SPI_Pullups__3__PORT, 3
.set SPI_Pullups__3__SHIFT, 7
.set SPI_Pullups__AG, CYREG_PRT3_AG
.set SPI_Pullups__AMUX, CYREG_PRT3_AMUX
.set SPI_Pullups__BIE, CYREG_PRT3_BIE
.set SPI_Pullups__BIT_MASK, CYREG_PRT3_BIT_MASK
.set SPI_Pullups__BYP, CYREG_PRT3_BYP
.set SPI_Pullups__CTL, CYREG_PRT3_CTL
.set SPI_Pullups__DM0, CYREG_PRT3_DM0
.set SPI_Pullups__DM1, CYREG_PRT3_DM1
.set SPI_Pullups__DM2, CYREG_PRT3_DM2
.set SPI_Pullups__DR, CYREG_PRT3_DR
.set SPI_Pullups__INP_DIS, CYREG_PRT3_INP_DIS
.set SPI_Pullups__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
.set SPI_Pullups__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
.set SPI_Pullups__LCD_EN, CYREG_PRT3_LCD_EN
.set SPI_Pullups__MASK, 0xF0
.set SPI_Pullups__PORT, 3
.set SPI_Pullups__PRT, CYREG_PRT3_PRT
.set SPI_Pullups__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
.set SPI_Pullups__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
.set SPI_Pullups__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
.set SPI_Pullups__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
.set SPI_Pullups__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
.set SPI_Pullups__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
.set SPI_Pullups__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
.set SPI_Pullups__PS, CYREG_PRT3_PS
.set SPI_Pullups__SHIFT, 4
.set SPI_Pullups__SLW, CYREG_PRT3_SLW
.set SPI_Pullups_1__0__INTTYPE, CYREG_PICU12_INTTYPE0
.set SPI_Pullups_1__0__MASK, 0x01
.set SPI_Pullups_1__0__PC, CYREG_PRT12_PC0
.set SPI_Pullups_1__0__PORT, 12
.set SPI_Pullups_1__0__SHIFT, 0
.set SPI_Pullups_1__1__INTTYPE, CYREG_PICU12_INTTYPE1
.set SPI_Pullups_1__1__MASK, 0x02
.set SPI_Pullups_1__1__PC, CYREG_PRT12_PC1
.set SPI_Pullups_1__1__PORT, 12
.set SPI_Pullups_1__1__SHIFT, 1
.set SPI_Pullups_1__AG, CYREG_PRT12_AG
.set SPI_Pullups_1__BIE, CYREG_PRT12_BIE
.set SPI_Pullups_1__BIT_MASK, CYREG_PRT12_BIT_MASK
.set SPI_Pullups_1__BYP, CYREG_PRT12_BYP
.set SPI_Pullups_1__DM0, CYREG_PRT12_DM0
.set SPI_Pullups_1__DM1, CYREG_PRT12_DM1
.set SPI_Pullups_1__DM2, CYREG_PRT12_DM2
.set SPI_Pullups_1__DR, CYREG_PRT12_DR
.set SPI_Pullups_1__INP_DIS, CYREG_PRT12_INP_DIS
.set SPI_Pullups_1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU12_BASE
.set SPI_Pullups_1__MASK, 0x03
.set SPI_Pullups_1__PORT, 12
.set SPI_Pullups_1__PRT, CYREG_PRT12_PRT
.set SPI_Pullups_1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
.set SPI_Pullups_1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
.set SPI_Pullups_1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
.set SPI_Pullups_1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
.set SPI_Pullups_1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
.set SPI_Pullups_1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
.set SPI_Pullups_1__PS, CYREG_PRT12_PS
.set SPI_Pullups_1__SHIFT, 0
.set SPI_Pullups_1__SIO_CFG, CYREG_PRT12_SIO_CFG
.set SPI_Pullups_1__SIO_DIFF, CYREG_PRT12_SIO_DIFF
.set SPI_Pullups_1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
.set SPI_Pullups_1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
.set SPI_Pullups_1__SLW, CYREG_PRT12_SLW
.set SD_Data_Clk__PM_STBY_MSK, 0x02
/* timer_clock */
.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0
.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1
.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2
.set timer_clock__CFG0, CYREG_CLKDIST_DCFG3_CFG0
.set timer_clock__CFG1, CYREG_CLKDIST_DCFG3_CFG1
.set timer_clock__CFG2, CYREG_CLKDIST_DCFG3_CFG2
.set timer_clock__CFG2_SRC_SEL_MASK, 0x07
.set timer_clock__INDEX, 0x02
.set timer_clock__INDEX, 0x03
.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
.set timer_clock__PM_ACT_MSK, 0x04
.set timer_clock__PM_ACT_MSK, 0x08
.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
.set timer_clock__PM_STBY_MSK, 0x04
.set timer_clock__PM_STBY_MSK, 0x08
/* SCSI_RST_ISR */
.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -2597,8 +2827,6 @@
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@ -2606,58 +2834,67 @@
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB15_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB15_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
/* SCSI_Glitch_Ctl */
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB14_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB14_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000

661
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
View File

@ -354,33 +354,101 @@ USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
/* NOR_SI */
NOR_SI__0__INTTYPE EQU CYREG_PICU3_INTTYPE6
NOR_SI__0__MASK EQU 0x40
NOR_SI__0__PC EQU CYREG_PRT3_PC6
NOR_SI__0__PORT EQU 3
NOR_SI__0__SHIFT EQU 6
NOR_SI__AG EQU CYREG_PRT3_AG
NOR_SI__AMUX EQU CYREG_PRT3_AMUX
NOR_SI__BIE EQU CYREG_PRT3_BIE
NOR_SI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
NOR_SI__BYP EQU CYREG_PRT3_BYP
NOR_SI__CTL EQU CYREG_PRT3_CTL
NOR_SI__DM0 EQU CYREG_PRT3_DM0
NOR_SI__DM1 EQU CYREG_PRT3_DM1
NOR_SI__DM2 EQU CYREG_PRT3_DM2
NOR_SI__DR EQU CYREG_PRT3_DR
NOR_SI__INP_DIS EQU CYREG_PRT3_INP_DIS
NOR_SI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
NOR_SI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
NOR_SI__LCD_EN EQU CYREG_PRT3_LCD_EN
NOR_SI__MASK EQU 0x40
NOR_SI__PORT EQU 3
NOR_SI__PRT EQU CYREG_PRT3_PRT
NOR_SI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
NOR_SI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
NOR_SI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
NOR_SI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
NOR_SI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
NOR_SI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
NOR_SI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
NOR_SI__PS EQU CYREG_PRT3_PS
NOR_SI__SHIFT EQU 6
NOR_SI__SLW EQU CYREG_PRT3_SLW
/* NOR_SO */
NOR_SO__0__INTTYPE EQU CYREG_PICU15_INTTYPE2
NOR_SO__0__MASK EQU 0x04
NOR_SO__0__PC EQU CYREG_IO_PC_PRT15_PC2
NOR_SO__0__PORT EQU 15
NOR_SO__0__SHIFT EQU 2
NOR_SO__AG EQU CYREG_PRT15_AG
NOR_SO__AMUX EQU CYREG_PRT15_AMUX
NOR_SO__BIE EQU CYREG_PRT15_BIE
NOR_SO__BIT_MASK EQU CYREG_PRT15_BIT_MASK
NOR_SO__BYP EQU CYREG_PRT15_BYP
NOR_SO__CTL EQU CYREG_PRT15_CTL
NOR_SO__DM0 EQU CYREG_PRT15_DM0
NOR_SO__DM1 EQU CYREG_PRT15_DM1
NOR_SO__DM2 EQU CYREG_PRT15_DM2
NOR_SO__DR EQU CYREG_PRT15_DR
NOR_SO__INP_DIS EQU CYREG_PRT15_INP_DIS
NOR_SO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
NOR_SO__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
NOR_SO__LCD_EN EQU CYREG_PRT15_LCD_EN
NOR_SO__MASK EQU 0x04
NOR_SO__PORT EQU 15
NOR_SO__PRT EQU CYREG_PRT15_PRT
NOR_SO__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
NOR_SO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
NOR_SO__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
NOR_SO__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
NOR_SO__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
NOR_SO__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
NOR_SO__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
NOR_SO__PS EQU CYREG_PRT15_PS
NOR_SO__SHIFT EQU 2
NOR_SO__SLW EQU CYREG_PRT15_SLW
/* SDCard */
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
@ -391,7 +459,11 @@ SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
@ -410,14 +482,12 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -425,9 +495,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST
/* SD_SCK */
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
@ -463,6 +533,137 @@ SD_SCK__PS EQU CYREG_PRT3_PS
SD_SCK__SHIFT EQU 1
SD_SCK__SLW EQU CYREG_PRT3_SLW
/* NOR_CTL */
NOR_CTL_Sync_ctrl_reg__0__MASK EQU 0x01
NOR_CTL_Sync_ctrl_reg__0__POS EQU 0
NOR_CTL_Sync_ctrl_reg__1__MASK EQU 0x02
NOR_CTL_Sync_ctrl_reg__1__POS EQU 1
NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
NOR_CTL_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB06_CTL
NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
NOR_CTL_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB06_CTL
NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
NOR_CTL_Sync_ctrl_reg__MASK EQU 0x03
NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
NOR_CTL_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB06_MSK
/* NOR_SCK */
NOR_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE7
NOR_SCK__0__MASK EQU 0x80
NOR_SCK__0__PC EQU CYREG_PRT3_PC7
NOR_SCK__0__PORT EQU 3
NOR_SCK__0__SHIFT EQU 7
NOR_SCK__AG EQU CYREG_PRT3_AG
NOR_SCK__AMUX EQU CYREG_PRT3_AMUX
NOR_SCK__BIE EQU CYREG_PRT3_BIE
NOR_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
NOR_SCK__BYP EQU CYREG_PRT3_BYP
NOR_SCK__CTL EQU CYREG_PRT3_CTL
NOR_SCK__DM0 EQU CYREG_PRT3_DM0
NOR_SCK__DM1 EQU CYREG_PRT3_DM1
NOR_SCK__DM2 EQU CYREG_PRT3_DM2
NOR_SCK__DR EQU CYREG_PRT3_DR
NOR_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
NOR_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
NOR_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
NOR_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
NOR_SCK__MASK EQU 0x80
NOR_SCK__PORT EQU 3
NOR_SCK__PRT EQU CYREG_PRT3_PRT
NOR_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
NOR_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
NOR_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
NOR_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
NOR_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
NOR_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
NOR_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
NOR_SCK__PS EQU CYREG_PRT3_PS
NOR_SCK__SHIFT EQU 7
NOR_SCK__SLW EQU CYREG_PRT3_SLW
/* NOR_SPI */
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL
NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL
NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK
NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20
NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5
NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40
NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6
NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70
NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0
NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1
NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0
NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1
NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1
NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01
NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0
NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02
NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04
NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2
NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08
NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3
NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F
NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
/* SCSI_In */
SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_In__0__MASK EQU 0x02
@ -1050,16 +1251,84 @@ TERM_EN__PS EQU CYREG_PRT15_PS
TERM_EN__SHIFT EQU 3
TERM_EN__SLW EQU CYREG_PRT15_SLW
/* nNOR_CS */
nNOR_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4
nNOR_CS__0__MASK EQU 0x10
nNOR_CS__0__PC EQU CYREG_PRT3_PC4
nNOR_CS__0__PORT EQU 3
nNOR_CS__0__SHIFT EQU 4
nNOR_CS__AG EQU CYREG_PRT3_AG
nNOR_CS__AMUX EQU CYREG_PRT3_AMUX
nNOR_CS__BIE EQU CYREG_PRT3_BIE
nNOR_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
nNOR_CS__BYP EQU CYREG_PRT3_BYP
nNOR_CS__CTL EQU CYREG_PRT3_CTL
nNOR_CS__DM0 EQU CYREG_PRT3_DM0
nNOR_CS__DM1 EQU CYREG_PRT3_DM1
nNOR_CS__DM2 EQU CYREG_PRT3_DM2
nNOR_CS__DR EQU CYREG_PRT3_DR
nNOR_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
nNOR_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
nNOR_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
nNOR_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
nNOR_CS__MASK EQU 0x10
nNOR_CS__PORT EQU 3
nNOR_CS__PRT EQU CYREG_PRT3_PRT
nNOR_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
nNOR_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
nNOR_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
nNOR_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
nNOR_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
nNOR_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
nNOR_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
nNOR_CS__PS EQU CYREG_PRT3_PS
nNOR_CS__SHIFT EQU 4
nNOR_CS__SLW EQU CYREG_PRT3_SLW
/* nNOR_WP */
nNOR_WP__0__INTTYPE EQU CYREG_PICU3_INTTYPE5
nNOR_WP__0__MASK EQU 0x20
nNOR_WP__0__PC EQU CYREG_PRT3_PC5
nNOR_WP__0__PORT EQU 3
nNOR_WP__0__SHIFT EQU 5
nNOR_WP__AG EQU CYREG_PRT3_AG
nNOR_WP__AMUX EQU CYREG_PRT3_AMUX
nNOR_WP__BIE EQU CYREG_PRT3_BIE
nNOR_WP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
nNOR_WP__BYP EQU CYREG_PRT3_BYP
nNOR_WP__CTL EQU CYREG_PRT3_CTL
nNOR_WP__DM0 EQU CYREG_PRT3_DM0
nNOR_WP__DM1 EQU CYREG_PRT3_DM1
nNOR_WP__DM2 EQU CYREG_PRT3_DM2
nNOR_WP__DR EQU CYREG_PRT3_DR
nNOR_WP__INP_DIS EQU CYREG_PRT3_INP_DIS
nNOR_WP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
nNOR_WP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
nNOR_WP__LCD_EN EQU CYREG_PRT3_LCD_EN
nNOR_WP__MASK EQU 0x20
nNOR_WP__PORT EQU 3
nNOR_WP__PRT EQU CYREG_PRT3_PRT
nNOR_WP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
nNOR_WP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
nNOR_WP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
nNOR_WP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
nNOR_WP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
nNOR_WP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
nNOR_WP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
nNOR_WP__PS EQU CYREG_PRT3_PS
nNOR_WP__SHIFT EQU 5
nNOR_WP__SLW EQU CYREG_PRT3_SLW
/* SCSI_CLK */
SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
SCSI_CLK__INDEX EQU 0x01
SCSI_CLK__INDEX EQU 0x02
SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
SCSI_CLK__PM_ACT_MSK EQU 0x02
SCSI_CLK__PM_ACT_MSK EQU 0x04
SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SCSI_CLK__PM_STBY_MSK EQU 0x02
SCSI_CLK__PM_STBY_MSK EQU 0x04
/* SCSI_Out */
SCSI_Out__0__AG EQU CYREG_PRT6_AG
@ -1514,15 +1783,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1535,35 +1804,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
@ -2011,6 +2280,17 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS
SCSI_Out_DBx__DB7__SHIFT EQU 5
SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW
/* NOR_Clock */
NOR_Clock__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
NOR_Clock__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
NOR_Clock__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
NOR_Clock__CFG2_SRC_SEL_MASK EQU 0x07
NOR_Clock__INDEX EQU 0x00
NOR_Clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
NOR_Clock__PM_ACT_MSK EQU 0x01
NOR_Clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
NOR_Clock__PM_STBY_MSK EQU 0x01
/* SD_RX_DMA */
SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
SD_RX_DMA__DRQ_NUMBER EQU 2
@ -2051,6 +2331,39 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* nNOR_HOLD */
nNOR_HOLD__0__INTTYPE EQU CYREG_PICU12_INTTYPE1
nNOR_HOLD__0__MASK EQU 0x02
nNOR_HOLD__0__PC EQU CYREG_PRT12_PC1
nNOR_HOLD__0__PORT EQU 12
nNOR_HOLD__0__SHIFT EQU 1
nNOR_HOLD__AG EQU CYREG_PRT12_AG
nNOR_HOLD__BIE EQU CYREG_PRT12_BIE
nNOR_HOLD__BIT_MASK EQU CYREG_PRT12_BIT_MASK
nNOR_HOLD__BYP EQU CYREG_PRT12_BYP
nNOR_HOLD__DM0 EQU CYREG_PRT12_DM0
nNOR_HOLD__DM1 EQU CYREG_PRT12_DM1
nNOR_HOLD__DM2 EQU CYREG_PRT12_DM2
nNOR_HOLD__DR EQU CYREG_PRT12_DR
nNOR_HOLD__INP_DIS EQU CYREG_PRT12_INP_DIS
nNOR_HOLD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE
nNOR_HOLD__MASK EQU 0x02
nNOR_HOLD__PORT EQU 12
nNOR_HOLD__PRT EQU CYREG_PRT12_PRT
nNOR_HOLD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
nNOR_HOLD__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
nNOR_HOLD__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
nNOR_HOLD__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
nNOR_HOLD__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
nNOR_HOLD__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
nNOR_HOLD__PS EQU CYREG_PRT12_PS
nNOR_HOLD__SHIFT EQU 1
nNOR_HOLD__SIO_CFG EQU CYREG_PRT12_SIO_CFG
nNOR_HOLD__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
nNOR_HOLD__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
nNOR_HOLD__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
nNOR_HOLD__SLW EQU CYREG_PRT12_SLW
/* SCSI_Noise */
SCSI_Noise__0__AG EQU CYREG_PRT4_AG
SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX
@ -2383,6 +2696,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2390,13 +2705,13 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
/* Debug_Timer */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2465,111 +2780,26 @@ SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SD_Data_Clk */
SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
SD_Data_Clk__INDEX EQU 0x00
SD_Data_Clk__INDEX EQU 0x01
SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
SD_Data_Clk__PM_ACT_MSK EQU 0x01
SD_Data_Clk__PM_ACT_MSK EQU 0x02
SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SD_Data_Clk__PM_STBY_MSK EQU 0x01
/* SPI_Pullups */
SPI_Pullups__0__INTTYPE EQU CYREG_PICU3_INTTYPE4
SPI_Pullups__0__MASK EQU 0x10
SPI_Pullups__0__PC EQU CYREG_PRT3_PC4
SPI_Pullups__0__PORT EQU 3
SPI_Pullups__0__SHIFT EQU 4
SPI_Pullups__1__INTTYPE EQU CYREG_PICU3_INTTYPE5
SPI_Pullups__1__MASK EQU 0x20
SPI_Pullups__1__PC EQU CYREG_PRT3_PC5
SPI_Pullups__1__PORT EQU 3
SPI_Pullups__1__SHIFT EQU 5
SPI_Pullups__2__INTTYPE EQU CYREG_PICU3_INTTYPE6
SPI_Pullups__2__MASK EQU 0x40
SPI_Pullups__2__PC EQU CYREG_PRT3_PC6
SPI_Pullups__2__PORT EQU 3
SPI_Pullups__2__SHIFT EQU 6
SPI_Pullups__3__INTTYPE EQU CYREG_PICU3_INTTYPE7
SPI_Pullups__3__MASK EQU 0x80
SPI_Pullups__3__PC EQU CYREG_PRT3_PC7
SPI_Pullups__3__PORT EQU 3
SPI_Pullups__3__SHIFT EQU 7
SPI_Pullups__AG EQU CYREG_PRT3_AG
SPI_Pullups__AMUX EQU CYREG_PRT3_AMUX
SPI_Pullups__BIE EQU CYREG_PRT3_BIE
SPI_Pullups__BIT_MASK EQU CYREG_PRT3_BIT_MASK
SPI_Pullups__BYP EQU CYREG_PRT3_BYP
SPI_Pullups__CTL EQU CYREG_PRT3_CTL
SPI_Pullups__DM0 EQU CYREG_PRT3_DM0
SPI_Pullups__DM1 EQU CYREG_PRT3_DM1
SPI_Pullups__DM2 EQU CYREG_PRT3_DM2
SPI_Pullups__DR EQU CYREG_PRT3_DR
SPI_Pullups__INP_DIS EQU CYREG_PRT3_INP_DIS
SPI_Pullups__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
SPI_Pullups__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
SPI_Pullups__LCD_EN EQU CYREG_PRT3_LCD_EN
SPI_Pullups__MASK EQU 0xF0
SPI_Pullups__PORT EQU 3
SPI_Pullups__PRT EQU CYREG_PRT3_PRT
SPI_Pullups__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
SPI_Pullups__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
SPI_Pullups__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
SPI_Pullups__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
SPI_Pullups__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
SPI_Pullups__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
SPI_Pullups__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
SPI_Pullups__PS EQU CYREG_PRT3_PS
SPI_Pullups__SHIFT EQU 4
SPI_Pullups__SLW EQU CYREG_PRT3_SLW
SPI_Pullups_1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0
SPI_Pullups_1__0__MASK EQU 0x01
SPI_Pullups_1__0__PC EQU CYREG_PRT12_PC0
SPI_Pullups_1__0__PORT EQU 12
SPI_Pullups_1__0__SHIFT EQU 0
SPI_Pullups_1__1__INTTYPE EQU CYREG_PICU12_INTTYPE1
SPI_Pullups_1__1__MASK EQU 0x02
SPI_Pullups_1__1__PC EQU CYREG_PRT12_PC1
SPI_Pullups_1__1__PORT EQU 12
SPI_Pullups_1__1__SHIFT EQU 1
SPI_Pullups_1__AG EQU CYREG_PRT12_AG
SPI_Pullups_1__BIE EQU CYREG_PRT12_BIE
SPI_Pullups_1__BIT_MASK EQU CYREG_PRT12_BIT_MASK
SPI_Pullups_1__BYP EQU CYREG_PRT12_BYP
SPI_Pullups_1__DM0 EQU CYREG_PRT12_DM0
SPI_Pullups_1__DM1 EQU CYREG_PRT12_DM1
SPI_Pullups_1__DM2 EQU CYREG_PRT12_DM2
SPI_Pullups_1__DR EQU CYREG_PRT12_DR
SPI_Pullups_1__INP_DIS EQU CYREG_PRT12_INP_DIS
SPI_Pullups_1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE
SPI_Pullups_1__MASK EQU 0x03
SPI_Pullups_1__PORT EQU 12
SPI_Pullups_1__PRT EQU CYREG_PRT12_PRT
SPI_Pullups_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
SPI_Pullups_1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
SPI_Pullups_1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
SPI_Pullups_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
SPI_Pullups_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
SPI_Pullups_1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
SPI_Pullups_1__PS EQU CYREG_PRT12_PS
SPI_Pullups_1__SHIFT EQU 0
SPI_Pullups_1__SIO_CFG EQU CYREG_PRT12_SIO_CFG
SPI_Pullups_1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
SPI_Pullups_1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
SPI_Pullups_1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
SPI_Pullups_1__SLW EQU CYREG_PRT12_SLW
SD_Data_Clk__PM_STBY_MSK EQU 0x02
/* timer_clock */
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1
timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2
timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
timer_clock__INDEX EQU 0x02
timer_clock__INDEX EQU 0x03
timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
timer_clock__PM_ACT_MSK EQU 0x04
timer_clock__PM_ACT_MSK EQU 0x08
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
timer_clock__PM_STBY_MSK EQU 0x04
timer_clock__PM_STBY_MSK EQU 0x08
/* SCSI_RST_ISR */
SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2596,8 +2826,6 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2605,58 +2833,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
/* SCSI_Glitch_Ctl */
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB14_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB14_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000

661
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
View File

@ -354,33 +354,101 @@ USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
; NOR_SI
NOR_SI__0__INTTYPE EQU CYREG_PICU3_INTTYPE6
NOR_SI__0__MASK EQU 0x40
NOR_SI__0__PC EQU CYREG_PRT3_PC6
NOR_SI__0__PORT EQU 3
NOR_SI__0__SHIFT EQU 6
NOR_SI__AG EQU CYREG_PRT3_AG
NOR_SI__AMUX EQU CYREG_PRT3_AMUX
NOR_SI__BIE EQU CYREG_PRT3_BIE
NOR_SI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
NOR_SI__BYP EQU CYREG_PRT3_BYP
NOR_SI__CTL EQU CYREG_PRT3_CTL
NOR_SI__DM0 EQU CYREG_PRT3_DM0
NOR_SI__DM1 EQU CYREG_PRT3_DM1
NOR_SI__DM2 EQU CYREG_PRT3_DM2
NOR_SI__DR EQU CYREG_PRT3_DR
NOR_SI__INP_DIS EQU CYREG_PRT3_INP_DIS
NOR_SI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
NOR_SI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
NOR_SI__LCD_EN EQU CYREG_PRT3_LCD_EN
NOR_SI__MASK EQU 0x40
NOR_SI__PORT EQU 3
NOR_SI__PRT EQU CYREG_PRT3_PRT
NOR_SI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
NOR_SI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
NOR_SI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
NOR_SI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
NOR_SI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
NOR_SI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
NOR_SI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
NOR_SI__PS EQU CYREG_PRT3_PS
NOR_SI__SHIFT EQU 6
NOR_SI__SLW EQU CYREG_PRT3_SLW
; NOR_SO
NOR_SO__0__INTTYPE EQU CYREG_PICU15_INTTYPE2
NOR_SO__0__MASK EQU 0x04
NOR_SO__0__PC EQU CYREG_IO_PC_PRT15_PC2
NOR_SO__0__PORT EQU 15
NOR_SO__0__SHIFT EQU 2
NOR_SO__AG EQU CYREG_PRT15_AG
NOR_SO__AMUX EQU CYREG_PRT15_AMUX
NOR_SO__BIE EQU CYREG_PRT15_BIE
NOR_SO__BIT_MASK EQU CYREG_PRT15_BIT_MASK
NOR_SO__BYP EQU CYREG_PRT15_BYP
NOR_SO__CTL EQU CYREG_PRT15_CTL
NOR_SO__DM0 EQU CYREG_PRT15_DM0
NOR_SO__DM1 EQU CYREG_PRT15_DM1
NOR_SO__DM2 EQU CYREG_PRT15_DM2
NOR_SO__DR EQU CYREG_PRT15_DR
NOR_SO__INP_DIS EQU CYREG_PRT15_INP_DIS
NOR_SO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
NOR_SO__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
NOR_SO__LCD_EN EQU CYREG_PRT15_LCD_EN
NOR_SO__MASK EQU 0x04
NOR_SO__PORT EQU 15
NOR_SO__PRT EQU CYREG_PRT15_PRT
NOR_SO__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
NOR_SO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
NOR_SO__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
NOR_SO__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
NOR_SO__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
NOR_SO__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
NOR_SO__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
NOR_SO__PS EQU CYREG_PRT15_PS
NOR_SO__SHIFT EQU 2
NOR_SO__SLW EQU CYREG_PRT15_SLW
; SDCard
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
@ -391,7 +459,11 @@ SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
@ -410,14 +482,12 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -425,9 +495,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST
; SD_SCK
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
@ -463,6 +533,137 @@ SD_SCK__PS EQU CYREG_PRT3_PS
SD_SCK__SHIFT EQU 1
SD_SCK__SLW EQU CYREG_PRT3_SLW
; NOR_CTL
NOR_CTL_Sync_ctrl_reg__0__MASK EQU 0x01
NOR_CTL_Sync_ctrl_reg__0__POS EQU 0
NOR_CTL_Sync_ctrl_reg__1__MASK EQU 0x02
NOR_CTL_Sync_ctrl_reg__1__POS EQU 1
NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
NOR_CTL_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB06_CTL
NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
NOR_CTL_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB06_CTL
NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
NOR_CTL_Sync_ctrl_reg__MASK EQU 0x03
NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
NOR_CTL_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB06_MSK
; NOR_SCK
NOR_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE7
NOR_SCK__0__MASK EQU 0x80
NOR_SCK__0__PC EQU CYREG_PRT3_PC7
NOR_SCK__0__PORT EQU 3
NOR_SCK__0__SHIFT EQU 7
NOR_SCK__AG EQU CYREG_PRT3_AG
NOR_SCK__AMUX EQU CYREG_PRT3_AMUX
NOR_SCK__BIE EQU CYREG_PRT3_BIE
NOR_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
NOR_SCK__BYP EQU CYREG_PRT3_BYP
NOR_SCK__CTL EQU CYREG_PRT3_CTL
NOR_SCK__DM0 EQU CYREG_PRT3_DM0
NOR_SCK__DM1 EQU CYREG_PRT3_DM1
NOR_SCK__DM2 EQU CYREG_PRT3_DM2
NOR_SCK__DR EQU CYREG_PRT3_DR
NOR_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
NOR_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
NOR_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
NOR_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
NOR_SCK__MASK EQU 0x80
NOR_SCK__PORT EQU 3
NOR_SCK__PRT EQU CYREG_PRT3_PRT
NOR_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
NOR_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
NOR_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
NOR_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
NOR_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
NOR_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
NOR_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
NOR_SCK__PS EQU CYREG_PRT3_PS
NOR_SCK__SHIFT EQU 7
NOR_SCK__SLW EQU CYREG_PRT3_SLW
; NOR_SPI
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL
NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL
NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK
NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20
NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5
NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40
NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6
NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70
NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0
NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1
NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0
NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1
NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1
NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01
NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0
NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02
NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04
NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2
NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08
NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3
NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F
NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
; SCSI_In
SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_In__0__MASK EQU 0x02
@ -1050,16 +1251,84 @@ TERM_EN__PS EQU CYREG_PRT15_PS
TERM_EN__SHIFT EQU 3
TERM_EN__SLW EQU CYREG_PRT15_SLW
; nNOR_CS
nNOR_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4
nNOR_CS__0__MASK EQU 0x10
nNOR_CS__0__PC EQU CYREG_PRT3_PC4
nNOR_CS__0__PORT EQU 3
nNOR_CS__0__SHIFT EQU 4
nNOR_CS__AG EQU CYREG_PRT3_AG
nNOR_CS__AMUX EQU CYREG_PRT3_AMUX
nNOR_CS__BIE EQU CYREG_PRT3_BIE
nNOR_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
nNOR_CS__BYP EQU CYREG_PRT3_BYP
nNOR_CS__CTL EQU CYREG_PRT3_CTL
nNOR_CS__DM0 EQU CYREG_PRT3_DM0
nNOR_CS__DM1 EQU CYREG_PRT3_DM1
nNOR_CS__DM2 EQU CYREG_PRT3_DM2
nNOR_CS__DR EQU CYREG_PRT3_DR
nNOR_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
nNOR_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
nNOR_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
nNOR_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
nNOR_CS__MASK EQU 0x10
nNOR_CS__PORT EQU 3
nNOR_CS__PRT EQU CYREG_PRT3_PRT
nNOR_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
nNOR_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
nNOR_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
nNOR_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
nNOR_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
nNOR_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
nNOR_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
nNOR_CS__PS EQU CYREG_PRT3_PS
nNOR_CS__SHIFT EQU 4
nNOR_CS__SLW EQU CYREG_PRT3_SLW
; nNOR_WP
nNOR_WP__0__INTTYPE EQU CYREG_PICU3_INTTYPE5
nNOR_WP__0__MASK EQU 0x20
nNOR_WP__0__PC EQU CYREG_PRT3_PC5
nNOR_WP__0__PORT EQU 3
nNOR_WP__0__SHIFT EQU 5
nNOR_WP__AG EQU CYREG_PRT3_AG
nNOR_WP__AMUX EQU CYREG_PRT3_AMUX
nNOR_WP__BIE EQU CYREG_PRT3_BIE
nNOR_WP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
nNOR_WP__BYP EQU CYREG_PRT3_BYP
nNOR_WP__CTL EQU CYREG_PRT3_CTL
nNOR_WP__DM0 EQU CYREG_PRT3_DM0
nNOR_WP__DM1 EQU CYREG_PRT3_DM1
nNOR_WP__DM2 EQU CYREG_PRT3_DM2
nNOR_WP__DR EQU CYREG_PRT3_DR
nNOR_WP__INP_DIS EQU CYREG_PRT3_INP_DIS
nNOR_WP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
nNOR_WP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
nNOR_WP__LCD_EN EQU CYREG_PRT3_LCD_EN
nNOR_WP__MASK EQU 0x20
nNOR_WP__PORT EQU 3
nNOR_WP__PRT EQU CYREG_PRT3_PRT
nNOR_WP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
nNOR_WP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
nNOR_WP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
nNOR_WP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
nNOR_WP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
nNOR_WP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
nNOR_WP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
nNOR_WP__PS EQU CYREG_PRT3_PS
nNOR_WP__SHIFT EQU 5
nNOR_WP__SLW EQU CYREG_PRT3_SLW
; SCSI_CLK
SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
SCSI_CLK__INDEX EQU 0x01
SCSI_CLK__INDEX EQU 0x02
SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
SCSI_CLK__PM_ACT_MSK EQU 0x02
SCSI_CLK__PM_ACT_MSK EQU 0x04
SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SCSI_CLK__PM_STBY_MSK EQU 0x02
SCSI_CLK__PM_STBY_MSK EQU 0x04
; SCSI_Out
SCSI_Out__0__AG EQU CYREG_PRT6_AG
@ -1514,15 +1783,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1535,35 +1804,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
@ -2011,6 +2280,17 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS
SCSI_Out_DBx__DB7__SHIFT EQU 5
SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW
; NOR_Clock
NOR_Clock__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
NOR_Clock__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
NOR_Clock__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
NOR_Clock__CFG2_SRC_SEL_MASK EQU 0x07
NOR_Clock__INDEX EQU 0x00
NOR_Clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
NOR_Clock__PM_ACT_MSK EQU 0x01
NOR_Clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
NOR_Clock__PM_STBY_MSK EQU 0x01
; SD_RX_DMA
SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
SD_RX_DMA__DRQ_NUMBER EQU 2
@ -2051,6 +2331,39 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; nNOR_HOLD
nNOR_HOLD__0__INTTYPE EQU CYREG_PICU12_INTTYPE1
nNOR_HOLD__0__MASK EQU 0x02
nNOR_HOLD__0__PC EQU CYREG_PRT12_PC1
nNOR_HOLD__0__PORT EQU 12
nNOR_HOLD__0__SHIFT EQU 1
nNOR_HOLD__AG EQU CYREG_PRT12_AG
nNOR_HOLD__BIE EQU CYREG_PRT12_BIE
nNOR_HOLD__BIT_MASK EQU CYREG_PRT12_BIT_MASK
nNOR_HOLD__BYP EQU CYREG_PRT12_BYP
nNOR_HOLD__DM0 EQU CYREG_PRT12_DM0
nNOR_HOLD__DM1 EQU CYREG_PRT12_DM1
nNOR_HOLD__DM2 EQU CYREG_PRT12_DM2
nNOR_HOLD__DR EQU CYREG_PRT12_DR
nNOR_HOLD__INP_DIS EQU CYREG_PRT12_INP_DIS
nNOR_HOLD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE
nNOR_HOLD__MASK EQU 0x02
nNOR_HOLD__PORT EQU 12
nNOR_HOLD__PRT EQU CYREG_PRT12_PRT
nNOR_HOLD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
nNOR_HOLD__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
nNOR_HOLD__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
nNOR_HOLD__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
nNOR_HOLD__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
nNOR_HOLD__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
nNOR_HOLD__PS EQU CYREG_PRT12_PS
nNOR_HOLD__SHIFT EQU 1
nNOR_HOLD__SIO_CFG EQU CYREG_PRT12_SIO_CFG
nNOR_HOLD__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
nNOR_HOLD__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
nNOR_HOLD__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
nNOR_HOLD__SLW EQU CYREG_PRT12_SLW
; SCSI_Noise
SCSI_Noise__0__AG EQU CYREG_PRT4_AG
SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX
@ -2383,6 +2696,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2390,13 +2705,13 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
; Debug_Timer
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2465,111 +2780,26 @@ SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SD_Data_Clk
SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
SD_Data_Clk__INDEX EQU 0x00
SD_Data_Clk__INDEX EQU 0x01
SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
SD_Data_Clk__PM_ACT_MSK EQU 0x01
SD_Data_Clk__PM_ACT_MSK EQU 0x02
SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SD_Data_Clk__PM_STBY_MSK EQU 0x01
; SPI_Pullups
SPI_Pullups__0__INTTYPE EQU CYREG_PICU3_INTTYPE4
SPI_Pullups__0__MASK EQU 0x10
SPI_Pullups__0__PC EQU CYREG_PRT3_PC4
SPI_Pullups__0__PORT EQU 3
SPI_Pullups__0__SHIFT EQU 4
SPI_Pullups__1__INTTYPE EQU CYREG_PICU3_INTTYPE5
SPI_Pullups__1__MASK EQU 0x20
SPI_Pullups__1__PC EQU CYREG_PRT3_PC5
SPI_Pullups__1__PORT EQU 3
SPI_Pullups__1__SHIFT EQU 5
SPI_Pullups__2__INTTYPE EQU CYREG_PICU3_INTTYPE6
SPI_Pullups__2__MASK EQU 0x40
SPI_Pullups__2__PC EQU CYREG_PRT3_PC6
SPI_Pullups__2__PORT EQU 3
SPI_Pullups__2__SHIFT EQU 6
SPI_Pullups__3__INTTYPE EQU CYREG_PICU3_INTTYPE7
SPI_Pullups__3__MASK EQU 0x80
SPI_Pullups__3__PC EQU CYREG_PRT3_PC7
SPI_Pullups__3__PORT EQU 3
SPI_Pullups__3__SHIFT EQU 7
SPI_Pullups__AG EQU CYREG_PRT3_AG
SPI_Pullups__AMUX EQU CYREG_PRT3_AMUX
SPI_Pullups__BIE EQU CYREG_PRT3_BIE
SPI_Pullups__BIT_MASK EQU CYREG_PRT3_BIT_MASK
SPI_Pullups__BYP EQU CYREG_PRT3_BYP
SPI_Pullups__CTL EQU CYREG_PRT3_CTL
SPI_Pullups__DM0 EQU CYREG_PRT3_DM0
SPI_Pullups__DM1 EQU CYREG_PRT3_DM1
SPI_Pullups__DM2 EQU CYREG_PRT3_DM2
SPI_Pullups__DR EQU CYREG_PRT3_DR
SPI_Pullups__INP_DIS EQU CYREG_PRT3_INP_DIS
SPI_Pullups__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
SPI_Pullups__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
SPI_Pullups__LCD_EN EQU CYREG_PRT3_LCD_EN
SPI_Pullups__MASK EQU 0xF0
SPI_Pullups__PORT EQU 3
SPI_Pullups__PRT EQU CYREG_PRT3_PRT
SPI_Pullups__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
SPI_Pullups__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
SPI_Pullups__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
SPI_Pullups__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
SPI_Pullups__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
SPI_Pullups__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
SPI_Pullups__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
SPI_Pullups__PS EQU CYREG_PRT3_PS
SPI_Pullups__SHIFT EQU 4
SPI_Pullups__SLW EQU CYREG_PRT3_SLW
SPI_Pullups_1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0
SPI_Pullups_1__0__MASK EQU 0x01
SPI_Pullups_1__0__PC EQU CYREG_PRT12_PC0
SPI_Pullups_1__0__PORT EQU 12
SPI_Pullups_1__0__SHIFT EQU 0
SPI_Pullups_1__1__INTTYPE EQU CYREG_PICU12_INTTYPE1
SPI_Pullups_1__1__MASK EQU 0x02
SPI_Pullups_1__1__PC EQU CYREG_PRT12_PC1
SPI_Pullups_1__1__PORT EQU 12
SPI_Pullups_1__1__SHIFT EQU 1
SPI_Pullups_1__AG EQU CYREG_PRT12_AG
SPI_Pullups_1__BIE EQU CYREG_PRT12_BIE
SPI_Pullups_1__BIT_MASK EQU CYREG_PRT12_BIT_MASK
SPI_Pullups_1__BYP EQU CYREG_PRT12_BYP
SPI_Pullups_1__DM0 EQU CYREG_PRT12_DM0
SPI_Pullups_1__DM1 EQU CYREG_PRT12_DM1
SPI_Pullups_1__DM2 EQU CYREG_PRT12_DM2
SPI_Pullups_1__DR EQU CYREG_PRT12_DR
SPI_Pullups_1__INP_DIS EQU CYREG_PRT12_INP_DIS
SPI_Pullups_1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE
SPI_Pullups_1__MASK EQU 0x03
SPI_Pullups_1__PORT EQU 12
SPI_Pullups_1__PRT EQU CYREG_PRT12_PRT
SPI_Pullups_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
SPI_Pullups_1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
SPI_Pullups_1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
SPI_Pullups_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
SPI_Pullups_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
SPI_Pullups_1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
SPI_Pullups_1__PS EQU CYREG_PRT12_PS
SPI_Pullups_1__SHIFT EQU 0
SPI_Pullups_1__SIO_CFG EQU CYREG_PRT12_SIO_CFG
SPI_Pullups_1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
SPI_Pullups_1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
SPI_Pullups_1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
SPI_Pullups_1__SLW EQU CYREG_PRT12_SLW
SD_Data_Clk__PM_STBY_MSK EQU 0x02
; timer_clock
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1
timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2
timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
timer_clock__INDEX EQU 0x02
timer_clock__INDEX EQU 0x03
timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
timer_clock__PM_ACT_MSK EQU 0x04
timer_clock__PM_ACT_MSK EQU 0x08
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
timer_clock__PM_STBY_MSK EQU 0x04
timer_clock__PM_STBY_MSK EQU 0x08
; SCSI_RST_ISR
SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2596,8 +2826,6 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2605,58 +2833,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
; SCSI_Glitch_Ctl
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB14_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB14_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000

226
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_CS.c Normal file
View File

@ -0,0 +1,226 @@
/*******************************************************************************
* File Name: nNOR_CS.c
* Version 2.20
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "nNOR_CS.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
nNOR_CS__PORT == 15 && ((nNOR_CS__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: nNOR_CS_Write
****************************************************************************//**
*
* \brief Writes the value to the physical port (data output register), masking
* and shifting the bits appropriately.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This function avoids changing
* other bits in the port by using the appropriate method (read-modify-write or
* bit banding).
*
* <b>Note</b> This function should not be used on a hardware digital output pin
* as it is driven by the hardware signal attached to it.
*
* \param value
* Value to write to the component instance.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic; the Interrupt
* Service Routines (ISR) can cause corruption of this function. An ISR that
* interrupts this function and performs writes to the Pins component data
* register can cause corrupted port data. To avoid this issue, you should
* either use the Per-Pin APIs (primary method) or disable interrupts around
* this function.
*
* \funcusage
* \snippet nNOR_CS_SUT.c usage_nNOR_CS_Write
*******************************************************************************/
void nNOR_CS_Write(uint8 value)
{
uint8 staticBits = (nNOR_CS_DR & (uint8)(~nNOR_CS_MASK));
nNOR_CS_DR = staticBits | ((uint8)(value << nNOR_CS_SHIFT) & nNOR_CS_MASK);
}
/*******************************************************************************
* Function Name: nNOR_CS_SetDriveMode
****************************************************************************//**
*
* \brief Sets the drive mode for each of the Pins component's pins.
*
* <b>Note</b> This affects all pins in the Pins component instance. Use the
* Per-Pin APIs if you wish to control individual pin's drive modes.
*
* \param mode
* Mode for the selected signals. Valid options are documented in
* \ref driveMode.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic, the ISR can
* cause corruption of this function. An ISR that interrupts this function
* and performs writes to the Pins component Drive Mode registers can cause
* corrupted port data. To avoid this issue, you should either use the Per-Pin
* APIs (primary method) or disable interrupts around this function.
*
* \funcusage
* \snippet nNOR_CS_SUT.c usage_nNOR_CS_SetDriveMode
*******************************************************************************/
void nNOR_CS_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(nNOR_CS_0, mode);
}
/*******************************************************************************
* Function Name: nNOR_CS_Read
****************************************************************************//**
*
* \brief Reads the associated physical port (pin status register) and masks
* the required bits according to the width and bit position of the component
* instance.
*
* The pin's status register returns the current logic level present on the
* physical pin.
*
* \return
* The current value for the pins in the component as a right justified number.
*
* \funcusage
* \snippet nNOR_CS_SUT.c usage_nNOR_CS_Read
*******************************************************************************/
uint8 nNOR_CS_Read(void)
{
return (nNOR_CS_PS & nNOR_CS_MASK) >> nNOR_CS_SHIFT;
}
/*******************************************************************************
* Function Name: nNOR_CS_ReadDataReg
****************************************************************************//**
*
* \brief Reads the associated physical port's data output register and masks
* the correct bits according to the width and bit position of the component
* instance.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This is not the same as the
* preferred nNOR_CS_Read() API because the
* nNOR_CS_ReadDataReg() reads the data register instead of the status
* register. For output pins this is a useful function to determine the value
* just written to the pin.
*
* \return
* The current value of the data register masked and shifted into a right
* justified number for the component instance.
*
* \funcusage
* \snippet nNOR_CS_SUT.c usage_nNOR_CS_ReadDataReg
*******************************************************************************/
uint8 nNOR_CS_ReadDataReg(void)
{
return (nNOR_CS_DR & nNOR_CS_MASK) >> nNOR_CS_SHIFT;
}
/* If interrupt is connected for this Pins component */
#if defined(nNOR_CS_INTSTAT)
/*******************************************************************************
* Function Name: nNOR_CS_SetInterruptMode
****************************************************************************//**
*
* \brief Configures the interrupt mode for each of the Pins component's
* pins. Alternatively you may set the interrupt mode for all the pins
* specified in the Pins component.
*
* <b>Note</b> The interrupt is port-wide and therefore any enabled pin
* interrupt may trigger it.
*
* \param position
* The pin position as listed in the Pins component. You may OR these to be
* able to configure the interrupt mode of multiple pins within a Pins
* component. Or you may use nNOR_CS_INTR_ALL to configure the
* interrupt mode of all the pins in the Pins component.
* - nNOR_CS_0_INTR (First pin in the list)
* - nNOR_CS_1_INTR (Second pin in the list)
* - ...
* - nNOR_CS_INTR_ALL (All pins in Pins component)
*
* \param mode
* Interrupt mode for the selected pins. Valid options are documented in
* \ref intrMode.
*
* \return
* None
*
* \sideeffect
* It is recommended that the interrupt be disabled before calling this
* function to avoid unintended interrupt requests. Note that the interrupt
* type is port wide, and therefore will trigger for any enabled pin on the
* port.
*
* \funcusage
* \snippet nNOR_CS_SUT.c usage_nNOR_CS_SetInterruptMode
*******************************************************************************/
void nNOR_CS_SetInterruptMode(uint16 position, uint16 mode)
{
if((position & nNOR_CS_0_INTR) != 0u)
{
nNOR_CS_0_INTTYPE_REG = (uint8)mode;
}
}
/*******************************************************************************
* Function Name: nNOR_CS_ClearInterrupt
****************************************************************************//**
*
* \brief Clears any active interrupts attached with the component and returns
* the value of the interrupt status register allowing determination of which
* pins generated an interrupt event.
*
* \return
* The right-shifted current value of the interrupt status register. Each pin
* has one bit set if it generated an interrupt event. For example, bit 0 is
* for pin 0 and bit 1 is for pin 1 of the Pins component.
*
* \sideeffect
* Clears all bits of the physical port's interrupt status register, not just
* those associated with the Pins component.
*
* \funcusage
* \snippet nNOR_CS_SUT.c usage_nNOR_CS_ClearInterrupt
*******************************************************************************/
uint8 nNOR_CS_ClearInterrupt(void)
{
return (nNOR_CS_INTSTAT & nNOR_CS_MASK) >> nNOR_CS_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

165
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_CS.h Normal file
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@ -0,0 +1,165 @@
/*******************************************************************************
* File Name: nNOR_CS.h
* Version 2.20
*
* Description:
* This file contains Pin function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_nNOR_CS_H) /* Pins nNOR_CS_H */
#define CY_PINS_nNOR_CS_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "nNOR_CS_aliases.h"
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
nNOR_CS__PORT == 15 && ((nNOR_CS__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_general
* @{
*/
void nNOR_CS_Write(uint8 value);
void nNOR_CS_SetDriveMode(uint8 mode);
uint8 nNOR_CS_ReadDataReg(void);
uint8 nNOR_CS_Read(void);
void nNOR_CS_SetInterruptMode(uint16 position, uint16 mode);
uint8 nNOR_CS_ClearInterrupt(void);
/** @} general */
/***************************************
* API Constants
***************************************/
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup driveMode Drive mode constants
* \brief Constants to be passed as "mode" parameter in the nNOR_CS_SetDriveMode() function.
* @{
*/
#define nNOR_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define nNOR_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define nNOR_CS_DM_RES_UP PIN_DM_RES_UP
#define nNOR_CS_DM_RES_DWN PIN_DM_RES_DWN
#define nNOR_CS_DM_OD_LO PIN_DM_OD_LO
#define nNOR_CS_DM_OD_HI PIN_DM_OD_HI
#define nNOR_CS_DM_STRONG PIN_DM_STRONG
#define nNOR_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN
/** @} driveMode */
/** @} group_constants */
/* Digital Port Constants */
#define nNOR_CS_MASK nNOR_CS__MASK
#define nNOR_CS_SHIFT nNOR_CS__SHIFT
#define nNOR_CS_WIDTH 1u
/* Interrupt constants */
#if defined(nNOR_CS__INTSTAT)
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup intrMode Interrupt constants
* \brief Constants to be passed as "mode" parameter in nNOR_CS_SetInterruptMode() function.
* @{
*/
#define nNOR_CS_INTR_NONE (uint16)(0x0000u)
#define nNOR_CS_INTR_RISING (uint16)(0x0001u)
#define nNOR_CS_INTR_FALLING (uint16)(0x0002u)
#define nNOR_CS_INTR_BOTH (uint16)(0x0003u)
/** @} intrMode */
/** @} group_constants */
#define nNOR_CS_INTR_MASK (0x01u)
#endif /* (nNOR_CS__INTSTAT) */
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define nNOR_CS_PS (* (reg8 *) nNOR_CS__PS)
/* Data Register */
#define nNOR_CS_DR (* (reg8 *) nNOR_CS__DR)
/* Port Number */
#define nNOR_CS_PRT_NUM (* (reg8 *) nNOR_CS__PRT)
/* Connect to Analog Globals */
#define nNOR_CS_AG (* (reg8 *) nNOR_CS__AG)
/* Analog MUX bux enable */
#define nNOR_CS_AMUX (* (reg8 *) nNOR_CS__AMUX)
/* Bidirectional Enable */
#define nNOR_CS_BIE (* (reg8 *) nNOR_CS__BIE)
/* Bit-mask for Aliased Register Access */
#define nNOR_CS_BIT_MASK (* (reg8 *) nNOR_CS__BIT_MASK)
/* Bypass Enable */
#define nNOR_CS_BYP (* (reg8 *) nNOR_CS__BYP)
/* Port wide control signals */
#define nNOR_CS_CTL (* (reg8 *) nNOR_CS__CTL)
/* Drive Modes */
#define nNOR_CS_DM0 (* (reg8 *) nNOR_CS__DM0)
#define nNOR_CS_DM1 (* (reg8 *) nNOR_CS__DM1)
#define nNOR_CS_DM2 (* (reg8 *) nNOR_CS__DM2)
/* Input Buffer Disable Override */
#define nNOR_CS_INP_DIS (* (reg8 *) nNOR_CS__INP_DIS)
/* LCD Common or Segment Drive */
#define nNOR_CS_LCD_COM_SEG (* (reg8 *) nNOR_CS__LCD_COM_SEG)
/* Enable Segment LCD */
#define nNOR_CS_LCD_EN (* (reg8 *) nNOR_CS__LCD_EN)
/* Slew Rate Control */
#define nNOR_CS_SLW (* (reg8 *) nNOR_CS__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define nNOR_CS_PRTDSI__CAPS_SEL (* (reg8 *) nNOR_CS__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define nNOR_CS_PRTDSI__DBL_SYNC_IN (* (reg8 *) nNOR_CS__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define nNOR_CS_PRTDSI__OE_SEL0 (* (reg8 *) nNOR_CS__PRTDSI__OE_SEL0)
#define nNOR_CS_PRTDSI__OE_SEL1 (* (reg8 *) nNOR_CS__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define nNOR_CS_PRTDSI__OUT_SEL0 (* (reg8 *) nNOR_CS__PRTDSI__OUT_SEL0)
#define nNOR_CS_PRTDSI__OUT_SEL1 (* (reg8 *) nNOR_CS__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define nNOR_CS_PRTDSI__SYNC_OUT (* (reg8 *) nNOR_CS__PRTDSI__SYNC_OUT)
/* SIO registers */
#if defined(nNOR_CS__SIO_CFG)
#define nNOR_CS_SIO_HYST_EN (* (reg8 *) nNOR_CS__SIO_HYST_EN)
#define nNOR_CS_SIO_REG_HIFREQ (* (reg8 *) nNOR_CS__SIO_REG_HIFREQ)
#define nNOR_CS_SIO_CFG (* (reg8 *) nNOR_CS__SIO_CFG)
#define nNOR_CS_SIO_DIFF (* (reg8 *) nNOR_CS__SIO_DIFF)
#endif /* (nNOR_CS__SIO_CFG) */
/* Interrupt Registers */
#if defined(nNOR_CS__INTSTAT)
#define nNOR_CS_INTSTAT (* (reg8 *) nNOR_CS__INTSTAT)
#define nNOR_CS_SNAP (* (reg8 *) nNOR_CS__SNAP)
#define nNOR_CS_0_INTTYPE_REG (* (reg8 *) nNOR_CS__0__INTTYPE)
#endif /* (nNOR_CS__INTSTAT) */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_nNOR_CS_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: nNOR_CS.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_nNOR_CS_ALIASES_H) /* Pins nNOR_CS_ALIASES_H */
#define CY_PINS_nNOR_CS_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define nNOR_CS_0 (nNOR_CS__0__PC)
#define nNOR_CS_0_INTR ((uint16)((uint16)0x0001u << nNOR_CS__0__SHIFT))
#define nNOR_CS_INTR_ALL ((uint16)(nNOR_CS_0_INTR))
#endif /* End Pins nNOR_CS_ALIASES_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: nNOR_HOLD.c
* Version 2.20
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "nNOR_HOLD.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
nNOR_HOLD__PORT == 15 && ((nNOR_HOLD__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: nNOR_HOLD_Write
****************************************************************************//**
*
* \brief Writes the value to the physical port (data output register), masking
* and shifting the bits appropriately.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This function avoids changing
* other bits in the port by using the appropriate method (read-modify-write or
* bit banding).
*
* <b>Note</b> This function should not be used on a hardware digital output pin
* as it is driven by the hardware signal attached to it.
*
* \param value
* Value to write to the component instance.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic; the Interrupt
* Service Routines (ISR) can cause corruption of this function. An ISR that
* interrupts this function and performs writes to the Pins component data
* register can cause corrupted port data. To avoid this issue, you should
* either use the Per-Pin APIs (primary method) or disable interrupts around
* this function.
*
* \funcusage
* \snippet nNOR_HOLD_SUT.c usage_nNOR_HOLD_Write
*******************************************************************************/
void nNOR_HOLD_Write(uint8 value)
{
uint8 staticBits = (nNOR_HOLD_DR & (uint8)(~nNOR_HOLD_MASK));
nNOR_HOLD_DR = staticBits | ((uint8)(value << nNOR_HOLD_SHIFT) & nNOR_HOLD_MASK);
}
/*******************************************************************************
* Function Name: nNOR_HOLD_SetDriveMode
****************************************************************************//**
*
* \brief Sets the drive mode for each of the Pins component's pins.
*
* <b>Note</b> This affects all pins in the Pins component instance. Use the
* Per-Pin APIs if you wish to control individual pin's drive modes.
*
* \param mode
* Mode for the selected signals. Valid options are documented in
* \ref driveMode.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic, the ISR can
* cause corruption of this function. An ISR that interrupts this function
* and performs writes to the Pins component Drive Mode registers can cause
* corrupted port data. To avoid this issue, you should either use the Per-Pin
* APIs (primary method) or disable interrupts around this function.
*
* \funcusage
* \snippet nNOR_HOLD_SUT.c usage_nNOR_HOLD_SetDriveMode
*******************************************************************************/
void nNOR_HOLD_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(nNOR_HOLD_0, mode);
}
/*******************************************************************************
* Function Name: nNOR_HOLD_Read
****************************************************************************//**
*
* \brief Reads the associated physical port (pin status register) and masks
* the required bits according to the width and bit position of the component
* instance.
*
* The pin's status register returns the current logic level present on the
* physical pin.
*
* \return
* The current value for the pins in the component as a right justified number.
*
* \funcusage
* \snippet nNOR_HOLD_SUT.c usage_nNOR_HOLD_Read
*******************************************************************************/
uint8 nNOR_HOLD_Read(void)
{
return (nNOR_HOLD_PS & nNOR_HOLD_MASK) >> nNOR_HOLD_SHIFT;
}
/*******************************************************************************
* Function Name: nNOR_HOLD_ReadDataReg
****************************************************************************//**
*
* \brief Reads the associated physical port's data output register and masks
* the correct bits according to the width and bit position of the component
* instance.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This is not the same as the
* preferred nNOR_HOLD_Read() API because the
* nNOR_HOLD_ReadDataReg() reads the data register instead of the status
* register. For output pins this is a useful function to determine the value
* just written to the pin.
*
* \return
* The current value of the data register masked and shifted into a right
* justified number for the component instance.
*
* \funcusage
* \snippet nNOR_HOLD_SUT.c usage_nNOR_HOLD_ReadDataReg
*******************************************************************************/
uint8 nNOR_HOLD_ReadDataReg(void)
{
return (nNOR_HOLD_DR & nNOR_HOLD_MASK) >> nNOR_HOLD_SHIFT;
}
/* If interrupt is connected for this Pins component */
#if defined(nNOR_HOLD_INTSTAT)
/*******************************************************************************
* Function Name: nNOR_HOLD_SetInterruptMode
****************************************************************************//**
*
* \brief Configures the interrupt mode for each of the Pins component's
* pins. Alternatively you may set the interrupt mode for all the pins
* specified in the Pins component.
*
* <b>Note</b> The interrupt is port-wide and therefore any enabled pin
* interrupt may trigger it.
*
* \param position
* The pin position as listed in the Pins component. You may OR these to be
* able to configure the interrupt mode of multiple pins within a Pins
* component. Or you may use nNOR_HOLD_INTR_ALL to configure the
* interrupt mode of all the pins in the Pins component.
* - nNOR_HOLD_0_INTR (First pin in the list)
* - nNOR_HOLD_1_INTR (Second pin in the list)
* - ...
* - nNOR_HOLD_INTR_ALL (All pins in Pins component)
*
* \param mode
* Interrupt mode for the selected pins. Valid options are documented in
* \ref intrMode.
*
* \return
* None
*
* \sideeffect
* It is recommended that the interrupt be disabled before calling this
* function to avoid unintended interrupt requests. Note that the interrupt
* type is port wide, and therefore will trigger for any enabled pin on the
* port.
*
* \funcusage
* \snippet nNOR_HOLD_SUT.c usage_nNOR_HOLD_SetInterruptMode
*******************************************************************************/
void nNOR_HOLD_SetInterruptMode(uint16 position, uint16 mode)
{
if((position & nNOR_HOLD_0_INTR) != 0u)
{
nNOR_HOLD_0_INTTYPE_REG = (uint8)mode;
}
}
/*******************************************************************************
* Function Name: nNOR_HOLD_ClearInterrupt
****************************************************************************//**
*
* \brief Clears any active interrupts attached with the component and returns
* the value of the interrupt status register allowing determination of which
* pins generated an interrupt event.
*
* \return
* The right-shifted current value of the interrupt status register. Each pin
* has one bit set if it generated an interrupt event. For example, bit 0 is
* for pin 0 and bit 1 is for pin 1 of the Pins component.
*
* \sideeffect
* Clears all bits of the physical port's interrupt status register, not just
* those associated with the Pins component.
*
* \funcusage
* \snippet nNOR_HOLD_SUT.c usage_nNOR_HOLD_ClearInterrupt
*******************************************************************************/
uint8 nNOR_HOLD_ClearInterrupt(void)
{
return (nNOR_HOLD_INTSTAT & nNOR_HOLD_MASK) >> nNOR_HOLD_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: nNOR_HOLD.h
* Version 2.20
*
* Description:
* This file contains Pin function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_nNOR_HOLD_H) /* Pins nNOR_HOLD_H */
#define CY_PINS_nNOR_HOLD_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "nNOR_HOLD_aliases.h"
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
nNOR_HOLD__PORT == 15 && ((nNOR_HOLD__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_general
* @{
*/
void nNOR_HOLD_Write(uint8 value);
void nNOR_HOLD_SetDriveMode(uint8 mode);
uint8 nNOR_HOLD_ReadDataReg(void);
uint8 nNOR_HOLD_Read(void);
void nNOR_HOLD_SetInterruptMode(uint16 position, uint16 mode);
uint8 nNOR_HOLD_ClearInterrupt(void);
/** @} general */
/***************************************
* API Constants
***************************************/
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup driveMode Drive mode constants
* \brief Constants to be passed as "mode" parameter in the nNOR_HOLD_SetDriveMode() function.
* @{
*/
#define nNOR_HOLD_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define nNOR_HOLD_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define nNOR_HOLD_DM_RES_UP PIN_DM_RES_UP
#define nNOR_HOLD_DM_RES_DWN PIN_DM_RES_DWN
#define nNOR_HOLD_DM_OD_LO PIN_DM_OD_LO
#define nNOR_HOLD_DM_OD_HI PIN_DM_OD_HI
#define nNOR_HOLD_DM_STRONG PIN_DM_STRONG
#define nNOR_HOLD_DM_RES_UPDWN PIN_DM_RES_UPDWN
/** @} driveMode */
/** @} group_constants */
/* Digital Port Constants */
#define nNOR_HOLD_MASK nNOR_HOLD__MASK
#define nNOR_HOLD_SHIFT nNOR_HOLD__SHIFT
#define nNOR_HOLD_WIDTH 1u
/* Interrupt constants */
#if defined(nNOR_HOLD__INTSTAT)
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup intrMode Interrupt constants
* \brief Constants to be passed as "mode" parameter in nNOR_HOLD_SetInterruptMode() function.
* @{
*/
#define nNOR_HOLD_INTR_NONE (uint16)(0x0000u)
#define nNOR_HOLD_INTR_RISING (uint16)(0x0001u)
#define nNOR_HOLD_INTR_FALLING (uint16)(0x0002u)
#define nNOR_HOLD_INTR_BOTH (uint16)(0x0003u)
/** @} intrMode */
/** @} group_constants */
#define nNOR_HOLD_INTR_MASK (0x01u)
#endif /* (nNOR_HOLD__INTSTAT) */
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define nNOR_HOLD_PS (* (reg8 *) nNOR_HOLD__PS)
/* Data Register */
#define nNOR_HOLD_DR (* (reg8 *) nNOR_HOLD__DR)
/* Port Number */
#define nNOR_HOLD_PRT_NUM (* (reg8 *) nNOR_HOLD__PRT)
/* Connect to Analog Globals */
#define nNOR_HOLD_AG (* (reg8 *) nNOR_HOLD__AG)
/* Analog MUX bux enable */
#define nNOR_HOLD_AMUX (* (reg8 *) nNOR_HOLD__AMUX)
/* Bidirectional Enable */
#define nNOR_HOLD_BIE (* (reg8 *) nNOR_HOLD__BIE)
/* Bit-mask for Aliased Register Access */
#define nNOR_HOLD_BIT_MASK (* (reg8 *) nNOR_HOLD__BIT_MASK)
/* Bypass Enable */
#define nNOR_HOLD_BYP (* (reg8 *) nNOR_HOLD__BYP)
/* Port wide control signals */
#define nNOR_HOLD_CTL (* (reg8 *) nNOR_HOLD__CTL)
/* Drive Modes */
#define nNOR_HOLD_DM0 (* (reg8 *) nNOR_HOLD__DM0)
#define nNOR_HOLD_DM1 (* (reg8 *) nNOR_HOLD__DM1)
#define nNOR_HOLD_DM2 (* (reg8 *) nNOR_HOLD__DM2)
/* Input Buffer Disable Override */
#define nNOR_HOLD_INP_DIS (* (reg8 *) nNOR_HOLD__INP_DIS)
/* LCD Common or Segment Drive */
#define nNOR_HOLD_LCD_COM_SEG (* (reg8 *) nNOR_HOLD__LCD_COM_SEG)
/* Enable Segment LCD */
#define nNOR_HOLD_LCD_EN (* (reg8 *) nNOR_HOLD__LCD_EN)
/* Slew Rate Control */
#define nNOR_HOLD_SLW (* (reg8 *) nNOR_HOLD__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define nNOR_HOLD_PRTDSI__CAPS_SEL (* (reg8 *) nNOR_HOLD__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define nNOR_HOLD_PRTDSI__DBL_SYNC_IN (* (reg8 *) nNOR_HOLD__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define nNOR_HOLD_PRTDSI__OE_SEL0 (* (reg8 *) nNOR_HOLD__PRTDSI__OE_SEL0)
#define nNOR_HOLD_PRTDSI__OE_SEL1 (* (reg8 *) nNOR_HOLD__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define nNOR_HOLD_PRTDSI__OUT_SEL0 (* (reg8 *) nNOR_HOLD__PRTDSI__OUT_SEL0)
#define nNOR_HOLD_PRTDSI__OUT_SEL1 (* (reg8 *) nNOR_HOLD__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define nNOR_HOLD_PRTDSI__SYNC_OUT (* (reg8 *) nNOR_HOLD__PRTDSI__SYNC_OUT)
/* SIO registers */
#if defined(nNOR_HOLD__SIO_CFG)
#define nNOR_HOLD_SIO_HYST_EN (* (reg8 *) nNOR_HOLD__SIO_HYST_EN)
#define nNOR_HOLD_SIO_REG_HIFREQ (* (reg8 *) nNOR_HOLD__SIO_REG_HIFREQ)
#define nNOR_HOLD_SIO_CFG (* (reg8 *) nNOR_HOLD__SIO_CFG)
#define nNOR_HOLD_SIO_DIFF (* (reg8 *) nNOR_HOLD__SIO_DIFF)
#endif /* (nNOR_HOLD__SIO_CFG) */
/* Interrupt Registers */
#if defined(nNOR_HOLD__INTSTAT)
#define nNOR_HOLD_INTSTAT (* (reg8 *) nNOR_HOLD__INTSTAT)
#define nNOR_HOLD_SNAP (* (reg8 *) nNOR_HOLD__SNAP)
#define nNOR_HOLD_0_INTTYPE_REG (* (reg8 *) nNOR_HOLD__0__INTTYPE)
#endif /* (nNOR_HOLD__INTSTAT) */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_nNOR_HOLD_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: nNOR_HOLD.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_nNOR_HOLD_ALIASES_H) /* Pins nNOR_HOLD_ALIASES_H */
#define CY_PINS_nNOR_HOLD_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define nNOR_HOLD_0 (nNOR_HOLD__0__PC)
#define nNOR_HOLD_0_INTR ((uint16)((uint16)0x0001u << nNOR_HOLD__0__SHIFT))
#define nNOR_HOLD_INTR_ALL ((uint16)(nNOR_HOLD_0_INTR))
#endif /* End Pins nNOR_HOLD_ALIASES_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: nNOR_WP.c
* Version 2.20
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "nNOR_WP.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
nNOR_WP__PORT == 15 && ((nNOR_WP__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: nNOR_WP_Write
****************************************************************************//**
*
* \brief Writes the value to the physical port (data output register), masking
* and shifting the bits appropriately.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This function avoids changing
* other bits in the port by using the appropriate method (read-modify-write or
* bit banding).
*
* <b>Note</b> This function should not be used on a hardware digital output pin
* as it is driven by the hardware signal attached to it.
*
* \param value
* Value to write to the component instance.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic; the Interrupt
* Service Routines (ISR) can cause corruption of this function. An ISR that
* interrupts this function and performs writes to the Pins component data
* register can cause corrupted port data. To avoid this issue, you should
* either use the Per-Pin APIs (primary method) or disable interrupts around
* this function.
*
* \funcusage
* \snippet nNOR_WP_SUT.c usage_nNOR_WP_Write
*******************************************************************************/
void nNOR_WP_Write(uint8 value)
{
uint8 staticBits = (nNOR_WP_DR & (uint8)(~nNOR_WP_MASK));
nNOR_WP_DR = staticBits | ((uint8)(value << nNOR_WP_SHIFT) & nNOR_WP_MASK);
}
/*******************************************************************************
* Function Name: nNOR_WP_SetDriveMode
****************************************************************************//**
*
* \brief Sets the drive mode for each of the Pins component's pins.
*
* <b>Note</b> This affects all pins in the Pins component instance. Use the
* Per-Pin APIs if you wish to control individual pin's drive modes.
*
* \param mode
* Mode for the selected signals. Valid options are documented in
* \ref driveMode.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic, the ISR can
* cause corruption of this function. An ISR that interrupts this function
* and performs writes to the Pins component Drive Mode registers can cause
* corrupted port data. To avoid this issue, you should either use the Per-Pin
* APIs (primary method) or disable interrupts around this function.
*
* \funcusage
* \snippet nNOR_WP_SUT.c usage_nNOR_WP_SetDriveMode
*******************************************************************************/
void nNOR_WP_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(nNOR_WP_0, mode);
}
/*******************************************************************************
* Function Name: nNOR_WP_Read
****************************************************************************//**
*
* \brief Reads the associated physical port (pin status register) and masks
* the required bits according to the width and bit position of the component
* instance.
*
* The pin's status register returns the current logic level present on the
* physical pin.
*
* \return
* The current value for the pins in the component as a right justified number.
*
* \funcusage
* \snippet nNOR_WP_SUT.c usage_nNOR_WP_Read
*******************************************************************************/
uint8 nNOR_WP_Read(void)
{
return (nNOR_WP_PS & nNOR_WP_MASK) >> nNOR_WP_SHIFT;
}
/*******************************************************************************
* Function Name: nNOR_WP_ReadDataReg
****************************************************************************//**
*
* \brief Reads the associated physical port's data output register and masks
* the correct bits according to the width and bit position of the component
* instance.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This is not the same as the
* preferred nNOR_WP_Read() API because the
* nNOR_WP_ReadDataReg() reads the data register instead of the status
* register. For output pins this is a useful function to determine the value
* just written to the pin.
*
* \return
* The current value of the data register masked and shifted into a right
* justified number for the component instance.
*
* \funcusage
* \snippet nNOR_WP_SUT.c usage_nNOR_WP_ReadDataReg
*******************************************************************************/
uint8 nNOR_WP_ReadDataReg(void)
{
return (nNOR_WP_DR & nNOR_WP_MASK) >> nNOR_WP_SHIFT;
}
/* If interrupt is connected for this Pins component */
#if defined(nNOR_WP_INTSTAT)
/*******************************************************************************
* Function Name: nNOR_WP_SetInterruptMode
****************************************************************************//**
*
* \brief Configures the interrupt mode for each of the Pins component's
* pins. Alternatively you may set the interrupt mode for all the pins
* specified in the Pins component.
*
* <b>Note</b> The interrupt is port-wide and therefore any enabled pin
* interrupt may trigger it.
*
* \param position
* The pin position as listed in the Pins component. You may OR these to be
* able to configure the interrupt mode of multiple pins within a Pins
* component. Or you may use nNOR_WP_INTR_ALL to configure the
* interrupt mode of all the pins in the Pins component.
* - nNOR_WP_0_INTR (First pin in the list)
* - nNOR_WP_1_INTR (Second pin in the list)
* - ...
* - nNOR_WP_INTR_ALL (All pins in Pins component)
*
* \param mode
* Interrupt mode for the selected pins. Valid options are documented in
* \ref intrMode.
*
* \return
* None
*
* \sideeffect
* It is recommended that the interrupt be disabled before calling this
* function to avoid unintended interrupt requests. Note that the interrupt
* type is port wide, and therefore will trigger for any enabled pin on the
* port.
*
* \funcusage
* \snippet nNOR_WP_SUT.c usage_nNOR_WP_SetInterruptMode
*******************************************************************************/
void nNOR_WP_SetInterruptMode(uint16 position, uint16 mode)
{
if((position & nNOR_WP_0_INTR) != 0u)
{
nNOR_WP_0_INTTYPE_REG = (uint8)mode;
}
}
/*******************************************************************************
* Function Name: nNOR_WP_ClearInterrupt
****************************************************************************//**
*
* \brief Clears any active interrupts attached with the component and returns
* the value of the interrupt status register allowing determination of which
* pins generated an interrupt event.
*
* \return
* The right-shifted current value of the interrupt status register. Each pin
* has one bit set if it generated an interrupt event. For example, bit 0 is
* for pin 0 and bit 1 is for pin 1 of the Pins component.
*
* \sideeffect
* Clears all bits of the physical port's interrupt status register, not just
* those associated with the Pins component.
*
* \funcusage
* \snippet nNOR_WP_SUT.c usage_nNOR_WP_ClearInterrupt
*******************************************************************************/
uint8 nNOR_WP_ClearInterrupt(void)
{
return (nNOR_WP_INTSTAT & nNOR_WP_MASK) >> nNOR_WP_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

165
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_WP.h Normal file
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@ -0,0 +1,165 @@
/*******************************************************************************
* File Name: nNOR_WP.h
* Version 2.20
*
* Description:
* This file contains Pin function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_nNOR_WP_H) /* Pins nNOR_WP_H */
#define CY_PINS_nNOR_WP_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "nNOR_WP_aliases.h"
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
nNOR_WP__PORT == 15 && ((nNOR_WP__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_general
* @{
*/
void nNOR_WP_Write(uint8 value);
void nNOR_WP_SetDriveMode(uint8 mode);
uint8 nNOR_WP_ReadDataReg(void);
uint8 nNOR_WP_Read(void);
void nNOR_WP_SetInterruptMode(uint16 position, uint16 mode);
uint8 nNOR_WP_ClearInterrupt(void);
/** @} general */
/***************************************
* API Constants
***************************************/
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup driveMode Drive mode constants
* \brief Constants to be passed as "mode" parameter in the nNOR_WP_SetDriveMode() function.
* @{
*/
#define nNOR_WP_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define nNOR_WP_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define nNOR_WP_DM_RES_UP PIN_DM_RES_UP
#define nNOR_WP_DM_RES_DWN PIN_DM_RES_DWN
#define nNOR_WP_DM_OD_LO PIN_DM_OD_LO
#define nNOR_WP_DM_OD_HI PIN_DM_OD_HI
#define nNOR_WP_DM_STRONG PIN_DM_STRONG
#define nNOR_WP_DM_RES_UPDWN PIN_DM_RES_UPDWN
/** @} driveMode */
/** @} group_constants */
/* Digital Port Constants */
#define nNOR_WP_MASK nNOR_WP__MASK
#define nNOR_WP_SHIFT nNOR_WP__SHIFT
#define nNOR_WP_WIDTH 1u
/* Interrupt constants */
#if defined(nNOR_WP__INTSTAT)
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup intrMode Interrupt constants
* \brief Constants to be passed as "mode" parameter in nNOR_WP_SetInterruptMode() function.
* @{
*/
#define nNOR_WP_INTR_NONE (uint16)(0x0000u)
#define nNOR_WP_INTR_RISING (uint16)(0x0001u)
#define nNOR_WP_INTR_FALLING (uint16)(0x0002u)
#define nNOR_WP_INTR_BOTH (uint16)(0x0003u)
/** @} intrMode */
/** @} group_constants */
#define nNOR_WP_INTR_MASK (0x01u)
#endif /* (nNOR_WP__INTSTAT) */
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define nNOR_WP_PS (* (reg8 *) nNOR_WP__PS)
/* Data Register */
#define nNOR_WP_DR (* (reg8 *) nNOR_WP__DR)
/* Port Number */
#define nNOR_WP_PRT_NUM (* (reg8 *) nNOR_WP__PRT)
/* Connect to Analog Globals */
#define nNOR_WP_AG (* (reg8 *) nNOR_WP__AG)
/* Analog MUX bux enable */
#define nNOR_WP_AMUX (* (reg8 *) nNOR_WP__AMUX)
/* Bidirectional Enable */
#define nNOR_WP_BIE (* (reg8 *) nNOR_WP__BIE)
/* Bit-mask for Aliased Register Access */
#define nNOR_WP_BIT_MASK (* (reg8 *) nNOR_WP__BIT_MASK)
/* Bypass Enable */
#define nNOR_WP_BYP (* (reg8 *) nNOR_WP__BYP)
/* Port wide control signals */
#define nNOR_WP_CTL (* (reg8 *) nNOR_WP__CTL)
/* Drive Modes */
#define nNOR_WP_DM0 (* (reg8 *) nNOR_WP__DM0)
#define nNOR_WP_DM1 (* (reg8 *) nNOR_WP__DM1)
#define nNOR_WP_DM2 (* (reg8 *) nNOR_WP__DM2)
/* Input Buffer Disable Override */
#define nNOR_WP_INP_DIS (* (reg8 *) nNOR_WP__INP_DIS)
/* LCD Common or Segment Drive */
#define nNOR_WP_LCD_COM_SEG (* (reg8 *) nNOR_WP__LCD_COM_SEG)
/* Enable Segment LCD */
#define nNOR_WP_LCD_EN (* (reg8 *) nNOR_WP__LCD_EN)
/* Slew Rate Control */
#define nNOR_WP_SLW (* (reg8 *) nNOR_WP__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define nNOR_WP_PRTDSI__CAPS_SEL (* (reg8 *) nNOR_WP__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define nNOR_WP_PRTDSI__DBL_SYNC_IN (* (reg8 *) nNOR_WP__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define nNOR_WP_PRTDSI__OE_SEL0 (* (reg8 *) nNOR_WP__PRTDSI__OE_SEL0)
#define nNOR_WP_PRTDSI__OE_SEL1 (* (reg8 *) nNOR_WP__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define nNOR_WP_PRTDSI__OUT_SEL0 (* (reg8 *) nNOR_WP__PRTDSI__OUT_SEL0)
#define nNOR_WP_PRTDSI__OUT_SEL1 (* (reg8 *) nNOR_WP__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define nNOR_WP_PRTDSI__SYNC_OUT (* (reg8 *) nNOR_WP__PRTDSI__SYNC_OUT)
/* SIO registers */
#if defined(nNOR_WP__SIO_CFG)
#define nNOR_WP_SIO_HYST_EN (* (reg8 *) nNOR_WP__SIO_HYST_EN)
#define nNOR_WP_SIO_REG_HIFREQ (* (reg8 *) nNOR_WP__SIO_REG_HIFREQ)
#define nNOR_WP_SIO_CFG (* (reg8 *) nNOR_WP__SIO_CFG)
#define nNOR_WP_SIO_DIFF (* (reg8 *) nNOR_WP__SIO_DIFF)
#endif /* (nNOR_WP__SIO_CFG) */
/* Interrupt Registers */
#if defined(nNOR_WP__INTSTAT)
#define nNOR_WP_INTSTAT (* (reg8 *) nNOR_WP__INTSTAT)
#define nNOR_WP_SNAP (* (reg8 *) nNOR_WP__SNAP)
#define nNOR_WP_0_INTTYPE_REG (* (reg8 *) nNOR_WP__0__INTTYPE)
#endif /* (nNOR_WP__INTSTAT) */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_nNOR_WP_H */
/* [] END OF FILE */

36
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_WP_aliases.h Normal file
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@ -0,0 +1,36 @@
/*******************************************************************************
* File Name: nNOR_WP.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_nNOR_WP_ALIASES_H) /* Pins nNOR_WP_ALIASES_H */
#define CY_PINS_nNOR_WP_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define nNOR_WP_0 (nNOR_WP__0__PC)
#define nNOR_WP_0_INTR ((uint16)((uint16)0x0001u << nNOR_WP__0__SHIFT))
#define nNOR_WP_INTR_ALL ((uint16)(nNOR_WP_0_INTR))
#endif /* End Pins nNOR_WP_ALIASES_H */
/* [] END OF FILE */

20
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
View File

@ -70,10 +70,22 @@
#include "SCSI_Glitch_Ctl.h"
#include "TERM_EN_aliases.h"
#include "TERM_EN.h"
#include "SPI_Pullups_aliases.h"
#include "SPI_Pullups.h"
#include "SPI_Pullups_1_aliases.h"
#include "SPI_Pullups_1.h"
#include "NOR_Clock.h"
#include "NOR_SO_aliases.h"
#include "NOR_SO.h"
#include "NOR_SPI.h"
#include "NOR_SPI_PVT.h"
#include "NOR_SCK_aliases.h"
#include "NOR_SCK.h"
#include "nNOR_HOLD_aliases.h"
#include "nNOR_HOLD.h"
#include "NOR_SI_aliases.h"
#include "NOR_SI.h"
#include "NOR_CTL.h"
#include "nNOR_CS_aliases.h"
#include "nNOR_CS.h"
#include "nNOR_WP_aliases.h"
#include "nNOR_WP.h"
#include "USBFS_Dm_aliases.h"
#include "USBFS_Dm.h"
#include "USBFS_Dp_aliases.h"

307
software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx
View File

@ -1,49 +1,20 @@
<?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x40006467" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x40006487" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006497" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
<field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt" hidden="false">
<value name="ENABLED" value="1" desc="Interrupt enabled" />
<value name="DISABLED" value="0" desc="Interrupt disabled" />
</field>
<field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level" hidden="false">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level" hidden="false">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear" hidden="false">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
<field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear" hidden="false">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
</register>
</block>
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" hidden="false" />
</block>
<block name="TERM_EN" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646E" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x4000648E" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649E" bitWidth="8" desc="" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
@ -70,122 +41,93 @@
</field>
</register>
</block>
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SPI_Pullups" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SPI_Pullups_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x4000646F" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x4000648F" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649F" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
<field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt" hidden="false">
<value name="ENABLED" value="1" desc="Interrupt enabled" />
<value name="DISABLED" value="0" desc="Interrupt disabled" />
</field>
<field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level" hidden="false">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level" hidden="false">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear" hidden="false">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
<field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear" hidden="false">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
</register>
</block>
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="TERM_EN" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647F" bitWidth="8" desc="" hidden="false" />
<block name="NOR_SI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_CTL" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="NOR_CTL_CONTROL_REG" address="0x40006576" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">
<field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." hidden="false" />
</register>
<register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">
<field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." hidden="false" />
<field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)" hidden="false">
<value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
<value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
</field>
<field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." hidden="false" />
<field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." hidden="false" />
<field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" hidden="false" />
<field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively." hidden="false">
<value name="Timer" value="0" desc="CMP and TC are output." />
<value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
</field>
<field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" hidden="false" />
</register>
<register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">
<field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" hidden="false" />
<field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled." hidden="false">
<value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
<value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
</field>
<field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." hidden="false" />
<field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." hidden="false" />
<field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." hidden="false" />
<field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." hidden="false" />
</register>
<register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">
<field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ" hidden="false">
<value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
<value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
<value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
<value name="Irq" value="11" desc="Timer runs until IRQ." />
</field>
<field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." hidden="false" />
<field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" hidden="false" />
<field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations" hidden="false">
<value name="Equal" value="0" desc="Compare Equal " />
<value name="Less than" value="1" desc="Compare Less Than " />
<value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
<value name="Greater" value="11" desc="Compare Greater Than ." />
<value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
</field>
<field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." hidden="false" />
</register>
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
</block>
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006476" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" hidden="false" />
</block>
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="NOR_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="nNOR_HOLD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="nNOR_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="nNOR_WP" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_SO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_SPI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
</block>
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_Clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">
<block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -1044,4 +986,77 @@
<field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />
</register>
</block>
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
</block>
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />
</block>
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">
<field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." hidden="false" />
</register>
<register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">
<field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." hidden="false" />
<field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)" hidden="false">
<value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
<value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
</field>
<field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." hidden="false" />
<field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." hidden="false" />
<field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" hidden="false" />
<field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively." hidden="false">
<value name="Timer" value="0" desc="CMP and TC are output." />
<value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
</field>
<field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" hidden="false" />
</register>
<register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">
<field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" hidden="false" />
<field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled." hidden="false">
<value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
<value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
</field>
<field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." hidden="false" />
<field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." hidden="false" />
<field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." hidden="false" />
<field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." hidden="false" />
</register>
<register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">
<field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ" hidden="false">
<value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
<value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
<value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
<value name="Irq" value="11" desc="Timer runs until IRQ." />
</field>
<field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." hidden="false" />
<field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" hidden="false" />
<field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations" hidden="false">
<value name="Equal" value="0" desc="Compare Equal " />
<value name="Less than" value="1" desc="Compare Less Than " />
<value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
<value name="Greater" value="11" desc="Compare Greater Than ." />
<value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
</field>
<field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." hidden="false" />
</register>
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
</block>
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006479" bitWidth="8" desc="" hidden="false" />
</block>
</blockRegMap>

34
software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cydwr
View File

@ -529,26 +529,31 @@
<Data key="1cbdffd4-eb85-452b-a8d5-fc63f832ad14" value="SCSI_RST" />
<Data key="4c15b41e-e284-4978-99e7-5aaee19bd0ce" value="SCSI_In_DBx" />
<Data key="5c1decb5-69e3-4a8d-bb0c-281221d15217" value="EXTLED" />
<Data key="8d318d8b-cf7b-4b6b-b02c-ab1c5c49d0ba" value="SPI_Pullups" />
<Data key="8d318d8b-cf7b-4b6b-b02c-ab1c5c49d0ba" value="NOR_SO" />
<Data key="11f071e8-9c92-47e0-872a-3f48765a75b8" value="SCSI_Out" />
<Data key="017bcc29-b1c3-4236-8d12-9482d3052409" value="SD_DAT2" />
<Data key="32f0aa9d-67c0-4e16-af15-f38ab16ecd75" value="SD_SCK" />
<Data key="52b56294-36b1-4f21-a98a-a7ce3de7f759" value="LED1" />
<Data key="52f31aa9-2f0a-497d-9a1f-1424095e13e6" value="SCSI_Out_DBx" />
<Data key="0953ba78-d08c-41cc-a5ba-a28ac6cf9ee6" value="SCSI_Noise" />
<Data key="1030e8e7-8e88-44ed-a03e-e5d56d4d7cfa" value="nNOR_CS" />
<Data key="159485ba-54a3-4125-8cfd-7e9d322656f5" value="EXTLED" />
<Data key="791071b3-a348-49c4-b578-64e66d701d0f/8b77a6c4-10a0-4390-971c-672353e2a49c" value="USBFS_Dm" />
<Data key="791071b3-a348-49c4-b578-64e66d701d0f/618a72fc-5ddd-4df5-958f-a3d55102db42" value="USBFS_Dp" />
<Data key="46848116-0f25-4b2a-8a9b-0d82783567cf" value="SPI_Pullups_1" />
<Data key="58466791-1a1b-4bf3-b8be-6107fa736756" value="NOR_SCK" />
<Data key="b5c06f19-4f88-40c3-af2b-cc20274db75a" value="SCSI_ID" />
<Data key="b09bcec5-301d-4f99-8875-4a704887e5b5" value="SD_WP" />
<Data key="b5255b72-3857-4b85-b455-d625a7fbd978" value="SD_MOSI" />
<Data key="b5324e10-5947-4eb7-9e5c-75dae671b6dc" value="SD_CD" />
<Data key="b8883755-657f-4f1f-9738-05dd936fb235" value="NOR_SI" />
<Data key="ba1e380f-c607-4906-96ae-bbe0f65227f0" value="SD_CS" />
<Data key="bc0102aa-f4d9-4793-b77a-8c3463edcafa" value="SCSI_In" />
<Data key="d222211b-a7f8-4948-bad6-d454b04ae84d" value="SD_DAT1" />
<Data key="d0457095-d736-4233-a1cd-0a3e62241836" value="nNOR_WP" />
<Data key="dd079500-ec14-46f6-83ef-ae112d8e7382" value="SCSI_ATN" />
<Data key="dfd0c8d1-a94a-4944-ad7d-8d06060d1de8" value="PARITY_EN" />
<Data key="e7d70154-7612-45c2-a360-1b255f3e9e11" value="nNOR_HOLD" />
<Data key="e851a3b9-efb8-48be-bbb8-b303b216c393" value="TERM_EN" />
</Group>
</Group>
@ -3688,7 +3693,7 @@
</Group>
<Group key="8d318d8b-cf7b-4b6b-b02c-ab1c5c49d0ba">
<Group key="0">
<Data key="Port Format" value="3,4" />
<Data key="Port Format" value="15,2" />
</Group>
<Group key="1">
<Data key="Port Format" value="3,5" />
@ -3793,6 +3798,11 @@
<Data key="Port Format" value="4,3" />
</Group>
</Group>
<Group key="1030e8e7-8e88-44ed-a03e-e5d56d4d7cfa">
<Group key="0">
<Data key="Port Format" value="3,4" />
</Group>
</Group>
<Group key="159485ba-54a3-4125-8cfd-7e9d322656f5">
<Group key="0">
<Data key="Port Format" value="0,0" />
@ -3816,6 +3826,11 @@
<Data key="Port Format" value="12,1" />
</Group>
</Group>
<Group key="58466791-1a1b-4bf3-b8be-6107fa736756">
<Group key="0">
<Data key="Port Format" value="3,7" />
</Group>
</Group>
<Group key="b5c06f19-4f88-40c3-af2b-cc20274db75a">
<Group key="0">
<Data key="Port Format" value="5,7" />
@ -3837,6 +3852,11 @@
<Data key="Port Format" value="3,2" />
</Group>
</Group>
<Group key="b8883755-657f-4f1f-9738-05dd936fb235">
<Group key="0">
<Data key="Port Format" value="3,6" />
</Group>
</Group>
<Group key="ba1e380f-c607-4906-96ae-bbe0f65227f0">
<Group key="0">
<Data key="Port Format" value="3,3" />
@ -3879,6 +3899,11 @@
<Data key="Port Format" value="3,0" />
</Group>
</Group>
<Group key="d0457095-d736-4233-a1cd-0a3e62241836">
<Group key="0">
<Data key="Port Format" value="3,5" />
</Group>
</Group>
<Group key="dd079500-ec14-46f6-83ef-ae112d8e7382">
<Group key="0">
<Data key="Port Format" value="2,0" />
@ -3889,6 +3914,11 @@
<Data key="Port Format" value="5,4" />
</Group>
</Group>
<Group key="e7d70154-7612-45c2-a360-1b255f3e9e11">
<Group key="0">
<Data key="Port Format" value="12,1" />
</Group>
</Group>
<Group key="e851a3b9-efb8-48be-bbb8-b303b216c393">
<Group key="0">
<Data key="Port Format" value="15,3" />

BIN
software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit
View File

Binary file not shown.

318
software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj
View File

@ -2232,27 +2232,27 @@
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