CIIN fix
This commit is contained in:
parent
59ffe6bf85
commit
1d57288caf
6
paste.sv
6
paste.sv
|
@ -25,7 +25,7 @@ module paste (
|
||||||
input wire cpuRnW, // 68030 Read/Write signal
|
input wire cpuRnW, // 68030 Read/Write signal
|
||||||
input wire ncpuBG, // 68030 Bus Grant signal
|
input wire ncpuBG, // 68030 Bus Grant signal
|
||||||
inout wire ncpuBerr, // 68030 Bus Error signal
|
inout wire ncpuBerr, // 68030 Bus Error signal
|
||||||
inout wire ncpuCiin, // 68030 Cache Enable In signal
|
inout wire ncpuCiin, // 68030 Cache Inhibit signal
|
||||||
input wire npdsReset, // PDS Reset signal
|
input wire npdsReset, // PDS Reset signal
|
||||||
inout wire npdsLds, // PDS Lower Data Strobe signal
|
inout wire npdsLds, // PDS Lower Data Strobe signal
|
||||||
inout wire npdsUds, // PDS Upper Data Strobe signal
|
inout wire npdsUds, // PDS Upper Data Strobe signal
|
||||||
|
@ -358,8 +358,8 @@ always_comb begin
|
||||||
ncpuBerr <= 1'bz;
|
ncpuBerr <= 1'bz;
|
||||||
end
|
end
|
||||||
|
|
||||||
//ncpuCiin
|
// CPU cache inhibit
|
||||||
if(cpuAddrHi < 4'h6) begin
|
if(cpuAddrHi >= 4'h6) begin
|
||||||
ncpuCiin <= 1'b0;
|
ncpuCiin <= 1'b0;
|
||||||
end else begin
|
end else begin
|
||||||
ncpuCiin <= 1'bz;
|
ncpuCiin <= 1'bz;
|
||||||
|
|
Loading…
Reference in New Issue