Syntax fixes, added CIIN
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5be40df484
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59ffe6bf85
81
paste.sv
81
paste.sv
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@ -8,7 +8,7 @@
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* well as additional logic for interfacing with the 68882 FPU.
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* well as additional logic for interfacing with the 68882 FPU.
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*****************************************************************************/
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*****************************************************************************/
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module paste {
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module paste (
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inout wire ncpuReset, // 68030 reset signal (tristate)
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inout wire ncpuReset, // 68030 reset signal (tristate)
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inout wire ncpuHalt, // 68030 halt signal (tristate)
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inout wire ncpuHalt, // 68030 halt signal (tristate)
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input wire ncpuDS, // 68030 data strobe signal
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input wire ncpuDS, // 68030 data strobe signal
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@ -25,6 +25,7 @@ module paste {
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input wire cpuRnW, // 68030 Read/Write signal
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input wire cpuRnW, // 68030 Read/Write signal
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input wire ncpuBG, // 68030 Bus Grant signal
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input wire ncpuBG, // 68030 Bus Grant signal
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inout wire ncpuBerr, // 68030 Bus Error signal
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inout wire ncpuBerr, // 68030 Bus Error signal
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inout wire ncpuCiin, // 68030 Cache Enable In signal
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input wire npdsReset, // PDS Reset signal
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input wire npdsReset, // PDS Reset signal
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inout wire npdsLds, // PDS Lower Data Strobe signal
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inout wire npdsLds, // PDS Lower Data Strobe signal
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inout wire npdsUds, // PDS Upper Data Strobe signal
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inout wire npdsUds, // PDS Upper Data Strobe signal
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@ -44,7 +45,7 @@ module paste {
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output wire nbufAEn, // Address buffer enable
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output wire nbufAEn, // Address buffer enable
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input wire nfpuSense, // FPU Presence Detect signal
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input wire nfpuSense, // FPU Presence Detect signal
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output wire nfpuCe // FPU Chip Select signal
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output wire nfpuCe // FPU Chip Select signal
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};
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);
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// define state machine states
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// define state machine states
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parameter
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parameter
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@ -79,7 +80,7 @@ always @(posedge pdsC8m or negedge npdsReset) begin
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// marked by assertion of npdsVpa and pdsClockE
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// marked by assertion of npdsVpa and pdsClockE
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if (npdsVpa == 1'b0 && pdsClockE == 1'b1) begin
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if (npdsVpa == 1'b0 && pdsClockE == 1'b1) begin
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vmagenState <= S1;
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vmagenState <= S1;
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else
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end else begin
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vmagenState <= S0;
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vmagenState <= S0;
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end
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end
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vmagenCount <= 4'h0;
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vmagenCount <= 4'h0;
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@ -88,7 +89,7 @@ always @(posedge pdsC8m or negedge npdsReset) begin
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// wait for deassertion of pdsClockE
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// wait for deassertion of pdsClockE
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if (pdsClockE == 1'b0) begin
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if (pdsClockE == 1'b0) begin
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vmagenState <= S2;
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vmagenState <= S2;
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else
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end else begin
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vmagenState <= S1;
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vmagenState <= S1;
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end
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end
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vmagenCount <= 4'h0;
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vmagenCount <= 4'h0;
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@ -98,7 +99,7 @@ always @(posedge pdsC8m or negedge npdsReset) begin
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if (vmagenCount == 4'hA) begin
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if (vmagenCount == 4'hA) begin
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vmagenState <= S0;
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vmagenState <= S0;
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vmagenCount <= 4'h0;
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vmagenCount <= 4'h0;
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else
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end else begin
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vmagenState <= S2;
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vmagenState <= S2;
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vmagenCount <= vmagenCount + 1'b1;
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vmagenCount <= vmagenCount + 1'b1;
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end
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end
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@ -123,7 +124,7 @@ always @(posedge cpuClock or negedge npdsReset) begin
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// wait for vmagenCount == 4'hA
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// wait for vmagenCount == 4'hA
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if (vmagenCount == 4'hA) begin
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if (vmagenCount == 4'hA) begin
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dsack68genState <= S1;
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dsack68genState <= S1;
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else
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end else begin
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dsack68genState <= S0;
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dsack68genState <= S0;
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end
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end
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end
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end
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@ -135,7 +136,7 @@ always @(posedge cpuClock or negedge npdsReset) begin
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// wait for vmagenCount to reset to 0
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// wait for vmagenCount to reset to 0
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if (vmagenCount == 4'h0) begin
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if (vmagenCount == 4'h0) begin
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dsack68genState <= S0;
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dsack68genState <= S0;
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else
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end else begin
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dsack68genState <= S2;
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dsack68genState <= S2;
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end
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end
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end
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end
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@ -158,7 +159,7 @@ always @(posedge cpuClock or negedge npdsReset) begin
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// wait for assertion of npdsDtack
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// wait for assertion of npdsDtack
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if(npdsDtack == 1'b0) begin
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if(npdsDtack == 1'b0) begin
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dsackSEgenState <= S1;
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dsackSEgenState <= S1;
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else
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end else begin
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dsackSEgenState <= S0;
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dsackSEgenState <= S0;
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end
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end
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end
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end
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@ -170,7 +171,7 @@ always @(posedge cpuClock or negedge npdsReset) begin
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// wait for deassertion of npdsDtack
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// wait for deassertion of npdsDtack
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if (npdsDtack == 1'b1) begin
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if (npdsDtack == 1'b1) begin
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dsackSEgenState <= S0;
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dsackSEgenState <= S0;
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else
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end else begin
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dsackSEgenState <= S2;
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dsackSEgenState <= S2;
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end
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end
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end
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end
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@ -183,7 +184,7 @@ always @(posedge cpuClock or negedge npdsReset) begin
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end
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end
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// state machine for power on reset
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// state machine for power on reset
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alwasy @(posedge cpuClock or negedge npdsReset) begin
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always @(posedge cpuClock or negedge npdsReset) begin
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// sync state machine clocked by primary CPU clock with async reset
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// sync state machine clocked by primary CPU clock with async reset
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if(npdsReset == 1'b0) begin
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if(npdsReset == 1'b0) begin
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resetgenState <= S0;
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resetgenState <= S0;
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@ -193,7 +194,7 @@ alwasy @(posedge cpuClock or negedge npdsReset) begin
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// wait for deassertion of npdsReset
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// wait for deassertion of npdsReset
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if(npdsReset == 1'b1) begin
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if(npdsReset == 1'b1) begin
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resetgenState <= S1;
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resetgenState <= S1;
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else
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end else begin
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// shouldn't actually end up here
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// shouldn't actually end up here
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resetgenState <= S0;
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resetgenState <= S0;
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end
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end
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@ -202,7 +203,7 @@ alwasy @(posedge cpuClock or negedge npdsReset) begin
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// wait for Bus Grant from SE
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// wait for Bus Grant from SE
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if(npdsBg == 1'b0) begin
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if(npdsBg == 1'b0) begin
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resetgenState <= S2;
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resetgenState <= S2;
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else
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end else begin
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resetgenState <= S1;
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resetgenState <= S1;
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end
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end
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end
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end
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@ -211,7 +212,7 @@ alwasy @(posedge cpuClock or negedge npdsReset) begin
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// stay here until the system resets again.
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// stay here until the system resets again.
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if(npdsReset == 1'b1) begin
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if(npdsReset == 1'b1) begin
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resetgenState <= S2;
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resetgenState <= S2;
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else
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end else begin
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resetgenState <= S0;
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resetgenState <= S0;
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end
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end
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end
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end
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@ -228,36 +229,36 @@ always_comb begin
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// DSACK intermediary signals
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// DSACK intermediary signals
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if(dsack68genState == S1) begin
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if(dsack68genState == S1) begin
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nDsack68 <= 1'b0;
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nDsack68 <= 1'b0;
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else
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end else begin
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nDsack68 <= 1'b1;
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nDsack68 <= 1'b1;
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end
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end
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if(dsackSEgenState == S1) begin
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if(dsackSEgenState == S1) begin
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nDsackSE <= 1'b0;
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nDsackSE <= 1'b0;
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else
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end else begin
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nDsackSE <= 1'b1;
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nDsackSE <= 1'b1;
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end
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end
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// Upper/Lower data byte intermediary signals
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// Upper/Lower data byte intermediary signals
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if(~cpuA0 || cpuRnW) begin
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if(~cpuA0 || cpuRnW) begin
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nUD <= 1'b0;
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nUD <= 1'b0;
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else
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end else begin
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nUD <= 1'b1;
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nUD <= 1'b1;
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end
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end
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if(cpuA0 || ~cpuSize0 || cpuSize1 || cpuRnW) begin
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if(cpuA0 || ~cpuSize0 || cpuSize1 || cpuRnW) begin
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nLD <= 1'b0;
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nLD <= 1'b0;
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else
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end else begin
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nLD <= 1'b1;
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nLD <= 1'b1;
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end
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end
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// Upper/Lower data strobes
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// Upper/Lower data strobes
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if(~ncpuDS || ~nUD) begin
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if(~ncpuDS || ~nUD) begin
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npdsUds <= 1'b0;
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npdsUds <= 1'b0;
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else
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end else begin
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npdsUds <= 1'bZ;
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npdsUds <= 1'bZ;
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end
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end
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if(~ncpuDS || ~nLD) begin
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if(~ncpuDS || ~nLD) begin
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npdsLds <= 1'b0;
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npdsLds <= 1'b0;
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else
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end else begin
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npdsLds <= 1'bZ;
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npdsLds <= 1'bZ;
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end
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end
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@ -265,27 +266,27 @@ always_comb begin
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if(ncpuBG == 1'b1) begin
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if(ncpuBG == 1'b1) begin
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if(~nUD || ~npdsBg) begin
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if(~nUD || ~npdsBg) begin
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nbufDhiEn <= 1'b0;
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nbufDhiEn <= 1'b0;
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else
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end else begin
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nbufDhiEn <= 1'b1;
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nbufDhiEn <= 1'b1;
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end
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end
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if(~nLD || nUD || ~npdsBg) begin
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if(~nLD || nUD || ~npdsBg) begin
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nbufDlo2En <= 1'b0;
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nbufDlo2En <= 1'b0;
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else
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end else begin
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nbufDlo2En <= 1'b1;
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nbufDlo2En <= 1'b1;
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end
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end
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if(~nLD || ~nUD || ~npdsBg) begin
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if(~nLD || ~nUD || ~npdsBg) begin
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nbufDlo1En <= 1'b0;
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nbufDlo1En <= 1'b0;
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else
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end else begin
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nbufDlo1En <= 1'b1;
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nbufDlo1En <= 1'b1;
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end
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end
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if(npdsBg <= 1'b0) begin
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if(npdsBg <= 1'b0) begin
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nbufAEn <= 1'b0;
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nbufAEn <= 1'b0;
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nbufCEn <= 1'b0;
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nbufCEn <= 1'b0;
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else
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end else begin
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nbufAEn <= 1'b1;
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nbufAEn <= 1'b1;
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nbufCEn <= 1'b1;
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nbufCEn <= 1'b1;
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end
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end
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else
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end else begin
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nbufDhiEn <= 1'b1;
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nbufDhiEn <= 1'b1;
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nbufDlo2En <= 1'b1;
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nbufDlo2En <= 1'b1;
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nbufDlo1En <= 1'b1;
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nbufDlo1En <= 1'b1;
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@ -299,26 +300,26 @@ always_comb begin
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// autovector request
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// autovector request
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if(cpuFC == 3'h7 && nDsack68 == 1'b0) begin
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if(cpuFC == 3'h7 && nDsack68 == 1'b0) begin
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ncpuAvec <= 1'b0;
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ncpuAvec <= 1'b0;
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else
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end else begin
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ncpuAvec <= 1'b1;
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ncpuAvec <= 1'b1;
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end
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end
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// VMA signal
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// VMA signal
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if(vmagenCount >= 4'h3) begin
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if(vmagenCount >= 4'h3) begin
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npdsVma <= 1'b0;
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npdsVma <= 1'b0;
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else
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end else begin
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npdsVma <= 1'bz;
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npdsVma <= 1'bz;
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end
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end
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// DS Ack signals
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// DS Ack signals
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if((nDsack68 == 1'b0 || (nDsackSE == 1'b0 && cpuAddrHi < 4'h5)) && cpuFC < 3'h7) begin
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if((nDsack68 == 1'b0 || (nDsackSE == 1'b0 && cpuAddrHi < 4'h5)) && cpuFC < 3'h7) begin
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ncpuDsack0 <= 1'b0;
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ncpuDsack0 <= 1'b0;
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else
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end else begin
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ncpuDsack1 <= 1'b1;
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ncpuDsack0 <= 1'b1;
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end
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end
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if(nDsackSE == 1'b0 && cpuAddrHi >= 4'h5 && cpuFC < 3'h7) begin
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if(nDsackSE == 1'b0 && cpuAddrHi >= 4'h5 && cpuFC < 3'h7) begin
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ncpuDsack1 <= 1'b0;
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ncpuDsack1 <= 1'b0;
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else
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end else begin
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ncpuDsack1 <= 1'b1;
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ncpuDsack1 <= 1'b1;
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end
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end
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@ -326,7 +327,7 @@ always_comb begin
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if(resetgenState == S2) begin
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if(resetgenState == S2) begin
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ncpuReset <= 1'b0;
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ncpuReset <= 1'b0;
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ncpuHalt <= 1'b0;
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ncpuHalt <= 1'b0;
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else
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end else begin
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ncpuReset <= 1'bz;
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ncpuReset <= 1'bz;
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ncpuHalt <= 1'bz;
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ncpuHalt <= 1'bz;
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end
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end
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@ -334,12 +335,12 @@ always_comb begin
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// bus request & grant
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// bus request & grant
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if(resetgenState == S0) begin
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if(resetgenState == S0) begin
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npdsBr <= 1'bz;
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npdsBr <= 1'bz;
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else
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end else begin
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npdsbr <= 1'b0;
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npdsBr <= 1'b0;
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end
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end
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if(resetgenState == S2) begin
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if(resetgenState == S2) begin
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npdsBGack <= 1'b0;
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npdsBGack <= 1'b0;
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else
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end else begin
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npdsBGack <= 1'bz;
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npdsBGack <= 1'bz;
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end
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end
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@ -349,11 +350,19 @@ always_comb begin
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if(nfpuSense == 1'b1) begin
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if(nfpuSense == 1'b1) begin
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// pulled high means FPU missing. assert bus error
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// pulled high means FPU missing. assert bus error
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ncpuBerr <= 1'b0;
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ncpuBerr <= 1'b0;
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else
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end else begin
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ncpuBerr <= 1'bz;
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ncpuBerr <= 1'bz;
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end
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end
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else
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end else begin
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nfpuCe <= 1'b1;
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nfpuCe <= 1'b1;
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ncpuBerr <= 1'bz;
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ncpuBerr <= 1'bz;
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end
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end
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end
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//ncpuCiin
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if(cpuAddrHi < 4'h6) begin
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ncpuCiin <= 1'b0;
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end else begin
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ncpuCiin <= 1'bz;
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end
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end
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endmodule
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