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SE-Exp30
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Bus Synchronization Fixes

This commit is contained in:
techav 2021-10-03 04:28:36 -05:00
parent 9336a5975f
commit 605e9dfc0d
2 changed files with 222 additions and 149 deletions
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255
Waveform.vwf
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@ -562,6 +562,16 @@ SIGNAL("pdsVPAn")
PARENT = "";
}
SIGNAL("pdsPMCYCn")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("cpuFC[2]")
{
NODE
@ -660,9 +670,7 @@ TRANSITION_LIST("cpuA0")
NODE
{
REPEAT = 1;
LEVEL 0 FOR 3740.0;
LEVEL 1 FOR 400.0;
LEVEL 0 FOR 5860.0;
LEVEL 0 FOR 10000.0;
}
}
@ -688,7 +696,9 @@ TRANSITION_LIST("cpuAHI[2]")
LEVEL 1 FOR 1100.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 1160.0;
LEVEL 0 FOR 6260.0;
LEVEL 0 FOR 560.0;
LEVEL 1 FOR 720.0;
LEVEL 0 FOR 4980.0;
}
}
@ -714,7 +724,9 @@ TRANSITION_LIST("cpuAHI[0]")
LEVEL 1 FOR 480.0;
LEVEL 0 FOR 1200.0;
LEVEL 1 FOR 1160.0;
LEVEL 0 FOR 6260.0;
LEVEL 0 FOR 560.0;
LEVEL 1 FOR 720.0;
LEVEL 0 FOR 4980.0;
}
}
@ -725,7 +737,9 @@ TRANSITION_LIST("cpuAMID[6]")
REPEAT = 1;
LEVEL 0 FOR 2580.0;
LEVEL 1 FOR 1160.0;
LEVEL 0 FOR 6260.0;
LEVEL 0 FOR 560.0;
LEVEL 1 FOR 720.0;
LEVEL 0 FOR 4980.0;
}
}
@ -736,7 +750,9 @@ TRANSITION_LIST("cpuAMID[5]")
REPEAT = 1;
LEVEL 0 FOR 2580.0;
LEVEL 1 FOR 1160.0;
LEVEL 0 FOR 6260.0;
LEVEL 0 FOR 560.0;
LEVEL 1 FOR 720.0;
LEVEL 0 FOR 4980.0;
}
}
@ -749,7 +765,9 @@ TRANSITION_LIST("cpuAMID[4]")
LEVEL 1 FOR 1160.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 120.0;
LEVEL 0 FOR 5740.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 720.0;
LEVEL 0 FOR 4980.0;
}
}
@ -760,7 +778,9 @@ TRANSITION_LIST("cpuAMID[3]")
REPEAT = 1;
LEVEL 0 FOR 2580.0;
LEVEL 1 FOR 1160.0;
LEVEL 0 FOR 6260.0;
LEVEL 0 FOR 560.0;
LEVEL 1 FOR 720.0;
LEVEL 0 FOR 4980.0;
}
}
@ -771,7 +791,9 @@ TRANSITION_LIST("cpuAMID[2]")
REPEAT = 1;
LEVEL 0 FOR 2580.0;
LEVEL 1 FOR 1160.0;
LEVEL 0 FOR 6260.0;
LEVEL 0 FOR 560.0;
LEVEL 1 FOR 720.0;
LEVEL 0 FOR 4980.0;
}
}
@ -782,7 +804,9 @@ TRANSITION_LIST("cpuAMID[1]")
REPEAT = 1;
LEVEL 0 FOR 2580.0;
LEVEL 1 FOR 1160.0;
LEVEL 0 FOR 6260.0;
LEVEL 0 FOR 560.0;
LEVEL 1 FOR 720.0;
LEVEL 0 FOR 4980.0;
}
}
@ -795,7 +819,9 @@ TRANSITION_LIST("cpuAMID[0]")
LEVEL 1 FOR 1160.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 120.0;
LEVEL 0 FOR 5740.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 720.0;
LEVEL 0 FOR 4980.0;
}
}
@ -816,7 +842,13 @@ TRANSITION_LIST("cpuASn")
LEVEL 0 FOR 360.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 5760.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 720.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 960.0;
LEVEL 1 FOR 220.0;
LEVEL 0 FOR 780.0;
LEVEL 1 FOR 2940.0;
}
}
@ -843,7 +875,7 @@ TRANSITION_LIST("cpuBGn")
NODE
{
REPEAT = 1;
LEVEL 0 FOR 10000.0;
LEVEL 1 FOR 10000.0;
}
}
@ -909,7 +941,9 @@ TRANSITION_LIST("cpuDSn")
LEVEL 0 FOR 320.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 5760.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 720.0;
LEVEL 1 FOR 4980.0;
}
}
@ -1014,7 +1048,8 @@ TRANSITION_LIST("pdsBGn")
NODE
{
REPEAT = 1;
LEVEL 0 FOR 10000.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 9760.0;
}
}
@ -1116,6 +1151,23 @@ TRANSITION_LIST("pdsVPAn")
}
}
TRANSITION_LIST("pdsPMCYCn")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 5060.0;
LEVEL 1 FOR 560.0;
LEVEL 0 FOR 440.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 440.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 440.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 2880.0;
}
}
DISPLAY_LINE
{
CHANNEL = "cpuClock";
@ -1145,7 +1197,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "cpuASn";
CHANNEL = "pdsPMCYCn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
@ -1154,7 +1206,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "cpuDSn";
CHANNEL = "cpuASn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
@ -1163,7 +1215,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "cpuRnW";
CHANNEL = "cpuDSn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
@ -1190,7 +1242,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "cpuSIZE0";
CHANNEL = "cpuRnW";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 8;
@ -1199,7 +1251,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "cpuSIZE1";
CHANNEL = "cpuA0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 9;
@ -1208,12 +1260,30 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "cpuFC";
CHANNEL = "cpuSIZE0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 10;
TREE_LEVEL = 0;
CHILDREN = 11, 12, 13;
}
DISPLAY_LINE
{
CHANNEL = "cpuSIZE1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 11;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "cpuFC";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 12;
TREE_LEVEL = 0;
CHILDREN = 13, 14, 15;
}
DISPLAY_LINE
@ -1221,9 +1291,9 @@ DISPLAY_LINE
CHANNEL = "cpuFC[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 11;
TREE_INDEX = 13;
TREE_LEVEL = 1;
PARENT = 10;
PARENT = 12;
}
DISPLAY_LINE
@ -1231,9 +1301,9 @@ DISPLAY_LINE
CHANNEL = "cpuFC[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 12;
TREE_INDEX = 14;
TREE_LEVEL = 1;
PARENT = 10;
PARENT = 12;
}
DISPLAY_LINE
@ -1241,18 +1311,9 @@ DISPLAY_LINE
CHANNEL = "cpuFC[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 13;
TREE_INDEX = 15;
TREE_LEVEL = 1;
PARENT = 10;
}
DISPLAY_LINE
{
CHANNEL = "cpuA0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 14;
TREE_LEVEL = 0;
PARENT = 12;
}
DISPLAY_LINE
@ -1260,9 +1321,9 @@ DISPLAY_LINE
CHANNEL = "cpuAHI";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 15;
TREE_INDEX = 16;
TREE_LEVEL = 0;
CHILDREN = 16, 17, 18, 19;
CHILDREN = 17, 18, 19, 20;
}
DISPLAY_LINE
@ -1270,9 +1331,9 @@ DISPLAY_LINE
CHANNEL = "cpuAHI[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 16;
TREE_INDEX = 17;
TREE_LEVEL = 1;
PARENT = 15;
PARENT = 16;
}
DISPLAY_LINE
@ -1280,9 +1341,9 @@ DISPLAY_LINE
CHANNEL = "cpuAHI[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 17;
TREE_INDEX = 18;
TREE_LEVEL = 1;
PARENT = 15;
PARENT = 16;
}
DISPLAY_LINE
@ -1290,9 +1351,9 @@ DISPLAY_LINE
CHANNEL = "cpuAHI[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 18;
TREE_INDEX = 19;
TREE_LEVEL = 1;
PARENT = 15;
PARENT = 16;
}
DISPLAY_LINE
@ -1300,9 +1361,9 @@ DISPLAY_LINE
CHANNEL = "cpuAHI[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 19;
TREE_INDEX = 20;
TREE_LEVEL = 1;
PARENT = 15;
PARENT = 16;
}
DISPLAY_LINE
@ -1310,9 +1371,9 @@ DISPLAY_LINE
CHANNEL = "cpuAMID";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 20;
TREE_INDEX = 21;
TREE_LEVEL = 0;
CHILDREN = 21, 22, 23, 24, 25, 26, 27;
CHILDREN = 22, 23, 24, 25, 26, 27, 28;
}
DISPLAY_LINE
@ -1320,9 +1381,9 @@ DISPLAY_LINE
CHANNEL = "cpuAMID[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 21;
TREE_INDEX = 22;
TREE_LEVEL = 1;
PARENT = 20;
PARENT = 21;
}
DISPLAY_LINE
@ -1330,9 +1391,9 @@ DISPLAY_LINE
CHANNEL = "cpuAMID[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 22;
TREE_INDEX = 23;
TREE_LEVEL = 1;
PARENT = 20;
PARENT = 21;
}
DISPLAY_LINE
@ -1340,9 +1401,9 @@ DISPLAY_LINE
CHANNEL = "cpuAMID[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 23;
TREE_INDEX = 24;
TREE_LEVEL = 1;
PARENT = 20;
PARENT = 21;
}
DISPLAY_LINE
@ -1350,9 +1411,9 @@ DISPLAY_LINE
CHANNEL = "cpuAMID[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 24;
TREE_INDEX = 25;
TREE_LEVEL = 1;
PARENT = 20;
PARENT = 21;
}
DISPLAY_LINE
@ -1360,9 +1421,9 @@ DISPLAY_LINE
CHANNEL = "cpuAMID[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 25;
TREE_INDEX = 26;
TREE_LEVEL = 1;
PARENT = 20;
PARENT = 21;
}
DISPLAY_LINE
@ -1370,9 +1431,9 @@ DISPLAY_LINE
CHANNEL = "cpuAMID[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 26;
TREE_INDEX = 27;
TREE_LEVEL = 1;
PARENT = 20;
PARENT = 21;
}
DISPLAY_LINE
@ -1380,9 +1441,9 @@ DISPLAY_LINE
CHANNEL = "cpuAMID[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 27;
TREE_INDEX = 28;
TREE_LEVEL = 1;
PARENT = 20;
PARENT = 21;
}
DISPLAY_LINE
@ -1390,22 +1451,13 @@ DISPLAY_LINE
CHANNEL = "cpuBGn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 28;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "cpuDSACK0nz";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 29;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "cpuDSACK1nz";
CHANNEL = "cpuDSACK0nz";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 30;
@ -1414,7 +1466,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "cpuHALTnz";
CHANNEL = "cpuDSACK1nz";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 31;
@ -1423,7 +1475,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "cpuRESETnz";
CHANNEL = "cpuHALTnz";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 32;
@ -1432,7 +1484,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "fpuCEn";
CHANNEL = "cpuRESETnz";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 33;
@ -1441,7 +1493,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "fpuSENSEn";
CHANNEL = "fpuCEn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 34;
@ -1450,7 +1502,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "pdsASnz";
CHANNEL = "fpuSENSEn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 35;
@ -1459,7 +1511,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "pdsBERRn";
CHANNEL = "pdsASnz";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 36;
@ -1468,7 +1520,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "pdsBGACKn";
CHANNEL = "pdsBERRn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 37;
@ -1477,7 +1529,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "pdsBGn";
CHANNEL = "pdsBGACKn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 38;
@ -1486,7 +1538,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "pdsBRn";
CHANNEL = "pdsBGn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 39;
@ -1495,7 +1547,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "pdsUDSnz";
CHANNEL = "pdsBRn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 40;
@ -1504,7 +1556,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "pdsLDSnz";
CHANNEL = "pdsUDSnz";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 41;
@ -1513,7 +1565,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "pdsVMAnz";
CHANNEL = "pdsLDSnz";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 42;
@ -1522,7 +1574,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "pdsRESETn";
CHANNEL = "pdsVMAnz";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 43;
@ -1531,7 +1583,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "cpuAVECn";
CHANNEL = "pdsRESETn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 44;
@ -1540,7 +1592,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "cpuBERRn";
CHANNEL = "cpuAVECn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 45;
@ -1549,7 +1601,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "bufACEn";
CHANNEL = "cpuBERRn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 46;
@ -1558,7 +1610,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "bufCCEn";
CHANNEL = "bufACEn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 47;
@ -1567,7 +1619,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "bufDDIR";
CHANNEL = "bufCCEn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 48;
@ -1576,7 +1628,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "bufDHICEn";
CHANNEL = "bufDDIR";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 49;
@ -1585,7 +1637,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "bufDLO1CEn";
CHANNEL = "bufDHICEn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 50;
@ -1594,7 +1646,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "bufDLO2CEn";
CHANNEL = "bufDLO1CEn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 51;
@ -1603,16 +1655,25 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "cpuCIINn";
CHANNEL = "bufDLO2CEn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 52;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "cpuCIINn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 53;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 4140000;
TIME = 5060000;
MASTER = TRUE;
}
;

116
paste.sv
View File

@ -38,6 +38,7 @@ module paste (
inout wire pdsVMAnz, // PDS Valid Memory Addr signal
input wire pdsVPAn, // PDS Valid Peripheral Addr signal
input wire pdsBERRn, // PDS Bus Error signal
input wire pdsPMCYCn, // PDS Memory Cycle signal
input wire pdsC8M, // PDS 8MHz System Clock signal
output wire pdsClockE, // PDS 800kHz 6800 bus E clock
output wire bufDHICEn, // Data buffer CPU[31:24] <=> PDS[15:8]
@ -50,11 +51,36 @@ module paste (
output wire fpuCEn // FPU Chip Select signal
);
// SE memory cycle syncronization
// the SE bus is fully synchronous and uses the PMCYCn singal to indicate when
// it is loading video data from memory and to indicate the beginning of a
// 68000 cpu cycle. Asserting PDS ASn during the S3-S4 transition will cause
// the memory RAS/CAS generator to glitch, and so should be avoided.
logic [1:0] cycCount;
always @(posedge pdsC8M or posedge pdsPMCYCn) begin
if(pdsPMCYCn) cycCount <= 0;
else if(pdsC8M) begin
cycCount <= cycCount + 2'h1;
end
end
// pds address strobe
// For ROM & peripheral accesses, PDS ASn can fall at any time, but for memory
// accesses, PDS ASn must be synchronized with the SE state machine
// For memory accesses, we need to check both the current address and the state
// of cycCount to meet timing requirements
logic pdsASnINNER;
always @(posedge pdsC8M or posedge cpuASn) begin
if(cpuASn) pdsASnINNER <= 1;
else if(pdsC8M && !cpuASn) pdsASnINNER <= 0;
else if(cpuAHI < 4'h4) begin
// this is a memory access cycle, we need to pay special attention to
// synchronization with the SE state machine
if(!pdsPMCYCn && cycCount != 1) pdsASnINNER <= 0;
else if(!pdsASnINNER && !cpuASn) pdsASnINNER <= 0; // keep low if already low as long as CPU holds low
else pdsASnINNER <= 1;
// I'm not entirely sure this is going to work, given internal timing
// of the CPLD, signal propagation times, etc.
end else if(pdsC8M && !cpuASn) pdsASnINNER <= 0;
else pdsASnINNER <= 1;
end
always_comb begin
@ -70,43 +96,29 @@ always @(posedge pdsC8M or posedge cpuASn) begin
else if(pdsC8M && !pdsASnINNER && !pdsDTACKn) cpuDTACKnINNER <= 0;
else cpuDTACKnINNER <= 1;
end
// since the 68000 had a 16-bit bus and did not support
// dynamic bus sizing the way the 68030 did, all our
// normal bus cycles will be terminated as 16-bit.
// The exception is interrupts, where we'll terminate
// with AVEC instead of DSACKx
always_comb begin
cpuDSACK0nz <= 1'bZ;
if(cpuFC == 3'h7) begin
// CPU space cycle
// interrupt autovector
if(!cpuDTACK68nINNER) begin
// interrupt autovector
cpuDSACK0nz <= 1'bZ;
cpuDSACK1nz <= 1'bZ;
cpuAVECn <= 0;
end else begin
// We shouldn't need anything else in CPU space
cpuDSACK0nz <= 1'bZ;
cpuDSACK1nz <= 1'bZ;
cpuAVECn <= 1;
end
end else begin
// normal memory or I/O cycle
if(cpuAHI < 4'h4) begin
// 16-bit RAM access cycle
if(cpuDTACKnINNER) begin
cpuDSACK0nz <= 1'bZ;
cpuDSACK1nz <= 1'bZ;
cpuAVECn <= 1;
end else begin
cpuDSACK0nz <= 1'bZ;
cpuDSACK1nz <= 0;
cpuAVECn <= 1;
end
if(!cpuDTACKnINNER || !cpuDTACK68nINNER) begin
cpuDSACK1nz <= 0;
cpuAVECn <= 1;
end else begin
if(!cpuDTACKnINNER || !cpuDTACK68nINNER) begin
cpuDSACK0nz <= 0;
cpuDSACK1nz <= 1'bZ;
cpuAVECn <= 1;
end else begin
cpuDSACK0nz <= 1'bZ;
cpuDSACK1nz <= 1'bZ;
cpuAVECn <= 1;
end
cpuDSACK1nz <= 1'bZ;
cpuAVECn <= 1;
end
end
end
@ -139,12 +151,27 @@ reg pdsDSnINNER;
wire pdsDSn2INNER;
wire pdsLDSnINNER;
wire pdsUDSnINNER;
wire pdsUPPERn, pdsLOWERn;
always @(posedge pdsC8M or posedge cpuASn) begin
if(cpuASn) pdsDSnINNER <= 1;
else if (pdsC8M && !pdsASnINNER) pdsDSnINNER <= 0;
else pdsDSnINNER <= 1;
end
always_comb begin
// upper strobe
if(cpuRnW) pdsUPPERn <= 0;
else begin
if(cpuA0) pdsUPPERn <= 1;
else pdsUPPERn <= 0;
end
// lower strobe
if(cpuRnW) pdsLOWERn <= 0;
else begin
if(cpuSIZE0 == 1 && cpuSIZE1 == 0 && cpuA0 == 0) pdsLOWERn <= 1;
else pdsLOWERn <= 0;
end
if(cpuRnW) pdsDSn2INNER <= pdsASnINNER;
else pdsDSn2INNER <= pdsDSnINNER;
@ -152,28 +179,14 @@ always_comb begin
if(pdsDSn2INNER) begin
pdsUDSnINNER <= 1;
end else begin
if(cpuRnW) begin
// read
pdsUDSnINNER <= 0;
end else begin
// write
if(cpuA0) pdsUDSnINNER <= 1;
else pdsUDSnINNER <= 0;
end
pdsUDSnINNER <= pdsUPPERn;
end
// Lower Data Strobe
if(pdsDSn2INNER) begin
pdsLDSnINNER <= 1;
end else begin
if(cpuRnW) begin
// read
pdsLDSnINNER <= 0;
end else begin
// write
if(cpuSIZE0 == 1 && cpuSIZE1 == 0 && cpuA0 == 0) pdsLDSnINNER <= 1;
else pdsLDSnINNER <= 0;
end
pdsLDSnINNER <= pdsLOWERn;
end
// Data Strobe outputs
@ -247,16 +260,15 @@ always_comb begin
end
// bus buffer controls
assign bufACEn = cpuASn;
assign bufCCEn = pdsBGn;
assign bufDDIR = cpuRnW;
wire bufCEn;
assign bufCEn = ~(cpuBGn & ~pdsBGn);
assign bufACEn = bufCEn;
assign bufCCEn = bufCEn;
assign bufDHICEn = bufCEn;
assign bufDLO1CEn = bufCEn;
wire siz, siza;
assign siz = cpuSIZE0 & ~cpuSIZE1;
assign bufDLO1CEn = siz | cpuDSn;
assign siza = siz & cpuA0;
assign bufDLO2CEn = ~siza | cpuDSn;
assign bufDHICEn = siza | cpuDSn;
// it turns out we don't actually need the Lo2 buffer
assign bufDLO2CEn = 1;
endmodule