CPU Snoop First Draft
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techav-homebrew
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90d5384b90
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175
se-xga.sv
175
se-xga.sv
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@ -97,7 +97,7 @@ end
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logic [8:0] vidData; // the video data we are displaying
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wire [2:0] vidSeq; // sequence counter, derived from hCount
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wire tick, tock; // even/odd pulses of pixel clock divided by 2
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wire [14:0] readAddr; // VRAM read address
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wire [14:0] readAddr; // VRAM read address
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assign vidSeq = hCount[3:1];
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assign tick = !hCount[0];
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@ -138,79 +138,122 @@ end
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/******************************************************************************
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* CPU Bus Snooping
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* Watch the CPU bus for writes to the video buffer regions of memory, cache
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* the data internally until a write slot is available, then store in VRAM.
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* This is the last step, and it's a big one. Once this is in place and
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* operational, the adapter should be fully operational.
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* Watch the CPU bus for writes to the video buffer regions of memory and write
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* that data to VRAM. VRAM write cycles can occur during vidSeq 1 through 7.
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* High-order bytes are passed to VRAM on tick states and low-order bytes are
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* passed to VRAM on tock states. After the VRAM writes are complete, state
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* machine waits for the CPU cycle to end before returning to idle.
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*****************************************************************************/
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// to remember for later:
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// vramCE[x] should be asserted when vidSeq == 0
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// vramOE should be asserted when vidSeq == 0 && vidActive
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// vramWE should be asserted on tock pulses of write sequences
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wire [14:0] writeAddr;
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reg vidBufSel;
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wire nvramCE0cpu, nvramCE1cpu;
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reg nvramWEpre;
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always @(negedge pixClk or negedge nReset) begin
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if(nReset) begin
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nvramWEpre <= 1;
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end else if(!pixClk && vidSeq != 0 && (!ncpuLDS || !ncpuUDS) && tock) begin
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// when cpu addresses the framebuffer, set our enable signal
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/* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
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* $8000 below the main frame buffer
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* ramSize is used to mask the CPU Address bits [21:19] to select the amount
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* of memory installed in the computer. Not all possible ramSize selections
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* are valid memory sizes when using 30-pin SIMMs in the Mac SE.
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* They may be possible using PDS RAM expansion cards.
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* ramSize mainBuffer altBuffer ramTop+1 ramSize Valid? Installed SIMMs
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* $7 $3fa700 $3f2700 $400000 4.0MB Y [ 1MB 1MB ][ 1MB 1MB ]
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* $6 $37a700 $372700 $380000 3.5MB N
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* $5 $2fa700 $2f2700 $300000 3.0MB N
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* $4 $27a700 $272700 $280000 2.5MB Y [ 1MB 1MB ][256kB 256kB]
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* $3 $1fa700 $1f2700 $200000 2.0MB Y [ 1MB 1MB ][ --- --- ]
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* $2 $17a700 $172700 $180000 1.5MB N
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* $1 $0fa700 $0f2700 $100000 1.0MB Y [256kB 256kB][256kB 256kB]
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* $0 $07a700 $072700 $080000 0.5MB Y [256kB 256kB][ --- --- ]
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*/
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wire cpuBufSel = ~cpuAddr[14];
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wire cpuBufAddr;
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always_comb begin
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// remember cpuAddr is shifted right by one since 68000 does not output A0
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if(!ncpuAS && !cpuRnW
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&& cpuAddr[22:21] == 2'b00 // initial constant
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&& ramSize == cpuAddr[20:18] // ram size selection
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&& cpuAddr[17:15] == 3'b111 // trailing constant
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// next bit is main/alt select
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&& (cpuAddr[13:0] >= 14'h1380 // bottom of buffer range (0x2700>>1)
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&& cpuAddr[13:0] <= 14'h3e3f) // top of buffer range (0x7C70>>1)
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) begin
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cpuBufAddr <= 1'b1;
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end else begin
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cpuBufAddr <= 1'b0;
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end
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end
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/*
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// link module that snoops cpu writes
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cpusnoop cpusnp(
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.nReset(nReset),
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.pixClock(pixClk),
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.seq(hCount[2:0]),
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.cpuAddr(cpuAddr),
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.cpuData(cpuData),
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.ncpuAS(ncpuAS),
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.ncpuUDS(ncpuUDS),
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.ncpuLDS(ncpuLDS),
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.cpuRnW(cpuRnW),
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.cpuClk(cpuClk),
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.vramAddr(cpuVramAddr),
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.vramDataOut(cpuVramData),
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.nvramWE(nvramWEpre),
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.nvramCE0(nvramCE0pre),
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.nvramCE1(nvramCE1pre),
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.vidBufSelOut(vidBufSel),
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.ramSize(ramSize)
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);
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*/
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wire [14:0] writeAddr;
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reg vidBufSel;
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wire nvramCE0cpu, nvramCE1cpu, nvramWEcpu;
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reg [1:0] snoopCycleState;
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/*
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cpusnoop cpusnp(
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.nReset(nReset),
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.pixClock(pixClk),
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.seq(vidSeq),
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.cpuAddr(cpuAddr),
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.cpuData(cpuData),
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.ncpuAS(ncpuAS),
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.ncpuUDS(ncpuUDS),
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.ncpuLDS(ncpuLDS),
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.cpuRnW(cpuRnW),
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.cpuClk(cpuClk),
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.vramAddr(writeAddr),
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.vramDataOut(),
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.nvramWE(),
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.nvramCE0(nvramCE0cpu),
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.nvramCE1(nvramCE1cpu),
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.vidBufSelOut(),
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.ramSize(ramSize)
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);
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*/
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// define state machine states
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parameter
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S0 = 2'b00, // idle
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S1 = 2'b01, // write high-order byte
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S2 = 2'b11, // write low-order byte
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S3 = 2'b10; // wait for CPU cycle end
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always @(negedge pixClk or negedge nReset) begin
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if(!nReset) begin snoopCycleState <= S0;
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else begin
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case (snoopCycleState)
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S0 : begin
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// idle, waiting for cpu to start a bus cycle
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// if we're on a tock state and not about to go into a VRAM
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// read cycle, and the CPU has asserted ncpuUDS, then we'll
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// move to S1 to handle the high-order byte write.
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// If ncpuUDS is not asserted, but ncpuLDS is, and we're on a
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// tick state, then we'll skip on down to S2.
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// Otherwise, we'll stay here on S0
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if(cpuBufAddr && tock && !ncpuUDS && vidSeq != 7) snoopCycleState <= S1;
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else if(cpuBufAddr && tick && !ncpuLDS && vidSeq != 1) snoopCycleState <= S2;
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else snoopCycleState <= S0;
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end
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S1 : begin
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// writing high-order byte to VRAM
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// if we also need to write a low-order byte, then move to S2,
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// else move to S3 to wait for the CPU cycle to end
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if(!ncpuLDS) snoopCycleState <= S2;
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else snoopCycleState <= S3;
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end
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S2 : begin
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// writing low-order byte to VRAM
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// this state will always be followed by S3
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snoopCycleState <= S3;
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end
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S3 : begin
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// waiting for CPU to end bus cycle
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if(!ncpuLDS || !ncpuUDS) snoopCycleState <= S3;
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else snoopCycleState <= S0;
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end
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default: begin
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// shouldn't ever be here
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snoopCycleState <= S0;
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end
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endcase
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end
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end
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always_comb begin
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if(snoopCycleState == S1) nvramCE0cpu <= 0;
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else nvramCE0cpu <= 1;
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if(snoopCycleState == S2) nvramCE1cpu <= 0;
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else nvramCE1cpu <= 1;
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if(snoopCycleState == S1 || snoopCycleState == S2) nvramWEcpu <= 0;
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else nvramWEcpu <= 1;
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if(snoopCycleState == S1) vramData <= cpuData[15:8];
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else if(snoopCycleState == S2) vramData <= cpuData[7:0];
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else vramData <= 8'hZ;
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writeAddr[13:0] <= cpuAddr[14:1];
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writeAddr[14] <= cpuBufSel;
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end
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// Pull everything together
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always_comb begin
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if(nvramOE == 0) vramAddr <= readAddr;
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else if(nvramWE == 0) vramAddr <= writeAddr;
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else if(nvramWEcpu == 0) vramAddr <= writeAddr;
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else vramAddr <= 0;
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if(nvramOE == 0) begin
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@ -223,6 +266,8 @@ always_comb begin
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nvramCE0 <= 1;
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nvramCE1 <= 1;
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end
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nvramWE <= nvramWEcpu;
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end
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endmodule
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