Debugging VRAM Write Timing
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techav
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97b0b72794
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373b0ec9b5
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se-xga.sv
91
se-xga.sv
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@ -9,7 +9,7 @@
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module sevga (
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input wire nReset, // System reset signal
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input wire pixClk, // 25.175MHz pixel clock
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input wire pixClk, // 65MHz pixel clock
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output wire nhSync, // HSync signal
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output wire nvSync, // VSync signal
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output wire vidOut, // 1-bit Monochrome video signal
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@ -38,31 +38,33 @@ module sevga (
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*****************************************************************************/
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logic [10:0] hCount; // 0..1343
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logic [9:0] vCount; // 0..805
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wire nhSyncInner;
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// horizontal counter
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always @(negedge pixClk or negedge nReset) begin
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if(!nReset) hCount <= 0;
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else if(!pixClk) begin
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if(hCount < 1343) hCount <= hCount + 11'd1;
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else hCount <= 0;
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else begin
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if(hCount < 11'd1343) hCount <= hCount + 11'd1;
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else hCount <= 11'd0;
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end
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end
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// vertical counter
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always @(negedge nhSync or negedge nReset) begin
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always @(negedge nhSyncInner or negedge nReset) begin
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if(!nReset) vCount <= 0;
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else if(!pixClk) begin
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if(vCount < 805) vCount <= vCount + 10'd1;
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else vCount <= 0;
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else begin
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if(vCount < 10'd805) vCount <= vCount + 10'd1;
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else vCount <= 10'd0;
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end
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end
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// horizontal and vertical sync signals
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always_comb begin
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if(hCount >= 1049 && hCount < 1184) nhSync <= 0;
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else nhSync <= 1;
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if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
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else nhSyncInner <= 1;
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nhSync <= nhSyncInner;
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if(vCount >= 729 && vCount < 735) nvSync <= 0;
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if(vCount >= 10'd729 && vCount < 10'd735) nvSync <= 0;
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else nvSync <= 1;
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end
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@ -78,7 +80,7 @@ wire hLoad; // load pixel data from vram when asserted
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assign vidActive = hActive & vActive;
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always_comb begin
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if(hCount >= 1 && hCount < 1025) hActive <= 1;
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if(hCount >= 0 && hCount < 1024) hActive <= 1;
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else hActive <= 0;
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if(vCount >= 0 && vCount < 684) vActive <= 1;
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@ -107,20 +109,19 @@ always @(negedge pixClk or negedge nReset) begin
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if(!nReset) vidData <= 0;
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else if(!pixClk) begin
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if(tock && hLoad && vidSeq == 3'd0) begin
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// store the VRAM data in vidData[8:1]
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//vidData[0] <= vidData[1]; // this should actually have already been done
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vidData[8:1] <= vramData;
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// store the VRAM data in vidData[7:0]
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vidData[7:0] <= vramData;
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end else if(tick && hLoad) begin
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// shift vidData
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vidData[7:0] <= vidData[8:1];
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vidData[8] <= 0;
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vidData[8:1] <= vidData[7:0];
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vidData[0] <= 0;
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end
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end
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end
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always_comb begin
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// here is where the shifted video data actually gets output
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if(vidActive) vidOut <= ~vidData[0];
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if(vidActive) vidOut <= ~vidData[8];
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else vidOut <= 0;
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// vram read signal can be asserted here
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@ -162,17 +163,17 @@ end
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* $1 $0fa700 $0f2700 $100000 1.0MB Y [256kB 256kB][256kB 256kB]
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* $0 $07a700 $072700 $080000 0.5MB Y [256kB 256kB][ --- --- ]
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*/
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wire cpuBufSel = ~cpuAddr[14];
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wire cpuBufSel = ~cpuAddr[15];
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wire cpuBufAddr;
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always_comb begin
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// remember cpuAddr is shifted right by one since 68000 does not output A0
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if(!ncpuAS && !cpuRnW
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&& cpuAddr[22:21] == 2'b00 // initial constant
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&& ramSize == cpuAddr[20:18] // ram size selection
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&& cpuAddr[17:15] == 3'b111 // trailing constant
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&& cpuAddr[23:22] == 2'b00 // initial constant
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&& ramSize == cpuAddr[21:19] // ram size selection
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&& cpuAddr[18:16] == 3'b111 // trailing constant
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// next bit is main/alt select
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&& (cpuAddr[13:0] >= 14'h1380 // bottom of buffer range (0x2700>>1)
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&& cpuAddr[13:0] <= 14'h3e3f) // top of buffer range (0x7C70>>1)
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&& (cpuAddr[14:1] >= 14'h1380 // bottom of buffer range (0x2700>>1)
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&& cpuAddr[14:1] <= 14'h3e3f) // top of buffer range (0x7C70>>1)
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) begin
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cpuBufAddr <= 1'b1;
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end else begin
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@ -187,14 +188,14 @@ reg [2:0] snoopCycleState;
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// define state machine states
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parameter
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S0 = 2'b000, // idle
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S1 = 2'b001, // write high-order byte
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S2 = 2'b011, // write low-order byte
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S3 = 2'b010, // wait for CPU cycle end
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S4 = 2'b110; // VIA write cycle
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S0 = 3'b000, // idle
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S1 = 3'b001, // write high-order byte
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S2 = 3'b011, // write low-order byte
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S3 = 3'b010, // wait for CPU cycle end
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S4 = 3'b110; // VIA write cycle
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always @(negedge pixClk or negedge nReset) begin
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if(!nReset) begin snoopCycleState <= S0;
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if(!nReset) snoopCycleState <= S0;
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else begin
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case (snoopCycleState)
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S0 : begin
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@ -205,24 +206,26 @@ always @(negedge pixClk or negedge nReset) begin
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// If ncpuUDS is not asserted, but ncpuLDS is, and we're on a
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// tick state, then we'll skip on down to S2.
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// Otherwise, we'll stay here on S0
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if(cpuBufAddr && tock && !ncpuUDS && vidSeq != 7) snoopCycleState <= S1;
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else if(cpuBufAddr && tick && !ncpuLDS && vidSeq != 1) snoopCycleState <= S2;
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if(cpuBufAddr && tock && !ncpuUDS && vidSeq != 7 && tock) snoopCycleState <= S1;
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else if(cpuBufAddr && tick && !ncpuLDS && vidSeq != 1 && tock) snoopCycleState <= S2;
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else if(!ncpuAS && !ncpuUDS && !cpuRnW
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&& cpuAddr[22:18] == 5'h1D
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&& cpuAddr[11:7] == 5'h1F) snoopCycleState <= S4;
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&& cpuAddr[23:19] == 5'h1D
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&& cpuAddr[12:8] == 5'h1F) snoopCycleState <= S4;
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else snoopCycleState <= S0;
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end
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S1 : begin
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// writing high-order byte to VRAM
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// if we also need to write a low-order byte, then move to S2,
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// else move to S3 to wait for the CPU cycle to end
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if(!ncpuLDS) snoopCycleState <= S2;
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else snoopCycleState <= S3;
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if(!ncpuLDS && tock) snoopCycleState <= S2;
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else if(tock) snoopCycleState <= S3;
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else snoopCycleState <= S1;
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end
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S2 : begin
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// writing low-order byte to VRAM
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// this state will always be followed by S3
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snoopCycleState <= S3;
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if(tock) snoopCycleState <= S3;
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else snoopCycleState <= S2;
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end
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S3 : begin
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// waiting for CPU to end bus cycle
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@ -234,10 +237,10 @@ always @(negedge pixClk or negedge nReset) begin
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// screen buffer. 1=Main, 0=Alt
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// After saving the selection, move to S3 to wait for cycle end
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vidBufSel <= !cpuData[14];
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snoopCycleState <= S3
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snoopCycleState <= S3;
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end
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default: begin
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// shouldn't ever be here
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// generally shouldn't be here
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snoopCycleState <= S0;
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end
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endcase
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@ -245,9 +248,9 @@ always @(negedge pixClk or negedge nReset) begin
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end
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always_comb begin
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if(snoopCycleState == S1) nvramCE0cpu <= 0;
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if(snoopCycleState == S1 && tick) nvramCE0cpu <= 0;
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else nvramCE0cpu <= 1;
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if(snoopCycleState == S2) nvramCE1cpu <= 0;
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if(snoopCycleState == S2 && tick) nvramCE1cpu <= 0;
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else nvramCE1cpu <= 1;
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if(snoopCycleState == S1 || snoopCycleState == S2) nvramWEcpu <= 0;
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else nvramWEcpu <= 1;
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@ -270,7 +273,7 @@ always_comb begin
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if(nvramOE == 0) begin
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nvramCE0 <= hCount[4];
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nvramCE1 <= ~hCount[4];
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end else if(nvramWE == 0) begin
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end else if(!nvramWEcpu) begin
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nvramCE0 <= nvramCE0cpu;
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nvramCE1 <= nvramCE1cpu;
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end else begin
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@ -278,7 +281,9 @@ always_comb begin
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nvramCE1 <= 1;
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end
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nvramWE <= nvramWEcpu;
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// make sure vram WE and OE signals aren't asserted simultaneously
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if(!nvramWEcpu && nvramOE) nvramWE <= 0;
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else nvramWE <= 1;
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end
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endmodule
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