CPU Snoop Fixes
Fix for VRAM writes sometimes overlapping VRAM reads
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04faf575f9
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26
cpusnoop.sv
26
cpusnoop.sv
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@ -84,11 +84,12 @@ module cpusnoop (
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always @(negedge pixClock or negedge nReset) begin
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always @(negedge pixClock or negedge nReset) begin
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if(!nReset) cpuCycleEnded <= 0;
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if(!nReset) cpuCycleEnded <= 0;
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else if(cycleState == S2) cpuCycleEnded <= 0;
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else if(cycleState == S2) cpuCycleEnded <= 0;
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else if(ncpuUDS == 1
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else if(ncpuUDS && ncpuLDS
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&& ncpuLDS == 1
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&& (cycleState == S3
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&& (cycleState == S3
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|| cycleState == S4
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|| cycleState == S4
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|| cycleState == S5)) begin
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|| cycleState == S5
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|| cycleState == S1)
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) begin
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cpuCycleEnded <= 1;
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cpuCycleEnded <= 1;
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end else cpuCycleEnded <= cpuCycleEnded;
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end else cpuCycleEnded <= cpuCycleEnded;
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end
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end
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@ -154,15 +155,16 @@ module cpusnoop (
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end
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end
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S2 : begin
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S2 : begin
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// wait for sequence
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// wait for sequence
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if(pendWriteLo && !seq[0]) cycleState <= S3;
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if(pendWriteLo == 1 && !seq[0]) cycleState <= S3;
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else if (pendWriteHi && !seq[0]) cycleState <= S4;
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else if (pendWriteHi ==1 && !seq[0]) cycleState <= S4;
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else if (!pendWriteHi && !pendWriteLo) cycleState <= S0; // in case something weird happens
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else if (pendWriteHi == 0 && pendWriteLo == 0) cycleState <= S0; // in case something weird happens
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else cycleState <= S2;
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else cycleState <= S2;
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end
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end
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S3 : begin
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S3 : begin
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// write CPU low byte to VRAM
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// write CPU low byte to VRAM
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if(pendWriteHi == 1) begin
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if (seq == 0) begin
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cycleState <= S3; // we shouldn't be here during a read cycle, so delay
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end else if(pendWriteHi == 1) begin
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cycleState <= S1; // move on to delay before second write cycle
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cycleState <= S1; // move on to delay before second write cycle
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end else begin
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end else begin
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cycleState <= S5;
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cycleState <= S5;
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@ -171,7 +173,11 @@ module cpusnoop (
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end
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end
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S4 : begin
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S4 : begin
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// write CPU high byte to VRAM
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// write CPU high byte to VRAM
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cycleState <= S5;
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if (seq == 0) begin
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cycleState <= S4; // we shouldn't be here during a read cycle, so delay
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end else begin
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cycleState <= S5;
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end
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pendWriteHi <= 0;
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pendWriteHi <= 0;
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end
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end
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S5 : begin
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S5 : begin
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@ -212,7 +218,7 @@ module cpusnoop (
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// Assert VRAM Write signal during CPU Cycle states S3 & S4
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// Assert VRAM Write signal during CPU Cycle states S3 & S4
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// Also assert VRAM chip enable signals based on which buffer the CPU
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// Also assert VRAM chip enable signals based on which buffer the CPU
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// addressed for the VRAM write cycle
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// addressed for the VRAM write cycle
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if(cycleState == S3 || cycleState == S4) begin
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if(seq != 0 && (cycleState == S3 || cycleState == S4)) begin
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nvramWE <= 0;
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nvramWE <= 0;
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nvramCE0 <= cpuCycleBufSel;
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nvramCE0 <= cpuCycleBufSel;
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nvramCE1 <= !cpuCycleBufSel;
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nvramCE1 <= !cpuCycleBufSel;
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