35 lines
1.3 KiB
Systemverilog
35 lines
1.3 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* VGA timing generator
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* techav
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* 2021-04-06
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******************************************************************************
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* Generates VGA timing signals & counters
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*****************************************************************************/
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`ifndef VGAGEN
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`define VGAGEN
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`include "vgacount.sv"
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module vgagen (
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input wire nReset, // master reset signal
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input wire pixClk, // 25.175MHz pixel clock
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output logic [9:0] hCount, // horizontal pixel count
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output wire hActive, // horizontal VGA active video signal
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output wire hSEActive, // horizontal SE active video signal
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output wire nhSync, // horizontal sync pulse signal
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output logic [9:0] vCount, // vertical line count
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output wire vActive, // vertical VGA active video signal
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output wire vSEActive, // vertical SE active video signal
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output wire nvSync // vertical sync pulse signal
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);
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// Generate horizontal signal timing
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vgacount #(800,592,688,576,736,512) hoz(nReset,pixClk,hCount,nhSync,hActive,hSEActive);
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// Generate vertical signal timing
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vgacount #(525,421,423,411,456,342) ver(nReset,nhSync,vCount,nvSync,vActive,vSEActive);
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endmodule
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`endif |