mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2024-11-26 09:49:18 +00:00
368 lines
60 KiB
Plaintext
368 lines
60 KiB
Plaintext
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE twReport [
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<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
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twDebug*, twFoot?, twClientInfo?)>
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<!ATTLIST twReport version CDATA "10,4">
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<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
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<!ELEMENT twExecVer (#PCDATA)>
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<!ELEMENT twCopyright (#PCDATA)>
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<!ELEMENT twCmdLine (#PCDATA)>
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<!ELEMENT twDesign (#PCDATA)>
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<!ELEMENT twPCF (#PCDATA)>
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<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
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<!ELEMENT twDevName (#PCDATA)>
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<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
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<!ELEMENT twSpeedGrade (#PCDATA)>
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<!ELEMENT twSpeedVer (#PCDATA)>
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<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
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<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
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<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
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<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
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<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
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<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
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<!ELEMENT twItemLimit (#PCDATA)>
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<!ELEMENT twUnconst EMPTY>
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<!ELEMENT twUnconstLimit (#PCDATA)>
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<!ELEMENT twEnvVar EMPTY>
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<!ATTLIST twEnvVar name CDATA #REQUIRED>
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<!ATTLIST twEnvVar description CDATA #REQUIRED>
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<!ELEMENT twWarn (#PCDATA)>
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<!ELEMENT twInfo (#PCDATA)>
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<!ELEMENT twDebug (#PCDATA)>
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<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
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<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
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<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
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<!ELEMENT twProc (#PCDATA)>
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<!ELEMENT twTemp (#PCDATA)>
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<!ELEMENT twVolt (#PCDATA)>
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<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
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<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
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<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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<!ELEMENT twCycles (twSigConn+)>
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<!ATTLIST twCycles twNum CDATA #REQUIRED>
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<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
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<!ELEMENT twSig (#PCDATA)>
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<!ELEMENT twDriver (#PCDATA)>
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<!ELEMENT twLoad (#PCDATA)>
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<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
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<!ATTLIST twConst twConstType (NET |
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NETDELAY |
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NETSKEW |
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PATH |
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DEFPERIOD |
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UNCONSTPATH |
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DEFPATH |
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PATH2SETUP |
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UNCONSTPATH2SETUP |
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PATHCLASS |
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PATHDELAY |
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PERIOD |
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FREQUENCY |
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PATHBLOCK |
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OFFSET |
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OFFSETIN |
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OFFSETINCLOCK |
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UNCONSTOFFSETINCLOCK |
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OFFSETINDELAY |
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OFFSETINMOD |
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OFFSETOUT |
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OFFSETOUTCLOCK |
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UNCONSTOFFSETOUTCLOCK |
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OFFSETOUTDELAY |
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OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
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<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
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twEndPtCnt?,
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twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
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<!ELEMENT twConstName (#PCDATA)>
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<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
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<!ATTLIST twConstHead uID CDATA #IMPLIED>
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<!ELEMENT twItemCnt (#PCDATA)>
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<!ELEMENT twErrCnt (#PCDATA)>
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<!ELEMENT twErrCntEndPt (#PCDATA)>
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<!ELEMENT twErrCntSetup (#PCDATA)>
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<!ELEMENT twErrCntHold (#PCDATA)>
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<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
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<!ELEMENT twEndPtCnt (#PCDATA)>
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<!ELEMENT twPathErrCnt (#PCDATA)>
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<!ELEMENT twMinPer (#PCDATA) >
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<!ELEMENT twFootnote EMPTY>
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<!ATTLIST twFootnote number CDATA #REQUIRED>
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<!ELEMENT twMaxDel (#PCDATA)>
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<!ELEMENT twMaxFreq (#PCDATA)>
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<!ELEMENT twMinOff (#PCDATA)>
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<!ELEMENT twMaxOff (#PCDATA)>
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<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
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<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
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<!ELEMENT twTIGName (#PCDATA)>
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<!ELEMENT twInstantiated (#PCDATA)>
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<!ELEMENT twBlocked (#PCDATA)>
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<!ELEMENT twRacePathRpt (twRacePath+)>
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<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
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<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
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<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
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twSimpleMinPath CDATA #IMPLIED>
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<!ELEMENT twTotDel (#PCDATA)>
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<!ELEMENT twSrc (#PCDATA)>
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<!ATTLIST twSrc BELType CDATA #IMPLIED>
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<!ELEMENT twDest (#PCDATA)>
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<!ATTLIST twDest BELType CDATA #IMPLIED>
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<!ELEMENT twDel (#PCDATA)>
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<!ELEMENT twSUTime (#PCDATA)>
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<!ELEMENT twTotPathDel (#PCDATA)>
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<!ELEMENT twClkSkew (#PCDATA)>
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<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
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<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
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<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
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<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
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<!ELEMENT twSlack (#PCDATA)>
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<!ELEMENT twDelConst (#PCDATA)>
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<!ELEMENT tw2Phase EMPTY>
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<!ELEMENT twClkUncert (#PCDATA)>
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<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
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fDCMJit CDATA #IMPLIED
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fPhaseErr CDATA #IMPLIED
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sEqu CDATA #IMPLIED>
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<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
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<!ELEMENT twPathRptBanner (#PCDATA)>
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<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
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<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
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<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
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<!ELEMENT twOff (#PCDATA)>
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<!ELEMENT twGuaranteed EMPTY>
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<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
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<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
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<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
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<!ELEMENT twClkDel (#PCDATA)>
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<!ELEMENT twClkSrc (#PCDATA)>
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<!ELEMENT twClkDest (#PCDATA)>
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<!ELEMENT twGuarInSetup (#PCDATA)>
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<!ELEMENT twOffSrc (#PCDATA)>
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<!ELEMENT twOffDest (#PCDATA)>
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<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
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<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
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<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
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<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
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<!ELEMENT twDataDel (#PCDATA)>
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<!ELEMENT twDataSrc (#PCDATA)>
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<!ELEMENT twDataDest (#PCDATA)>
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<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
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<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twLogLvls (#PCDATA)>
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<!ELEMENT twSrcSite (#PCDATA)>
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<!ELEMENT twSrcClk (#PCDATA)>
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<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
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<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
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<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
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<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
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<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
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<!ELEMENT twDelInfo (#PCDATA)>
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<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
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<!ELEMENT twSite (#PCDATA)>
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<!ELEMENT twDelType (#PCDATA)>
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<!ELEMENT twFanCnt (#PCDATA)>
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<!ELEMENT twComp (#PCDATA)>
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<!ELEMENT twNet (#PCDATA)>
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<!ELEMENT twBEL (#PCDATA)>
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<!ELEMENT twLogDel (#PCDATA)>
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<!ELEMENT twRouteDel (#PCDATA)>
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<!ELEMENT twDestClk (#PCDATA)>
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<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
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<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
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<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
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<!ELEMENT twPctLog (#PCDATA)>
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<!ELEMENT twPctRoute (#PCDATA)>
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<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
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<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
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<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
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<!ELEMENT twTimeConst (#PCDATA)>
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<!ELEMENT twAbsSlack (#PCDATA)>
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<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
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<!ELEMENT twSkew (#PCDATA)>
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<!ELEMENT twDetNet (twNetDel*)>
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<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
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<!ELEMENT twNetDelInfo (#PCDATA)>
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<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
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<!ELEMENT twDetSkewNet (twNetSkew*)>
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<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
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<!ELEMENT twClkSkewLimit EMPTY>
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<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
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arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
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<!ELEMENT twConstRollupTable (twConstRollup*)>
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<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
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<!ELEMENT twConstRollup EMPTY>
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<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
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<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
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<!ELEMENT twConstList (twConstListItem)*>
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<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
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<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
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<!ELEMENT twNotMet EMPTY>
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<!ELEMENT twReqVal (#PCDATA)>
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<!ELEMENT twActVal (#PCDATA)>
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<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
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<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
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<!ELEMENT twConstStats (twConstName)>
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<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
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<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
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<!ATTLIST twConstStats twActual CDATA #IMPLIED>
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<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
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<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
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<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
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<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
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<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
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<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
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<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
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<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
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<!ELEMENT twConstData EMPTY>
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<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
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best CDATA #IMPLIED requested CDATA #IMPLIED
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errors CDATA #IMPLIED
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score CDATA #IMPLIED>
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<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
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<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
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<!ELEMENT twTimeGrpName (#PCDATA)>
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<!ELEMENT twCompList (twCompName+)>
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<!ELEMENT twCompName (#PCDATA)>
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<!ELEMENT twSigList (twSigName+)>
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<!ELEMENT twSigName (#PCDATA)>
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<!ELEMENT twBELList (twBELName+)>
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<!ELEMENT twBELName (#PCDATA)>
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<!ELEMENT twBlockList (twBlockName+)>
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<!ELEMENT twBlockName (#PCDATA)>
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<!ELEMENT twMacList (twMacName+)>
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<!ELEMENT twMacName (#PCDATA)>
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<!ELEMENT twPinList (twPinName+)>
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<!ELEMENT twPinName (#PCDATA)>
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<!ELEMENT twUnmetConstCnt (#PCDATA)>
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<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
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<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
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<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
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<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
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<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
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<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
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<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
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<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
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<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
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<!ELEMENT twSU2ClkTime (#PCDATA)>
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<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twH2ClkTime (#PCDATA)>
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<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
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<!ELEMENT twClk2Pad (twDest, twTime)>
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<!ELEMENT twTime (#PCDATA)>
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<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||
|
|
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
|
||
|
|
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
|
||
|
|
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
|
||
|
|
<!ELEMENT twClk2Out EMPTY>
|
||
|
|
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
|
||
|
|
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
|
||
|
|
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
|
||
|
|
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
|
||
|
|
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
|
||
|
|
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
|
||
|
|
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
|
||
|
|
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
|
||
|
|
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
|
||
|
|
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
|
||
|
|
<!ELEMENT twRiseRise (#PCDATA)>
|
||
|
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<!ELEMENT twFallRise (#PCDATA)>
|
||
|
|
<!ELEMENT twRiseFall (#PCDATA)>
|
||
|
|
<!ELEMENT twFallFall (#PCDATA)>
|
||
|
|
<!ELEMENT twPad2PadList (twPad2Pad+)>
|
||
|
|
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
|
||
|
|
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
|
||
|
|
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
|
||
|
|
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
|
||
|
|
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
|
||
|
|
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
|
||
|
|
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
|
||
|
|
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
|
||
|
|
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
|
||
|
|
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
|
||
|
|
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
|
||
|
|
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
|
||
|
|
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
|
||
|
|
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
|
||
|
|
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
|
||
|
|
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
|
||
|
|
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
|
||
|
|
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
|
||
|
|
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
|
||
|
|
<!ELEMENT twOffOutTblRow EMPTY>
|
||
|
|
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
|
||
|
|
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
|
||
|
|
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
|
||
|
|
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
|
||
|
|
<!ELEMENT twNonDedClk (#PCDATA)>
|
||
|
|
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
|
||
|
|
<!ELEMENT twScore (#PCDATA)>
|
||
|
|
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
|
||
|
|
<!ELEMENT twPathCnt (#PCDATA)>
|
||
|
|
<!ELEMENT twNetCnt (#PCDATA)>
|
||
|
|
<!ELEMENT twConnCnt (#PCDATA)>
|
||
|
|
<!ELEMENT twPct (#PCDATA)>
|
||
|
|
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
|
||
|
|
<!ELEMENT twMaxCombDel (#PCDATA)>
|
||
|
|
<!ELEMENT twMaxFromToDel (#PCDATA)>
|
||
|
|
<!ELEMENT twMaxNetDel (#PCDATA)>
|
||
|
|
<!ELEMENT twMaxNetSkew (#PCDATA)>
|
||
|
|
<!ELEMENT twMaxInAfterClk (#PCDATA)>
|
||
|
|
<!ELEMENT twMinInBeforeClk (#PCDATA)>
|
||
|
|
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
|
||
|
|
<!ELEMENT twMinOutAfterClk (#PCDATA)>
|
||
|
|
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
|
||
|
|
<!ELEMENT twTimestamp (#PCDATA)>
|
||
|
|
<!ELEMENT twFootnoteExplanation EMPTY>
|
||
|
|
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
|
||
|
|
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
|
||
|
|
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
|
||
|
|
<!ELEMENT twClientName (#PCDATA)>
|
||
|
|
<!ELEMENT twAttrList (twAttrListItem)*>
|
||
|
|
<!ELEMENT twAttrListItem (twName, twValue*)>
|
||
|
|
<!ELEMENT twName (#PCDATA)>
|
||
|
|
<!ELEMENT twValue (#PCDATA)>
|
||
|
|
]>
|
||
|
|
<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (nt)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
|
||
|
|
3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||
|
|
|
||
|
|
</twCmdLine><twDesign>WarpLC.ncd</twDesign><twDesignPath>WarpLC.ncd</twDesignPath><twPCF>WarpLC.pcf</twPCF><twPcfPath>WarpLC.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="ftg256"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="NET CLKIN PERIOD = 20ns HIGH;" ScopeName="">NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>5.000</twMinPer></twConstHead><twPinLimitRpt anchorID="6"><twPinLimitBanner>Component Switching Limit Checks: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="7" type="MINLOWPULSE" name="Tdcmpw_CLKIN_50_100" slack="15.000" period="20.000" constraintValue="10.000" deviceLimit="2.500" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN2" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/><twPinLimit anchorID="8" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_50_100" slack="15.000" period="20.000" constraintValue="10.000" deviceLimit="2.500" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN2" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/><twPinLimit anchorID="9" type="MINPERIOD" name="Tpllper_CLKIN(Finmax)" slack="17.780" period="20.000" constraintValue="20.000" deviceLimit="2.220" freqLimit="450.450" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN2" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/></twPinLimitRpt></twConst><twConst anchorID="10" twConstType="PERIOD" ><twConstHead uID="4"><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS </twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.666</twMinPer></twConstHead><twPinLimitRpt anchorID="11"><twPinLimitBanner>Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkfbout" derived from
|
||
|
|
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||
|
|
duty cycle corrected to 20 nS HIGH 10 nS
|
||
|
|
</twPinLimitBanner><twPinLimit anchorID="12" type="MINPERIOD" name="Tbcper_I" slack="17.334" period="20.000" constraintValue="20.000" deviceLimit="2.666" freqLimit="375.094" physResource="instance_name/clkfbout_bufg/I0" logResource="instance_name/clkfbout_bufg/I0" locationPin="BUFGMUX_X2Y3.I0" clockNet="instance_name/clkfbout"/><twPinLimit anchorID="13" type="MINPERIOD" name="Tockper" slack="17.751" period="20.000" constraintValue="20.000" deviceLimit="2.249" freqLimit="444.642" physResource="CLKFB_OUT_OBUF/CLK0" logResource="instance_name/clkfbout_oddr/CK0" locationPin="OLOGIC_X0Y50.CLK0" clockNet="instance_name/clkfb_bufg_out"/><twPinLimit anchorID="14" type="MINPERIOD" name="Tpllper_CLKFB" slack="17.780" period="20.000" constraintValue="20.000" deviceLimit="2.220" freqLimit="450.450" physResource="instance_name/pll_base_inst/PLL_ADV/CLKFBOUT" logResource="instance_name/pll_base_inst/PLL_ADV/CLKFBOUT" locationPin="PLL_ADV_X0Y1.CLKFBOUT" clockNet="instance_name/clkfbout"/></twPinLimitRpt></twConst><twConst anchorID="15" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkout1" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS </twConstName><twItemCnt>3</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>3</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>7.082</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point FPUCLK (OLOGIC_X6Y2.D1), 1 path
|
||
|
|
</twPathRptBanner><twPathRpt anchorID="16"><twConstPath anchorID="17" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.459</twSlack><twSrc BELType="FF">CPUCLKr1</twSrc><twDest BELType="FF">FPUCLK</twDest><twTotPathDel>3.914</twTotPathDel><twClkSkew dest = "1.178" src = "0.657">-0.521</twClkSkew><twDelConst>5.000</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>CPUCLKr1</twSrc><twDest BELType='FF'>FPUCLK</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X5Y28.CLK</twSrcSite><twSrcClk twEdge ="twFalling" twArriveTime ="5.000">CPUCLKi</twSrcClk><twPathDel><twSite>SLICE_X5Y28.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>CPUCLKr1</twComp><twBEL>CPUCLKr1</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X6Y2.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">2.306</twDelInfo><twComp>CPUCLKr1</twComp></twPathDel><twPathDel><twSite>OLOGIC_X6Y2.CLK0</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">1.178</twDelInfo><twComp>FPUCLK_OBUF</twComp><twBEL>FPUCLK</twBEL></twPathDel><twLogDel>1.608</twLogDel><twRouteDel>2.306</twRouteDel><twTotDel>3.914</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">CPUCLKi</twDestClk><twPctLog>41.1</twPctLog><twPctRoute>58.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point CPUCLK (OLOGIC_X0Y46.D1), 1 path
|
||
|
|
</twPathRptBanner><twPathRpt anchorID="18"><twConstPath anchorID="19" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.562</twSlack><twSrc BELType="FF">CPUCLKr1</twSrc><twDest BELType="FF">CPUCLK</twDest><twTotPathDel>3.815</twTotPathDel><twClkSkew dest = "1.275" src = "0.750">-0.525</twClkSkew><twDelConst>5.000</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>CPUCLKr1</twSrc><twDest BELType='FF'>CPUCLK</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X5Y28.CLK</twSrcSite><twSrcClk twEdge ="twFalling" twArriveTime ="5.000">CPUCLKi</twSrcClk><twPathDel><twSite>SLICE_X5Y28.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>CPUCLKr1</twComp><twBEL>CPUCLKr1</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X0Y46.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">2.207</twDelInfo><twComp>CPUCLKr1</twComp></twPathDel><twPathDel><twSite>OLOGIC_X0Y46.CLK0</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">1.178</twDelInfo><twComp>CPUCLK_OBUF</twComp><twBEL>CPUCLK</twBEL></twPathDel><twLogDel>1.608</twLogDel><twRouteDel>2.207</twRouteDel><twTotDel>3.815</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">CPUCLKi</twDestClk><twPctLog>42.1</twPctLog><twPctRoute>57.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point CPUCLKr1 (SLICE_X5Y28.AX), 1 path
|
||
|
|
</twPathRptBanner><twPathRpt anchorID="20"><twConstPath anchorID="21" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.862</twSlack><twSrc BELType="FF">CPUCLKr0</twSrc><twDest BELType="FF">CPUCLKr1</twDest><twTotPathDel>1.209</twTotPathDel><twClkSkew dest = "1.489" src = "2.150">0.661</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.268</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>CPUCLKr0</twSrc><twDest BELType='FF'>CPUCLKr1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X4Y28.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X4Y28.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>CPUCLKr0</twComp><twBEL>CPUCLKr0</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y28.AX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>CPUCLKr0</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y28.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.114</twDelInfo><twComp>CPUCLKr1</twComp><twBEL>CPUCLKr1</twBEL></twPathDel><twLogDel>0.639</twLogDel><twRouteDel>0.570</twRouteDel><twTotDel>1.209</twTotDel><twDestClk twEdge ="twFalling" twArriveTime ="5.000">CPUCLKi</twDestClk><twPctLog>52.9</twPctLog><twPctRoute>47.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: PERIOD analysis for net "instance_name/clkout1" derived from
|
||
|
|
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||
|
|
divided by 2.00 to 10 nS
|
||
|
|
|
||
|
|
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point CPUCLKr1 (SLICE_X5Y28.AX), 1 path
|
||
|
|
</twPathRptBanner><twPathRpt anchorID="22"><twConstPath anchorID="23" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>4.848</twSlack><twSrc BELType="FF">CPUCLKr0</twSrc><twDest BELType="FF">CPUCLKr1</twDest><twTotPathDel>0.441</twTotPathDel><twClkSkew dest = "1.035" src = "0.710">-0.325</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.268</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>CPUCLKr0</twSrc><twDest BELType='FF'>CPUCLKr1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X4Y28.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X4Y28.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>CPUCLKr0</twComp><twBEL>CPUCLKr0</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y28.AX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.148</twDelInfo><twComp>CPUCLKr0</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X5Y28.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>CPUCLKr1</twComp><twBEL>CPUCLKr1</twBEL></twPathDel><twLogDel>0.293</twLogDel><twRouteDel>0.148</twRouteDel><twTotDel>0.441</twTotDel><twDestClk twEdge ="twFalling" twArriveTime ="5.000">CPUCLKi</twDestClk><twPctLog>66.4</twPctLog><twPctRoute>33.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point CPUCLK (OLOGIC_X0Y46.D1), 1 path
|
||
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</twPathRptBanner><twPathRpt anchorID="24"><twConstPath anchorID="25" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>6.414</twSlack><twSrc BELType="FF">CPUCLKr1</twSrc><twDest BELType="FF">CPUCLK</twDest><twTotPathDel>1.812</twTotPathDel><twClkSkew dest = "0.604" src = "0.354">-0.250</twClkSkew><twDelConst>5.000</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>CPUCLKr1</twSrc><twDest BELType='FF'>CPUCLK</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X5Y28.CLK</twSrcSite><twSrcClk twEdge ="twFalling" twArriveTime ="15.000">CPUCLKi</twSrcClk><twPathDel><twSite>SLICE_X5Y28.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>CPUCLKr1</twComp><twBEL>CPUCLKr1</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X0Y46.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">1.204</twDelInfo><twComp>CPUCLKr1</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>OLOGIC_X0Y46.CLK0</twSite><twDelType>Tockd</twDelType><twDelInfo twEdge="twFalling">0.410</twDelInfo><twComp>CPUCLK_OBUF</twComp><twBEL>CPUCLK</twBEL></twPathDel><twLogDel>0.608</twLogDel><twRouteDel>1.204</twRouteDel><twTotDel>1.812</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">CPUCLKi</twDestClk><twPctLog>33.6</twPctLog><twPctRoute>66.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point FPUCLK (OLOGIC_X6Y2.D1), 1 path
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</twPathRptBanner><twPathRpt anchorID="26"><twConstPath anchorID="27" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>6.438</twSlack><twSrc BELType="FF">CPUCLKr1</twSrc><twDest BELType="FF">FPUCLK</twDest><twTotPathDel>1.825</twTotPathDel><twClkSkew dest = "0.566" src = "0.327">-0.239</twClkSkew><twDelConst>5.000</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>CPUCLKr1</twSrc><twDest BELType='FF'>FPUCLK</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X5Y28.CLK</twSrcSite><twSrcClk twEdge ="twFalling" twArriveTime ="15.000">CPUCLKi</twSrcClk><twPathDel><twSite>SLICE_X5Y28.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>CPUCLKr1</twComp><twBEL>CPUCLKr1</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X6Y2.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">1.217</twDelInfo><twComp>CPUCLKr1</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>OLOGIC_X6Y2.CLK0</twSite><twDelType>Tockd</twDelType><twDelInfo twEdge="twFalling">0.410</twDelInfo><twComp>FPUCLK_OBUF</twComp><twBEL>FPUCLK</twBEL></twPathDel><twLogDel>0.608</twLogDel><twRouteDel>1.217</twRouteDel><twTotDel>1.825</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">CPUCLKi</twDestClk><twPctLog>33.3</twPctLog><twPctRoute>66.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="28"><twPinLimitBanner>Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout1" derived from
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NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
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divided by 2.00 to 10 nS
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</twPinLimitBanner><twPinLimit anchorID="29" type="MINPERIOD" name="Tbcper_I" slack="7.334" period="10.000" constraintValue="10.000" deviceLimit="2.666" freqLimit="375.094" physResource="instance_name/clkout2_buf/I0" logResource="instance_name/clkout2_buf/I0" locationPin="BUFGMUX_X3Y13.I0" clockNet="instance_name/clkout1"/><twPinLimit anchorID="30" type="MINPERIOD" name="Tockper" slack="7.751" period="10.000" constraintValue="10.000" deviceLimit="2.249" freqLimit="444.642" physResource="CPUCLK_OBUF/CLK0" logResource="CPUCLK/CK0" locationPin="OLOGIC_X0Y46.CLK0" clockNet="CPUCLKi"/><twPinLimit anchorID="31" type="MINPERIOD" name="Tockper" slack="7.751" period="10.000" constraintValue="10.000" deviceLimit="2.249" freqLimit="444.642" physResource="FPUCLK_OBUF/CLK0" logResource="FPUCLK/CK0" locationPin="OLOGIC_X6Y2.CLK0" clockNet="CPUCLKi"/></twPinLimitRpt></twConst><twConst anchorID="32" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS </twConstName><twItemCnt>54</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>5</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>4.697</twMinPer></twConstHead><twPathRptBanner iPaths="30" iCriticalPaths="0" sType="EndPoint">Paths for end point CPU_nSTERM (SLICE_X0Y39.B3), 30 paths
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</twPathRptBanner><twPathRpt anchorID="33"><twConstPath anchorID="34" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>5.303</twSlack><twSrc BELType="FF">LastA_6</twSrc><twDest BELType="FF">CPU_nSTERM</twDest><twTotPathDel>4.515</twTotPathDel><twClkSkew dest = "0.720" src = "0.754">0.034</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>LastA_6</twSrc><twDest BELType='FF'>CPU_nSTERM</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X2Y21.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X2Y21.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>LastA<9></twComp><twBEL>LastA_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y21.B2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.201</twDelInfo><twComp>LastA<6></twComp></twPathDel><twPathDel><twSite>SLICE_X0Y21.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<3></twComp><twBEL>Mcompar_FSB_A[31]_LastA[31]_equal_4_o_lut<1></twBEL><twBEL>Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y22.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X0Y22.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7></twComp><twBEL>Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7></twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y23.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7></twComp></twPathDel><twPathDel><twSite>SLICE_X0Y23.BMUX</twSite><twDelType>Tcinb</twDelType><twDelInfo twEdge="twRising">0.286</twDelInfo><twComp>LastAWR<15></twComp><twBEL>Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<9></twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y39.B3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.631</twDelInfo><twComp>FSB_A[31]_LastA[31]_equal_4_o</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y39.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp><twBEL>CPU_nSTERM_rstpot1</twBEL><twBEL>CPU_nSTERM</twBEL></twPathDel><twLogDel>1.677</twLogDel><twRouteDel>2.838</twRouteDel><twTotDel>4.515</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>37.1</twPctLog><twPctRoute>62.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="35"><twConstPath anchorID="36" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>5.534</twSlack><twSrc BELType="FF">LastA_21</twSrc><twDest BELType="FF">CPU_nSTERM</twDest><twTotPathDel>4.289</twTotPathDel><twClkSkew dest = "0.720" src = "0.749">0.029</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>LastA_21</twSrc><twDest BELType='FF'>CPU_nSTERM</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X2Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X2Y24.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>LastA<21></twComp><twBEL>LastA_21</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y22.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.226</twDelInfo><twComp>LastA<21></twComp></twPathDel><tw
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</twPathRptBanner><twPathRpt anchorID="39"><twConstPath anchorID="40" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>5.724</twSlack><twSrc BELType="FF">LastAWR_11</twSrc><twDest BELType="FF">CPU_nSTERM</twDest><twTotPathDel>4.099</twTotPathDel><twClkSkew dest = "0.720" src = "0.749">0.029</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>LastAWR_11</twSrc><twDest BELType='FF'>CPU_nSTERM</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X1Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X1Y24.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>LastAWR<14></twComp><twBEL>LastAWR_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y24.A2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.231</twDelInfo><twComp>LastAWR<11></twComp></twPathDel><twPathDel><twSite>SLICE_X0Y24.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.474</twDelInfo><twComp>Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3></twComp><twBEL>Mcompar_FSB_A[31]_GND_1_o_equal_5_o_lut<0></twBEL><twBEL>Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y25.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X0Y25.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7></twComp><twBEL>Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7></twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y26.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7></twComp></twPathDel><twPathDel><twSite>SLICE_X0Y26.AMUX</twSite><twDelType>Tcina</twDelType><twDelInfo twEdge="twRising">0.230</twDelInfo><twComp>LastAWR<19></twComp><twBEL>Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<8></twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y39.B4</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.296</twDelInfo><twComp>FSB_A[31]_GND_1_o_equal_5_o</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y39.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp><twBEL>CPU_nSTERM_rstpot1</twBEL><twBEL>CPU_nSTERM</twBEL></twPathDel><twLogDel>1.566</twLogDel><twRouteDel>2.533</twRouteDel><twTotDel>4.099</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>38.2</twPctLog><twPctRoute>61.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="41"><twConstPath anchorID="42" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>5.878</twSlack><twSrc BELType="FF">LastAWR_23</twSrc><twDest BELType="FF">CPU_nSTERM</twDest><twTotPathDel>3.943</twTotPathDel><twClkSkew dest = "0.720" src = "0.751">0.031</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>LastAWR_23</twSrc><twDest BELType='FF'>CPU_nSTERM</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X1Y25.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X1Y25.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>LastAWR<26></twComp><twBEL>LastAWR_23</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y25.A2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.171</twDelInfo><twComp>LastAWR<23></twComp></twPath
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</twPathRptBanner><twPathRpt anchorID="45"><twConstPath anchorID="46" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>8.834</twSlack><twSrc BELType="FF">nRESOE</twSrc><twDest BELType="FF">nRESOE</twDest><twTotPathDel>1.018</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>nRESOE</twSrc><twDest BELType='FF'>nRESOE</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X0Y56.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X0Y56.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>nRESOE_OBUF</twComp><twBEL>nRESOE</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y56.D6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.154</twDelInfo><twComp>nRESOE_OBUF</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y56.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>nRESOE_OBUF</twComp><twBEL>nRESOE_rstpot1_INV_0</twBEL><twBEL>nRESOE</twBEL></twPathDel><twLogDel>0.864</twLogDel><twRouteDel>0.154</twRouteDel><twTotDel>1.018</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>84.9</twPctLog><twPctRoute>15.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: PERIOD analysis for net "instance_name/clkout0" derived from
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NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
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divided by 2.00 to 10 nS
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</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point LE (SLICE_X10Y2.A6), 1 path
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</twPathRptBanner><twPathRpt anchorID="47"><twConstPath anchorID="48" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.414</twSlack><twSrc BELType="FF">LE</twSrc><twDest BELType="FF">LE</twDest><twTotPathDel>0.414</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>LE</twSrc><twDest BELType='FF'>LE</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X10Y2.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X10Y2.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>LE</twComp><twBEL>LE</twBEL></twPathDel><twPathDel><twSite>SLICE_X10Y2.A6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.024</twDelInfo><twComp>LE</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X10Y2.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>LE</twComp><twBEL>LE_rstpot1_INV_0</twBEL><twBEL>LE</twBEL></twPathDel><twLogDel>0.390</twLogDel><twRouteDel>0.024</twRouteDel><twTotDel>0.414</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>94.2</twPctLog><twPctRoute>5.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point nRESOE (SLICE_X0Y56.D6), 1 path
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</twPathRptBanner><twPathRpt anchorID="49"><twConstPath anchorID="50" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.456</twSlack><twSrc BELType="FF">nRESOE</twSrc><twDest BELType="FF">nRESOE</twDest><twTotPathDel>0.456</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>nRESOE</twSrc><twDest BELType='FF'>nRESOE</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X0Y56.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X0Y56.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>nRESOE_OBUF</twComp><twBEL>nRESOE</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y56.D6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.025</twDelInfo><twComp>nRESOE_OBUF</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X0Y56.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.197</twDelInfo><twComp>nRESOE_OBUF</twComp><twBEL>nRESOE_rstpot1_INV_0</twBEL><twBEL>nRESOE</twBEL></twPathDel><twLogDel>0.431</twLogDel><twRouteDel>0.025</twRouteDel><twTotDel>0.456</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>94.5</twPctLog><twPctRoute>5.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point CPUCLKr0 (SLICE_X4Y28.A6), 1 path
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</twPathRptBanner><twPathRpt anchorID="51"><twConstPath anchorID="52" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.456</twSlack><twSrc BELType="FF">CPUCLKr0</twSrc><twDest BELType="FF">CPUCLKr0</twDest><twTotPathDel>0.456</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>CPUCLKr0</twSrc><twDest BELType='FF'>CPUCLKr0</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X4Y28.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X4Y28.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>CPUCLKr0</twComp><twBEL>CPUCLKr0</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y28.A6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.025</twDelInfo><twComp>CPUCLKr0</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X4Y28.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.197</twDelInfo><twComp>CPUCLKr0</twComp><twBEL>CPUCLKr0_INV_2_o1_INV_0</twBEL><twBEL>CPUCLKr0</twBEL></twPathDel><twLogDel>0.431</twLogDel><twRouteDel>0.025</twRouteDel><twTotDel>0.456</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>94.5</twPctLog><twPctRoute>5.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="53"><twPinLimitBanner>Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout0" derived from
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NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
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divided by 2.00 to 10 nS
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</twPinLimitBanner><twPinLimit anchorID="54" type="MINPERIOD" name="Tbcper_I" slack="7.334" period="10.000" constraintValue="10.000" deviceLimit="2.666" freqLimit="375.094" physResource="instance_name/clkout1_buf/I0" logResource="instance_name/clkout1_buf/I0" locationPin="BUFGMUX_X2Y2.I0" clockNet="instance_name/clkout0"/><twPinLimit anchorID="55" type="MINPERIOD" name="Tockper" slack="7.751" period="10.000" constraintValue="10.000" deviceLimit="2.249" freqLimit="444.642" physResource="CPU_nBERR_OBUF/CLK0" logResource="CPU_nBERR/CK0" locationPin="OLOGIC_X0Y49.CLK0" clockNet="FSBCLK"/><twPinLimit anchorID="56" type="MINPERIOD" name="Tockper" slack="7.751" period="10.000" constraintValue="10.000" deviceLimit="2.249" freqLimit="444.642" physResource="RAM_CLK01_OBUF/CLK0" logResource="RAM_CLK01_ODDR_inst/CK0" locationPin="OLOGIC_X0Y51.CLK0" clockNet="FSBCLK"/></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="57"><twConstRollup name="instance_name/clkin1" fullName="NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="5.000" actualRollup="14.164" errors="0" errorRollup="0" items="0" itemsRollup="57"/><twConstRollup name="instance_name/clkfbout" fullName="PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS " type="child" depth="1" requirement="20.000" prefType="period" actual="2.666" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="instance_name/clkout1" fullName="PERIOD analysis for net "instance_name/clkout1" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS " type="child" depth="1" requirement="10.000" prefType="period" actual="7.082" actualRollup="N/A" errors="0" errorRollup="0" items="3" itemsRollup="0"/><twConstRollup name="instance_name/clkout0" fullName="PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS " type="child" depth="1" requirement="10.000" prefType="period" actual="4.697" actualRollup="N/A" errors="0" errorRollup="0" items="54" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="58">0</twUnmetConstCnt><twDataSheet anchorID="59" twNameLen="15"><twClk2SUList anchorID="60" twDestWidth="5"><twDest>CLKIN</twDest><twClk2SU><twSrc>CLKIN</twSrc><twRiseRise>4.697</twRiseRise><twFallRise>3.541</twFallRise><twRiseFall>2.138</twRiseFall></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="61"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>57</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>93</twConnCnt></twConstCov><twStats anchorID="62"><twMinPer>7.082</twMinPer><twFootnote number="1" /><twMaxFreq>141.203</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Fri Oct 29 10:03:09 2021 </twTimestamp></twFoot><twClientInfo anchorID="63"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
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Peak Memory Usage: 168 MB
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</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
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