mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2025-02-19 18:31:12 +00:00
screwing around
This commit is contained in:
Zane Kaminski
parent
55c77e7fba
commit
8c91d823f7
6
fpga/PLL.ucf
Normal file
6
fpga/PLL.ucf
Normal file
@ -0,0 +1,6 @@
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NET CLKFB_OUT FEEDBACK = 160ps NET CLKFB_IN;
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NET FSBCLK FEEDBACK = 160ps NET CLKFB_IN;
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NET CPUCLKi FEEDBACK = 160ps NET CLKFB_IN;
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NET nRESOE SLEW = "QUIETIO";
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NET CLKIN PERIOD = 20ns HIGH;
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NET CPU_nAS OFFSET = IN 10ns VALID 11ns BEFORE FSBCLK;
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865
fpga/WarpLC.bld
Normal file
865
fpga/WarpLC.bld
Normal file
@ -0,0 +1,865 @@
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Release 14.7 ngdbuild P.20131013 (nt)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
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ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2
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WarpLC.ngc WarpLC.ngd
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Reading NGO file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.ngc" ...
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Gathering constraint information from source properties...
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Done.
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Annotating constraints to design from ucf file "PLL.ucf" ...
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Resolving constraint associations...
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Checking Constraint Associations...
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<9>" IOBDELAY = NONE>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<9>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<9>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<9>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<10>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<10>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<10>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<10>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<11>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<11>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<11>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<11>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<12>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<12>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<12>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<12>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<13>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<13>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<13>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<13>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<14>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<14>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<14>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<14>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<15>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<15>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<15>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<15>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<16>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<16>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<16>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<16>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<17>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<17>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<17>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<17>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<18>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<18>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<18>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<18>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<19>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<19>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<19>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<19>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<20>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<20>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<20>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<20>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<21>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<21>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<21>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<21>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<22>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<22>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<22>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<22>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<23>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<23>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<23>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<23>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<24>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<24>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<24>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<24>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<25>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<25>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<25>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<25>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<26>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<26>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<26>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<26>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<27>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<27>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<27>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<27>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<28>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<28>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<28>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<28>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<29>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<29>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<29>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<29>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<30>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<30>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<30>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<30>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<31>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<31>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<31>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<31>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "IOB_nBERR" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/IOB_nBERR' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "IOBCLK" IOBDELAY = NONE>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/IOBCLK' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "nRES" IOBDELAY = NONE>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/nRES' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nCBREQ" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/CPU_nCBREQ' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nDS" IOBDELAY = NONE>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/CPU_nDS' because those design objects do not
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contain or drive any instances of the correct type.
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|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nECS" IOBDELAY = NONE>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/CPU_nECS' because those design objects do not
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contain or drive any instances of the correct type.
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||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nCIOUT" IOBDELAY = NONE>:
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||||
This constraint cannot be distributed from the design objects matching 'NET:
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||||
UniqueName: /WarpLC/EXPANDED/CPU_nCIOUT' because those design objects do not
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contain or drive any instances of the correct type.
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||||
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||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_nDSACK<0>" IOBDELAY = NONE>:
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||||
This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/IOB_nDSACK<0>' because those design objects do
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not contain or drive any instances of the correct type.
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||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_nDSACK<1>" IOBDELAY = NONE>:
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||||
This constraint cannot be distributed from the design objects matching 'NET:
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||||
UniqueName: /WarpLC/EXPANDED/IOB_nDSACK<1>' because those design objects do
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not contain or drive any instances of the correct type.
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||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_SIZ<0>" IOBDELAY = NONE>:
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||||
This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_SIZ<0>' because those design objects do not
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||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_SIZ<1>" IOBDELAY = NONE>:
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||||
This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_SIZ<1>' because those design objects do not
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contain or drive any instances of the correct type.
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||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<0>" IOBDELAY = NONE>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_A<0>' because those design objects do not
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contain or drive any instances of the correct type.
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|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_CLK23" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/RAM_CLK23' because those design objects do not
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contain or drive any instances of the correct type.
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|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_CKE" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/RAM_CKE' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "RAM_nWE" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/RAM_nWE' because those design objects do not
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contain or drive any instances of the correct type.
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||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_nCAS" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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||||
UniqueName: /WarpLC/EXPANDED/RAM_nCAS' because those design objects do not
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contain or drive any instances of the correct type.
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||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_nRAS" SLEW = FAST>: This
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||||
constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/RAM_nRAS' because those design objects do not
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||||
contain or drive any instances of the correct type.
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||||
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||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_nCS" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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||||
UniqueName: /WarpLC/EXPANDED/RAM_nCS' because those design objects do not
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||||
contain or drive any instances of the correct type.
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||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nCIIN" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nCIIN' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nCBACK" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nCBACK' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_DDIR" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_DDIR' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nDOE" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nDOE' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nDSACKOE" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nDSACKOE' because those design objects do
|
||||
not contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_nRMC" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_nRMC' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<0>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<1>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<2>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<2>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<3>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<3>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<4>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<4>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<5>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<5>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<6>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<6>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<7>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<7>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<8>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<8>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<9>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<9>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<10>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<10>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<11>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<11>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<12>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<12>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<13>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<13>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<14>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<14>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<15>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<15>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<16>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<16>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<17>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<17>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<18>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<18>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<19>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<19>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<20>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<20>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<21>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<21>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<22>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<22>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<23>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<23>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<24>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<24>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<25>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<25>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<26>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<26>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<27>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<27>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<28>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<28>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<29>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<29>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<30>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<30>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<31>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<31>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_DQM<0>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_DQM<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_DQM<1>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_DQM<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_DQM<2>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_DQM<2>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_DQM<3>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_DQM<3>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<0>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<1>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<2>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<2>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<3>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<3>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<4>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<4>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<5>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<5>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<6>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<6>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<7>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<7>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<8>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<8>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<9>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<9>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<10>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<10>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<11>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<11>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<12>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<12>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_BA<0>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_BA<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_BA<1>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_BA<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<0>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<0>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<1>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<1>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<2>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<2>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<2>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<2>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<3>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<3>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<3>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<3>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<4>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<4>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<4>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<4>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<5>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<5>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<5>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<5>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<6>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<6>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<6>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<6>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<7>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<7>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<7>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<7>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<8>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<8>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<8>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<8>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:130 - Constraint <NET FSBCLK FEEDBACK = 160ps NET
|
||||
CLKFB_IN;> [PLL.ucf(2)]: NET "FSBCLK" is not connected to an input or output
|
||||
pad.
|
||||
|
||||
WARNING:ConstraintSystem:85 - Constraint <NET FSBCLK FEEDBACK = 160ps NET
|
||||
CLKFB_IN;> [PLL.ucf(2)]: This constraint will be ignored because NET "FSBCLK"
|
||||
could not be found.
|
||||
|
||||
WARNING:ConstraintSystem:130 - Constraint <NET CPUCLKi FEEDBACK = 160ps NET
|
||||
CLKFB_IN;> [PLL.ucf(3)]: NET "CPUCLKi" is not connected to an input or output
|
||||
pad.
|
||||
|
||||
WARNING:ConstraintSystem:85 - Constraint <NET CPUCLKi FEEDBACK = 160ps NET
|
||||
CLKFB_IN;> [PLL.ucf(3)]: This constraint will be ignored because NET
|
||||
"CPUCLKi" could not be found.
|
||||
|
||||
WARNING:ConstraintSystem:168 - Constraint <NET CPU_nAS OFFSET = IN 10ns VALID
|
||||
11ns BEFORE FSBCLK;> [PLL.ucf(6)]: This constraint will be ignored because
|
||||
NET "FSBCLK" could not be found or was not connected to a PAD.
|
||||
|
||||
INFO:ConstraintSystem - The Period constraint <NET CLKIN PERIOD = 20ns HIGH;>
|
||||
[PLL.ucf(5)], is specified using the Net Period method which is not
|
||||
recommended. Please use the Timespec PERIOD method.
|
||||
|
||||
Done...
|
||||
|
||||
Checking expanded design ...
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_A<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<31>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<30>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<29>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<28>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<27>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<26>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<25>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<24>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<23>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<22>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<21>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<20>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<19>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<18>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<17>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<16>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<15>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<14>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<13>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<12>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<11>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<10>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<9>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<8>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<7>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<6>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<5>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<4>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<3>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<2>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_BA<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_BA<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<12>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<11>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<10>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<9>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<8>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<7>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<6>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<5>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<4>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<3>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<2>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_DQM<3>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_DQM<2>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_DQM<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_DQM<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_A<3>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_A<2>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_A<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_A<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_SIZ<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_SIZ<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<31>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<30>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<29>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<28>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<27>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<26>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<25>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<24>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<23>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<22>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<21>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<20>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<19>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<18>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<17>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<16>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<15>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<14>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<13>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<12>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<11>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<10>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<9>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<8>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<7>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<6>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<5>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<4>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<3>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<2>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_nRMC' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_nAOE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_nDSACKOE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_nDOE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_DDIR' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_nCBACK' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_nCIIN' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_nHALT' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_nCS' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_nRAS' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_nCAS' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_nWE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_CKE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_CLK23' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_nAOE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_ADoutLE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_nAS' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_nDS' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_nDOE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_DDIR' has no driver
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
NGDBUILD Design Results Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 254
|
||||
|
||||
Total memory usage is 134032 kilobytes
|
||||
|
||||
Writing NGD file "WarpLC.ngd" ...
|
||||
Total REAL time to NGDBUILD completion: 3 sec
|
||||
Total CPU time to NGDBUILD completion: 1 sec
|
||||
|
||||
Writing NGDBUILD log file "WarpLC.bld"...
|
||||
281
fpga/WarpLC.cmd_log
Normal file
281
fpga/WarpLC.cmd_log
Normal file
@ -0,0 +1,281 @@
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
191
fpga/WarpLC.gise
Normal file
191
fpga/WarpLC.gise
Normal file
@ -0,0 +1,191 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="WarpLC.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="WarpLC.bld"/>
|
||||
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="WarpLC.cmd_log"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="WarpLC.lso"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="WarpLC.ncd" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="WarpLC.ngc"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="WarpLC.ngd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="WarpLC.ngr"/>
|
||||
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="WarpLC.pad"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="WarpLC.par" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="WarpLC.pcf" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="WarpLC.prj"/>
|
||||
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="WarpLC.ptwx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="WarpLC.stx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="WarpLC.syr"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="WarpLC.twr" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="WarpLC.twx" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="WarpLC.unroutes" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:fileType="FILE_XPI" xil_pn:name="WarpLC.xpi"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="WarpLC.xst"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="WarpLC_envsettings.html"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="WarpLC_fpga_editor.log"/>
|
||||
<file xil_pn:fileType="FILE_NCD" xil_pn:name="WarpLC_guide.ncd" xil_pn:origination="imported"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="WarpLC_map.map" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="WarpLC_map.mrp" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="WarpLC_map.ncd" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="WarpLC_map.ngm" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="WarpLC_map.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="WarpLC_ngdbuild.xrpt"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="WarpLC_pad.csv" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="WarpLC_pad.txt" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="WarpLC_par.xrpt"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="WarpLC_preroute.twr" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="WarpLC_preroute.twx" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="WarpLC_summary.html"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="WarpLC_summary.xml"/>
|
||||
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="WarpLC_usage.xml"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="WarpLC_xst.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635516166">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3515295135630071778" xil_pn:start_ts="1635516166">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:in_ck="-7186897629097209311" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4864019295268560826" xil_pn:start_ts="1635516166">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="ipcore_dir/CLK.v"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:in_ck="2640051198016270512" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635516166">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6691162141195559328" xil_pn:start_ts="1635516166">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:in_ck="2640051198016270512" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745411629038" xil_pn:start_ts="1635516166">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="5917552782042024336" xil_pn:start_ts="1635516166">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516171" xil_pn:in_ck="-5185463249901030118" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7414298865524902037" xil_pn:start_ts="1635516166">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="WarpLC.lso"/>
|
||||
<outfile xil_pn:name="WarpLC.ngc"/>
|
||||
<outfile xil_pn:name="WarpLC.ngr"/>
|
||||
<outfile xil_pn:name="WarpLC.prj"/>
|
||||
<outfile xil_pn:name="WarpLC.stx"/>
|
||||
<outfile xil_pn:name="WarpLC.syr"/>
|
||||
<outfile xil_pn:name="WarpLC.xst"/>
|
||||
<outfile xil_pn:name="WarpLC_xst.xrpt"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516171" xil_pn:in_ck="-7789573454286277367" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704523" xil_pn:start_ts="1635516171">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516176" xil_pn:in_ck="5584679923051828355" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2511870374322119143" xil_pn:start_ts="1635516171">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="WarpLC.bld"/>
|
||||
<outfile xil_pn:name="WarpLC.ngd"/>
|
||||
<outfile xil_pn:name="WarpLC_ngdbuild.xrpt"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516182" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="111412226054857016" xil_pn:start_ts="1635516176">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="WarpLC.pcf"/>
|
||||
<outfile xil_pn:name="WarpLC_map.map"/>
|
||||
<outfile xil_pn:name="WarpLC_map.mrp"/>
|
||||
<outfile xil_pn:name="WarpLC_map.ncd"/>
|
||||
<outfile xil_pn:name="WarpLC_map.ngm"/>
|
||||
<outfile xil_pn:name="WarpLC_map.xrpt"/>
|
||||
<outfile xil_pn:name="WarpLC_summary.xml"/>
|
||||
<outfile xil_pn:name="WarpLC_usage.xml"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516187" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1635516182">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="WarpLC.ncd"/>
|
||||
<outfile xil_pn:name="WarpLC.pad"/>
|
||||
<outfile xil_pn:name="WarpLC.par"/>
|
||||
<outfile xil_pn:name="WarpLC.ptwx"/>
|
||||
<outfile xil_pn:name="WarpLC.unroutes"/>
|
||||
<outfile xil_pn:name="WarpLC.xpi"/>
|
||||
<outfile xil_pn:name="WarpLC_pad.csv"/>
|
||||
<outfile xil_pn:name="WarpLC_pad.txt"/>
|
||||
<outfile xil_pn:name="WarpLC_par.xrpt"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635505623" xil_pn:in_ck="4179226981374028" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1635505621">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516191" xil_pn:in_ck="5584679923051828224" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1635516187">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="WarpLC.twr"/>
|
||||
<outfile xil_pn:name="WarpLC.twx"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635510526" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791352" xil_pn:start_ts="1635510523">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
1
fpga/WarpLC.lso
Normal file
1
fpga/WarpLC.lso
Normal file
@ -0,0 +1 @@
|
||||
work
|
||||
3
fpga/WarpLC.ncd
Normal file
3
fpga/WarpLC.ncd
Normal file
File diff suppressed because one or more lines are too long
3
fpga/WarpLC.ngc
Normal file
3
fpga/WarpLC.ngc
Normal file
File diff suppressed because one or more lines are too long
3
fpga/WarpLC.ngd
Normal file
3
fpga/WarpLC.ngd
Normal file
File diff suppressed because one or more lines are too long
3
fpga/WarpLC.ngr
Normal file
3
fpga/WarpLC.ngr
Normal file
File diff suppressed because one or more lines are too long
286
fpga/WarpLC.pad
Normal file
286
fpga/WarpLC.pad
Normal file
@ -0,0 +1,286 @@
|
||||
Release 14.7 - par P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Fri Oct 29 10:03:06 2021
|
||||
|
||||
|
||||
# NOTE: This file is designed to be imported into a spreadsheet program
|
||||
# such as Microsoft Excel for viewing, printing and sorting. The |
|
||||
# character is used as the data field separator. This file is also designed
|
||||
# to support parsing.
|
||||
#
|
||||
INPUT FILE: WarpLC_map.ncd
|
||||
OUTPUT FILE: WarpLC.pad
|
||||
PART TYPE: xc6slx9
|
||||
SPEED GRADE: -2
|
||||
PACKAGE: ftg256
|
||||
|
||||
Pinout by Pin Number:
|
||||
|
||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
|
||||
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
|
||||
A1|||GND||||||||||||
|
||||
A2|CLKFB_OUT|IOB|IO_L52N_M3A9_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
A3||IOBS|IO_L83N_VREF_3|UNUSED||3|||||||||
|
||||
A4||IOBS|IO_L1N_VREF_0|UNUSED||0|||||||||
|
||||
A5||IOBS|IO_L2N_0|UNUSED||0|||||||||
|
||||
A6||IOBS|IO_L4N_0|UNUSED||0|||||||||
|
||||
A7||IOBS|IO_L6N_0|UNUSED||0|||||||||
|
||||
A8||IOBS|IO_L33N_0|UNUSED||0|||||||||
|
||||
A9||IOBS|IO_L34N_GCLK18_0|UNUSED||0|||||||||
|
||||
A10||IOBS|IO_L35N_GCLK16_0|UNUSED||0|||||||||
|
||||
A11||IOBS|IO_L39N_0|UNUSED||0|||||||||
|
||||
A12||IOBS|IO_L62N_VREF_0|UNUSED||0|||||||||
|
||||
A13||IOBS|IO_L63N_SCP6_0|UNUSED||0|||||||||
|
||||
A14||IOBS|IO_L65N_SCP2_0|UNUSED||0|||||||||
|
||||
A15|||TMS||||||||||||
|
||||
A16|||GND||||||||||||
|
||||
B1|CPUCLK|IOB|IO_L50N_M3BA2_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
B2|RAM_CLK01|IOB|IO_L52P_M3A8_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
B3||IOBM|IO_L83P_3|UNUSED||3|||||||||
|
||||
B4|||VCCO_0|||0|||||any******||||
|
||||
B5||IOBM|IO_L2P_0|UNUSED||0|||||||||
|
||||
B6||IOBM|IO_L4P_0|UNUSED||0|||||||||
|
||||
B7|||GND||||||||||||
|
||||
B8||IOBM|IO_L33P_0|UNUSED||0|||||||||
|
||||
B9|||VCCO_0|||0|||||any******||||
|
||||
B10||IOBM|IO_L35P_GCLK17_0|UNUSED||0|||||||||
|
||||
B11|||GND||||||||||||
|
||||
B12||IOBM|IO_L62P_0|UNUSED||0|||||||||
|
||||
B13|||VCCO_0|||0|||||any******||||
|
||||
B14||IOBM|IO_L65P_SCP3_0|UNUSED||0|||||||||
|
||||
B15||IOBM|IO_L29P_A23_M1A13_1|UNUSED||1|||||||||
|
||||
B16||IOBS|IO_L29N_A22_M1A14_1|UNUSED||1|||||||||
|
||||
C1|CPU_nDSACK|IOB|IO_L50P_M3WE_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|NO|NONE|
|
||||
C2|CPU_nSTERM|IOB|IO_L48N_M3BA1_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|NO|NONE|
|
||||
C3|FSB_FC<2>|IOB|IO_L48P_M3BA0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
C4||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0|||||||||
|
||||
C5||IOBS|IO_L3N_0|UNUSED||0|||||||||
|
||||
C6||IOBS|IO_L7N_0|UNUSED||0|||||||||
|
||||
C7||IOBM|IO_L6P_0|UNUSED||0|||||||||
|
||||
C8||IOBS|IO_L38N_VREF_0|UNUSED||0|||||||||
|
||||
C9||IOBM|IO_L34P_GCLK19_0|UNUSED||0|||||||||
|
||||
C10||IOBS|IO_L37N_GCLK12_0|UNUSED||0|||||||||
|
||||
C11||IOBM|IO_L39P_0|UNUSED||0|||||||||
|
||||
C12|||TDI||||||||||||
|
||||
C13||IOBM|IO_L63P_SCP7_0|UNUSED||0|||||||||
|
||||
C14|||TCK||||||||||||
|
||||
C15||IOBM|IO_L33P_A15_M1A10_1|UNUSED||1|||||||||
|
||||
C16||IOBS|IO_L33N_A14_M1A4_1|UNUSED||1|||||||||
|
||||
D1|FSB_RnW|IOB|IO_L49N_M3A2_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
D2|||VCCO_3|||3|||||3.30||||
|
||||
D3|CPU_nAS|IOB|IO_L49P_M3A7_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
D4|||GND||||||||||||
|
||||
D5||IOBM|IO_L3P_0|UNUSED||0|||||||||
|
||||
D6||IOBM|IO_L7P_0|UNUSED||0|||||||||
|
||||
D7|||VCCO_0|||0|||||any******||||
|
||||
D8||IOBM|IO_L38P_0|UNUSED||0|||||||||
|
||||
D9||IOBS|IO_L40N_0|UNUSED||0|||||||||
|
||||
D10|||VCCO_0|||0|||||any******||||
|
||||
D11||IOBM|IO_L66P_SCP1_0|UNUSED||0|||||||||
|
||||
D12||IOBS|IO_L66N_SCP0_0|UNUSED||0|||||||||
|
||||
D13|||GND||||||||||||
|
||||
D14||IOBM|IO_L31P_A19_M1CKE_1|UNUSED||1|||||||||
|
||||
D15|||VCCO_1|||1|||||any******||||
|
||||
D16||IOBS|IO_L31N_A18_M1A12_1|UNUSED||1|||||||||
|
||||
E1|nFPUCS|IOB|IO_L46N_M3CLKN_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|NO|NONE|
|
||||
E2|FSB_A<31>|IOB|IO_L46P_M3CLK_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
E3||IOBS|IO_L54N_M3A11_3|UNUSED||3|||||||||
|
||||
E4||IOBM|IO_L54P_M3RESET_3|UNUSED||3|||||||||
|
||||
E5|||VCCAUX||||||||2.5||||
|
||||
E6||IOBS|IO_L5N_0|UNUSED||0|||||||||
|
||||
E7||IOBM|IO_L36P_GCLK15_0|UNUSED||0|||||||||
|
||||
E8||IOBS|IO_L36N_GCLK14_0|UNUSED||0|||||||||
|
||||
E9|||GND||||||||||||
|
||||
E10||IOBM|IO_L37P_GCLK13_0|UNUSED||0|||||||||
|
||||
E11||IOBS|IO_L64N_SCP4_0|UNUSED||0|||||||||
|
||||
E12||IOBS|IO_L1N_A24_VREF_1|UNUSED||1|||||||||
|
||||
E13||IOBM|IO_L1P_A25_1|UNUSED||1|||||||||
|
||||
E14|||TDO||||||||||||
|
||||
E15||IOBM|IO_L34P_A13_M1WE_1|UNUSED||1|||||||||
|
||||
E16||IOBS|IO_L34N_A12_M1BA2_1|UNUSED||1|||||||||
|
||||
F1|FSB_A<27>|IOB|IO_L41N_GCLK26_M3DQ5_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
F2|FSB_A<25>|IOB|IO_L41P_GCLK27_M3DQ4_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
F3|nRESOE|IOB|IO_L53N_M3A12_3|OUTPUT|LVCMOS33|3|2|QUIETIO||||UNLOCATED|NO|NONE|
|
||||
F4||IOBM|IO_L53P_M3CKE_3|UNUSED||3|||||||||
|
||||
F5||IOBS|IO_L55N_M3A14_3|UNUSED||3|||||||||
|
||||
F6||IOBM|IO_L55P_M3A13_3|UNUSED||3|||||||||
|
||||
F7||IOBM|IO_L5P_0|UNUSED||0|||||||||
|
||||
F8|||VCCAUX||||||||2.5||||
|
||||
F9||IOBM|IO_L40P_0|UNUSED||0|||||||||
|
||||
F10||IOBM|IO_L64P_SCP5_0|UNUSED||0|||||||||
|
||||
F11|||VCCAUX||||||||2.5||||
|
||||
F12||IOBM|IO_L30P_A21_M1RESET_1|UNUSED||1|||||||||
|
||||
F13||IOBM|IO_L32P_A17_M1A8_1|UNUSED||1|||||||||
|
||||
F14||IOBS|IO_L32N_A16_M1A9_1|UNUSED||1|||||||||
|
||||
F15||IOBM|IO_L35P_A11_M1A7_1|UNUSED||1|||||||||
|
||||
F16||IOBS|IO_L35N_A10_M1A2_1|UNUSED||1|||||||||
|
||||
G1|FSB_A<15>|IOB|IO_L40N_M3DQ7_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
G2|||GND||||||||||||
|
||||
G3|FSB_A<16>|IOB|IO_L40P_M3DQ6_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
G4|||VCCO_3|||3|||||3.30||||
|
||||
G5|CPUCLKIN|IOB|IO_L51N_M3A4_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
G6|CPU_nBERR|IOB|IO_L51P_M3A10_3|OUTPUT|LVCMOS33|3|2|SLOW||||UNLOCATED|YES|NONE|
|
||||
G7|||VCCINT||||||||1.2||||
|
||||
G8|||GND||||||||||||
|
||||
G9|||VCCINT||||||||1.2||||
|
||||
G10|||VCCAUX||||||||2.5||||
|
||||
G11||IOBS|IO_L30N_A20_M1A11_1|UNUSED||1|||||||||
|
||||
G12||IOBM|IO_L38P_A5_M1CLK_1|UNUSED||1|||||||||
|
||||
G13|||VCCO_1|||1|||||any******||||
|
||||
G14||IOBM|IO_L36P_A9_M1BA0_1|UNUSED||1|||||||||
|
||||
G15|||GND||||||||||||
|
||||
G16||IOBS|IO_L36N_A8_M1BA1_1|UNUSED||1|||||||||
|
||||
H1|FSB_A<20>|IOB|IO_L39N_M3LDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H2|FSB_A<22>|IOB|IO_L39P_M3LDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H3|FSB_A<28>|IOB|IO_L44N_GCLK20_M3A6_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H4|CLKFB_IN|IOB|IO_L44P_GCLK21_M3A5_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H5|FSB_A<19>|IOB|IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H6|||VCCAUX||||||||2.5||||
|
||||
H7|||GND||||||||||||
|
||||
H8|||VCCINT||||||||1.2||||
|
||||
H9|||GND||||||||||||
|
||||
H10|||VCCINT||||||||1.2||||
|
||||
H11||IOBS|IO_L38N_A4_M1CLKN_1|UNUSED||1|||||||||
|
||||
H12|||GND||||||||||||
|
||||
H13||IOBM|IO_L39P_M1A3_1|UNUSED||1|||||||||
|
||||
H14||IOBS|IO_L39N_M1ODT_1|UNUSED||1|||||||||
|
||||
H15||IOBM|IO_L37P_A7_M1A0_1|UNUSED||1|||||||||
|
||||
H16||IOBS|IO_L37N_A6_M1A1_1|UNUSED||1|||||||||
|
||||
J1|FSB_A<23>|IOB|IO_L38N_M3DQ3_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J2|||VCCO_3|||3|||||3.30||||
|
||||
J3|FSB_A<17>|IOB|IO_L38P_M3DQ2_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J4|CLKIN|IOB|IO_L42N_GCLK24_M3LDM_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J5|||GND||||||||||||
|
||||
J6|FSB_A<26>|IOB|IO_L43P_GCLK23_M3RASN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J7|||VCCINT||||||||1.2||||
|
||||
J8|||GND||||||||||||
|
||||
J9|||VCCINT||||||||1.2||||
|
||||
J10|||VCCAUX||||||||2.5||||
|
||||
J11||IOBM|IO_L40P_GCLK11_M1A5_1|UNUSED||1|||||||||
|
||||
J12||IOBS|IO_L40N_GCLK10_M1A6_1|UNUSED||1|||||||||
|
||||
J13||IOBM|IO_L41P_GCLK9_IRDY1_M1RASN_1|UNUSED||1|||||||||
|
||||
J14||IOBM|IO_L43P_GCLK5_M1DQ4_1|UNUSED||1|||||||||
|
||||
J15|||VCCO_1|||1|||||any******||||
|
||||
J16||IOBS|IO_L43N_GCLK4_M1DQ5_1|UNUSED||1|||||||||
|
||||
K1|FSB_A<21>|IOB|IO_L37N_M3DQ1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K2|FSB_A<24>|IOB|IO_L37P_M3DQ0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K3|FSB_A<18>|IOB|IO_L42P_GCLK25_TRDY2_M3UDM_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K4|||VCCO_3|||3|||||3.30||||
|
||||
K5|FSB_FC<0>|IOB|IO_L47P_M3A0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K6|FSB_FC<1>|IOB|IO_L47N_M3A1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K7|||GND||||||||||||
|
||||
K8|||VCCINT||||||||1.2||||
|
||||
K9|||GND||||||||||||
|
||||
K10|||VCCINT||||||||1.2||||
|
||||
K11||IOBS|IO_L42N_GCLK6_TRDY1_M1LDM_1|UNUSED||1|||||||||
|
||||
K12||IOBM|IO_L42P_GCLK7_M1UDM_1|UNUSED||1|||||||||
|
||||
K13|||VCCO_1|||1|||||any******||||
|
||||
K14||IOBS|IO_L41N_GCLK8_M1CASN_1|UNUSED||1|||||||||
|
||||
K15||IOBM|IO_L44P_A3_M1DQ6_1|UNUSED||1|||||||||
|
||||
K16||IOBS|IO_L44N_A2_M1DQ7_1|UNUSED||1|||||||||
|
||||
L1|FSB_A<14>|IOB|IO_L36N_M3DQ9_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L2|||GND||||||||||||
|
||||
L3|FSB_A<13>|IOB|IO_L36P_M3DQ8_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L4|FSB_A<29>|IOB|IO_L45P_M3A3_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L5|FSB_A<30>|IOB|IO_L45N_M3ODT_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L6|||VCCAUX||||||||2.5||||
|
||||
L7||IOBS|IO_L62N_D6_2|UNUSED||2|||||||||
|
||||
L8||IOBM|IO_L62P_D5_2|UNUSED||2|||||||||
|
||||
L9|||VCCAUX||||||||2.5||||
|
||||
L10||IOBM|IO_L16P_2|UNUSED||2|||||||||
|
||||
L11|||CMPCS_B_2||||||||||||
|
||||
L12||IOBM|IO_L53P_1|UNUSED||1|||||||||
|
||||
L13||IOBS|IO_L53N_VREF_1|UNUSED||1|||||||||
|
||||
L14||IOBM|IO_L47P_FWE_B_M1DQ0_1|UNUSED||1|||||||||
|
||||
L15|||GND||||||||||||
|
||||
L16||IOBS|IO_L47N_LDC_M1DQ1_1|UNUSED||1|||||||||
|
||||
M1|FSB_A<12>|IOB|IO_L35N_M3DQ11_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M2|FSB_A<11>|IOB|IO_L35P_M3DQ10_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M3|FSB_A<2>|IOB|IO_L1N_VREF_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M4|FSB_A<1>|IOB|IO_L1P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M5|FSB_A<3>|IOB|IO_L2P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M6||IOBM|IO_L64P_D8_2|UNUSED||2|||||||||
|
||||
M7||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2|||||||||
|
||||
M8|||GND||||||||||||
|
||||
M9||IOBM|IO_L29P_GCLK3_2|UNUSED||2|||||||||
|
||||
M10||IOBS|IO_L16N_VREF_2|UNUSED||2|||||||||
|
||||
M11||IOBS|IO_L2N_CMPMOSI_2|UNUSED||2|||||||||
|
||||
M12||IOBM|IO_L2P_CMPCLK_2|UNUSED||2|||||||||
|
||||
M13||IOBM|IO_L74P_AWAKE_1|UNUSED||1|||||||||
|
||||
M14||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1|||||||||
|
||||
M15||IOBM|IO_L46P_FCS_B_M1DQ2_1|UNUSED||1|||||||||
|
||||
M16||IOBS|IO_L46N_FOE_B_M1DQ3_1|UNUSED||1|||||||||
|
||||
N1|FSB_A<10>|IOB|IO_L34N_M3UDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N2|||VCCO_3|||3|||||3.30||||
|
||||
N3|FSB_A<9>|IOB|IO_L34P_M3UDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N4|FSB_A<4>|IOB|IO_L2N_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N5||IOBM|IO_L49P_D3_2|UNUSED||2|||||||||
|
||||
N6||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
|
||||
N7|||VCCO_2|||2|||||3.30||||
|
||||
N8||IOBS|IO_L29N_GCLK2_2|UNUSED||2|||||||||
|
||||
N9||IOBM|IO_L14P_D11_2|UNUSED||2|||||||||
|
||||
N10|||VCCO_2|||2|||||3.30||||
|
||||
N11||IOBM|IO_L13P_M1_2|UNUSED||2|||||||||
|
||||
N12||IOBM|IO_L12P_D1_MISO2_2|UNUSED||2|||||||||
|
||||
N13|||GND||||||||||||
|
||||
N14||IOBM|IO_L45P_A1_M1LDQS_1|UNUSED||1|||||||||
|
||||
N15|||VCCO_1|||1|||||any******||||
|
||||
N16||IOBS|IO_L45N_A0_M1LDQSN_1|UNUSED||1|||||||||
|
||||
P1|FSB_A<8>|IOB|IO_L33N_M3DQ13_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
P2|FSB_A<7>|IOB|IO_L33P_M3DQ12_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
P3|||GND||||||||||||
|
||||
P4||IOBM|IO_L63P_2|UNUSED||2|||||||||
|
||||
P5||IOBS|IO_L49N_D4_2|UNUSED||2|||||||||
|
||||
P6||IOBM|IO_L47P_2|UNUSED||2|||||||||
|
||||
P7||IOBM|IO_L31P_GCLK31_D14_2|UNUSED||2|||||||||
|
||||
P8||IOBM|IO_L30P_GCLK1_D13_2|UNUSED||2|||||||||
|
||||
P9||IOBS|IO_L14N_D12_2|UNUSED||2|||||||||
|
||||
P10||IOBM|IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED||2|||||||||
|
||||
P11||IOBS|IO_L13N_D10_2|UNUSED||2|||||||||
|
||||
P12||IOBS|IO_L12N_D2_MISO3_2|UNUSED||2|||||||||
|
||||
P13|||DONE_2||||||||||||
|
||||
P14|||SUSPEND||||||||||||
|
||||
P15||IOBM|IO_L48P_HDC_M1DQ8_1|UNUSED||1|||||||||
|
||||
P16||IOBS|IO_L48N_M1DQ9_1|UNUSED||1|||||||||
|
||||
R1|FSB_A<6>|IOB|IO_L32N_M3DQ15_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
R2|FSB_A<5>|IOB|IO_L32P_M3DQ14_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
R3||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
|
||||
R4|||VCCO_2|||2|||||3.30||||
|
||||
R5||IOBM|IO_L48P_D7_2|UNUSED||2|||||||||
|
||||
R6|||GND||||||||||||
|
||||
R7|IOB_nHALT|IOB|IO_L32P_GCLK29_2|INPUT|LVCMOS33|2||||NONE||UNLOCATED|YES|NONE|
|
||||
R8|||VCCO_2|||2|||||3.30||||
|
||||
R9||IOBM|IO_L23P_2|UNUSED||2|||||||||
|
||||
R10|||GND||||||||||||
|
||||
R11||IOBM|IO_L1P_CCLK_2|UNUSED||2|||||||||
|
||||
R12||IOBM|IO_L52P_M1DQ14_1|UNUSED||1|||||||||
|
||||
R13|||VCCO_1|||1|||||any******||||
|
||||
R14||IOBM|IO_L50P_M1UDQS_1|UNUSED||1|||||||||
|
||||
R15||IOBM|IO_L49P_M1DQ10_1|UNUSED||1|||||||||
|
||||
R16||IOBS|IO_L49N_M1DQ11_1|UNUSED||1|||||||||
|
||||
T1|||GND||||||||||||
|
||||
T2|||PROGRAM_B_2||||||||||||
|
||||
T3||IOBS|IO_L65N_CSO_B_2|UNUSED||2|||||||||
|
||||
T4||IOBS|IO_L63N_2|UNUSED||2|||||||||
|
||||
T5||IOBS|IO_L48N_RDWR_B_VREF_2|UNUSED||2|||||||||
|
||||
T6||IOBS|IO_L47N_2|UNUSED||2|||||||||
|
||||
T7|FPUCLK|IOB|IO_L32N_GCLK28_2|OUTPUT|LVCMOS33|2|24|FAST||||UNLOCATED|YES|NONE|
|
||||
T8||IOBS|IO_L30N_GCLK0_USERCCLK_2|UNUSED||2|||||||||
|
||||
T9||IOBS|IO_L23N_2|UNUSED||2|||||||||
|
||||
T10||IOBS|IO_L3N_MOSI_CSI_B_MISO0_2|UNUSED||2|||||||||
|
||||
T11||IOBS|IO_L1N_M0_CMPMISO_2|UNUSED||2|||||||||
|
||||
T12||IOBS|IO_L52N_M1DQ15_1|UNUSED||1|||||||||
|
||||
T13||IOBS|IO_L51N_M1DQ13_1|UNUSED||1|||||||||
|
||||
T14||IOBM|IO_L51P_M1DQ12_1|UNUSED||1|||||||||
|
||||
T15||IOBS|IO_L50N_M1UDQSN_1|UNUSED||1|||||||||
|
||||
T16|||GND||||||||||||
|
||||
|
||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
|
||||
|
||||
* Default value.
|
||||
** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
****** Special VCCO requirements may apply. Please consult the device
|
||||
family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
245
fpga/WarpLC.par
Normal file
245
fpga/WarpLC.par
Normal file
@ -0,0 +1,245 @@
|
||||
Release 14.7 par P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
ZANEPC:: Fri Oct 29 10:03:03 2021
|
||||
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
|
||||
|
||||
Constraints file: WarpLC.pcf.
|
||||
Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
|
||||
"WarpLC" is an NCD, version 3.2, device xc6slx9, package ftg256, speed -2
|
||||
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
|
||||
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
|
||||
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
|
||||
'C:\ispLEVER_Classic2_0\license\license.dat;C:\lscc\diamond\3.12\license\license.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'.
|
||||
INFO:Security:54 - 'xc6slx9' is a WebPack part.
|
||||
INFO:Security:66 - Your license for 'ISE' is for evaluation use only.
|
||||
WARNING:Security:43 - No license file was found in the standard Xilinx license directory.
|
||||
WARNING:Security:44 - Since no license file was found,
|
||||
please run the Xilinx License Configuration Manager
|
||||
(xlcm or "Manage Xilinx Licenses")
|
||||
to assist in obtaining a license.
|
||||
WARNING:Security:40 - Your license for 'ISE' expires in 4 days.
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
||||
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
|
||||
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
||||
|
||||
|
||||
Device speed data version: "PRODUCTION 1.23 2013-10-13".
|
||||
|
||||
|
||||
|
||||
Device Utilization Summary:
|
||||
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 56 out of 11,440 1%
|
||||
Number used as Flip Flops: 56
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 59 out of 5,720 1%
|
||||
Number used as logic: 56 out of 5,720 1%
|
||||
Number using O6 output only: 24
|
||||
Number using O5 output only: 29
|
||||
Number using O5 and O6: 3
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 0 out of 1,440 0%
|
||||
Number used exclusively as route-thrus: 3
|
||||
Number with same-slice register load: 2
|
||||
Number with same-slice carry load: 1
|
||||
Number with other load: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 25 out of 1,430 1%
|
||||
Number of MUXCYs used: 56 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 76
|
||||
Number with an unused Flip Flop: 22 out of 76 28%
|
||||
Number with an unused LUT: 17 out of 76 22%
|
||||
Number of fully used LUT-FF pairs: 37 out of 76 48%
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 0 out of 11,440 0%
|
||||
|
||||
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
||||
one Flip Flop within a slice. A control set is a unique combination of
|
||||
clock, reset, set, and enable signals for a registered element.
|
||||
The Slice Logic Distribution report is not meaningful if the design is
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 49 out of 186 26%
|
||||
IOB Flip Flops: 5
|
||||
IOB Latches: 1
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 0 out of 32 0%
|
||||
Number of RAMB8BWERs: 0 out of 64 0%
|
||||
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2s: 1
|
||||
Number used as BUFIO2_2CLKs: 0
|
||||
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2FBs: 1
|
||||
Number used as BUFIO2FB_2CLKs: 0
|
||||
Number of BUFG/BUFGMUXs: 3 out of 16 18%
|
||||
Number used as BUFGs: 3
|
||||
Number used as BUFGMUX: 0
|
||||
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
|
||||
Number of ILOGIC2/ISERDES2s: 1 out of 200 1%
|
||||
Number used as ILOGIC2s: 1
|
||||
Number used as ISERDES2s: 0
|
||||
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
|
||||
Number of OLOGIC2/OSERDES2s: 5 out of 200 2%
|
||||
Number used as OLOGIC2s: 5
|
||||
Number used as OSERDES2s: 0
|
||||
Number of BSCANs: 0 out of 4 0%
|
||||
Number of BUFHs: 0 out of 128 0%
|
||||
Number of BUFPLLs: 0 out of 8 0%
|
||||
Number of BUFPLL_MCBs: 0 out of 4 0%
|
||||
Number of DSP48A1s: 0 out of 16 0%
|
||||
Number of ICAPs: 0 out of 1 0%
|
||||
Number of MCBs: 0 out of 2 0%
|
||||
Number of PCILOGICSEs: 0 out of 2 0%
|
||||
Number of PLL_ADVs: 1 out of 2 50%
|
||||
Number of PMVs: 0 out of 1 0%
|
||||
Number of STARTUPs: 0 out of 1 0%
|
||||
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
||||
|
||||
|
||||
Overall effort level (-ol): High
|
||||
Router effort level (-rl): High
|
||||
|
||||
Starting initial Timing Analysis. REAL time: 2 secs
|
||||
Finished initial Timing Analysis. REAL time: 2 secs
|
||||
|
||||
Starting Router
|
||||
|
||||
|
||||
Phase 1 : 315 unrouted; REAL time: 2 secs
|
||||
|
||||
Phase 2 : 228 unrouted; REAL time: 2 secs
|
||||
|
||||
Phase 3 : 98 unrouted; REAL time: 2 secs
|
||||
|
||||
Phase 4 : 98 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
|
||||
Updating file: WarpLC.ncd with current fully routed design.
|
||||
|
||||
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
|
||||
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
|
||||
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
|
||||
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
|
||||
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
|
||||
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
Total REAL time to Router completion: 2 secs
|
||||
Total CPU time to Router completion: 2 secs
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
Generating "PAR" statistics.
|
||||
|
||||
**************************
|
||||
Generating Clock Report
|
||||
**************************
|
||||
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
|instance_name/clkfb_ | | | | | |
|
||||
| bufg_out | BUFGMUX_X2Y3| No | 2 | 0.000 | 2.163 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| CPUCLKi | BUFGMUX_X3Y13| No | 3 | 0.633 | 2.069 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| FSBCLK | BUFGMUX_X2Y2| No | 21 | 0.728 | 2.163 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| LE | Local| | 2 | 0.000 | 0.979 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
|
||||
* Net Skew is the difference between the minimum and maximum routing
|
||||
only delays for the net. Note this is different from Clock Skew which
|
||||
is reported in TRCE timing report. Clock Skew is the difference between
|
||||
the minimum and maximum path delays which includes logic delays.
|
||||
|
||||
* The fanout is the number of component pins not the individual BEL loads,
|
||||
for example SLICE loads not FF loads.
|
||||
|
||||
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
|
||||
|
||||
Number of Timing Constraints that were not applied: 2
|
||||
|
||||
Asterisk (*) preceding a constraint indicates it was not met.
|
||||
This may be due to a setup or hold violation.
|
||||
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
Constraint | Check | Worst Case | Best Case | Timing | Timing
|
||||
| | Slack | Achievable | Errors | Score
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
PERIOD analysis for net "instance_name/cl | SETUP | 1.459ns| 7.082ns| 0| 0
|
||||
kout1" derived from NET "instance_name/c | HOLD | 4.848ns| | 0| 0
|
||||
lkin1" PERIOD = 20 ns HIGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
PERIOD analysis for net "instance_name/cl | SETUP | 5.303ns| 4.697ns| 0| 0
|
||||
kout0" derived from NET "instance_name/c | HOLD | 0.414ns| | 0| 0
|
||||
lkin1" PERIOD = 20 ns HIGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns | MINLOWPULSE | 15.000ns| 5.000ns| 0| 0
|
||||
HIGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
PERIOD analysis for net "instance_name/cl | MINPERIOD | 17.334ns| 2.666ns| 0| 0
|
||||
kfbout" derived from NET "instance_name/ | | | | |
|
||||
clkin1" PERIOD = 20 ns HIGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Derived Constraint Report
|
||||
Review Timing Report for more details on the following derived constraints.
|
||||
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
|
||||
or "Run Timing Analysis" from Timing Analyzer (timingan).
|
||||
Derived Constraints for instance_name/clkin1
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
| | Period | Actual Period | Timing Errors | Paths Analyzed |
|
||||
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|
||||
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|instance_name/clkin1 | 20.000ns| 5.000ns| 14.164ns| 0| 0| 0| 57|
|
||||
| instance_name/clkfbout | 20.000ns| 2.666ns| N/A| 0| 0| 0| 0|
|
||||
| instance_name/clkout1 | 10.000ns| 7.082ns| N/A| 0| 0| 3| 0|
|
||||
| instance_name/clkout0 | 10.000ns| 4.697ns| N/A| 0| 0| 54| 0|
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|
||||
All constraints were met.
|
||||
|
||||
|
||||
Generating Pad Report.
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
Total REAL time to PAR completion: 2 secs
|
||||
Total CPU time to PAR completion: 2 secs
|
||||
|
||||
Peak Memory Usage: 256 MB
|
||||
|
||||
Placer: Placement generated during map.
|
||||
Routing: Completed - No errors found.
|
||||
Timing: Completed - No errors found.
|
||||
|
||||
Number of error messages: 0
|
||||
Number of warning messages: 0
|
||||
Number of info messages: 0
|
||||
|
||||
Writing design to file WarpLC.ncd
|
||||
|
||||
|
||||
|
||||
PAR done!
|
||||
9
fpga/WarpLC.pcf
Normal file
9
fpga/WarpLC.pcf
Normal file
@ -0,0 +1,9 @@
|
||||
//! **************************************************************************
|
||||
// Written by: Map P.20131013 on Fri Oct 29 10:03:01 2021
|
||||
//! **************************************************************************
|
||||
|
||||
SCHEMATIC START;
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
BEL "CLKFB_OUT" FEEDBACK = 0.16 ns BEL "CLKFB_IN";
|
||||
SCHEMATIC END;
|
||||
|
||||
2
fpga/WarpLC.prj
Normal file
2
fpga/WarpLC.prj
Normal file
@ -0,0 +1,2 @@
|
||||
verilog work "ipcore_dir/CLK.v"
|
||||
verilog work "WarpLC.v"
|
||||
332
fpga/WarpLC.ptwx
Normal file
332
fpga/WarpLC.ptwx
Normal file
@ -0,0 +1,332 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE twReport [
|
||||
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
|
||||
twDebug*, twFoot?, twClientInfo?)>
|
||||
<!ATTLIST twReport version CDATA "10,4">
|
||||
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
|
||||
<!ELEMENT twExecVer (#PCDATA)>
|
||||
<!ELEMENT twCopyright (#PCDATA)>
|
||||
<!ELEMENT twCmdLine (#PCDATA)>
|
||||
<!ELEMENT twDesign (#PCDATA)>
|
||||
<!ELEMENT twPCF (#PCDATA)>
|
||||
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
|
||||
<!ELEMENT twDevName (#PCDATA)>
|
||||
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
|
||||
<!ELEMENT twSpeedGrade (#PCDATA)>
|
||||
<!ELEMENT twSpeedVer (#PCDATA)>
|
||||
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
|
||||
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
|
||||
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
|
||||
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
|
||||
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
|
||||
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twItemLimit (#PCDATA)>
|
||||
<!ELEMENT twUnconst EMPTY>
|
||||
<!ELEMENT twUnconstLimit (#PCDATA)>
|
||||
<!ELEMENT twEnvVar EMPTY>
|
||||
<!ATTLIST twEnvVar name CDATA #REQUIRED>
|
||||
<!ATTLIST twEnvVar description CDATA #REQUIRED>
|
||||
<!ELEMENT twWarn (#PCDATA)>
|
||||
<!ELEMENT twInfo (#PCDATA)>
|
||||
<!ELEMENT twDebug (#PCDATA)>
|
||||
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
|
||||
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
|
||||
<!ELEMENT twProc (#PCDATA)>
|
||||
<!ELEMENT twTemp (#PCDATA)>
|
||||
<!ELEMENT twVolt (#PCDATA)>
|
||||
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
|
||||
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
|
||||
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twCycles (twSigConn+)>
|
||||
<!ATTLIST twCycles twNum CDATA #REQUIRED>
|
||||
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
|
||||
<!ELEMENT twSig (#PCDATA)>
|
||||
<!ELEMENT twDriver (#PCDATA)>
|
||||
<!ELEMENT twLoad (#PCDATA)>
|
||||
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
|
||||
<!ATTLIST twConst twConstType (NET |
|
||||
NETDELAY |
|
||||
NETSKEW |
|
||||
PATH |
|
||||
DEFPERIOD |
|
||||
UNCONSTPATH |
|
||||
DEFPATH |
|
||||
PATH2SETUP |
|
||||
UNCONSTPATH2SETUP |
|
||||
PATHCLASS |
|
||||
PATHDELAY |
|
||||
PERIOD |
|
||||
FREQUENCY |
|
||||
PATHBLOCK |
|
||||
OFFSET |
|
||||
OFFSETIN |
|
||||
OFFSETINCLOCK |
|
||||
UNCONSTOFFSETINCLOCK |
|
||||
OFFSETINDELAY |
|
||||
OFFSETINMOD |
|
||||
OFFSETOUT |
|
||||
OFFSETOUTCLOCK |
|
||||
UNCONSTOFFSETOUTCLOCK |
|
||||
OFFSETOUTDELAY |
|
||||
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
|
||||
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
|
||||
twEndPtCnt?,
|
||||
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
|
||||
<!ELEMENT twConstName (#PCDATA)>
|
||||
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
|
||||
<!ATTLIST twConstHead uID CDATA #IMPLIED>
|
||||
<!ELEMENT twItemCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCntEndPt (#PCDATA)>
|
||||
<!ELEMENT twErrCntSetup (#PCDATA)>
|
||||
<!ELEMENT twErrCntHold (#PCDATA)>
|
||||
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twEndPtCnt (#PCDATA)>
|
||||
<!ELEMENT twPathErrCnt (#PCDATA)>
|
||||
<!ELEMENT twMinPer (#PCDATA) >
|
||||
<!ELEMENT twFootnote EMPTY>
|
||||
<!ATTLIST twFootnote number CDATA #REQUIRED>
|
||||
<!ELEMENT twMaxDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFreq (#PCDATA)>
|
||||
<!ELEMENT twMinOff (#PCDATA)>
|
||||
<!ELEMENT twMaxOff (#PCDATA)>
|
||||
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
|
||||
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
|
||||
<!ELEMENT twTIGName (#PCDATA)>
|
||||
<!ELEMENT twInstantiated (#PCDATA)>
|
||||
<!ELEMENT twBlocked (#PCDATA)>
|
||||
<!ELEMENT twRacePathRpt (twRacePath+)>
|
||||
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
|
||||
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
|
||||
twSimpleMinPath CDATA #IMPLIED>
|
||||
<!ELEMENT twTotDel (#PCDATA)>
|
||||
<!ELEMENT twSrc (#PCDATA)>
|
||||
<!ATTLIST twSrc BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDest (#PCDATA)>
|
||||
<!ATTLIST twDest BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDel (#PCDATA)>
|
||||
<!ELEMENT twSUTime (#PCDATA)>
|
||||
<!ELEMENT twTotPathDel (#PCDATA)>
|
||||
<!ELEMENT twClkSkew (#PCDATA)>
|
||||
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
|
||||
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
|
||||
<!ELEMENT twSlack (#PCDATA)>
|
||||
<!ELEMENT twDelConst (#PCDATA)>
|
||||
<!ELEMENT tw2Phase EMPTY>
|
||||
<!ELEMENT twClkUncert (#PCDATA)>
|
||||
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
|
||||
fDCMJit CDATA #IMPLIED
|
||||
fPhaseErr CDATA #IMPLIED
|
||||
sEqu CDATA #IMPLIED>
|
||||
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
|
||||
<!ELEMENT twPathRptBanner (#PCDATA)>
|
||||
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twOff (#PCDATA)>
|
||||
<!ELEMENT twGuaranteed EMPTY>
|
||||
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
|
||||
<!ELEMENT twClkDel (#PCDATA)>
|
||||
<!ELEMENT twClkSrc (#PCDATA)>
|
||||
<!ELEMENT twClkDest (#PCDATA)>
|
||||
<!ELEMENT twGuarInSetup (#PCDATA)>
|
||||
<!ELEMENT twOffSrc (#PCDATA)>
|
||||
<!ELEMENT twOffDest (#PCDATA)>
|
||||
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ELEMENT twDataDel (#PCDATA)>
|
||||
<!ELEMENT twDataSrc (#PCDATA)>
|
||||
<!ELEMENT twDataDest (#PCDATA)>
|
||||
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
|
||||
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twLogLvls (#PCDATA)>
|
||||
<!ELEMENT twSrcSite (#PCDATA)>
|
||||
<!ELEMENT twSrcClk (#PCDATA)>
|
||||
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
|
||||
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twDelInfo (#PCDATA)>
|
||||
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twSite (#PCDATA)>
|
||||
<!ELEMENT twDelType (#PCDATA)>
|
||||
<!ELEMENT twFanCnt (#PCDATA)>
|
||||
<!ELEMENT twComp (#PCDATA)>
|
||||
<!ELEMENT twNet (#PCDATA)>
|
||||
<!ELEMENT twBEL (#PCDATA)>
|
||||
<!ELEMENT twLogDel (#PCDATA)>
|
||||
<!ELEMENT twRouteDel (#PCDATA)>
|
||||
<!ELEMENT twDestClk (#PCDATA)>
|
||||
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPctLog (#PCDATA)>
|
||||
<!ELEMENT twPctRoute (#PCDATA)>
|
||||
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
|
||||
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
|
||||
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
|
||||
<!ELEMENT twTimeConst (#PCDATA)>
|
||||
<!ELEMENT twAbsSlack (#PCDATA)>
|
||||
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
|
||||
<!ELEMENT twSkew (#PCDATA)>
|
||||
<!ELEMENT twDetNet (twNetDel*)>
|
||||
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
|
||||
<!ELEMENT twNetDelInfo (#PCDATA)>
|
||||
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twDetSkewNet (twNetSkew*)>
|
||||
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
|
||||
<!ELEMENT twClkSkewLimit EMPTY>
|
||||
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
|
||||
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollupTable (twConstRollup*)>
|
||||
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollup EMPTY>
|
||||
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
|
||||
<!ELEMENT twConstList (twConstListItem)*>
|
||||
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
|
||||
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
|
||||
<!ELEMENT twNotMet EMPTY>
|
||||
<!ELEMENT twReqVal (#PCDATA)>
|
||||
<!ELEMENT twActVal (#PCDATA)>
|
||||
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
|
||||
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
|
||||
<!ELEMENT twConstStats (twConstName)>
|
||||
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
|
||||
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
|
||||
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
|
||||
<!ELEMENT twConstData EMPTY>
|
||||
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
|
||||
best CDATA #IMPLIED requested CDATA #IMPLIED
|
||||
errors CDATA #IMPLIED
|
||||
score CDATA #IMPLIED>
|
||||
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
|
||||
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
|
||||
<!ELEMENT twTimeGrpName (#PCDATA)>
|
||||
<!ELEMENT twCompList (twCompName+)>
|
||||
<!ELEMENT twCompName (#PCDATA)>
|
||||
<!ELEMENT twSigList (twSigName+)>
|
||||
<!ELEMENT twSigName (#PCDATA)>
|
||||
<!ELEMENT twBELList (twBELName+)>
|
||||
<!ELEMENT twBELName (#PCDATA)>
|
||||
<!ELEMENT twBlockList (twBlockName+)>
|
||||
<!ELEMENT twBlockName (#PCDATA)>
|
||||
<!ELEMENT twMacList (twMacName+)>
|
||||
<!ELEMENT twMacName (#PCDATA)>
|
||||
<!ELEMENT twPinList (twPinName+)>
|
||||
<!ELEMENT twPinName (#PCDATA)>
|
||||
<!ELEMENT twUnmetConstCnt (#PCDATA)>
|
||||
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
|
||||
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
|
||||
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
|
||||
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
|
||||
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
|
||||
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
|
||||
<!ELEMENT twSU2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twH2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
|
||||
<!ELEMENT twClk2Pad (twDest, twTime)>
|
||||
<!ELEMENT twTime (#PCDATA)>
|
||||
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
|
||||
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2Out EMPTY>
|
||||
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
|
||||
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
|
||||
<!ELEMENT twRiseRise (#PCDATA)>
|
||||
<!ELEMENT twFallRise (#PCDATA)>
|
||||
<!ELEMENT twRiseFall (#PCDATA)>
|
||||
<!ELEMENT twFallFall (#PCDATA)>
|
||||
<!ELEMENT twPad2PadList (twPad2Pad+)>
|
||||
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
|
||||
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
|
||||
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
|
||||
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
|
||||
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
|
||||
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffOutTblRow EMPTY>
|
||||
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
|
||||
<!ELEMENT twNonDedClk (#PCDATA)>
|
||||
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
|
||||
<!ELEMENT twScore (#PCDATA)>
|
||||
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
|
||||
<!ELEMENT twPathCnt (#PCDATA)>
|
||||
<!ELEMENT twNetCnt (#PCDATA)>
|
||||
<!ELEMENT twConnCnt (#PCDATA)>
|
||||
<!ELEMENT twPct (#PCDATA)>
|
||||
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
|
||||
<!ELEMENT twMaxCombDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFromToDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetSkew (#PCDATA)>
|
||||
<!ELEMENT twMaxInAfterClk (#PCDATA)>
|
||||
<!ELEMENT twMinInBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMinOutAfterClk (#PCDATA)>
|
||||
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
|
||||
<!ELEMENT twTimestamp (#PCDATA)>
|
||||
<!ELEMENT twFootnoteExplanation EMPTY>
|
||||
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
|
||||
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
|
||||
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
|
||||
<!ELEMENT twClientName (#PCDATA)>
|
||||
<!ELEMENT twAttrList (twAttrListItem)*>
|
||||
<!ELEMENT twAttrListItem (twName, twValue*)>
|
||||
<!ELEMENT twName (#PCDATA)>
|
||||
<!ELEMENT twValue (#PCDATA)>
|
||||
]>
|
||||
<twReport><twBody><twSumRpt><twConstRollupTable uID="1" anchorID="11"><twConstRollup name="instance_name/clkin1" fullName="NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="5.000" actualRollup="14.164" errors="0" errorRollup="0" items="0" itemsRollup="57"/><twConstRollup name="instance_name/clkfbout" fullName="PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS " type="child" depth="1" requirement="20.000" prefType="period" actual="2.666" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="instance_name/clkout1" fullName="PERIOD analysis for net "instance_name/clkout1" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS " type="child" depth="1" requirement="10.000" prefType="period" actual="7.082" actualRollup="N/A" errors="0" errorRollup="0" items="3" itemsRollup="0"/><twConstRollup name="instance_name/clkout0" fullName="PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS " type="child" depth="1" requirement="10.000" prefType="period" actual="4.697" actualRollup="N/A" errors="0" errorRollup="0" items="54" itemsRollup="0"/></twConstRollupTable><twConstSummaryTable twEmptyConstraints = "2" ><twConstSummary><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkout1" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="1.459" best="7.082" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="4.848" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="5.303" best="4.697" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.414" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%</twConstName><twConstData type="MINLOWPULSE" slack="15.000" best="5.000" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="17.334" best="2.666" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="12">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
|
||||
0
fpga/WarpLC.stx
Normal file
0
fpga/WarpLC.stx
Normal file
1003
fpga/WarpLC.syr
Normal file
1003
fpga/WarpLC.syr
Normal file
File diff suppressed because it is too large
Load Diff
800
fpga/WarpLC.twr
Normal file
800
fpga/WarpLC.twr
Normal file
@ -0,0 +1,800 @@
|
||||
--------------------------------------------------------------------------------
|
||||
Release 14.7 Trace (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
|
||||
3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
|
||||
Design file: WarpLC.ncd
|
||||
Physical constraint file: WarpLC.pcf
|
||||
Device,package,speed: xc6slx9,ftg256,C,-2 (PRODUCTION 1.23 2013-10-13)
|
||||
Report level: verbose report
|
||||
|
||||
Environment Variable Effect
|
||||
-------------------- ------
|
||||
NONE No environment variables were set
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
|
||||
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
|
||||
option. All paths that are not constrained will be reported in the
|
||||
unconstrained paths section(s) of the report.
|
||||
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
||||
a 50 Ohm transmission line loading model. For the details of this model,
|
||||
and for more information on accounting for different loading conditions,
|
||||
please see the device datasheet.
|
||||
|
||||
================================================================================
|
||||
Timing constraint: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
||||
0 timing errors detected. (0 component switching limit errors)
|
||||
Minimum period is 5.000ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Component Switching Limit Checks: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 15.000ns (period - (min low pulse limit / (low pulse / period)))
|
||||
Period: 20.000ns
|
||||
Low pulse: 10.000ns
|
||||
Low pulse limit: 2.500ns (Tdcmpw_CLKIN_50_100)
|
||||
Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
|
||||
Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
|
||||
Location pin: PLL_ADV_X0Y1.CLKIN2
|
||||
Clock network: instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 15.000ns (period - (min high pulse limit / (high pulse / period)))
|
||||
Period: 20.000ns
|
||||
High pulse: 10.000ns
|
||||
High pulse limit: 2.500ns (Tdcmpw_CLKIN_50_100)
|
||||
Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
|
||||
Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
|
||||
Location pin: PLL_ADV_X0Y1.CLKIN2
|
||||
Clock network: instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 17.780ns (period - min period limit)
|
||||
Period: 20.000ns
|
||||
Min period limit: 2.220ns (450.450MHz) (Tpllper_CLKIN(Finmax))
|
||||
Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
|
||||
Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
|
||||
Location pin: PLL_ADV_X0Y1.CLKIN2
|
||||
Clock network: instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
================================================================================
|
||||
Timing constraint: PERIOD analysis for net "instance_name/clkfbout" derived
|
||||
from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected
|
||||
to 20 nS HIGH 10 nS
|
||||
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
||||
0 timing errors detected. (0 component switching limit errors)
|
||||
Minimum period is 2.666ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkfbout" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
duty cycle corrected to 20 nS HIGH 10 nS
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 17.334ns (period - min period limit)
|
||||
Period: 20.000ns
|
||||
Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
|
||||
Physical resource: instance_name/clkfbout_bufg/I0
|
||||
Logical resource: instance_name/clkfbout_bufg/I0
|
||||
Location pin: BUFGMUX_X2Y3.I0
|
||||
Clock network: instance_name/clkfbout
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 17.751ns (period - min period limit)
|
||||
Period: 20.000ns
|
||||
Min period limit: 2.249ns (444.642MHz) (Tockper)
|
||||
Physical resource: CLKFB_OUT_OBUF/CLK0
|
||||
Logical resource: instance_name/clkfbout_oddr/CK0
|
||||
Location pin: OLOGIC_X0Y50.CLK0
|
||||
Clock network: instance_name/clkfb_bufg_out
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 17.780ns (period - min period limit)
|
||||
Period: 20.000ns
|
||||
Min period limit: 2.220ns (450.450MHz) (Tpllper_CLKFB)
|
||||
Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKFBOUT
|
||||
Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKFBOUT
|
||||
Location pin: PLL_ADV_X0Y1.CLKFBOUT
|
||||
Clock network: instance_name/clkfbout
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
================================================================================
|
||||
Timing constraint: PERIOD analysis for net "instance_name/clkout1" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS
|
||||
|
||||
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
3 paths analyzed, 3 endpoints analyzed, 0 failing endpoints
|
||||
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
|
||||
Minimum period is 7.082ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point FPUCLK (OLOGIC_X6Y2.D1), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 1.459ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: CPUCLKr1 (FF)
|
||||
Destination: FPUCLK (FF)
|
||||
Requirement: 5.000ns
|
||||
Data Path Delay: 3.914ns (Levels of Logic = 0)
|
||||
Clock Path Skew: 0.521ns (1.178 - 0.657)
|
||||
Source Clock: CPUCLKi falling at 5.000ns
|
||||
Destination Clock: CPUCLKi rising at 10.000ns
|
||||
Clock Uncertainty: 0.148ns
|
||||
|
||||
Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: CPUCLKr1 to FPUCLK
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X5Y28.AQ Tcko 0.430 CPUCLKr1
|
||||
CPUCLKr1
|
||||
OLOGIC_X6Y2.D1 net (fanout=2) 2.306 CPUCLKr1
|
||||
OLOGIC_X6Y2.CLK0 Todck 1.178 FPUCLK_OBUF
|
||||
FPUCLK
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 3.914ns (1.608ns logic, 2.306ns route)
|
||||
(41.1% logic, 58.9% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point CPUCLK (OLOGIC_X0Y46.D1), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 1.562ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: CPUCLKr1 (FF)
|
||||
Destination: CPUCLK (FF)
|
||||
Requirement: 5.000ns
|
||||
Data Path Delay: 3.815ns (Levels of Logic = 0)
|
||||
Clock Path Skew: 0.525ns (1.275 - 0.750)
|
||||
Source Clock: CPUCLKi falling at 5.000ns
|
||||
Destination Clock: CPUCLKi rising at 10.000ns
|
||||
Clock Uncertainty: 0.148ns
|
||||
|
||||
Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: CPUCLKr1 to CPUCLK
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X5Y28.AQ Tcko 0.430 CPUCLKr1
|
||||
CPUCLKr1
|
||||
OLOGIC_X0Y46.D1 net (fanout=2) 2.207 CPUCLKr1
|
||||
OLOGIC_X0Y46.CLK0 Todck 1.178 CPUCLK_OBUF
|
||||
CPUCLK
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 3.815ns (1.608ns logic, 2.207ns route)
|
||||
(42.1% logic, 57.9% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point CPUCLKr1 (SLICE_X5Y28.AX), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 2.862ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: CPUCLKr0 (FF)
|
||||
Destination: CPUCLKr1 (FF)
|
||||
Requirement: 5.000ns
|
||||
Data Path Delay: 1.209ns (Levels of Logic = 0)
|
||||
Clock Path Skew: -0.661ns (1.489 - 2.150)
|
||||
Source Clock: FSBCLK rising at 0.000ns
|
||||
Destination Clock: CPUCLKi falling at 5.000ns
|
||||
Clock Uncertainty: 0.268ns
|
||||
|
||||
Clock Uncertainty: 0.268ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.120ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: CPUCLKr0 to CPUCLKr1
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X4Y28.AQ Tcko 0.525 CPUCLKr0
|
||||
CPUCLKr0
|
||||
SLICE_X5Y28.AX net (fanout=2) 0.570 CPUCLKr0
|
||||
SLICE_X5Y28.CLK Tdick 0.114 CPUCLKr1
|
||||
CPUCLKr1
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 1.209ns (0.639ns logic, 0.570ns route)
|
||||
(52.9% logic, 47.1% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Hold Paths: PERIOD analysis for net "instance_name/clkout1" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
divided by 2.00 to 10 nS
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point CPUCLKr1 (SLICE_X5Y28.AX), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (hold path): 4.848ns (requirement - (clock path skew + uncertainty - data path))
|
||||
Source: CPUCLKr0 (FF)
|
||||
Destination: CPUCLKr1 (FF)
|
||||
Requirement: 5.000ns
|
||||
Data Path Delay: 0.441ns (Levels of Logic = 0)
|
||||
Clock Path Skew: 0.325ns (1.035 - 0.710)
|
||||
Source Clock: FSBCLK rising at 10.000ns
|
||||
Destination Clock: CPUCLKi falling at 5.000ns
|
||||
Clock Uncertainty: 0.268ns
|
||||
|
||||
Clock Uncertainty: 0.268ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.120ns
|
||||
|
||||
Minimum Data Path at Fast Process Corner: CPUCLKr0 to CPUCLKr1
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X4Y28.AQ Tcko 0.234 CPUCLKr0
|
||||
CPUCLKr0
|
||||
SLICE_X5Y28.AX net (fanout=2) 0.148 CPUCLKr0
|
||||
SLICE_X5Y28.CLK Tckdi (-Th) -0.059 CPUCLKr1
|
||||
CPUCLKr1
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 0.441ns (0.293ns logic, 0.148ns route)
|
||||
(66.4% logic, 33.6% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point CPUCLK (OLOGIC_X0Y46.D1), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (hold path): 6.414ns (requirement - (clock path skew + uncertainty - data path))
|
||||
Source: CPUCLKr1 (FF)
|
||||
Destination: CPUCLK (FF)
|
||||
Requirement: 5.000ns
|
||||
Data Path Delay: 1.812ns (Levels of Logic = 0)
|
||||
Clock Path Skew: 0.250ns (0.604 - 0.354)
|
||||
Source Clock: CPUCLKi falling at 15.000ns
|
||||
Destination Clock: CPUCLKi rising at 10.000ns
|
||||
Clock Uncertainty: 0.148ns
|
||||
|
||||
Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Minimum Data Path at Fast Process Corner: CPUCLKr1 to CPUCLK
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X5Y28.AQ Tcko 0.198 CPUCLKr1
|
||||
CPUCLKr1
|
||||
OLOGIC_X0Y46.D1 net (fanout=2) 1.204 CPUCLKr1
|
||||
OLOGIC_X0Y46.CLK0 Tockd (-Th) -0.410 CPUCLK_OBUF
|
||||
CPUCLK
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 1.812ns (0.608ns logic, 1.204ns route)
|
||||
(33.6% logic, 66.4% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point FPUCLK (OLOGIC_X6Y2.D1), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (hold path): 6.438ns (requirement - (clock path skew + uncertainty - data path))
|
||||
Source: CPUCLKr1 (FF)
|
||||
Destination: FPUCLK (FF)
|
||||
Requirement: 5.000ns
|
||||
Data Path Delay: 1.825ns (Levels of Logic = 0)
|
||||
Clock Path Skew: 0.239ns (0.566 - 0.327)
|
||||
Source Clock: CPUCLKi falling at 15.000ns
|
||||
Destination Clock: CPUCLKi rising at 10.000ns
|
||||
Clock Uncertainty: 0.148ns
|
||||
|
||||
Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Minimum Data Path at Fast Process Corner: CPUCLKr1 to FPUCLK
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X5Y28.AQ Tcko 0.198 CPUCLKr1
|
||||
CPUCLKr1
|
||||
OLOGIC_X6Y2.D1 net (fanout=2) 1.217 CPUCLKr1
|
||||
OLOGIC_X6Y2.CLK0 Tockd (-Th) -0.410 FPUCLK_OBUF
|
||||
FPUCLK
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 1.825ns (0.608ns logic, 1.217ns route)
|
||||
(33.3% logic, 66.7% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout1" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
divided by 2.00 to 10 nS
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 7.334ns (period - min period limit)
|
||||
Period: 10.000ns
|
||||
Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
|
||||
Physical resource: instance_name/clkout2_buf/I0
|
||||
Logical resource: instance_name/clkout2_buf/I0
|
||||
Location pin: BUFGMUX_X3Y13.I0
|
||||
Clock network: instance_name/clkout1
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 7.751ns (period - min period limit)
|
||||
Period: 10.000ns
|
||||
Min period limit: 2.249ns (444.642MHz) (Tockper)
|
||||
Physical resource: CPUCLK_OBUF/CLK0
|
||||
Logical resource: CPUCLK/CK0
|
||||
Location pin: OLOGIC_X0Y46.CLK0
|
||||
Clock network: CPUCLKi
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 7.751ns (period - min period limit)
|
||||
Period: 10.000ns
|
||||
Min period limit: 2.249ns (444.642MHz) (Tockper)
|
||||
Physical resource: FPUCLK_OBUF/CLK0
|
||||
Logical resource: FPUCLK/CK0
|
||||
Location pin: OLOGIC_X6Y2.CLK0
|
||||
Clock network: CPUCLKi
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
================================================================================
|
||||
Timing constraint: PERIOD analysis for net "instance_name/clkout0" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS
|
||||
|
||||
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
54 paths analyzed, 5 endpoints analyzed, 0 failing endpoints
|
||||
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
|
||||
Minimum period is 4.697ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point CPU_nSTERM (SLICE_X0Y39.B3), 30 paths
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 5.303ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: LastA_6 (FF)
|
||||
Destination: CPU_nSTERM (FF)
|
||||
Requirement: 10.000ns
|
||||
Data Path Delay: 4.515ns (Levels of Logic = 4)
|
||||
Clock Path Skew: -0.034ns (0.720 - 0.754)
|
||||
Source Clock: FSBCLK rising at 0.000ns
|
||||
Destination Clock: FSBCLK rising at 10.000ns
|
||||
Clock Uncertainty: 0.148ns
|
||||
|
||||
Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: LastA_6 to CPU_nSTERM
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X2Y21.AQ Tcko 0.476 LastA<9>
|
||||
LastA_6
|
||||
SLICE_X0Y21.B2 net (fanout=1) 1.201 LastA<6>
|
||||
SLICE_X0Y21.COUT Topcyb 0.483 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<3>
|
||||
Mcompar_FSB_A[31]_LastA[31]_equal_4_o_lut<1>
|
||||
Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<3>
|
||||
SLICE_X0Y22.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<3>
|
||||
SLICE_X0Y22.COUT Tbyp 0.093 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7>
|
||||
Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7>
|
||||
SLICE_X0Y23.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7>
|
||||
SLICE_X0Y23.BMUX Tcinb 0.286 LastAWR<15>
|
||||
Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<9>
|
||||
SLICE_X0Y39.B3 net (fanout=2) 1.631 FSB_A[31]_LastA[31]_equal_4_o
|
||||
SLICE_X0Y39.CLK Tas 0.339 CPU_nSTERM_OBUF
|
||||
CPU_nSTERM_rstpot1
|
||||
CPU_nSTERM
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 4.515ns (1.677ns logic, 2.838ns route)
|
||||
(37.1% logic, 62.9% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 5.534ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: LastA_21 (FF)
|
||||
Destination: CPU_nSTERM (FF)
|
||||
Requirement: 10.000ns
|
||||
Data Path Delay: 4.289ns (Levels of Logic = 3)
|
||||
Clock Path Skew: -0.029ns (0.720 - 0.749)
|
||||
Source Clock: FSBCLK rising at 0.000ns
|
||||
Destination Clock: FSBCLK rising at 10.000ns
|
||||
Clock Uncertainty: 0.148ns
|
||||
|
||||
Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: LastA_21 to CPU_nSTERM
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X2Y24.DQ Tcko 0.476 LastA<21>
|
||||
LastA_21
|
||||
SLICE_X0Y22.C2 net (fanout=1) 1.226 LastA<21>
|
||||
SLICE_X0Y22.COUT Topcyc 0.328 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7>
|
||||
Mcompar_FSB_A[31]_LastA[31]_equal_4_o_lut<6>
|
||||
Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7>
|
||||
SLICE_X0Y23.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7>
|
||||
SLICE_X0Y23.BMUX Tcinb 0.286 LastAWR<15>
|
||||
Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<9>
|
||||
SLICE_X0Y39.B3 net (fanout=2) 1.631 FSB_A[31]_LastA[31]_equal_4_o
|
||||
SLICE_X0Y39.CLK Tas 0.339 CPU_nSTERM_OBUF
|
||||
CPU_nSTERM_rstpot1
|
||||
CPU_nSTERM
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 4.289ns (1.429ns logic, 2.860ns route)
|
||||
(33.3% logic, 66.7% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 5.624ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: LastA_18 (FF)
|
||||
Destination: CPU_nSTERM (FF)
|
||||
Requirement: 10.000ns
|
||||
Data Path Delay: 4.199ns (Levels of Logic = 3)
|
||||
Clock Path Skew: -0.029ns (0.720 - 0.749)
|
||||
Source Clock: FSBCLK rising at 0.000ns
|
||||
Destination Clock: FSBCLK rising at 10.000ns
|
||||
Clock Uncertainty: 0.148ns
|
||||
|
||||
Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: LastA_18 to CPU_nSTERM
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X2Y24.AQ Tcko 0.476 LastA<21>
|
||||
LastA_18
|
||||
SLICE_X0Y22.B1 net (fanout=1) 0.981 LastA<18>
|
||||
SLICE_X0Y22.COUT Topcyb 0.483 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7>
|
||||
Mcompar_FSB_A[31]_LastA[31]_equal_4_o_lut<5>
|
||||
Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7>
|
||||
SLICE_X0Y23.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7>
|
||||
SLICE_X0Y23.BMUX Tcinb 0.286 LastAWR<15>
|
||||
Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<9>
|
||||
SLICE_X0Y39.B3 net (fanout=2) 1.631 FSB_A[31]_LastA[31]_equal_4_o
|
||||
SLICE_X0Y39.CLK Tas 0.339 CPU_nSTERM_OBUF
|
||||
CPU_nSTERM_rstpot1
|
||||
CPU_nSTERM
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 4.199ns (1.584ns logic, 2.615ns route)
|
||||
(37.7% logic, 62.3% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point CPU_nSTERM (SLICE_X0Y39.B4), 21 paths
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 5.724ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: LastAWR_11 (FF)
|
||||
Destination: CPU_nSTERM (FF)
|
||||
Requirement: 10.000ns
|
||||
Data Path Delay: 4.099ns (Levels of Logic = 4)
|
||||
Clock Path Skew: -0.029ns (0.720 - 0.749)
|
||||
Source Clock: FSBCLK rising at 0.000ns
|
||||
Destination Clock: FSBCLK rising at 10.000ns
|
||||
Clock Uncertainty: 0.148ns
|
||||
|
||||
Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: LastAWR_11 to CPU_nSTERM
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X1Y24.AQ Tcko 0.430 LastAWR<14>
|
||||
LastAWR_11
|
||||
SLICE_X0Y24.A2 net (fanout=1) 1.231 LastAWR<11>
|
||||
SLICE_X0Y24.COUT Topcya 0.474 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3>
|
||||
Mcompar_FSB_A[31]_GND_1_o_equal_5_o_lut<0>
|
||||
Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3>
|
||||
SLICE_X0Y25.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3>
|
||||
SLICE_X0Y25.COUT Tbyp 0.093 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7>
|
||||
Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7>
|
||||
SLICE_X0Y26.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7>
|
||||
SLICE_X0Y26.AMUX Tcina 0.230 LastAWR<19>
|
||||
Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<8>
|
||||
SLICE_X0Y39.B4 net (fanout=2) 1.296 FSB_A[31]_GND_1_o_equal_5_o
|
||||
SLICE_X0Y39.CLK Tas 0.339 CPU_nSTERM_OBUF
|
||||
CPU_nSTERM_rstpot1
|
||||
CPU_nSTERM
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 4.099ns (1.566ns logic, 2.533ns route)
|
||||
(38.2% logic, 61.8% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 5.878ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: LastAWR_23 (FF)
|
||||
Destination: CPU_nSTERM (FF)
|
||||
Requirement: 10.000ns
|
||||
Data Path Delay: 3.943ns (Levels of Logic = 3)
|
||||
Clock Path Skew: -0.031ns (0.720 - 0.751)
|
||||
Source Clock: FSBCLK rising at 0.000ns
|
||||
Destination Clock: FSBCLK rising at 10.000ns
|
||||
Clock Uncertainty: 0.148ns
|
||||
|
||||
Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: LastAWR_23 to CPU_nSTERM
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X1Y25.AQ Tcko 0.430 LastAWR<26>
|
||||
LastAWR_23
|
||||
SLICE_X0Y25.A2 net (fanout=1) 1.171 LastAWR<23>
|
||||
SLICE_X0Y25.COUT Topcya 0.474 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7>
|
||||
Mcompar_FSB_A[31]_GND_1_o_equal_5_o_lut<4>
|
||||
Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7>
|
||||
SLICE_X0Y26.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7>
|
||||
SLICE_X0Y26.AMUX Tcina 0.230 LastAWR<19>
|
||||
Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<8>
|
||||
SLICE_X0Y39.B4 net (fanout=2) 1.296 FSB_A[31]_GND_1_o_equal_5_o
|
||||
SLICE_X0Y39.CLK Tas 0.339 CPU_nSTERM_OBUF
|
||||
CPU_nSTERM_rstpot1
|
||||
CPU_nSTERM
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 3.943ns (1.473ns logic, 2.470ns route)
|
||||
(37.4% logic, 62.6% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 6.107ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: LastAWR_16 (FF)
|
||||
Destination: CPU_nSTERM (FF)
|
||||
Requirement: 10.000ns
|
||||
Data Path Delay: 3.716ns (Levels of Logic = 4)
|
||||
Clock Path Skew: -0.029ns (0.720 - 0.749)
|
||||
Source Clock: FSBCLK rising at 0.000ns
|
||||
Destination Clock: FSBCLK rising at 10.000ns
|
||||
Clock Uncertainty: 0.148ns
|
||||
|
||||
Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: LastAWR_16 to CPU_nSTERM
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X0Y23.CQ Tcko 0.525 LastAWR<15>
|
||||
LastAWR_16
|
||||
SLICE_X0Y24.B2 net (fanout=1) 0.744 LastAWR<16>
|
||||
SLICE_X0Y24.COUT Topcyb 0.483 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3>
|
||||
Mcompar_FSB_A[31]_GND_1_o_equal_5_o_lut<1>
|
||||
Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3>
|
||||
SLICE_X0Y25.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3>
|
||||
SLICE_X0Y25.COUT Tbyp 0.093 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7>
|
||||
Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7>
|
||||
SLICE_X0Y26.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7>
|
||||
SLICE_X0Y26.AMUX Tcina 0.230 LastAWR<19>
|
||||
Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<8>
|
||||
SLICE_X0Y39.B4 net (fanout=2) 1.296 FSB_A[31]_GND_1_o_equal_5_o
|
||||
SLICE_X0Y39.CLK Tas 0.339 CPU_nSTERM_OBUF
|
||||
CPU_nSTERM_rstpot1
|
||||
CPU_nSTERM
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 3.716ns (1.670ns logic, 2.046ns route)
|
||||
(44.9% logic, 55.1% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point nRESOE (SLICE_X0Y56.D6), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 8.834ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: nRESOE (FF)
|
||||
Destination: nRESOE (FF)
|
||||
Requirement: 10.000ns
|
||||
Data Path Delay: 1.018ns (Levels of Logic = 1)
|
||||
Clock Path Skew: 0.000ns
|
||||
Source Clock: FSBCLK rising at 0.000ns
|
||||
Destination Clock: FSBCLK rising at 10.000ns
|
||||
Clock Uncertainty: 0.148ns
|
||||
|
||||
Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: nRESOE to nRESOE
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X0Y56.DQ Tcko 0.525 nRESOE_OBUF
|
||||
nRESOE
|
||||
SLICE_X0Y56.D6 net (fanout=2) 0.154 nRESOE_OBUF
|
||||
SLICE_X0Y56.CLK Tas 0.339 nRESOE_OBUF
|
||||
nRESOE_rstpot1_INV_0
|
||||
nRESOE
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 1.018ns (0.864ns logic, 0.154ns route)
|
||||
(84.9% logic, 15.1% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Hold Paths: PERIOD analysis for net "instance_name/clkout0" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
divided by 2.00 to 10 nS
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point LE (SLICE_X10Y2.A6), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (hold path): 0.414ns (requirement - (clock path skew + uncertainty - data path))
|
||||
Source: LE (FF)
|
||||
Destination: LE (FF)
|
||||
Requirement: 0.000ns
|
||||
Data Path Delay: 0.414ns (Levels of Logic = 1)
|
||||
Clock Path Skew: 0.000ns
|
||||
Source Clock: FSBCLK rising at 10.000ns
|
||||
Destination Clock: FSBCLK rising at 10.000ns
|
||||
Clock Uncertainty: 0.000ns
|
||||
|
||||
Minimum Data Path at Fast Process Corner: LE to LE
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X10Y2.AQ Tcko 0.200 LE
|
||||
LE
|
||||
SLICE_X10Y2.A6 net (fanout=2) 0.024 LE
|
||||
SLICE_X10Y2.CLK Tah (-Th) -0.190 LE
|
||||
LE_rstpot1_INV_0
|
||||
LE
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 0.414ns (0.390ns logic, 0.024ns route)
|
||||
(94.2% logic, 5.8% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point nRESOE (SLICE_X0Y56.D6), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (hold path): 0.456ns (requirement - (clock path skew + uncertainty - data path))
|
||||
Source: nRESOE (FF)
|
||||
Destination: nRESOE (FF)
|
||||
Requirement: 0.000ns
|
||||
Data Path Delay: 0.456ns (Levels of Logic = 1)
|
||||
Clock Path Skew: 0.000ns
|
||||
Source Clock: FSBCLK rising at 10.000ns
|
||||
Destination Clock: FSBCLK rising at 10.000ns
|
||||
Clock Uncertainty: 0.000ns
|
||||
|
||||
Minimum Data Path at Fast Process Corner: nRESOE to nRESOE
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X0Y56.DQ Tcko 0.234 nRESOE_OBUF
|
||||
nRESOE
|
||||
SLICE_X0Y56.D6 net (fanout=2) 0.025 nRESOE_OBUF
|
||||
SLICE_X0Y56.CLK Tah (-Th) -0.197 nRESOE_OBUF
|
||||
nRESOE_rstpot1_INV_0
|
||||
nRESOE
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 0.456ns (0.431ns logic, 0.025ns route)
|
||||
(94.5% logic, 5.5% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point CPUCLKr0 (SLICE_X4Y28.A6), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (hold path): 0.456ns (requirement - (clock path skew + uncertainty - data path))
|
||||
Source: CPUCLKr0 (FF)
|
||||
Destination: CPUCLKr0 (FF)
|
||||
Requirement: 0.000ns
|
||||
Data Path Delay: 0.456ns (Levels of Logic = 1)
|
||||
Clock Path Skew: 0.000ns
|
||||
Source Clock: FSBCLK rising at 10.000ns
|
||||
Destination Clock: FSBCLK rising at 10.000ns
|
||||
Clock Uncertainty: 0.000ns
|
||||
|
||||
Minimum Data Path at Fast Process Corner: CPUCLKr0 to CPUCLKr0
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X4Y28.AQ Tcko 0.234 CPUCLKr0
|
||||
CPUCLKr0
|
||||
SLICE_X4Y28.A6 net (fanout=2) 0.025 CPUCLKr0
|
||||
SLICE_X4Y28.CLK Tah (-Th) -0.197 CPUCLKr0
|
||||
CPUCLKr0_INV_2_o1_INV_0
|
||||
CPUCLKr0
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 0.456ns (0.431ns logic, 0.025ns route)
|
||||
(94.5% logic, 5.5% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout0" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
divided by 2.00 to 10 nS
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 7.334ns (period - min period limit)
|
||||
Period: 10.000ns
|
||||
Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
|
||||
Physical resource: instance_name/clkout1_buf/I0
|
||||
Logical resource: instance_name/clkout1_buf/I0
|
||||
Location pin: BUFGMUX_X2Y2.I0
|
||||
Clock network: instance_name/clkout0
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 7.751ns (period - min period limit)
|
||||
Period: 10.000ns
|
||||
Min period limit: 2.249ns (444.642MHz) (Tockper)
|
||||
Physical resource: CPU_nBERR_OBUF/CLK0
|
||||
Logical resource: CPU_nBERR/CK0
|
||||
Location pin: OLOGIC_X0Y49.CLK0
|
||||
Clock network: FSBCLK
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 7.751ns (period - min period limit)
|
||||
Period: 10.000ns
|
||||
Min period limit: 2.249ns (444.642MHz) (Tockper)
|
||||
Physical resource: RAM_CLK01_OBUF/CLK0
|
||||
Logical resource: RAM_CLK01_ODDR_inst/CK0
|
||||
Location pin: OLOGIC_X0Y51.CLK0
|
||||
Clock network: FSBCLK
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Derived Constraint Report
|
||||
Derived Constraints for instance_name/clkin1
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
| | Period | Actual Period | Timing Errors | Paths Analyzed |
|
||||
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|
||||
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|instance_name/clkin1 | 20.000ns| 5.000ns| 14.164ns| 0| 0| 0| 57|
|
||||
| instance_name/clkfbout | 20.000ns| 2.666ns| N/A| 0| 0| 0| 0|
|
||||
| instance_name/clkout1 | 10.000ns| 7.082ns| N/A| 0| 0| 3| 0|
|
||||
| instance_name/clkout0 | 10.000ns| 4.697ns| N/A| 0| 0| 54| 0|
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|
||||
All constraints were met.
|
||||
|
||||
|
||||
Data Sheet report:
|
||||
-----------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
Clock to Setup on destination clock CLKIN
|
||||
---------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
---------------+---------+---------+---------+---------+
|
||||
CLKIN | 4.697| 3.541| 2.138| |
|
||||
---------------+---------+---------+---------+---------+
|
||||
|
||||
|
||||
Timing summary:
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
|
||||
|
||||
Constraints cover 57 paths, 0 nets, and 93 connections
|
||||
|
||||
Design statistics:
|
||||
Minimum period: 7.082ns{1} (Maximum frequency: 141.203MHz)
|
||||
|
||||
|
||||
------------------------------------Footnotes-----------------------------------
|
||||
1) The minimum period statistic assumes all single cycle delays.
|
||||
|
||||
Analysis completed Fri Oct 29 10:03:09 2021
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Trace Settings:
|
||||
-------------------------
|
||||
Trace Settings
|
||||
|
||||
Peak Memory Usage: 168 MB
|
||||
|
||||
|
||||
|
||||
367
fpga/WarpLC.twx
Normal file
367
fpga/WarpLC.twx
Normal file
File diff suppressed because one or more lines are too long
9
fpga/WarpLC.unroutes
Normal file
9
fpga/WarpLC.unroutes
Normal file
@ -0,0 +1,9 @@
|
||||
Release 14.7 - par P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Fri Oct 29 10:03:06 2021
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
|
||||
377
fpga/WarpLC.v
Normal file
377
fpga/WarpLC.v
Normal file
@ -0,0 +1,377 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 06:27:24 10/29/2021
|
||||
// Design Name:
|
||||
// Module Name: WarpLC
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module WarpLC(
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
inout [2:0] FSB_FC,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
inout [31:0] FSB_A,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
inout FSB_RnW,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
inout FSB_nRMC,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input [1:0] FSB_SIZ,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CPU_nCIOUT,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output CPU_nAOE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CPU_nECS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CPU_nAS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CPU_nDS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CPU_nCBREQ,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output CPU_nDSACK,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output CPU_nDSACKOE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output CPU_nDOE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
output CPU_DDIR,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
inout [31:0] FSB_D,
|
||||
|
||||
(* IOB = "FORCE" *)
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output reg CPUCLK,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CPUCLKIN,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CLKIN,
|
||||
|
||||
(* IOB = "FORCE" *)
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output reg FPUCLK,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output nFPUCS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output reg CPU_nSTERM,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output CPU_nCBACK,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output CPU_nCIIN,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output reg CPU_nHALT,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output reg CPU_nBERR,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_nCS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_nRAS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_nCAS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_nWE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_CKE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output [1:0] RAM_BA,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output [12:0] RAM_A,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output [3:0] RAM_DQM,
|
||||
|
||||
(* IOB = "FORCE" *)
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_CLK01,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_CLK23,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output [3:0] IOB_A,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output [1:0] IOB_SIZ,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output IOB_nAOE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output IOB_ADoutLE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output IOB_nAS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output IOB_nDS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input [1:0] IOB_nDSACK,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output IOB_nDOE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output IOB_DDIR,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
inout [31:0] IOB_D,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output reg nRESOE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input nRES,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input IOBCLK,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input IOB_nHALT,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input IOB_nBERR,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CLKFB_IN,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output CLKFB_OUT);
|
||||
|
||||
wire FSBCLK, CPUCLKi;
|
||||
CLK instance_name (
|
||||
.CLKIN(CLKIN),
|
||||
.CLKFB_IN(CLKFB_IN),
|
||||
.FSBCLK(FSBCLK),
|
||||
.CPUCLK(CPUCLKi),
|
||||
.CLKFB_OUT(CLKFB_OUT));
|
||||
|
||||
reg CPUCLKr0 = 0;
|
||||
reg CPUCLKr1 = 0;
|
||||
reg CPUCLKd = 0;
|
||||
always @(posedge FSBCLK) begin
|
||||
CPUCLKr0 <= ~CPUCLKr0;
|
||||
end
|
||||
always @(negedge CPUCLKi) begin
|
||||
CPUCLKr1 <= CPUCLKr0;
|
||||
end
|
||||
always @(posedge CPUCLKi) begin
|
||||
CPUCLK <= CPUCLKr1;
|
||||
FPUCLK <= CPUCLKr1;
|
||||
end
|
||||
|
||||
wire RAM_CLK01_ODDR;
|
||||
assign RAM_CLK01 = RAM_CLK01_ODDR;
|
||||
ODDR2 #(
|
||||
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
||||
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
|
||||
.SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
|
||||
RAM_CLK01_ODDR_inst (
|
||||
.Q(RAM_CLK01_ODDR), // 1-bit DDR output data
|
||||
.C0(FSBCLK), // 1-bit clock input
|
||||
.C1(~FSBCLK), // 1-bit clock input
|
||||
.CE(1'b1), // 1-bit clock enable input
|
||||
.D0(1'b0), // 1-bit data input (associated with C0)
|
||||
.D1(1'b1), // 1-bit data input (associated with C1)
|
||||
.R(1'b0), // 1-bit reset input
|
||||
.S(1'b0)); // 1-bit set input
|
||||
|
||||
assign CPU_nDSACK = ~((FSB_A[31:2]==LastA[31:2] || FSB_A[31:1]==LastAWR[31:11]) && FSB_RnW);
|
||||
|
||||
reg [31:2] LastA;
|
||||
reg [31:11] LastAWR;
|
||||
always @(posedge FSBCLK) begin
|
||||
if (FSB_RnW && ~CPU_nAS) LastA[31:2] <= FSB_A[31:2] + 1;
|
||||
if (~FSB_RnW && ~CPU_nAS) LastAWR[31:11] <= FSB_A[31:11];
|
||||
CPU_nSTERM <= ~((FSB_A[31:2]==LastA[31:2] || FSB_A[31:1]==LastAWR[31:11]) && FSB_RnW);
|
||||
nRESOE <= ~nRESOE;
|
||||
end
|
||||
|
||||
wire FPUCS = FSB_FC[02:00]==3'h7 && FSB_A[19:16]==4'h2 && FSB_A[15:13]==3'h1;
|
||||
assign nFPUCS = ~((FPUCS && ~CPUCLKIN) || (FPUCS && ~CPU_nAS));
|
||||
|
||||
(* IOB = "FORCE" *)
|
||||
reg LHALT;
|
||||
reg LE;
|
||||
always @(posedge FSBCLK) begin
|
||||
LE <= ~LE;
|
||||
end
|
||||
always @(LE, IOB_nHALT) begin
|
||||
if (~LE) begin
|
||||
LHALT <= IOB_nHALT;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge FSBCLK) begin
|
||||
CPU_nBERR <= LHALT;
|
||||
end
|
||||
|
||||
endmodule
|
||||
411
fpga/WarpLC.xise
Normal file
411
fpga/WarpLC.xise
Normal file
@ -0,0 +1,411 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="WarpLC.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/CLK.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="PLL.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/CLK.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|WarpLC" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="WarpLC.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/WarpLC" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="WarpLC" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ftg256" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="WarpLC_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="WarpLC_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="WarpLC_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="WarpLC_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target UCF File Name" xil_pn:value="PLL.ucf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="WarpLC" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-10-29T06:11:44" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="048F5CC81F664AF08A457B4C46CE1270" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
3
fpga/WarpLC.xpi
Normal file
3
fpga/WarpLC.xpi
Normal file
@ -0,0 +1,3 @@
|
||||
PROGRAM=PAR
|
||||
STATE=ROUTED
|
||||
TIMESPECS_MET=YES
|
||||
53
fpga/WarpLC.xst
Normal file
53
fpga/WarpLC.xst
Normal file
@ -0,0 +1,53 @@
|
||||
set -tmpdir "xst/projnav.tmp"
|
||||
set -xsthdpdir "xst"
|
||||
run
|
||||
-ifn WarpLC.prj
|
||||
-ofn WarpLC
|
||||
-ofmt NGC
|
||||
-p xc6slx9-2-ftg256
|
||||
-top WarpLC
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-keep_hierarchy No
|
||||
-netlist_hierarchy As_Optimized
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-sd {"ipcore_dir" }
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case Maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-lc Auto
|
||||
-reduce_control_sets Auto
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style LUT
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-shreg_extract YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-shreg_min_size 2
|
||||
-use_dsp48 Auto
|
||||
-iobuf YES
|
||||
-max_fanout 100000
|
||||
-bufg 16
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob Auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
550
fpga/WarpLC_envsettings.html
Normal file
550
fpga/WarpLC_envsettings.html
Normal file
@ -0,0 +1,550 @@
|
||||
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<center><big><big><b>System Settings</b></big></big></center><br>
|
||||
<A NAME="Environment Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Environment Variable</b></td>
|
||||
<td><b>xst</b></td>
|
||||
<td><b>ngdbuild</b></td>
|
||||
<td><b>map</b></td>
|
||||
<td><b>par</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>PATHEXT</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Path</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_DSP</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_PLANAHEAD</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Synthesis Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ifn</td>
|
||||
<td> </td>
|
||||
<td>WarpLC.prj</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ofn</td>
|
||||
<td> </td>
|
||||
<td>WarpLC</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ofmt</td>
|
||||
<td> </td>
|
||||
<td>NGC</td>
|
||||
<td>NGC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xc6slx9-2-ftg256</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-top</td>
|
||||
<td> </td>
|
||||
<td>WarpLC</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-opt_mode</td>
|
||||
<td>Optimization Goal</td>
|
||||
<td>Speed</td>
|
||||
<td>Speed</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-opt_level</td>
|
||||
<td>Optimization Effort</td>
|
||||
<td>1</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-power</td>
|
||||
<td>Power Reduction</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iuc</td>
|
||||
<td>Use synthesis Constraints File</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-keep_hierarchy</td>
|
||||
<td>Keep Hierarchy</td>
|
||||
<td>No</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-netlist_hierarchy</td>
|
||||
<td>Netlist Hierarchy</td>
|
||||
<td>As_Optimized</td>
|
||||
<td>As_Optimized</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rtlview</td>
|
||||
<td>Generate RTL Schematic</td>
|
||||
<td>Yes</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-glob_opt</td>
|
||||
<td>Global Optimization Goal</td>
|
||||
<td>AllClockNets</td>
|
||||
<td>AllClockNets</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-read_cores</td>
|
||||
<td>Read Cores</td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-sd</td>
|
||||
<td>Cores Search Directories</td>
|
||||
<td>{"ipcore_dir" }</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-write_timing_constraints</td>
|
||||
<td>Write Timing Constraints</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-cross_clock_analysis</td>
|
||||
<td>Cross Clock Analysis</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bus_delimiter</td>
|
||||
<td>Bus Delimiter</td>
|
||||
<td><></td>
|
||||
<td><></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-slice_utilization_ratio</td>
|
||||
<td>Slice Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bram_utilization_ratio</td>
|
||||
<td>BRAM Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-dsp_utilization_ratio</td>
|
||||
<td>DSP Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-reduce_control_sets</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_extract</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_encoding</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-safe_implementation</td>
|
||||
<td> </td>
|
||||
<td>No</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_style</td>
|
||||
<td> </td>
|
||||
<td>LUT</td>
|
||||
<td>LUT</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ram_extract</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ram_style</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rom_extract</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-shreg_extract</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rom_style</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-auto_bram_packing</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-resource_sharing</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-async_to_sync</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_dsp48</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iobuf</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-max_fanout</td>
|
||||
<td> </td>
|
||||
<td>100000</td>
|
||||
<td>100000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bufg</td>
|
||||
<td> </td>
|
||||
<td>16</td>
|
||||
<td>16</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-register_duplication</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-register_balancing</td>
|
||||
<td> </td>
|
||||
<td>No</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-optimize_primitives</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_clock_enable</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_sync_set</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_sync_reset</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iob</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-equivalent_register_removal</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-slice_utilization_ratio_maxmargin</td>
|
||||
<td> </td>
|
||||
<td>5</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Translation Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-dd</td>
|
||||
<td> </td>
|
||||
<td>_ngo</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xc6slx9-ftg256-2</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-sd</td>
|
||||
<td>Macro Search Path</td>
|
||||
<td>ipcore_dir</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-uc</td>
|
||||
<td> </td>
|
||||
<td>PLL.ucf</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Map Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ol</td>
|
||||
<td>Place & Route Effort Level (Overall)</td>
|
||||
<td>high</td>
|
||||
<td>high</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-xt</td>
|
||||
<td>Extra Cost Tables</td>
|
||||
<td>0</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ir</td>
|
||||
<td>Use RLOC Constraints</td>
|
||||
<td>OFF</td>
|
||||
<td>OFF</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-t</td>
|
||||
<td>Starting Placer Cost Table (1-100) Map</td>
|
||||
<td>1</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-r</td>
|
||||
<td>Register Ordering</td>
|
||||
<td>4</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-lc</td>
|
||||
<td>LUT Combining</td>
|
||||
<td>off</td>
|
||||
<td>off</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-o</td>
|
||||
<td> </td>
|
||||
<td>WarpLC_map.ncd</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-w</td>
|
||||
<td> </td>
|
||||
<td>true</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-pr</td>
|
||||
<td>Pack I/O Registers/Latches into IOBs</td>
|
||||
<td>off</td>
|
||||
<td>off</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xc6slx9-ftg256-2</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Place and Route Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-mt</td>
|
||||
<td>Enable Multi-Threading</td>
|
||||
<td>off</td>
|
||||
<td>off</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ol</td>
|
||||
<td>Place & Route Effort Level (Overall)</td>
|
||||
<td>high</td>
|
||||
<td>std</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-w</td>
|
||||
<td> </td>
|
||||
<td>true</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Operating System Information"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Operating System Information</b></td>
|
||||
<td><b>xst</b></td>
|
||||
<td><b>ngdbuild</b></td>
|
||||
<td><b>map</b></td>
|
||||
<td><b>par</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>CPU Architecture/Speed</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Host</td>
|
||||
<td>ZanePC</td>
|
||||
<td>ZanePC</td>
|
||||
<td>ZanePC</td>
|
||||
<td>ZanePC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Name</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Release</td>
|
||||
<td>major release (build 9200)</td>
|
||||
<td>major release (build 9200)</td>
|
||||
<td>major release (build 9200)</td>
|
||||
<td>major release (build 9200)</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
</BODY> </HTML>
|
||||
150
fpga/WarpLC_fpga_editor.log
Normal file
150
fpga/WarpLC_fpga_editor.log
Normal file
@ -0,0 +1,150 @@
|
||||
#:C49
|
||||
#Xilinx FPGA Editor Command Log File
|
||||
#Editor Version:
|
||||
#:V NT M2.1 P.20131013
|
||||
#Current Working Directory:
|
||||
#:D C:\Users\zanek\Documents\GitHub\Warp-LC\fpga
|
||||
#Date/Time:
|
||||
#:T Fri Oct 29 09:30:37 2021
|
||||
#------------------------------
|
||||
#Reading WarpLC.ncd...
|
||||
#Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
|
||||
# "WarpLC" is an NCD, version 3.2, device xc6slx9, package ftg256, speed -2
|
||||
#Design creation date: 2021.10.29.13.29.43
|
||||
#Building chip graphics...
|
||||
#Loading speed info...
|
||||
#1
|
||||
setattr main edit-mode no-logic-changes
|
||||
#2
|
||||
select -k comp 'LHALT'
|
||||
#3
|
||||
unselect -all
|
||||
#4
|
||||
select comp 'LHALT'
|
||||
#comp "LHALT", site "ILOGIC_X6Y0", type = ILOGIC2 (RPM grid X34Y0)
|
||||
#5
|
||||
unselect -all
|
||||
#6
|
||||
select comp 'LHALT'
|
||||
#comp "LHALT", site "ILOGIC_X6Y0", type = ILOGIC2 (RPM grid X34Y0)
|
||||
#7
|
||||
post block
|
||||
#8
|
||||
unselect -all
|
||||
#9
|
||||
unselect -all
|
||||
#10
|
||||
unselect -all
|
||||
#11
|
||||
post block
|
||||
#ERROR:FPGAEditor:79 - The "post block" command without any other arguments cannot
|
||||
#be performed unless the selection contains only a single site
|
||||
#or single component. Change the selection and try again.
|
||||
#12
|
||||
unselect -all
|
||||
#13
|
||||
unselect -all
|
||||
#14
|
||||
unselect -all
|
||||
#15
|
||||
select site 'TIEOFF_X14Y0'
|
||||
#site "TIEOFF_X14Y0", type = TIEOFF (RPM grid X32Y0)
|
||||
#16
|
||||
unselect -all
|
||||
#17
|
||||
select site 'TIEOFF_X14Y0'
|
||||
#site "TIEOFF_X14Y0", type = TIEOFF (RPM grid X32Y0)
|
||||
#18
|
||||
post block
|
||||
#19
|
||||
unselect -all
|
||||
#20
|
||||
select site 'TIEOFF_X15Y0'
|
||||
#site "TIEOFF_X15Y0", type = TIEOFF (RPM grid X33Y1)
|
||||
#21
|
||||
post block
|
||||
#22
|
||||
unselect -all
|
||||
#23
|
||||
unselect -all
|
||||
#24
|
||||
unselect -all
|
||||
#25
|
||||
unselect -all
|
||||
#26
|
||||
unselect -all
|
||||
#27
|
||||
select site 'ILOGIC_X6Y2'
|
||||
#site "ILOGIC_X6Y2", type = ILOGIC2 (RPM grid X34Y4)
|
||||
#28
|
||||
unselect -all
|
||||
#29
|
||||
select site 'ILOGIC_X6Y2'
|
||||
#site "ILOGIC_X6Y2", type = ILOGIC2 (RPM grid X34Y4)
|
||||
#30
|
||||
post block
|
||||
#31
|
||||
unselect -all
|
||||
#32
|
||||
post block
|
||||
#ERROR:FPGAEditor:79 - The "post block" command without any other arguments cannot
|
||||
#be performed unless the selection contains only a single site
|
||||
#or single component. Change the selection and try again.
|
||||
#33
|
||||
unselect -all
|
||||
#34
|
||||
select comp 'LE'
|
||||
#comp "LE", site "SLICE_X11Y2", type = SLICEX (RPM grid X35Y8)
|
||||
#35
|
||||
unselect -all
|
||||
#36
|
||||
select comp 'LE'
|
||||
#comp "LE", site "SLICE_X11Y2", type = SLICEX (RPM grid X35Y8)
|
||||
#37
|
||||
post block
|
||||
#38
|
||||
unselect -all
|
||||
#39
|
||||
select pin 'SLICE_X0Y29.WE'
|
||||
#site.pin = SLICE_X0Y29.WE
|
||||
#40
|
||||
unselect -all
|
||||
#41
|
||||
select pin 'SLICE_X0Y29.WE'
|
||||
#site.pin = SLICE_X0Y29.WE
|
||||
#42
|
||||
unselect -all
|
||||
#43
|
||||
select pin 'SLICE_X0Y29.WE'
|
||||
#site.pin = SLICE_X0Y29.WE
|
||||
#44
|
||||
post block
|
||||
#ERROR:FPGAEditor:79 - The "post block" command without any other arguments cannot
|
||||
#be performed unless the selection contains only a single site
|
||||
#or single component. Change the selection and try again.
|
||||
#45
|
||||
unselect -all
|
||||
#46
|
||||
unselect -all
|
||||
#47
|
||||
select comp 'nFPUCS2'
|
||||
#comp "nFPUCS2", site "SLICE_X0Y29", type = SLICEX (RPM grid X5Y116)
|
||||
#48
|
||||
unselect -all
|
||||
#49
|
||||
select comp 'nFPUCS2'
|
||||
#comp "nFPUCS2", site "SLICE_X0Y29", type = SLICEX (RPM grid X5Y116)
|
||||
#50
|
||||
unselect -all
|
||||
#51
|
||||
select comp 'nFPUCS2'
|
||||
#comp "nFPUCS2", site "SLICE_X0Y29", type = SLICEX (RPM grid X5Y116)
|
||||
#52
|
||||
post block
|
||||
#53
|
||||
unselect -all
|
||||
#54
|
||||
select comp 'LastA<31>'
|
||||
#comp "LastA<31>", site "SLICE_X0Y27", type = SLICEL (RPM grid X5Y108)
|
||||
#55
|
||||
post block
|
||||
3
fpga/WarpLC_guide.ncd
Normal file
3
fpga/WarpLC_guide.ncd
Normal file
File diff suppressed because one or more lines are too long
180
fpga/WarpLC_map.map
Normal file
180
fpga/WarpLC_map.map
Normal file
@ -0,0 +1,180 @@
|
||||
Release 14.7 Map P.20131013 (nt)
|
||||
Xilinx Map Application Log File for Design 'WarpLC'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol
|
||||
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
|
||||
-pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
Target Device : xc6slx9
|
||||
Target Package : ftg256
|
||||
Target Speed : -2
|
||||
Mapper Version : spartan6 -- $Revision: 1.55 $
|
||||
Mapped Date : Fri Oct 29 10:02:57 2021
|
||||
|
||||
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
|
||||
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
|
||||
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
|
||||
'C:\ispLEVER_Classic2_0\license\license.dat;C:\lscc\diamond\3.12\license\license
|
||||
.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'.
|
||||
INFO:Security:54 - 'xc6slx9' is a WebPack part.
|
||||
INFO:Security:66 - Your license for 'ISE' is for evaluation use only.
|
||||
WARNING:Security:43 - No license file was found in the standard Xilinx license
|
||||
directory.
|
||||
WARNING:Security:44 - Since no license file was found,
|
||||
please run the Xilinx License Configuration Manager
|
||||
(xlcm or "Manage Xilinx Licenses")
|
||||
to assist in obtaining a license.
|
||||
WARNING:Security:40 - Your license for 'ISE' expires in 4 days.
|
||||
----------------------------------------------------------------------
|
||||
Mapping design into LUTs...
|
||||
WARNING:MapLib:53 - The offset specification "OFFSET=IN 10000 pS VALID 11000 pS
|
||||
BEFORE FSBCLK" has been discarded because the referenced clock pad net
|
||||
(FSBCLK) was optimized away.
|
||||
Running directed packing...
|
||||
Running delay-based LUT packing...
|
||||
Updating timing models...
|
||||
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
|
||||
(.mrp).
|
||||
Running timing-driven placement...
|
||||
Total REAL time at the beginning of Placer: 2 secs
|
||||
Total CPU time at the beginning of Placer: 2 secs
|
||||
|
||||
Phase 1.1 Initial Placement Analysis
|
||||
Phase 1.1 Initial Placement Analysis (Checksum:67ca) REAL time: 2 secs
|
||||
|
||||
Phase 2.7 Design Feasibility Check
|
||||
Phase 2.7 Design Feasibility Check (Checksum:67ca) REAL time: 2 secs
|
||||
|
||||
Phase 3.31 Local Placement Optimization
|
||||
Phase 3.31 Local Placement Optimization (Checksum:67ca) REAL time: 2 secs
|
||||
|
||||
Phase 4.2 Initial Placement for Architecture Specific Features
|
||||
...
|
||||
......
|
||||
Phase 4.2 Initial Placement for Architecture Specific Features
|
||||
(Checksum:2cdc04b) REAL time: 3 secs
|
||||
|
||||
Phase 5.36 Local Placement Optimization
|
||||
Phase 5.36 Local Placement Optimization (Checksum:2cdc04b) REAL time: 3 secs
|
||||
|
||||
Phase 6.30 Global Clock Region Assignment
|
||||
Phase 6.30 Global Clock Region Assignment (Checksum:2cdc04b) REAL time: 3 secs
|
||||
|
||||
Phase 7.3 Local Placement Optimization
|
||||
....
|
||||
Phase 7.3 Local Placement Optimization (Checksum:c5a22b64) REAL time: 3 secs
|
||||
|
||||
Phase 8.5 Local Placement Optimization
|
||||
Phase 8.5 Local Placement Optimization (Checksum:c5a22b64) REAL time: 3 secs
|
||||
|
||||
Phase 9.8 Global Placement
|
||||
..
|
||||
................
|
||||
..
|
||||
Phase 9.8 Global Placement (Checksum:3e86b47) REAL time: 3 secs
|
||||
|
||||
Phase 10.5 Local Placement Optimization
|
||||
Phase 10.5 Local Placement Optimization (Checksum:3e86b47) REAL time: 3 secs
|
||||
|
||||
Phase 11.18 Placement Optimization
|
||||
Phase 11.18 Placement Optimization (Checksum:8081ee) REAL time: 4 secs
|
||||
|
||||
Phase 12.5 Local Placement Optimization
|
||||
Phase 12.5 Local Placement Optimization (Checksum:8081ee) REAL time: 4 secs
|
||||
|
||||
Phase 13.34 Placement Validation
|
||||
Phase 13.34 Placement Validation (Checksum:8081ee) REAL time: 4 secs
|
||||
|
||||
Total REAL time to Placer completion: 4 secs
|
||||
Total CPU time to Placer completion: 4 secs
|
||||
Running post-placement packing...
|
||||
Writing output files...
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Design Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 1
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 56 out of 11,440 1%
|
||||
Number used as Flip Flops: 56
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 59 out of 5,720 1%
|
||||
Number used as logic: 56 out of 5,720 1%
|
||||
Number using O6 output only: 24
|
||||
Number using O5 output only: 29
|
||||
Number using O5 and O6: 3
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 0 out of 1,440 0%
|
||||
Number used exclusively as route-thrus: 3
|
||||
Number with same-slice register load: 2
|
||||
Number with same-slice carry load: 1
|
||||
Number with other load: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 25 out of 1,430 1%
|
||||
Number of MUXCYs used: 56 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 76
|
||||
Number with an unused Flip Flop: 22 out of 76 28%
|
||||
Number with an unused LUT: 17 out of 76 22%
|
||||
Number of fully used LUT-FF pairs: 37 out of 76 48%
|
||||
Number of unique control sets: 4
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 16 out of 11,440 1%
|
||||
|
||||
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
||||
one Flip Flop within a slice. A control set is a unique combination of
|
||||
clock, reset, set, and enable signals for a registered element.
|
||||
The Slice Logic Distribution report is not meaningful if the design is
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 49 out of 186 26%
|
||||
IOB Flip Flops: 5
|
||||
IOB Latches: 1
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 0 out of 32 0%
|
||||
Number of RAMB8BWERs: 0 out of 64 0%
|
||||
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2s: 1
|
||||
Number used as BUFIO2_2CLKs: 0
|
||||
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2FBs: 1
|
||||
Number used as BUFIO2FB_2CLKs: 0
|
||||
Number of BUFG/BUFGMUXs: 3 out of 16 18%
|
||||
Number used as BUFGs: 3
|
||||
Number used as BUFGMUX: 0
|
||||
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
|
||||
Number of ILOGIC2/ISERDES2s: 1 out of 200 1%
|
||||
Number used as ILOGIC2s: 1
|
||||
Number used as ISERDES2s: 0
|
||||
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
|
||||
Number of OLOGIC2/OSERDES2s: 5 out of 200 2%
|
||||
Number used as OLOGIC2s: 5
|
||||
Number used as OSERDES2s: 0
|
||||
Number of BSCANs: 0 out of 4 0%
|
||||
Number of BUFHs: 0 out of 128 0%
|
||||
Number of BUFPLLs: 0 out of 8 0%
|
||||
Number of BUFPLL_MCBs: 0 out of 4 0%
|
||||
Number of DSP48A1s: 0 out of 16 0%
|
||||
Number of ICAPs: 0 out of 1 0%
|
||||
Number of MCBs: 0 out of 2 0%
|
||||
Number of PCILOGICSEs: 0 out of 2 0%
|
||||
Number of PLL_ADVs: 1 out of 2 50%
|
||||
Number of PMVs: 0 out of 1 0%
|
||||
Number of STARTUPs: 0 out of 1 0%
|
||||
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 2.16
|
||||
|
||||
Peak Memory Usage: 272 MB
|
||||
Total REAL time to MAP completion: 4 secs
|
||||
Total CPU time to MAP completion: 4 secs
|
||||
|
||||
Mapping completed.
|
||||
See MAP report file "WarpLC_map.mrp" for details.
|
||||
274
fpga/WarpLC_map.mrp
Normal file
274
fpga/WarpLC_map.mrp
Normal file
@ -0,0 +1,274 @@
|
||||
Release 14.7 Map P.20131013 (nt)
|
||||
Xilinx Mapping Report File for Design 'WarpLC'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol
|
||||
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
|
||||
-pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
Target Device : xc6slx9
|
||||
Target Package : ftg256
|
||||
Target Speed : -2
|
||||
Mapper Version : spartan6 -- $Revision: 1.55 $
|
||||
Mapped Date : Fri Oct 29 10:02:57 2021
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
Number of errors: 0
|
||||
Number of warnings: 1
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 56 out of 11,440 1%
|
||||
Number used as Flip Flops: 56
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 59 out of 5,720 1%
|
||||
Number used as logic: 56 out of 5,720 1%
|
||||
Number using O6 output only: 24
|
||||
Number using O5 output only: 29
|
||||
Number using O5 and O6: 3
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 0 out of 1,440 0%
|
||||
Number used exclusively as route-thrus: 3
|
||||
Number with same-slice register load: 2
|
||||
Number with same-slice carry load: 1
|
||||
Number with other load: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 25 out of 1,430 1%
|
||||
Number of MUXCYs used: 56 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 76
|
||||
Number with an unused Flip Flop: 22 out of 76 28%
|
||||
Number with an unused LUT: 17 out of 76 22%
|
||||
Number of fully used LUT-FF pairs: 37 out of 76 48%
|
||||
Number of unique control sets: 4
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 16 out of 11,440 1%
|
||||
|
||||
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
||||
one Flip Flop within a slice. A control set is a unique combination of
|
||||
clock, reset, set, and enable signals for a registered element.
|
||||
The Slice Logic Distribution report is not meaningful if the design is
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 49 out of 186 26%
|
||||
IOB Flip Flops: 5
|
||||
IOB Latches: 1
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 0 out of 32 0%
|
||||
Number of RAMB8BWERs: 0 out of 64 0%
|
||||
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2s: 1
|
||||
Number used as BUFIO2_2CLKs: 0
|
||||
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2FBs: 1
|
||||
Number used as BUFIO2FB_2CLKs: 0
|
||||
Number of BUFG/BUFGMUXs: 3 out of 16 18%
|
||||
Number used as BUFGs: 3
|
||||
Number used as BUFGMUX: 0
|
||||
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
|
||||
Number of ILOGIC2/ISERDES2s: 1 out of 200 1%
|
||||
Number used as ILOGIC2s: 1
|
||||
Number used as ISERDES2s: 0
|
||||
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
|
||||
Number of OLOGIC2/OSERDES2s: 5 out of 200 2%
|
||||
Number used as OLOGIC2s: 5
|
||||
Number used as OSERDES2s: 0
|
||||
Number of BSCANs: 0 out of 4 0%
|
||||
Number of BUFHs: 0 out of 128 0%
|
||||
Number of BUFPLLs: 0 out of 8 0%
|
||||
Number of BUFPLL_MCBs: 0 out of 4 0%
|
||||
Number of DSP48A1s: 0 out of 16 0%
|
||||
Number of ICAPs: 0 out of 1 0%
|
||||
Number of MCBs: 0 out of 2 0%
|
||||
Number of PCILOGICSEs: 0 out of 2 0%
|
||||
Number of PLL_ADVs: 1 out of 2 50%
|
||||
Number of PMVs: 0 out of 1 0%
|
||||
Number of STARTUPs: 0 out of 1 0%
|
||||
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 2.16
|
||||
|
||||
Peak Memory Usage: 272 MB
|
||||
Total REAL time to MAP completion: 4 secs
|
||||
Total CPU time to MAP completion: 4 secs
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
Section 1 - Errors
|
||||
Section 2 - Warnings
|
||||
Section 3 - Informational
|
||||
Section 4 - Removed Logic Summary
|
||||
Section 5 - Removed Logic
|
||||
Section 6 - IOB Properties
|
||||
Section 7 - RPMs
|
||||
Section 8 - Guide Report
|
||||
Section 9 - Area Group and Partition Summary
|
||||
Section 10 - Timing Report
|
||||
Section 11 - Configuration String Information
|
||||
Section 12 - Control Set Information
|
||||
Section 13 - Utilization by Hierarchy
|
||||
|
||||
Section 1 - Errors
|
||||
------------------
|
||||
|
||||
Section 2 - Warnings
|
||||
--------------------
|
||||
WARNING:Security:43 - No license file was found in the standard Xilinx license
|
||||
directory.
|
||||
WARNING:Security:44 - Since no license file was found,
|
||||
WARNING:Security:40 - Your license for 'ISE' expires in 4 days.
|
||||
WARNING:MapLib:53 - The offset specification "OFFSET=IN 10000 pS VALID 11000 pS
|
||||
BEFORE FSBCLK" has been discarded because the referenced clock pad net
|
||||
(FSBCLK) was optimized away.
|
||||
|
||||
Section 3 - Informational
|
||||
-------------------------
|
||||
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
|
||||
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
|
||||
'C:\ispLEVER_Classic2_0\license\license.dat;C:\lscc\diamond\3.12\license\license
|
||||
.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'.
|
||||
INFO:Security:54 - 'xc6slx9' is a WebPack part.
|
||||
INFO:Security:66 - Your license for 'ISE' is for evaluation use only.
|
||||
INFO:LIT:243 - Logical network FSB_A<0> has no load.
|
||||
INFO:LIT:395 - The above info message is repeated 120 more times for the
|
||||
following (max. 5 shown):
|
||||
FSB_SIZ<1>,
|
||||
FSB_SIZ<0>,
|
||||
IOB_nDSACK<1>,
|
||||
IOB_nDSACK<0>,
|
||||
CPU_nCIOUT
|
||||
To see the details of these info messages, please use the -detail switch.
|
||||
INFO:MapLib:562 - No environment variables are currently set.
|
||||
INFO:MapLib:159 - Net Timing constraints on signal CLKIN are pushed forward
|
||||
through input buffer.
|
||||
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
|
||||
0.000 to 85.000 Celsius)
|
||||
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
|
||||
1.260 Volts)
|
||||
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
|
||||
(.mrp).
|
||||
INFO:Pack:1650 - Map created a placed design.
|
||||
|
||||
Section 4 - Removed Logic Summary
|
||||
---------------------------------
|
||||
2 block(s) optimized away
|
||||
|
||||
Section 5 - Removed Logic
|
||||
-------------------------
|
||||
|
||||
Optimized Block(s):
|
||||
TYPE BLOCK
|
||||
GND XST_GND
|
||||
VCC XST_VCC
|
||||
|
||||
To enable printing of redundant blocks removed and signals merged, set the
|
||||
detailed map report option and rerun map.
|
||||
|
||||
Section 6 - IOB Properties
|
||||
--------------------------
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
|
||||
| | | | | Term | Strength | Rate | | | Delay |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| CLKFB_IN | IOB | INPUT | LVCMOS25 | | | | | | |
|
||||
| CLKFB_OUT | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
| CLKIN | IOB | INPUT | LVCMOS25 | | | | | | |
|
||||
| CPUCLK | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | OFF | | |
|
||||
| CPUCLKIN | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| CPU_nAS | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| CPU_nBERR | IOB | OUTPUT | LVCMOS33 | | 2 | SLOW | OFF | | |
|
||||
| CPU_nDSACK | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | | | |
|
||||
| CPU_nSTERM | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | | | |
|
||||
| FPUCLK | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | OFF | | |
|
||||
| FSB_A<1> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<2> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<3> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<4> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<5> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<6> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<7> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<8> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<9> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<10> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<11> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<12> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<13> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<14> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<15> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<16> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<17> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<18> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<19> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<20> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<21> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<22> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<23> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<24> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<25> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<26> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<27> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<28> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<29> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<30> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<31> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_FC<0> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_FC<1> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_FC<2> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_RnW | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| IOB_nHALT | IOB | INPUT | LVCMOS33 | | | | ILATCH | | |
|
||||
| RAM_CLK01 | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
| nFPUCS | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | | | |
|
||||
| nRESOE | IOB | OUTPUT | LVCMOS33 | | 2 | QUIE | | | |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
Section 7 - RPMs
|
||||
----------------
|
||||
|
||||
Section 8 - Guide Report
|
||||
------------------------
|
||||
Guide not run on this design.
|
||||
|
||||
Section 9 - Area Group and Partition Summary
|
||||
--------------------------------------------
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
Area Group Information
|
||||
----------------------
|
||||
|
||||
No area groups were found in this design.
|
||||
|
||||
----------------------
|
||||
|
||||
Section 10 - Timing Report
|
||||
--------------------------
|
||||
A logic-level (pre-route) timing report can be generated by using Xilinx static
|
||||
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
|
||||
mapped NCD and PCF files. Please note that this timing report will be generated
|
||||
using estimated delay information. For accurate numbers, please generate a
|
||||
timing report with the post Place and Route NCD file.
|
||||
|
||||
For more information about the Timing Analyzer, consult the Xilinx Timing
|
||||
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
|
||||
Command Line Tools User Guide "TRACE" chapter.
|
||||
|
||||
Section 11 - Configuration String Details
|
||||
-----------------------------------------
|
||||
Use the "-detail" map option to print out Configuration Strings
|
||||
|
||||
Section 12 - Control Set Information
|
||||
------------------------------------
|
||||
Use the "-detail" map option to print out Control Set Information.
|
||||
|
||||
Section 13 - Utilization by Hierarchy
|
||||
-------------------------------------
|
||||
Use the "-detail" map option to print out the Utilization by Hierarchy section.
|
||||
3
fpga/WarpLC_map.ncd
Normal file
3
fpga/WarpLC_map.ncd
Normal file
File diff suppressed because one or more lines are too long
3
fpga/WarpLC_map.ngm
Normal file
3
fpga/WarpLC_map.ngm
Normal file
File diff suppressed because one or more lines are too long
641
fpga/WarpLC_map.xrpt
Normal file
641
fpga/WarpLC_map.xrpt
Normal file
@ -0,0 +1,641 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="nt" product="ISE" version="14.7">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Map" timeStamp="Fri Oct 29 10:03:01 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files\Microchip\xc8\v2.31\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\PuTTY\;C:\Program Files\WinMerge;C:\Program Files\dotnet\;C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;C:\Users\zanek\AppData\Local\GitHubDesktop\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\zanek\.dotnet\tools;C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item stringID="variable" value="XILINX_DSP"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item stringID="variable" value="XILINX_EDK"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item stringID="variable" value="XILINX_PLANAHEAD"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="ZanePC"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz"/>
|
||||
<item stringID="speed" value="3500 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="MAP_OPTION_SUMMARY">
|
||||
<item DEFAULT="high" label="-ol" stringID="MAP_EFFORTLEVEL" value="high"/>
|
||||
<item DEFAULT="0" label="-xt" stringID="MAP_EXTRA_COST_TABLE" value="0"/>
|
||||
<item DEFAULT="OFF" label="-ir" stringID="MAP_IGNORERLOCS" value="OFF"/>
|
||||
<item DEFAULT="OFF" stringID="MAP_LUTCOMPRESSIONMODE" value="OFF"/>
|
||||
<item DEFAULT="0" label="-t" stringID="MAP_PLACERCOSTTABLE" value="1"/>
|
||||
<item DEFAULT="4" label="-r" stringID="MAP_REGORDERING" value="4"/>
|
||||
<item DEFAULT="FALSE" stringID="MAP_REPLICATELUTS" value="TRUE"/>
|
||||
<item DEFAULT="None" label="-intstyle" stringID="MAP_INTSTYLE" value="ise"/>
|
||||
<item DEFAULT="off" label="-lc" stringID="MAP_LUT_COMBINING" value="off"/>
|
||||
<item DEFAULT="None" label="-o" stringID="MAP_OUTFILE" value="WarpLC_map.ncd"/>
|
||||
<item DEFAULT="false" label="-w" stringID="MAP_OVERWRITE_OUTPUT" value="true"/>
|
||||
<item DEFAULT="off" label="-pr" stringID="MAP_PACK_INTERNAL" value="off"/>
|
||||
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx9-ftg256-2"/>
|
||||
</section>
|
||||
<task stringID="MAP_PACK_REPORT">
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="56">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="56"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="57">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="29"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="24"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="3"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="1"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="1"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="49"/>
|
||||
<item AVAILABLE="14" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="5"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="1"/>
|
||||
<item AVAILABLE="7" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
|
||||
<item AVAILABLE="93" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
|
||||
<item AVAILABLE="7" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
|
||||
<item AVAILABLE="93" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
|
||||
<section stringID="MAP_DESIGN_INFORMATION">
|
||||
<item stringID="MAP_PART" value="6slx9ftg256-2"/>
|
||||
<item stringID="MAP_DEVICE" value="xc6slx9"/>
|
||||
<item stringID="MAP_ARCHITECTURE" value="spartan6"/>
|
||||
<item stringID="MAP_PACKAGE" value="ftg256"/>
|
||||
<item stringID="MAP_SPEED" value="-2"/>
|
||||
</section>
|
||||
<section stringID="MAP_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="1"/>
|
||||
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="278280"/>
|
||||
<item stringID="MAP_TOTAL_REAL_TIME" value="4 secs "/>
|
||||
<item stringID="MAP_TOTAL_CPU_TIME" value="4 secs "/>
|
||||
</section>
|
||||
<section stringID="MAP_SLICE_REPORTING">
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="56">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="56"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="59">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="29"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="24"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="3"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="1"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="2"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="2"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="1"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="25">
|
||||
<item AVAILABLE="355" dataType="int" stringID="MAP_NUM_SLICEL" value="14"/>
|
||||
<item AVAILABLE="360" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
|
||||
<item AVAILABLE="715" dataType="int" stringID="MAP_NUM_SLICEX" value="11"/>
|
||||
</item>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="76">
|
||||
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="22"/>
|
||||
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="17"/>
|
||||
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="37"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="MAP_IOB_REPORTING">
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="49"/>
|
||||
<item AVAILABLE="14" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="5"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="1"/>
|
||||
<item AVAILABLE="7" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
|
||||
<item AVAILABLE="93" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
|
||||
<item AVAILABLE="7" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
|
||||
<item AVAILABLE="93" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_HARD_IP_REPORTING"/>
|
||||
<section stringID="MAP_RAM_FIFO_DATA">
|
||||
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
|
||||
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_IP_DATA">
|
||||
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
|
||||
<item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
|
||||
<item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
|
||||
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
|
||||
<item AVAILABLE="16" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="1"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_BUFG_DATA">
|
||||
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="3"/>
|
||||
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
|
||||
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
|
||||
</section>
|
||||
<section stringID="MAP_MACRO_RPM_REPORTING">
|
||||
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_RPMS" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_IOB_PROPERTIES">
|
||||
<table stringID="MAP_IOB_TABLE">
|
||||
<column label="IOB
Name" sort="smart" stringID="IOB_NAME"/>
|
||||
<column stringID="Type"/>
|
||||
<column stringID="Direction"/>
|
||||
<column label="IO
Standard" sort="smart" stringID="IO_STANDARD"/>
|
||||
<column label="Diff
Term" stringID="DIFF_TERM"/>
|
||||
<column label="Drive
Strength" stringID="DRIVE_STRENGTH"/>
|
||||
<column label="Slew
Rate" stringID="SLEW_RATE"/>
|
||||
<column label="Reg
(s)" stringID="REGS"/>
|
||||
<column stringID="Resistor"/>
|
||||
<column label="IOB
Delay" stringID="IOB_DELAY"/>
|
||||
<row stringID="row" value="1">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CLKFB_IN"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CLKFB_OUT"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="ODDR"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CLKIN"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPUCLK"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPUCLKIN"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="6">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPU_nAS"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="7">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPU_nBERR"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="2"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="8">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPU_nDSACK"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
</row>
|
||||
<row stringID="row" value="9">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPU_nSTERM"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
</row>
|
||||
<row stringID="row" value="10">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FPUCLK"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="11">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<1>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="12">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<2>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="13">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<3>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="14">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<4>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="15">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<5>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="16">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<6>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="17">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<7>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="18">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<8>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="19">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<9>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="20">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<10>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="21">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<11>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="22">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<12>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="23">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<13>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="24">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<14>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="25">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<15>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="26">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<16>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="27">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<17>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="28">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<18>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="29">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<19>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="30">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<20>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="31">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<21>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="32">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<22>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="33">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<23>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="34">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<24>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="35">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<25>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="36">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<26>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="37">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<27>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="38">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<28>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="39">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<29>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="40">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<30>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="41">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<31>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="42">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_FC<0>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="43">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_FC<1>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="44">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_FC<2>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="45">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_RnW"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="46">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="IOB_nHALT"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="ILATCH"/>
|
||||
</row>
|
||||
<row stringID="row" value="47">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RAM_CLK01"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="ODDR"/>
|
||||
</row>
|
||||
<row stringID="row" value="48">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="nFPUCS"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
</row>
|
||||
<row stringID="row" value="49">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="nRESOE"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="2"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="QUIETIO"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="MAP_RPM_MACROS">
|
||||
<section stringID="MAP_SHAPE_SECTION">
|
||||
<item dataType="int" stringID="MAP_NUM_SHAPE" value="3"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="MAP_GUIDE_REPORT"/>
|
||||
<section stringID="MAP_AREA_GROUPS_PARTITIONS"/>
|
||||
<section stringID="MAP_TIMING_REPORT"/>
|
||||
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
|
||||
<section stringID="MAP_GENERAL_CONFIG_DATA">
|
||||
<item stringID="MAP_BANDWIDTH" value="OPTIMIZED"/>
|
||||
<item stringID="MAP_CLK_FEEDBACK" value="CLKFBOUT"/>
|
||||
<item stringID="MAP_COMPENSATION" value="EXTERNAL"/>
|
||||
<item stringID="MAP_CLKFBOUT_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKIN1_PERIOD" value="30"/>
|
||||
<item stringID="MAP_CLKIN2_PERIOD" value="30"/>
|
||||
<item stringID="MAP_CLKOUT0_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT0_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT1_DIVIDE" value="6"/>
|
||||
<item stringID="MAP_CLKOUT1_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT1_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT2_DIVIDE" value="1"/>
|
||||
<item stringID="MAP_CLKOUT2_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT2_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT3_DIVIDE" value="1"/>
|
||||
<item stringID="MAP_CLKOUT3_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT3_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT4_DIVIDE" value="1"/>
|
||||
<item stringID="MAP_CLKOUT4_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT4_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT5_DIVIDE" value="1"/>
|
||||
<item stringID="MAP_CLKOUT5_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT5_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_DIVCLK_DIVIDE" value="1"/>
|
||||
</section>
|
||||
<section stringID="MAP_CONTROL_SET_INFORMATION">
|
||||
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="4"/>
|
||||
<tree stringID="MAP_CONTROL_SET_HIERARCHY">
|
||||
<property stringID="MAP_CLOCK_SIGNAL"/>
|
||||
<property stringID="MAP_RESET_SIGNAL"/>
|
||||
<property stringID="MAP_SET_SIGNAL"/>
|
||||
<property stringID="MAP_ENABLE_SIGNAL"/>
|
||||
<property label="Slice
Load Count" stringID="MAP_SLICE_LOAD_COUNT"/>
|
||||
<property label="Bel
Load Count" stringID="MAP_BEL_LOAD_COUNT"/>
|
||||
</tree>
|
||||
</section>
|
||||
</task>
|
||||
<section stringID="MAP_RAM_FIFO_DATA">
|
||||
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
|
||||
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_IP_DATA">
|
||||
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
|
||||
<item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
|
||||
<item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
|
||||
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
|
||||
<item AVAILABLE="16" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="1"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_BUFG_DATA">
|
||||
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="3"/>
|
||||
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
|
||||
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
|
||||
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_RPMS" value="0"/>
|
||||
<item stringID="MAP_BANDWIDTH" value="OPTIMIZED"/>
|
||||
<item stringID="MAP_CLK_FEEDBACK" value="CLKFBOUT"/>
|
||||
<item stringID="MAP_COMPENSATION" value="EXTERNAL"/>
|
||||
<item stringID="MAP_CLKFBOUT_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKIN1_PERIOD" value="30"/>
|
||||
<item stringID="MAP_CLKIN2_PERIOD" value="30"/>
|
||||
<item stringID="MAP_CLKOUT0_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT0_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT1_DIVIDE" value="6"/>
|
||||
<item stringID="MAP_CLKOUT1_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT1_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT2_DIVIDE" value="1"/>
|
||||
<item stringID="MAP_CLKOUT2_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT2_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT3_DIVIDE" value="1"/>
|
||||
<item stringID="MAP_CLKOUT3_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT3_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT4_DIVIDE" value="1"/>
|
||||
<item stringID="MAP_CLKOUT4_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT4_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT5_DIVIDE" value="1"/>
|
||||
<item stringID="MAP_CLKOUT5_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT5_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_DIVCLK_DIVIDE" value="1"/>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
125
fpga/WarpLC_ngdbuild.xrpt
Normal file
125
fpga/WarpLC_ngdbuild.xrpt
Normal file
@ -0,0 +1,125 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="nt" product="ISE" version="14.7">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Fri Oct 29 10:02:55 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files\Microchip\xc8\v2.31\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\PuTTY\;C:\Program Files\WinMerge;C:\Program Files\dotnet\;C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;C:\Users\zanek\AppData\Local\GitHubDesktop\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\zanek\.dotnet\tools;C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item stringID="variable" value="XILINX_DSP"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item stringID="variable" value="XILINX_EDK"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item stringID="variable" value="XILINX_PLANAHEAD"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="ZanePC"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz"/>
|
||||
<item stringID="speed" value="3500 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<task stringID="NGDBUILD_OPTION_SUMMARY">
|
||||
<section stringID="NGDBUILD_OPTION_SUMMARY">
|
||||
<item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
|
||||
<item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
|
||||
<item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc6slx9-ftg256-2"/>
|
||||
<item DEFAULT="None" label="-sd" stringID="NGDBUILD_search_path" value="ipcore_dir"/>
|
||||
<item DEFAULT="None" label="-uc" stringID="NGDBUILD_ucf_file" value="PLL.ucf"/>
|
||||
</section>
|
||||
</task>
|
||||
<task stringID="NGDBUILD_REPORT">
|
||||
<section stringID="NGDBUILD_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="254"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="1"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFIO2FB" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="51"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="38"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LD_1" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="29"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="20"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="48"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="9"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ODDR2" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="30"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFIO2FB" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="51"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="38"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LD_1" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="29"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="20"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="48"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="9"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ODDR2" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_PLL_ADV" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="30"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
|
||||
<section stringID="NGDBUILD_CORE_INSTANCES">
|
||||
<scope stringID="NGDBUILD_CORE_INSTANCE" value="CLK">
|
||||
<item stringID="NGDBUILD_CORE_INFO" type="clk_wiz_v3_6" value="CLK"/>
|
||||
<item clkin1_period="30.0" clkin2_period="30.0" clock_mgr_type="MANUAL" component_name="CLK" feedback_source="FDBK_AUTO_OFFCHIP" feedback_type="SINGLE" manual_override="false" num_out_clk="2" primtype_sel="PLL_BASE" stringID="NGDBUILD_CORE_PARAMETERS" use_clk_valid="false" use_dyn_phase_shift="false" use_dyn_reconfig="false" use_freeze="false" use_inclk_stopped="false" use_inclk_switchover="false" use_locked="false" use_max_i_jitter="false" use_min_o_jitter="false" use_phase_alignment="true" use_power_down="false" use_reset="false" use_status="false" value="CLK"/>
|
||||
</scope>
|
||||
</section>
|
||||
</section>
|
||||
</task>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
286
fpga/WarpLC_pad.txt
Normal file
286
fpga/WarpLC_pad.txt
Normal file
@ -0,0 +1,286 @@
|
||||
Release 14.7 - par P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Fri Oct 29 10:03:06 2021
|
||||
|
||||
|
||||
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
|
||||
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
|
||||
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
|
||||
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
|
||||
|
||||
INPUT FILE: WarpLC_map.ncd
|
||||
OUTPUT FILE: WarpLC_pad.txt
|
||||
PART TYPE: xc6slx9
|
||||
SPEED GRADE: -2
|
||||
PACKAGE: ftg256
|
||||
|
||||
Pinout by Pin Number:
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|A1 | | |GND | | | | | | | | | | | |
|
||||
|A2 |CLKFB_OUT |IOB |IO_L52N_M3A9_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|A3 | |IOBS |IO_L83N_VREF_3 |UNUSED | |3 | | | | | | | | |
|
||||
|A4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A5 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A6 | |IOBS |IO_L4N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A7 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A8 | |IOBS |IO_L33N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A9 | |IOBS |IO_L34N_GCLK18_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A10 | |IOBS |IO_L35N_GCLK16_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A11 | |IOBS |IO_L39N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A12 | |IOBS |IO_L62N_VREF_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A13 | |IOBS |IO_L63N_SCP6_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A14 | |IOBS |IO_L65N_SCP2_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A15 | | |TMS | | | | | | | | | | | |
|
||||
|A16 | | |GND | | | | | | | | | | | |
|
||||
|B1 |CPUCLK |IOB |IO_L50N_M3BA2_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|B2 |RAM_CLK01 |IOB |IO_L52P_M3A8_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|B3 | |IOBM |IO_L83P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|B4 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|B5 | |IOBM |IO_L2P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B6 | |IOBM |IO_L4P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B7 | | |GND | | | | | | | | | | | |
|
||||
|B8 | |IOBM |IO_L33P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B9 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|B10 | |IOBM |IO_L35P_GCLK17_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B11 | | |GND | | | | | | | | | | | |
|
||||
|B12 | |IOBM |IO_L62P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B13 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|B14 | |IOBM |IO_L65P_SCP3_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B15 | |IOBM |IO_L29P_A23_M1A13_1 |UNUSED | |1 | | | | | | | | |
|
||||
|B16 | |IOBS |IO_L29N_A22_M1A14_1 |UNUSED | |1 | | | | | | | | |
|
||||
|C1 |CPU_nDSACK |IOB |IO_L50P_M3WE_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |NO |NONE |
|
||||
|C2 |CPU_nSTERM |IOB |IO_L48N_M3BA1_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |NO |NONE |
|
||||
|C3 |FSB_FC<2> |IOB |IO_L48P_M3BA0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|C4 | |IOBM |IO_L1P_HSWAPEN_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C5 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C6 | |IOBS |IO_L7N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C7 | |IOBM |IO_L6P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C8 | |IOBS |IO_L38N_VREF_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C9 | |IOBM |IO_L34P_GCLK19_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C10 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C11 | |IOBM |IO_L39P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C12 | | |TDI | | | | | | | | | | | |
|
||||
|C13 | |IOBM |IO_L63P_SCP7_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C14 | | |TCK | | | | | | | | | | | |
|
||||
|C15 | |IOBM |IO_L33P_A15_M1A10_1 |UNUSED | |1 | | | | | | | | |
|
||||
|C16 | |IOBS |IO_L33N_A14_M1A4_1 |UNUSED | |1 | | | | | | | | |
|
||||
|D1 |FSB_RnW |IOB |IO_L49N_M3A2_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|D2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|D3 |CPU_nAS |IOB |IO_L49P_M3A7_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|D4 | | |GND | | | | | | | | | | | |
|
||||
|D5 | |IOBM |IO_L3P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D6 | |IOBM |IO_L7P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D7 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|D8 | |IOBM |IO_L38P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D9 | |IOBS |IO_L40N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D10 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|D11 | |IOBM |IO_L66P_SCP1_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D12 | |IOBS |IO_L66N_SCP0_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D13 | | |GND | | | | | | | | | | | |
|
||||
|D14 | |IOBM |IO_L31P_A19_M1CKE_1 |UNUSED | |1 | | | | | | | | |
|
||||
|D15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|D16 | |IOBS |IO_L31N_A18_M1A12_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E1 |nFPUCS |IOB |IO_L46N_M3CLKN_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |NO |NONE |
|
||||
|E2 |FSB_A<31> |IOB |IO_L46P_M3CLK_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E3 | |IOBS |IO_L54N_M3A11_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E4 | |IOBM |IO_L54P_M3RESET_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E5 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|E6 | |IOBS |IO_L5N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E7 | |IOBM |IO_L36P_GCLK15_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E8 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E9 | | |GND | | | | | | | | | | | |
|
||||
|E10 | |IOBM |IO_L37P_GCLK13_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E11 | |IOBS |IO_L64N_SCP4_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E12 | |IOBS |IO_L1N_A24_VREF_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E13 | |IOBM |IO_L1P_A25_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E14 | | |TDO | | | | | | | | | | | |
|
||||
|E15 | |IOBM |IO_L34P_A13_M1WE_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E16 | |IOBS |IO_L34N_A12_M1BA2_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F1 |FSB_A<27> |IOB |IO_L41N_GCLK26_M3DQ5_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F2 |FSB_A<25> |IOB |IO_L41P_GCLK27_M3DQ4_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F3 |nRESOE |IOB |IO_L53N_M3A12_3 |OUTPUT |LVCMOS33 |3 |2 |QUIETIO | | | |UNLOCATED |NO |NONE |
|
||||
|F4 | |IOBM |IO_L53P_M3CKE_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F5 | |IOBS |IO_L55N_M3A14_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F6 | |IOBM |IO_L55P_M3A13_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F7 | |IOBM |IO_L5P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|F8 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|F9 | |IOBM |IO_L40P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|F10 | |IOBM |IO_L64P_SCP5_0 |UNUSED | |0 | | | | | | | | |
|
||||
|F11 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|F12 | |IOBM |IO_L30P_A21_M1RESET_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F13 | |IOBM |IO_L32P_A17_M1A8_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F14 | |IOBS |IO_L32N_A16_M1A9_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F15 | |IOBM |IO_L35P_A11_M1A7_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F16 | |IOBS |IO_L35N_A10_M1A2_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G1 |FSB_A<15> |IOB |IO_L40N_M3DQ7_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G2 | | |GND | | | | | | | | | | | |
|
||||
|G3 |FSB_A<16> |IOB |IO_L40P_M3DQ6_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G4 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|G5 |CPUCLKIN |IOB |IO_L51N_M3A4_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G6 |CPU_nBERR |IOB |IO_L51P_M3A10_3 |OUTPUT |LVCMOS33 |3 |2 |SLOW | | | |UNLOCATED |YES |NONE |
|
||||
|G7 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|G8 | | |GND | | | | | | | | | | | |
|
||||
|G9 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|G10 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|G11 | |IOBS |IO_L30N_A20_M1A11_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G12 | |IOBM |IO_L38P_A5_M1CLK_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G13 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|G14 | |IOBM |IO_L36P_A9_M1BA0_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G15 | | |GND | | | | | | | | | | | |
|
||||
|G16 | |IOBS |IO_L36N_A8_M1BA1_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H1 |FSB_A<20> |IOB |IO_L39N_M3LDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H2 |FSB_A<22> |IOB |IO_L39P_M3LDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H3 |FSB_A<28> |IOB |IO_L44N_GCLK20_M3A6_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H4 |CLKFB_IN |IOB |IO_L44P_GCLK21_M3A5_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H5 |FSB_A<19> |IOB |IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H6 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|H7 | | |GND | | | | | | | | | | | |
|
||||
|H8 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|H9 | | |GND | | | | | | | | | | | |
|
||||
|H10 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|H11 | |IOBS |IO_L38N_A4_M1CLKN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H12 | | |GND | | | | | | | | | | | |
|
||||
|H13 | |IOBM |IO_L39P_M1A3_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H14 | |IOBS |IO_L39N_M1ODT_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H15 | |IOBM |IO_L37P_A7_M1A0_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H16 | |IOBS |IO_L37N_A6_M1A1_1 |UNUSED | |1 | | | | | | | | |
|
||||
|J1 |FSB_A<23> |IOB |IO_L38N_M3DQ3_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|J3 |FSB_A<17> |IOB |IO_L38P_M3DQ2_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J4 |CLKIN |IOB |IO_L42N_GCLK24_M3LDM_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J5 | | |GND | | | | | | | | | | | |
|
||||
|J6 |FSB_A<26> |IOB |IO_L43P_GCLK23_M3RASN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J7 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|J8 | | |GND | | | | | | | | | | | |
|
||||
|J9 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|J10 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|J11 | |IOBM |IO_L40P_GCLK11_M1A5_1 |UNUSED | |1 | | | | | | | | |
|
||||
|J12 | |IOBS |IO_L40N_GCLK10_M1A6_1 |UNUSED | |1 | | | | | | | | |
|
||||
|J13 | |IOBM |IO_L41P_GCLK9_IRDY1_M1RASN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|J14 | |IOBM |IO_L43P_GCLK5_M1DQ4_1 |UNUSED | |1 | | | | | | | | |
|
||||
|J15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|J16 | |IOBS |IO_L43N_GCLK4_M1DQ5_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K1 |FSB_A<21> |IOB |IO_L37N_M3DQ1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K2 |FSB_A<24> |IOB |IO_L37P_M3DQ0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K3 |FSB_A<18> |IOB |IO_L42P_GCLK25_TRDY2_M3UDM_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K4 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|K5 |FSB_FC<0> |IOB |IO_L47P_M3A0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K6 |FSB_FC<1> |IOB |IO_L47N_M3A1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K7 | | |GND | | | | | | | | | | | |
|
||||
|K8 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|K9 | | |GND | | | | | | | | | | | |
|
||||
|K10 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|K11 | |IOBS |IO_L42N_GCLK6_TRDY1_M1LDM_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K12 | |IOBM |IO_L42P_GCLK7_M1UDM_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K13 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|K14 | |IOBS |IO_L41N_GCLK8_M1CASN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K15 | |IOBM |IO_L44P_A3_M1DQ6_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K16 | |IOBS |IO_L44N_A2_M1DQ7_1 |UNUSED | |1 | | | | | | | | |
|
||||
|L1 |FSB_A<14> |IOB |IO_L36N_M3DQ9_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L2 | | |GND | | | | | | | | | | | |
|
||||
|L3 |FSB_A<13> |IOB |IO_L36P_M3DQ8_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L4 |FSB_A<29> |IOB |IO_L45P_M3A3_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L5 |FSB_A<30> |IOB |IO_L45N_M3ODT_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L6 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|L7 | |IOBS |IO_L62N_D6_2 |UNUSED | |2 | | | | | | | | |
|
||||
|L8 | |IOBM |IO_L62P_D5_2 |UNUSED | |2 | | | | | | | | |
|
||||
|L9 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|L10 | |IOBM |IO_L16P_2 |UNUSED | |2 | | | | | | | | |
|
||||
|L11 | | |CMPCS_B_2 | | | | | | | | | | | |
|
||||
|L12 | |IOBM |IO_L53P_1 |UNUSED | |1 | | | | | | | | |
|
||||
|L13 | |IOBS |IO_L53N_VREF_1 |UNUSED | |1 | | | | | | | | |
|
||||
|L14 | |IOBM |IO_L47P_FWE_B_M1DQ0_1 |UNUSED | |1 | | | | | | | | |
|
||||
|L15 | | |GND | | | | | | | | | | | |
|
||||
|L16 | |IOBS |IO_L47N_LDC_M1DQ1_1 |UNUSED | |1 | | | | | | | | |
|
||||
|M1 |FSB_A<12> |IOB |IO_L35N_M3DQ11_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M2 |FSB_A<11> |IOB |IO_L35P_M3DQ10_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M3 |FSB_A<2> |IOB |IO_L1N_VREF_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M4 |FSB_A<1> |IOB |IO_L1P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M5 |FSB_A<3> |IOB |IO_L2P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M6 | |IOBM |IO_L64P_D8_2 |UNUSED | |2 | | | | | | | | |
|
||||
|M7 | |IOBS |IO_L31N_GCLK30_D15_2 |UNUSED | |2 | | | | | | | | |
|
||||
|M8 | | |GND | | | | | | | | | | | |
|
||||
|M9 | |IOBM |IO_L29P_GCLK3_2 |UNUSED | |2 | | | | | | | | |
|
||||
|M10 | |IOBS |IO_L16N_VREF_2 |UNUSED | |2 | | | | | | | | |
|
||||
|M11 | |IOBS |IO_L2N_CMPMOSI_2 |UNUSED | |2 | | | | | | | | |
|
||||
|M12 | |IOBM |IO_L2P_CMPCLK_2 |UNUSED | |2 | | | | | | | | |
|
||||
|M13 | |IOBM |IO_L74P_AWAKE_1 |UNUSED | |1 | | | | | | | | |
|
||||
|M14 | |IOBS |IO_L74N_DOUT_BUSY_1 |UNUSED | |1 | | | | | | | | |
|
||||
|M15 | |IOBM |IO_L46P_FCS_B_M1DQ2_1 |UNUSED | |1 | | | | | | | | |
|
||||
|M16 | |IOBS |IO_L46N_FOE_B_M1DQ3_1 |UNUSED | |1 | | | | | | | | |
|
||||
|N1 |FSB_A<10> |IOB |IO_L34N_M3UDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|N3 |FSB_A<9> |IOB |IO_L34P_M3UDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N4 |FSB_A<4> |IOB |IO_L2N_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N5 | |IOBM |IO_L49P_D3_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N6 | |IOBS |IO_L64N_D9_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N7 | | |VCCO_2 | | |2 | | | | |3.30 | | | |
|
||||
|N8 | |IOBS |IO_L29N_GCLK2_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N9 | |IOBM |IO_L14P_D11_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N10 | | |VCCO_2 | | |2 | | | | |3.30 | | | |
|
||||
|N11 | |IOBM |IO_L13P_M1_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N12 | |IOBM |IO_L12P_D1_MISO2_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N13 | | |GND | | | | | | | | | | | |
|
||||
|N14 | |IOBM |IO_L45P_A1_M1LDQS_1 |UNUSED | |1 | | | | | | | | |
|
||||
|N15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|N16 | |IOBS |IO_L45N_A0_M1LDQSN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P1 |FSB_A<8> |IOB |IO_L33N_M3DQ13_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|P2 |FSB_A<7> |IOB |IO_L33P_M3DQ12_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|P3 | | |GND | | | | | | | | | | | |
|
||||
|P4 | |IOBM |IO_L63P_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P5 | |IOBS |IO_L49N_D4_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P6 | |IOBM |IO_L47P_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P7 | |IOBM |IO_L31P_GCLK31_D14_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P8 | |IOBM |IO_L30P_GCLK1_D13_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P9 | |IOBS |IO_L14N_D12_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P10 | |IOBM |IO_L3P_D0_DIN_MISO_MISO1_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P11 | |IOBS |IO_L13N_D10_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P12 | |IOBS |IO_L12N_D2_MISO3_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P13 | | |DONE_2 | | | | | | | | | | | |
|
||||
|P14 | | |SUSPEND | | | | | | | | | | | |
|
||||
|P15 | |IOBM |IO_L48P_HDC_M1DQ8_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P16 | |IOBS |IO_L48N_M1DQ9_1 |UNUSED | |1 | | | | | | | | |
|
||||
|R1 |FSB_A<6> |IOB |IO_L32N_M3DQ15_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|R2 |FSB_A<5> |IOB |IO_L32P_M3DQ14_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|R3 | |IOBM |IO_L65P_INIT_B_2 |UNUSED | |2 | | | | | | | | |
|
||||
|R4 | | |VCCO_2 | | |2 | | | | |3.30 | | | |
|
||||
|R5 | |IOBM |IO_L48P_D7_2 |UNUSED | |2 | | | | | | | | |
|
||||
|R6 | | |GND | | | | | | | | | | | |
|
||||
|R7 |IOB_nHALT |IOB |IO_L32P_GCLK29_2 |INPUT |LVCMOS33 |2 | | | |NONE | |UNLOCATED |YES |NONE |
|
||||
|R8 | | |VCCO_2 | | |2 | | | | |3.30 | | | |
|
||||
|R9 | |IOBM |IO_L23P_2 |UNUSED | |2 | | | | | | | | |
|
||||
|R10 | | |GND | | | | | | | | | | | |
|
||||
|R11 | |IOBM |IO_L1P_CCLK_2 |UNUSED | |2 | | | | | | | | |
|
||||
|R12 | |IOBM |IO_L52P_M1DQ14_1 |UNUSED | |1 | | | | | | | | |
|
||||
|R13 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|R14 | |IOBM |IO_L50P_M1UDQS_1 |UNUSED | |1 | | | | | | | | |
|
||||
|R15 | |IOBM |IO_L49P_M1DQ10_1 |UNUSED | |1 | | | | | | | | |
|
||||
|R16 | |IOBS |IO_L49N_M1DQ11_1 |UNUSED | |1 | | | | | | | | |
|
||||
|T1 | | |GND | | | | | | | | | | | |
|
||||
|T2 | | |PROGRAM_B_2 | | | | | | | | | | | |
|
||||
|T3 | |IOBS |IO_L65N_CSO_B_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T4 | |IOBS |IO_L63N_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T5 | |IOBS |IO_L48N_RDWR_B_VREF_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T6 | |IOBS |IO_L47N_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T7 |FPUCLK |IOB |IO_L32N_GCLK28_2 |OUTPUT |LVCMOS33 |2 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|T8 | |IOBS |IO_L30N_GCLK0_USERCCLK_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T9 | |IOBS |IO_L23N_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T10 | |IOBS |IO_L3N_MOSI_CSI_B_MISO0_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T11 | |IOBS |IO_L1N_M0_CMPMISO_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T12 | |IOBS |IO_L52N_M1DQ15_1 |UNUSED | |1 | | | | | | | | |
|
||||
|T13 | |IOBS |IO_L51N_M1DQ13_1 |UNUSED | |1 | | | | | | | | |
|
||||
|T14 | |IOBM |IO_L51P_M1DQ12_1 |UNUSED | |1 | | | | | | | | |
|
||||
|T15 | |IOBS |IO_L50N_M1UDQSN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|T16 | | |GND | | | | | | | | | | | |
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
* Default value.
|
||||
** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
****** Special VCCO requirements may apply. Please consult the device
|
||||
family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
2220
fpga/WarpLC_par.xrpt
Normal file
2220
fpga/WarpLC_par.xrpt
Normal file
File diff suppressed because it is too large
Load Diff
160
fpga/WarpLC_preroute.twr
Normal file
160
fpga/WarpLC_preroute.twr
Normal file
@ -0,0 +1,160 @@
|
||||
--------------------------------------------------------------------------------
|
||||
Release 14.7 Trace (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
|
||||
3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr
|
||||
WarpLC.pcf -ucf PLL.ucf
|
||||
|
||||
Design file: WarpLC_map.ncd
|
||||
Physical constraint file: WarpLC.pcf
|
||||
Device,package,speed: xc6slx9,ftg256,C,-2 (PRODUCTION 1.23 2013-10-13)
|
||||
Report level: verbose report
|
||||
|
||||
Environment Variable Effect
|
||||
-------------------- ------
|
||||
NONE No environment variables were set
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
|
||||
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
|
||||
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
|
||||
option. All paths that are not constrained will be reported in the
|
||||
unconstrained paths section(s) of the report.
|
||||
INFO:Timing:3284 - This timing report was generated using estimated delay
|
||||
information. For accurate numbers, please refer to the post Place and Route
|
||||
timing report.
|
||||
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
||||
a 50 Ohm transmission line loading model. For the details of this model,
|
||||
and for more information on accounting for different loading conditions,
|
||||
please see the device datasheet.
|
||||
|
||||
|
||||
|
||||
Data Sheet report:
|
||||
-----------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
Setup/Hold to clock CLKIN
|
||||
------------+------------+------------+------------+------------+------------------+--------+
|
||||
|Max Setup to| Process |Max Hold to | Process | | Clock |
|
||||
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
|
||||
------------+------------+------------+------------+------------+------------------+--------+
|
||||
FSB_A<0> | 13.023(R)| SLOW | -7.585(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<1> | 12.884(R)| SLOW | -7.431(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<2> | 12.631(R)| SLOW | -7.394(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<3> | 12.641(R)| SLOW | -7.409(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<4> | 12.880(R)| SLOW | -7.561(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<5> | 12.741(R)| SLOW | -7.407(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<6> | 12.296(R)| SLOW | -7.155(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<7> | 12.306(R)| SLOW | -7.170(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<8> | 12.539(R)| SLOW | -7.316(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<9> | 12.400(R)| SLOW | -7.162(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<10> | 11.961(R)| SLOW | -6.916(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<11> | 12.140(R)| SLOW | -7.100(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<12> | 11.370(R)| SLOW | -6.243(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<13> | 11.798(R)| SLOW | -6.633(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<14> | 11.760(R)| SLOW | -6.788(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<15> | 11.233(R)| SLOW | -6.266(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<16> | 11.974(R)| SLOW | -6.920(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<17> | 11.982(R)| SLOW | -6.936(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<18> | 11.664(R)| SLOW | -6.788(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<19> | 11.544(R)| SLOW | -6.696(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<20> | 11.618(R)| SLOW | -6.683(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<21> | 11.622(R)| SLOW | -6.672(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<22> | 11.438(R)| SLOW | -6.681(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<23> | 11.192(R)| SLOW | -6.440(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<24> | 11.518(R)| SLOW | -6.679(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<25> | 11.768(R)| SLOW | -6.914(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<26> | 11.702(R)| SLOW | -7.041(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<27> | 11.630(R)| SLOW | -6.974(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<28> | 11.573(R)| SLOW | -6.971(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<29> | 11.565(R)| SLOW | -6.929(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<30> | 11.495(R)| SLOW | -7.056(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<31> | 11.352(R)| SLOW | -6.975(R)| FAST |FSBCLK | 0.000|
|
||||
------------+------------+------------+------------+------------+------------------+--------+
|
||||
|
||||
Clock CLKIN to Pad
|
||||
------------+-----------------+------------+-----------------+------------+----------------------------+--------+
|
||||
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
|
||||
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
|
||||
------------+-----------------+------------+-----------------+------------+----------------------------+--------+
|
||||
CLKFB_OUT | -0.063(R)| FAST | -0.086(R)| SLOW |instance_name/clkfb_bufg_out| 0.000|
|
||||
| -0.057(F)| FAST | -0.086(F)| SLOW |instance_name/clkfb_bufg_out| 0.000|
|
||||
CPUCLK | -0.151(R)| FAST | -0.159(R)| SLOW |CPUCLKi | 0.000|
|
||||
CPU_nDSACK | 2.827(R)| FAST | 2.128(R)| SLOW |FSBCLK | 0.000|
|
||||
CPU_nSTERM | 1.831(R)| FAST | 1.400(R)| SLOW |FSBCLK | 0.000|
|
||||
RAM_CLK01 | -0.063(R)| FAST | -0.086(R)| SLOW |FSBCLK | 0.000|
|
||||
| -0.057(F)| FAST | -0.086(F)| SLOW |FSBCLK | 0.000|
|
||||
nFPUCS | 2.114(R)| FAST | 1.715(R)| SLOW |CPUCLKi | 0.000|
|
||||
------------+-----------------+------------+-----------------+------------+----------------------------+--------+
|
||||
|
||||
Clock to Setup on destination clock CLKIN
|
||||
---------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
---------------+---------+---------+---------+---------+
|
||||
CLKIN | 2.278| 3.404| 1.399| |
|
||||
---------------+---------+---------+---------+---------+
|
||||
|
||||
Pad to Pad
|
||||
---------------+---------------+---------+
|
||||
Source Pad |Destination Pad| Delay |
|
||||
---------------+---------------+---------+
|
||||
CPU_nAS |nFPUCS | 9.241|
|
||||
FSB_A<0> |CPU_nDSACK | 11.438|
|
||||
FSB_A<1> |CPU_nDSACK | 11.056|
|
||||
FSB_A<2> |CPU_nDSACK | 10.934|
|
||||
FSB_A<3> |CPU_nDSACK | 11.272|
|
||||
FSB_A<4> |CPU_nDSACK | 10.959|
|
||||
FSB_A<5> |CPU_nDSACK | 10.647|
|
||||
FSB_A<6> |CPU_nDSACK | 11.009|
|
||||
FSB_A<7> |CPU_nDSACK | 10.884|
|
||||
FSB_A<8> |CPU_nDSACK | 10.427|
|
||||
FSB_A<9> |CPU_nDSACK | 10.796|
|
||||
FSB_A<10> |CPU_nDSACK | 10.296|
|
||||
FSB_A<11> |CPU_nDSACK | 9.984|
|
||||
FSB_A<12> |CPU_nDSACK | 10.429|
|
||||
FSB_A<13> |CPU_nDSACK | 10.457|
|
||||
FSB_A<13> |nFPUCS | 10.825|
|
||||
FSB_A<14> |CPU_nDSACK | 10.376|
|
||||
FSB_A<14> |nFPUCS | 11.030|
|
||||
FSB_A<15> |CPU_nDSACK | 10.288|
|
||||
FSB_A<15> |nFPUCS | 11.487|
|
||||
FSB_A<16> |CPU_nDSACK | 10.253|
|
||||
FSB_A<16> |nFPUCS | 12.145|
|
||||
FSB_A<17> |CPU_nDSACK | 9.855|
|
||||
FSB_A<17> |nFPUCS | 11.537|
|
||||
FSB_A<18> |CPU_nDSACK | 10.759|
|
||||
FSB_A<18> |nFPUCS | 10.887|
|
||||
FSB_A<19> |CPU_nDSACK | 10.601|
|
||||
FSB_A<19> |nFPUCS | 10.945|
|
||||
FSB_A<20> |CPU_nDSACK | 9.890|
|
||||
FSB_A<21> |CPU_nDSACK | 10.054|
|
||||
FSB_A<22> |CPU_nDSACK | 10.300|
|
||||
FSB_A<23> |CPU_nDSACK | 10.098|
|
||||
FSB_A<24> |CPU_nDSACK | 10.551|
|
||||
FSB_A<25> |CPU_nDSACK | 10.797|
|
||||
FSB_A<26> |CPU_nDSACK | 10.476|
|
||||
FSB_A<27> |CPU_nDSACK | 10.851|
|
||||
FSB_A<28> |CPU_nDSACK | 11.005|
|
||||
FSB_A<29> |CPU_nDSACK | 10.668|
|
||||
FSB_A<30> |CPU_nDSACK | 10.761|
|
||||
FSB_A<31> |CPU_nDSACK | 10.776|
|
||||
FSB_FC<0> |nFPUCS | 11.389|
|
||||
FSB_FC<1> |nFPUCS | 10.227|
|
||||
FSB_FC<2> |nFPUCS | 11.232|
|
||||
---------------+---------------+---------+
|
||||
|
||||
|
||||
Analysis completed Fri Oct 29 08:28:45 2021
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Trace Settings:
|
||||
-------------------------
|
||||
Trace Settings
|
||||
|
||||
Peak Memory Usage: 167 MB
|
||||
|
||||
|
||||
|
||||
339
fpga/WarpLC_preroute.twx
Normal file
339
fpga/WarpLC_preroute.twx
Normal file
File diff suppressed because one or more lines are too long
464
fpga/WarpLC_summary.html
Normal file
464
fpga/WarpLC_summary.html
Normal file
@ -0,0 +1,464 @@
|
||||
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>WarpLC Project Status (10/29/2021 - 10:03:11)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>WarpLC.xise</TD>
|
||||
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
|
||||
<TD> No Errors </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
|
||||
<TD>WarpLC</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
|
||||
<TD>Placed and Routed</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
|
||||
<TD>xc6slx9-2ftg256</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
|
||||
<TD>
|
||||
No Errors</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/*.xmsgs?&DataKey=Warning'>527 Warnings (2 new)</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
<TD>Balanced</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.unroutes'>All Signals Completely Routed</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
|
||||
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_envsettings.html'>
|
||||
System Settings</A>
|
||||
</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
|
||||
<TD>0 <A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
|
||||
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
|
||||
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
|
||||
<TD ALIGN=RIGHT>56</TD>
|
||||
<TD ALIGN=RIGHT>11,440</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD>
|
||||
<TD ALIGN=RIGHT>56</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
|
||||
<TD ALIGN=RIGHT>59</TD>
|
||||
<TD ALIGN=RIGHT>5,720</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
|
||||
<TD ALIGN=RIGHT>56</TD>
|
||||
<TD ALIGN=RIGHT>5,720</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
|
||||
<TD ALIGN=RIGHT>24</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
|
||||
<TD ALIGN=RIGHT>29</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
|
||||
<TD ALIGN=RIGHT>3</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1,440</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD>
|
||||
<TD ALIGN=RIGHT>3</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
|
||||
<TD ALIGN=RIGHT>25</TD>
|
||||
<TD ALIGN=RIGHT>1,430</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
|
||||
<TD ALIGN=RIGHT>56</TD>
|
||||
<TD ALIGN=RIGHT>2,860</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
|
||||
<TD ALIGN=RIGHT>76</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD>
|
||||
<TD ALIGN=RIGHT>22</TD>
|
||||
<TD ALIGN=RIGHT>76</TD>
|
||||
<TD ALIGN=RIGHT>28%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD>
|
||||
<TD ALIGN=RIGHT>17</TD>
|
||||
<TD ALIGN=RIGHT>76</TD>
|
||||
<TD ALIGN=RIGHT>22%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD>
|
||||
<TD ALIGN=RIGHT>37</TD>
|
||||
<TD ALIGN=RIGHT>76</TD>
|
||||
<TD ALIGN=RIGHT>48%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD>
|
||||
<TD ALIGN=RIGHT>16</TD>
|
||||
<TD ALIGN=RIGHT>11,440</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
|
||||
<TD ALIGN=RIGHT>49</TD>
|
||||
<TD ALIGN=RIGHT>186</TD>
|
||||
<TD ALIGN=RIGHT>26%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Flip Flops</TD>
|
||||
<TD ALIGN=RIGHT>5</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Latches</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>32</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>64</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>32</TD>
|
||||
<TD ALIGN=RIGHT>3%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2s</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2_2CLKs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>32</TD>
|
||||
<TD ALIGN=RIGHT>3%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2FBs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2FB_2CLKs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
|
||||
<TD ALIGN=RIGHT>3</TD>
|
||||
<TD ALIGN=RIGHT>16</TD>
|
||||
<TD ALIGN=RIGHT>18%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD>
|
||||
<TD ALIGN=RIGHT>3</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>200</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ILOGIC2s</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ISERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>200</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>5</TD>
|
||||
<TD ALIGN=RIGHT>200</TD>
|
||||
<TD ALIGN=RIGHT>2%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as OLOGIC2s</TD>
|
||||
<TD ALIGN=RIGHT>5</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as OSERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>128</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>8</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>16</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>50%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
|
||||
<TD ALIGN=RIGHT>2.16</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
|
||||
<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
|
||||
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
|
||||
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.unroutes'>All Signals Completely Routed</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
|
||||
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B> </B></TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:02:50 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>272 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:02:55 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>254 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:03:01 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/map.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (1 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:03:06 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:03:09 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri Oct 29 08:28:45 2021</TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 10/29/2021 - 10:03:11</center>
|
||||
</BODY></HTML>
|
||||
199
fpga/WarpLC_xst.xrpt
Normal file
199
fpga/WarpLC_xst.xrpt
Normal file
@ -0,0 +1,199 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="nt" product="ISE" version="14.7">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Fri Oct 29 10:02:47 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files\Microchip\xc8\v2.31\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\PuTTY\;C:\Program Files\WinMerge;C:\Program Files\dotnet\;C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;C:\Users\zanek\AppData\Local\GitHubDesktop\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\zanek\.dotnet\tools;C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item stringID="variable" value="XILINX_DSP"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item stringID="variable" value="XILINX_EDK"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item stringID="variable" value="XILINX_PLANAHEAD"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="ZanePC"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz"/>
|
||||
<item stringID="speed" value="3500 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="XST_OPTION_SUMMARY">
|
||||
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="WarpLC.prj"/>
|
||||
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="WarpLC"/>
|
||||
<item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
|
||||
<item DEFAULT="" label="-p" stringID="XST_P" value="xc6slx9-2-ftg256"/>
|
||||
<item DEFAULT="" label="-top" stringID="XST_TOP" value="WarpLC"/>
|
||||
<item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
|
||||
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
|
||||
<item DEFAULT="No" label="-power" stringID="XST_POWER" value="NO"/>
|
||||
<item DEFAULT="No" label="-iuc" stringID="XST_IUC" value="NO"/>
|
||||
<item DEFAULT="No" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
|
||||
<item DEFAULT="As_Optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
|
||||
<item DEFAULT="No" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
|
||||
<item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
|
||||
<item DEFAULT="Yes" label="-read_cores" stringID="XST_READCORES" value="YES"/>
|
||||
<item DEFAULT="" label="-sd" stringID="XST_SD" value="{"ipcore_dir" }"/>
|
||||
<item DEFAULT="No" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
|
||||
<item DEFAULT="No" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
|
||||
<item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
|
||||
<item DEFAULT="<>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="<>"/>
|
||||
<item DEFAULT="Maintain" stringID="XST_CASE" value="Maintain"/>
|
||||
<item DEFAULT="100" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="100" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="100" label="-dsp_utilization_ratio" stringID="XST_DSPUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="Auto" stringID="XST_LC" value="Auto"/>
|
||||
<item DEFAULT="Auto" label="-reduce_control_sets" stringID="XST_REDUCECONTROLSETS" value="Auto"/>
|
||||
<item DEFAULT="Yes" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
|
||||
<item DEFAULT="Auto" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
|
||||
<item DEFAULT="No" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
|
||||
<item DEFAULT="LUT" label="-fsm_style" stringID="XST_FSMSTYLE" value="LUT"/>
|
||||
<item DEFAULT="Yes" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="Auto" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
|
||||
<item DEFAULT="Yes" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="Yes" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
|
||||
<item DEFAULT="Auto" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
|
||||
<item DEFAULT="No" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
|
||||
<item DEFAULT="Yes" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
|
||||
<item DEFAULT="No" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
|
||||
<item DEFAULT="2" stringID="XST_SHREGMINSIZE" value="2"/>
|
||||
<item DEFAULT="Auto" label="-use_dsp48" stringID="XST_USEDSP48" value="Auto"/>
|
||||
<item DEFAULT="Yes" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
|
||||
<item DEFAULT="100000" label="-max_fanout" stringID="XST_MAXFANOUT" value="100000"/>
|
||||
<item DEFAULT="16" label="-bufg" stringID="XST_BUFG" value="16"/>
|
||||
<item DEFAULT="Yes" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
|
||||
<item DEFAULT="No" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
|
||||
<item DEFAULT="No" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
|
||||
<item DEFAULT="Auto" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Auto"/>
|
||||
<item DEFAULT="Auto" label="-use_sync_set" stringID="XST_USESYNCSET" value="Auto"/>
|
||||
<item DEFAULT="Auto" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Auto"/>
|
||||
<item DEFAULT="Auto" label="-iob" stringID="XST_IOB" value="Auto"/>
|
||||
<item DEFAULT="Yes" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
|
||||
<item DEFAULT="0" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
|
||||
</section>
|
||||
<section stringID="XST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="XST_NUM_BUFG" value="1"/>
|
||||
<item dataType="int" stringID="XST_NUM_BUFIO2FB" value="1"/>
|
||||
<item dataType="int" stringID="XST_NUM_IBUFG" value="1"/>
|
||||
<item dataType="int" stringID="XST_NUM_ODDR2" value="2"/>
|
||||
</section>
|
||||
<section stringID="XST_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="10">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="8"/>
|
||||
<item dataType="int" stringID="XST_30BIT_REGISTER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="2">
|
||||
<item dataType="int" stringID="XST_30BIT_COMPARATOR_EQUAL" value="1"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="59">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="59"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="2">
|
||||
<item dataType="int" stringID="XST_30BIT_COMPARATOR_EQUAL" value="1"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_FINAL_REGISTER_REPORT">
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="59">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="59"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_REPORT">
|
||||
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_DESIGN_SUMMARY">
|
||||
<section stringID="XST_">
|
||||
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="WarpLC.ngc"/>
|
||||
</section>
|
||||
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="141">
|
||||
<item dataType="int" stringID="XST_GND" value="1"/>
|
||||
<item dataType="int" stringID="XST_INV" value="6"/>
|
||||
<item dataType="int" stringID="XST_LUT1" value="29"/>
|
||||
<item dataType="int" stringID="XST_LUT2" value="3"/>
|
||||
<item dataType="int" stringID="XST_LUT3" value="2"/>
|
||||
<item dataType="int" stringID="XST_LUT4" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT6" value="20"/>
|
||||
<item dataType="int" stringID="XST_MUXCY" value="48"/>
|
||||
<item dataType="int" stringID="XST_VCC" value="1"/>
|
||||
<item dataType="int" stringID="XST_XORCY" value="30"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="62">
|
||||
<item dataType="int" stringID="XST_FD" value="7"/>
|
||||
<item dataType="int" stringID="XST_FD1" value="1"/>
|
||||
<item dataType="int" stringID="XST_FDE" value="51"/>
|
||||
<item dataType="int" stringID="XST_ODDR2" value="2"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="3">
|
||||
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="3"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="49">
|
||||
<item dataType="int" stringID="XST_IBUF" value="38"/>
|
||||
<item dataType="int" stringID="XST_IBUFG" value="2"/>
|
||||
<item dataType="int" stringID="XST_OBUF" value="9"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_OTHERS" value="2"></item>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
|
||||
<item stringID="XST_SELECTED_DEVICE" value="6slx9ftg256-2"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="61"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="61"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="61"/>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="114"/>
|
||||
<item AVAILABLE="114" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="53"/>
|
||||
<item AVAILABLE="114" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="53"/>
|
||||
<item AVAILABLE="114" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="8"/>
|
||||
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="5"/>
|
||||
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="170"/>
|
||||
<item AVAILABLE="186" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="49"/>
|
||||
<item dataType="int" label="IOB Flip Flops/Latches" stringID="XST_IOB_FLIP_FLOPSLATCHES" value="1"/>
|
||||
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="3"/>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
<section stringID="XST_ERRORS_STATISTICS">
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="272"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="2"/>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
2
fpga/_ngo/netlist.lst
Normal file
2
fpga/_ngo/netlist.lst
Normal file
@ -0,0 +1,2 @@
|
||||
C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.ngc 1635516170
|
||||
OK
|
||||
42
fpga/_xmsgs/map.xmsgs
Normal file
42
fpga/_xmsgs/map.xmsgs
Normal file
@ -0,0 +1,42 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">FSB_A<0></arg> has no load.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">120</arg> more times for the following (max. 5 shown):
|
||||
<arg fmt="%s" index="3">FSB_SIZ<1>,
|
||||
FSB_SIZ<0>,
|
||||
IOB_nDSACK<1>,
|
||||
IOB_nDSACK<0>,
|
||||
CPU_nCIOUT</arg>
|
||||
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="MapLib" num="159" delta="new" >Net Timing constraints on signal <arg fmt="%s" index="1">CLKIN</arg> are pushed forward through input buffer.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="MapLib" num="53" delta="new" >The offset specification "<arg fmt="%s" index="1">OFFSET=IN 10000 pS VALID 11000 pS BEFORE FSBCLK</arg>" has been discarded because the referenced clock pad net (<arg fmt="%s" index="2">FSBCLK</arg>) was optimized away.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
774
fpga/_xmsgs/ngdbuild.xmsgs
Normal file
774
fpga/_xmsgs/ngdbuild.xmsgs
Normal file
@ -0,0 +1,774 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<9>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<9></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<9>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<9></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<10>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<10></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<10>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<10></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<11>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<11></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<11>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<11></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<12>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<12></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<12>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<12></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<13>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<13></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<13>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<13></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<14>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<14></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<14>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<14></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<15>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<15></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<15>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<15></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<16>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<16></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<16>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<16></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<17>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<17></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<17>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<17></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<18>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<18></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<18>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<18></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<19>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<19></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<19>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<19></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<20>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<20></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<20>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<20></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<21>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<21></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<21>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<21></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<22>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<22></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<22>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<22></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<23>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<23></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<23>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<23></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<24>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<24></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<24>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<24></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<25>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<25></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<25>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<25></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<26>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<26></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<26>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<26></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<27>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<27></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<27>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<27></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<28>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<28></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<28>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<28></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<29>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<29></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<29>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<29></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<30>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<30></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<30>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<30></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<31>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<31></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<31>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<31></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_nBERR" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_nBERR</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOBCLK" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOBCLK</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "nRES" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/nRES</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nCBREQ" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nCBREQ</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nDS" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nDS</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nECS" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nECS</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nCIOUT" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nCIOUT</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_nDSACK<0>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_nDSACK<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_nDSACK<1>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_nDSACK<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_SIZ<0>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_SIZ<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_SIZ<1>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_SIZ<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<0>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_CLK23" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_CLK23</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_CKE" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_CKE</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_nWE" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_nWE</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_nCAS" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_nCAS</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_nRAS" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_nRAS</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_nCS" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_nCS</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nCIIN" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nCIIN</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nCBACK" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nCBACK</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_DDIR" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_DDIR</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nDOE" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nDOE</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nDSACKOE" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nDSACKOE</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_nRMC" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_nRMC</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<0>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<1>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<2>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<2></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<3>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<3></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<4>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<4></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<5>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<5></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<6>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<6></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<7>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<7></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<8>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<8></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<9>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<9></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<10>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<10></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<11>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<11></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<12>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<12></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<13>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<13></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<14>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<14></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<15>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<15></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<16>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<16></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<17>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<17></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<18>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<18></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<19>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<19></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<20>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<20></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<21>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<21></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<22>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<22></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<23>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<23></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<24>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<24></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<25>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<25></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<26>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<26></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<27>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<27></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<28>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<28></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<29>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<29></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<30>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<30></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<31>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<31></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_DQM<0>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_DQM<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_DQM<1>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_DQM<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_DQM<2>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_DQM<2></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_DQM<3>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_DQM<3></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<0>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<1>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<2>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<2></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<3>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<3></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<4>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<4></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<5>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<5></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<6>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<6></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<7>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<7></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<8>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<8></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<9>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<9></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<10>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<10></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<11>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<11></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<12>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<12></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_BA<0>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_BA<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_BA<1>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_BA<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<0>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<0>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<1>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<1>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<2>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<2></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<2>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<2></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<3>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<3></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<3>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<3></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<4>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<4></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<4>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<4></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<5>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<5></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<5>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<5></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<6>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<6></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<6>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<6></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<7>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<7></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<7>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<7></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<8>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<8></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<8>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<8></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="130" delta="old" >Constraint <arg fmt="%s" index="1"><NET FSBCLK FEEDBACK = 160ps NET CLKFB_IN;> [PLL.ucf(2)]</arg>: <arg fmt="%s" index="2">NET "FSBCLK"</arg> is not connected to an input or output pad.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="85" delta="old" >Constraint <arg fmt="%s" index="1"><NET FSBCLK FEEDBACK = 160ps NET CLKFB_IN;> [PLL.ucf(2)]</arg>: This constraint will be ignored because <arg fmt="%s" index="2">NET "FSBCLK"</arg> could not be found.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="130" delta="old" >Constraint <arg fmt="%s" index="1"><NET CPUCLKi FEEDBACK = 160ps NET CLKFB_IN;> [PLL.ucf(3)]</arg>: <arg fmt="%s" index="2">NET "CPUCLKi"</arg> is not connected to an input or output pad.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="85" delta="old" >Constraint <arg fmt="%s" index="1"><NET CPUCLKi FEEDBACK = 160ps NET CLKFB_IN;> [PLL.ucf(3)]</arg>: This constraint will be ignored because <arg fmt="%s" index="2">NET "CPUCLKi"</arg> could not be found.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="168" delta="new" >Constraint <arg fmt="%s" index="1"><NET CPU_nAS OFFSET = IN 10ns VALID 11ns BEFORE FSBCLK;> [PLL.ucf(6)]</arg>: This constraint will be ignored because <arg fmt="%s" index="2">NET "FSBCLK"</arg> could not be found or was not connected to a PAD.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ConstraintSystem" num="0" >The Period constraint <NET CLKIN PERIOD = 20ns HIGH;> [PLL.ucf(5)], is specified using the Net Period method which is not recommended. Please use the Timespec PERIOD method.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_A<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<31></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<30></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<29></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<28></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<27></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<26></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<25></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<24></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<23></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<22></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<21></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<20></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<19></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<18></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<17></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<16></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<15></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<14></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<13></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<12></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<11></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<10></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<9></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<8></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<7></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<6></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<5></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<4></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<3></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<2></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_BA<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_BA<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<12></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<11></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<10></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<9></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<8></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<7></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<6></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<5></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<4></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<3></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<2></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_DQM<3></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_DQM<2></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_DQM<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_DQM<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_A<3></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_A<2></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_A<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_A<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_SIZ<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_SIZ<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<31></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<30></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<29></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<28></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<27></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<26></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<25></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<24></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<23></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<22></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<21></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<20></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<19></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<18></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<17></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<16></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<15></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<14></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<13></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<12></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<11></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<10></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<9></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<8></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<7></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<6></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<5></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<4></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<3></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<2></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_nRMC</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_nAOE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_nDSACKOE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_nDOE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_DDIR</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_nCBACK</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_nCIIN</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_nHALT</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_nCS</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_nRAS</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_nCAS</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_nWE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_CKE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_CLK23</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_nAOE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_ADoutLE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_nAS</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_nDS</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_nDOE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_DDIR</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
9
fpga/_xmsgs/par.xmsgs
Normal file
9
fpga/_xmsgs/par.xmsgs
Normal file
@ -0,0 +1,9 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
</messages>
|
||||
|
||||
12
fpga/_xmsgs/pn_parser.xmsgs
Normal file
12
fpga/_xmsgs/pn_parser.xmsgs
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated -->
|
||||
<!-- by the Xilinx ISE software. Any direct editing or -->
|
||||
<!-- changes made to this file may result in unpredictable -->
|
||||
<!-- behavior or data corruption. It is strongly advised that -->
|
||||
<!-- users do not edit the contents of this file. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<messages>
|
||||
</messages>
|
||||
|
||||
15
fpga/_xmsgs/trce.xmsgs
Normal file
15
fpga/_xmsgs/trce.xmsgs
Normal file
@ -0,0 +1,15 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
831
fpga/_xmsgs/xst.xmsgs
Normal file
831
fpga/_xmsgs/xst.xmsgs
Normal file
@ -0,0 +1,831 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 133: Assignment to <arg fmt="%s" index="1">clkout2_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 134: Assignment to <arg fmt="%s" index="1">clkout3_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 135: Assignment to <arg fmt="%s" index="1">clkout4_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 136: Assignment to <arg fmt="%s" index="1">clkout5_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 137: Assignment to <arg fmt="%s" index="1">locked_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 352: Result of <arg fmt="%d" index="1">31</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">30</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">FSB_A<0:0></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">FSB_SIZ</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">IOB_nDSACK</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CPU_nCIOUT</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CPU_nECS</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CPU_nDS</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CPU_nCBREQ</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">nRES</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">IOBCLK</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">IOB_nBERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">LHALT</arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="1901" delta="old" >Instance <arg fmt="%s" index="1">pll_base_inst</arg> in unit <arg fmt="%s" index="2">pll_base_inst</arg> of type <arg fmt="%s" index="3">PLL_BASE</arg> has been replaced by <arg fmt="%s" index="4">PLL_ADV</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Flip flop associated with net</arg> <arg fmt="%s" index="2">RAM_CLK01_OBUF</arg> not found, property <arg fmt="%s" index="3">IOB</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_FC<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_FC<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_FC<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<31></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<30></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<29></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<28></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<27></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<26></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<25></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<24></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<23></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<22></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<21></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<20></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<19></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<18></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<17></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<16></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<15></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<14></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<13></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<12></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<11></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<10></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<9></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<8></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<7></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<6></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<5></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<4></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_RnW</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<31></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<31></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<30></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<30></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<29></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<29></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<28></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<28></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<27></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<27></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<26></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<26></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<25></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<25></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<24></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<24></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<23></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<23></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<22></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<22></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<21></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<21></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<20></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<20></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<19></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<19></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<18></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<18></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<17></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<17></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<16></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<16></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<15></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<15></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<14></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<14></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<13></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<13></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<12></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<12></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<11></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<11></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<10></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<10></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<9></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<9></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<8></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<8></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<7></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<7></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<6></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<6></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<5></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<5></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<4></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<4></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<3></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<2></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_BA<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_BA<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_BA<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_BA<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<12></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<12></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<11></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<11></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<10></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<10></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<9></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<9></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<8></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<8></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<7></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<7></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<6></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<6></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<5></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<5></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<4></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<4></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<3></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<2></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<3></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<2></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<3></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<2></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_SIZ<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_SIZ<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_SIZ<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_SIZ<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<31></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<31></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<30></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<30></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<29></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<29></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<28></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<28></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<27></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<27></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<26></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<26></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<25></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<25></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<24></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<24></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<23></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<23></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<22></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<22></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<21></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<21></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<20></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<20></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<19></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<19></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<18></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<18></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<17></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<17></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<16></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<16></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<15></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<15></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<14></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<14></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<13></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<13></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<12></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<12></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<11></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<11></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<10></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<10></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<9></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<9></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<8></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<8></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<7></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<7></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<6></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<6></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<5></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<5></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<4></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<4></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<3></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<2></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_nRMC</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_nRMC</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nAOE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nAOE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nDSACKOE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nDSACKOE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nDOE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nDOE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_DDIR</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_DDIR</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nCBACK</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nCBACK</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nCIIN</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nCIIN</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nHALT</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nHALT</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nCS</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nCS</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nRAS</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nRAS</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nCAS</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nCAS</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nWE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nWE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_CKE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_CKE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_CLK23</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_CLK23</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nAOE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nAOE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_ADoutLE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_ADoutLE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nAS</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nAS</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nDS</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nDS</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nDOE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nDOE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_DDIR</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_DDIR</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
25
fpga/ipcore_dir/CLK.asy
Normal file
25
fpga/ipcore_dir/CLK.asy
Normal file
@ -0,0 +1,25 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 CLK
|
||||
RECTANGLE Normal 32 32 576 1088
|
||||
LINE Normal 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName clk_in1
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 304 32 304
|
||||
PIN 0 304 LEFT 36
|
||||
PINATTR PinName clkfb_in
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 608 80 576 80
|
||||
PIN 608 80 RIGHT 36
|
||||
PINATTR PinName clk_out1
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 176 576 176
|
||||
PIN 608 176 RIGHT 36
|
||||
PINATTR PinName clk_out2
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 752 576 752
|
||||
PIN 608 752 RIGHT 36
|
||||
PINATTR PinName clkfb_out
|
||||
PINATTR Polarity OUT
|
||||
|
||||
52
fpga/ipcore_dir/CLK.gise
Normal file
52
fpga/ipcore_dir/CLK.gise
Normal file
@ -0,0 +1,52 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="CLK.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="CLK.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="CLK.veo" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1635507384" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635507384">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1194492726557041007" xil_pn:start_ts="1635516166">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6061207241259343081" xil_pn:start_ts="1635516166">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635516166">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1097761553319033393" xil_pn:start_ts="1635516166">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
64
fpga/ipcore_dir/CLK.ncf
Normal file
64
fpga/ipcore_dir/CLK.ncf
Normal file
@ -0,0 +1,64 @@
|
||||
# file: CLK.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 303.03ps;
|
||||
|
||||
|
||||
# Constraints for external feedback.
|
||||
# Change delay numbers as per requirement
|
||||
#-----------------------------------------------------------------
|
||||
NET "CLKFB_IN" FEEDBACK = 0.1 ns NET "CLKFB_OUT";
|
||||
|
||||
# FALSE PATH constraints
|
||||
|
||||
|
||||
24
fpga/ipcore_dir/CLK.sym
Normal file
24
fpga/ipcore_dir/CLK.sym
Normal file
@ -0,0 +1,24 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<symbol version="7" name="CLK">
|
||||
<symboltype>BLOCK</symboltype>
|
||||
<timestamp>2021-10-29T12:25:33</timestamp>
|
||||
<pin polarity="Input" x="0" y="80" name="clk_in1" />
|
||||
<pin polarity="Input" x="0" y="304" name="clkfb_in" />
|
||||
<pin polarity="Output" x="608" y="80" name="clk_out1" />
|
||||
<pin polarity="Output" x="608" y="176" name="clk_out2" />
|
||||
<pin polarity="Output" x="608" y="752" name="clkfb_out" />
|
||||
<graph>
|
||||
<text style="fontsize:40;fontname:Arial" x="32" y="32">CLK</text>
|
||||
<rect width="544" x="32" y="32" height="1056" />
|
||||
<line x2="32" y1="80" y2="80" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin clk_in1" />
|
||||
<line x2="32" y1="304" y2="304" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="304" type="pin clkfb_in" />
|
||||
<line x2="576" y1="80" y2="80" x1="608" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="80" type="pin clk_out1" />
|
||||
<line x2="576" y1="176" y2="176" x1="608" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="176" type="pin clk_out2" />
|
||||
<line x2="576" y1="752" y2="752" x1="608" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="752" type="pin clkfb_out" />
|
||||
</graph>
|
||||
</symbol>
|
||||
63
fpga/ipcore_dir/CLK.ucf
Normal file
63
fpga/ipcore_dir/CLK.ucf
Normal file
@ -0,0 +1,63 @@
|
||||
# file: CLK.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 303.03ps;
|
||||
|
||||
|
||||
# Constraints for external feedback.
|
||||
# Change delay numbers as per requirement
|
||||
#-----------------------------------------------------------------
|
||||
NET "CLKFB_IN" FEEDBACK = 0.1 ns NET "CLKFB_OUT";
|
||||
|
||||
# FALSE PATH constraints
|
||||
|
||||
179
fpga/ipcore_dir/CLK.v
Normal file
179
fpga/ipcore_dir/CLK.v
Normal file
@ -0,0 +1,179 @@
|
||||
// file: CLK.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____66.667______0.000______50.0______306.616____267.927
|
||||
// CLK_OUT2____66.667______0.000______50.0______306.616____267.927
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________33.333___________0.010101
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "CLK,clk_wiz_v3_6,{component_name=CLK,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO_OFFCHIP,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=30.0,clkin2_period=30.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
|
||||
module CLK
|
||||
(// Clock in ports
|
||||
input CLKIN,
|
||||
input CLKFB_IN,
|
||||
// Clock out ports
|
||||
output FSBCLK,
|
||||
output CPUCLK,
|
||||
output CLKFB_OUT
|
||||
);
|
||||
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
IBUFG clkin1_buf
|
||||
(.O (clkin1),
|
||||
.I (CLKIN));
|
||||
|
||||
wire clkfb_ibuf2bufio2fb;
|
||||
wire clkfb_in_buf_out;
|
||||
|
||||
// feedback clock input buffer
|
||||
IBUFG clkfb_ibufg
|
||||
(.O (clkfb_ibuf2bufio2fb),
|
||||
.I (CLKFB_IN));
|
||||
|
||||
// bufio2fb instantiation
|
||||
BUFIO2FB #(.DIVIDE_BYPASS("TRUE")) clkfb_bufio2fb
|
||||
(.O(clkfb_in_buf_out),
|
||||
.I(clkfb_ibuf2bufio2fb));
|
||||
|
||||
// Clocking primitive
|
||||
//------------------------------------
|
||||
// Instantiation of the PLL primitive
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire locked_unused;
|
||||
wire clkfbout;
|
||||
wire clkfbout_buf;
|
||||
wire clkout2_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
|
||||
PLL_BASE
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLK_FEEDBACK ("CLKFBOUT"),
|
||||
.COMPENSATION ("EXTERNAL"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT (12),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKOUT0_DIVIDE (6),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_DIVIDE (6),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKIN_PERIOD (30.0),
|
||||
.REF_JITTER (0.010))
|
||||
pll_base_inst
|
||||
// Output clocks
|
||||
(.CLKFBOUT (clkfbout),
|
||||
.CLKOUT0 (clkout0),
|
||||
.CLKOUT1 (clkout1),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.LOCKED (locked_unused),
|
||||
.RST (1'b0),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfb_in_buf_out),
|
||||
.CLKIN (clkin1));
|
||||
|
||||
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
wire clkfb_bufg_out;
|
||||
wire clkfb_bufg_out_n;
|
||||
wire clkfb_oddr_out;
|
||||
// Instantiate bufg on fbout
|
||||
BUFG clkfbout_bufg
|
||||
(.O (clkfb_bufg_out),
|
||||
.I (clkfbout));
|
||||
// Locally invert clkfb_bufg_out for use in ODDR2
|
||||
assign clkfb_bufg_out_n = ~clkfb_bufg_out;
|
||||
|
||||
// Forward the feedback clock off-chip
|
||||
ODDR2 clkfbout_oddr
|
||||
(.Q (clkfb_oddr_out),
|
||||
.C0 (clkfb_bufg_out),
|
||||
.C1 (clkfb_bufg_out_n),
|
||||
.CE (1'b1),
|
||||
.D0 (1'b1),
|
||||
.D1 (1'b0),
|
||||
.R (1'b0),
|
||||
.S (1'b0));
|
||||
|
||||
assign CLKFB_OUT = clkfb_oddr_out;
|
||||
BUFG clkout1_buf
|
||||
(.O (FSBCLK),
|
||||
.I (clkout0));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (CPUCLK),
|
||||
.I (clkout1));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
79
fpga/ipcore_dir/CLK.veo
Normal file
79
fpga/ipcore_dir/CLK.veo
Normal file
@ -0,0 +1,79 @@
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____66.667______0.000______50.0______306.616____267.927
|
||||
// CLK_OUT2____66.667______0.000______50.0______306.616____267.927
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________33.333___________0.010101
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
CLK instance_name
|
||||
(// Clock in ports
|
||||
.CLKIN(CLKIN), // IN
|
||||
.CLKFB_IN(CLKFB_IN), // IN
|
||||
// Clock out ports
|
||||
.FSBCLK(FSBCLK), // OUT
|
||||
.CPUCLK(CPUCLK), // OUT
|
||||
.CLKFB_OUT(CLKFB_OUT)); // OUT
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
269
fpga/ipcore_dir/CLK.xco
Normal file
269
fpga/ipcore_dir/CLK.xco
Normal file
@ -0,0 +1,269 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.7
|
||||
# Date: Fri Oct 29 12:25:16 2021
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:clk_wiz:3.6
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx9
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ftg256
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET calc_done=DONE
|
||||
CSET clk_in_sel_port=CLK_IN_SEL
|
||||
CSET clk_out1_port=FSBCLK
|
||||
CSET clk_out1_use_fine_ps_gui=false
|
||||
CSET clk_out2_port=CPUCLK
|
||||
CSET clk_out2_use_fine_ps_gui=false
|
||||
CSET clk_out3_port=CPUCLK
|
||||
CSET clk_out3_use_fine_ps_gui=false
|
||||
CSET clk_out4_port=FPUCLK
|
||||
CSET clk_out4_use_fine_ps_gui=false
|
||||
CSET clk_out5_port=CLK_OUT5
|
||||
CSET clk_out5_use_fine_ps_gui=false
|
||||
CSET clk_out6_port=CLK_OUT6
|
||||
CSET clk_out6_use_fine_ps_gui=false
|
||||
CSET clk_out7_port=CLK_OUT7
|
||||
CSET clk_out7_use_fine_ps_gui=false
|
||||
CSET clk_valid_port=CLK_VALID
|
||||
CSET clkfb_in_n_port=CLKFB_IN_N
|
||||
CSET clkfb_in_p_port=CLKFB_IN_P
|
||||
CSET clkfb_in_port=CLKFB_IN
|
||||
CSET clkfb_in_signaling=SINGLE
|
||||
CSET clkfb_out_n_port=CLKFB_OUT_N
|
||||
CSET clkfb_out_p_port=CLKFB_OUT_P
|
||||
CSET clkfb_out_port=CLKFB_OUT
|
||||
CSET clkfb_stopped_port=CLKFB_STOPPED
|
||||
CSET clkin1_jitter_ps=303.03
|
||||
CSET clkin1_ui_jitter=303.030
|
||||
CSET clkin2_jitter_ps=33.000033
|
||||
CSET clkin2_ui_jitter=100.000
|
||||
CSET clkout1_drives=BUFG
|
||||
CSET clkout1_requested_duty_cycle=50.0
|
||||
CSET clkout1_requested_out_freq=66.667
|
||||
CSET clkout1_requested_phase=0.000
|
||||
CSET clkout2_drives=BUFG
|
||||
CSET clkout2_requested_duty_cycle=50.0
|
||||
CSET clkout2_requested_out_freq=66.667
|
||||
CSET clkout2_requested_phase=0
|
||||
CSET clkout2_used=true
|
||||
CSET clkout3_drives=BUFG
|
||||
CSET clkout3_requested_duty_cycle=50.0
|
||||
CSET clkout3_requested_out_freq=33.333
|
||||
CSET clkout3_requested_phase=0
|
||||
CSET clkout3_used=false
|
||||
CSET clkout4_drives=BUFG
|
||||
CSET clkout4_requested_duty_cycle=50.0
|
||||
CSET clkout4_requested_out_freq=33.333
|
||||
CSET clkout4_requested_phase=0
|
||||
CSET clkout4_used=false
|
||||
CSET clkout5_drives=BUFG
|
||||
CSET clkout5_requested_duty_cycle=50.0
|
||||
CSET clkout5_requested_out_freq=40
|
||||
CSET clkout5_requested_phase=0.000
|
||||
CSET clkout5_used=false
|
||||
CSET clkout6_drives=BUFG
|
||||
CSET clkout6_requested_duty_cycle=50.0
|
||||
CSET clkout6_requested_out_freq=33.000
|
||||
CSET clkout6_requested_phase=0.000
|
||||
CSET clkout6_used=false
|
||||
CSET clkout7_drives=BUFG
|
||||
CSET clkout7_requested_duty_cycle=50.0
|
||||
CSET clkout7_requested_out_freq=33.000
|
||||
CSET clkout7_requested_phase=0.000
|
||||
CSET clkout7_used=false
|
||||
CSET clock_mgr_type=MANUAL
|
||||
CSET component_name=CLK
|
||||
CSET daddr_port=DADDR
|
||||
CSET dclk_port=DCLK
|
||||
CSET dcm_clk_feedback=NONE
|
||||
CSET dcm_clk_out1_port=CLKFX
|
||||
CSET dcm_clk_out2_port=CLKFX
|
||||
CSET dcm_clk_out3_port=CLKFX
|
||||
CSET dcm_clk_out4_port=CLKFX
|
||||
CSET dcm_clk_out5_port=CLKFX
|
||||
CSET dcm_clk_out6_port=CLK0
|
||||
CSET dcm_clkdv_divide=2.0
|
||||
CSET dcm_clkfx_divide=2
|
||||
CSET dcm_clkfx_multiply=2
|
||||
CSET dcm_clkgen_clk_out1_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out2_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out3_port=CLKFX180
|
||||
CSET dcm_clkgen_clkfx_divide=2
|
||||
CSET dcm_clkgen_clkfx_md_max=0.000
|
||||
CSET dcm_clkgen_clkfx_multiply=2
|
||||
CSET dcm_clkgen_clkfxdv_divide=2
|
||||
CSET dcm_clkgen_clkin_period=30.303
|
||||
CSET dcm_clkgen_notes=None
|
||||
CSET dcm_clkgen_spread_spectrum=NONE
|
||||
CSET dcm_clkgen_startup_wait=false
|
||||
CSET dcm_clkin_divide_by_2=false
|
||||
CSET dcm_clkin_period=30.303
|
||||
CSET dcm_clkout_phase_shift=NONE
|
||||
CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
|
||||
CSET dcm_notes=None
|
||||
CSET dcm_phase_shift=0
|
||||
CSET dcm_pll_cascade=NONE
|
||||
CSET dcm_startup_wait=false
|
||||
CSET den_port=DEN
|
||||
CSET din_port=DIN
|
||||
CSET dout_port=DOUT
|
||||
CSET drdy_port=DRDY
|
||||
CSET dwe_port=DWE
|
||||
CSET feedback_source=FDBK_AUTO_OFFCHIP
|
||||
CSET in_freq_units=Units_MHz
|
||||
CSET in_jitter_units=Units_UI
|
||||
CSET input_clk_stopped_port=INPUT_CLK_STOPPED
|
||||
CSET jitter_options=PS
|
||||
CSET jitter_sel=No_Jitter
|
||||
CSET locked_port=LOCKED
|
||||
CSET mmcm_bandwidth=OPTIMIZED
|
||||
CSET mmcm_clkfbout_mult_f=4.000
|
||||
CSET mmcm_clkfbout_phase=0.000
|
||||
CSET mmcm_clkfbout_use_fine_ps=false
|
||||
CSET mmcm_clkin1_period=10.000
|
||||
CSET mmcm_clkin2_period=10.000
|
||||
CSET mmcm_clkout0_divide_f=4.000
|
||||
CSET mmcm_clkout0_duty_cycle=0.500
|
||||
CSET mmcm_clkout0_phase=0.000
|
||||
CSET mmcm_clkout0_use_fine_ps=false
|
||||
CSET mmcm_clkout1_divide=1
|
||||
CSET mmcm_clkout1_duty_cycle=0.500
|
||||
CSET mmcm_clkout1_phase=0.000
|
||||
CSET mmcm_clkout1_use_fine_ps=false
|
||||
CSET mmcm_clkout2_divide=1
|
||||
CSET mmcm_clkout2_duty_cycle=0.500
|
||||
CSET mmcm_clkout2_phase=0.000
|
||||
CSET mmcm_clkout2_use_fine_ps=false
|
||||
CSET mmcm_clkout3_divide=1
|
||||
CSET mmcm_clkout3_duty_cycle=0.500
|
||||
CSET mmcm_clkout3_phase=0.000
|
||||
CSET mmcm_clkout3_use_fine_ps=false
|
||||
CSET mmcm_clkout4_cascade=false
|
||||
CSET mmcm_clkout4_divide=1
|
||||
CSET mmcm_clkout4_duty_cycle=0.500
|
||||
CSET mmcm_clkout4_phase=0.000
|
||||
CSET mmcm_clkout4_use_fine_ps=false
|
||||
CSET mmcm_clkout5_divide=1
|
||||
CSET mmcm_clkout5_duty_cycle=0.500
|
||||
CSET mmcm_clkout5_phase=0.000
|
||||
CSET mmcm_clkout5_use_fine_ps=false
|
||||
CSET mmcm_clkout6_divide=1
|
||||
CSET mmcm_clkout6_duty_cycle=0.500
|
||||
CSET mmcm_clkout6_phase=0.000
|
||||
CSET mmcm_clkout6_use_fine_ps=false
|
||||
CSET mmcm_clock_hold=false
|
||||
CSET mmcm_compensation=ZHOLD
|
||||
CSET mmcm_divclk_divide=1
|
||||
CSET mmcm_notes=None
|
||||
CSET mmcm_ref_jitter1=0.010
|
||||
CSET mmcm_ref_jitter2=0.010
|
||||
CSET mmcm_startup_wait=false
|
||||
CSET num_out_clks=2
|
||||
CSET override_dcm=false
|
||||
CSET override_dcm_clkgen=false
|
||||
CSET override_mmcm=false
|
||||
CSET override_pll=false
|
||||
CSET platform=nt
|
||||
CSET pll_bandwidth=OPTIMIZED
|
||||
CSET pll_clk_feedback=CLKFBOUT
|
||||
CSET pll_clkfbout_mult=12
|
||||
CSET pll_clkfbout_phase=0.000
|
||||
CSET pll_clkin_period=30.0
|
||||
CSET pll_clkout0_divide=6
|
||||
CSET pll_clkout0_duty_cycle=0.500
|
||||
CSET pll_clkout0_phase=0.000
|
||||
CSET pll_clkout1_divide=6
|
||||
CSET pll_clkout1_duty_cycle=0.500
|
||||
CSET pll_clkout1_phase=0.000
|
||||
CSET pll_clkout2_divide=12
|
||||
CSET pll_clkout2_duty_cycle=0.500
|
||||
CSET pll_clkout2_phase=0.000
|
||||
CSET pll_clkout3_divide=12
|
||||
CSET pll_clkout3_duty_cycle=0.500
|
||||
CSET pll_clkout3_phase=0.000
|
||||
CSET pll_clkout4_divide=10
|
||||
CSET pll_clkout4_duty_cycle=0.500
|
||||
CSET pll_clkout4_phase=0.000
|
||||
CSET pll_clkout5_divide=1
|
||||
CSET pll_clkout5_duty_cycle=0.500
|
||||
CSET pll_clkout5_phase=0.000
|
||||
CSET pll_compensation=EXTERNAL
|
||||
CSET pll_divclk_divide=1
|
||||
CSET pll_notes=None
|
||||
CSET pll_ref_jitter=0.010
|
||||
CSET power_down_port=POWER_DOWN
|
||||
CSET prim_in_freq=33.333
|
||||
CSET prim_in_jitter=0.010101
|
||||
CSET prim_source=Single_ended_clock_capable_pin
|
||||
CSET primary_port=CLKIN
|
||||
CSET primitive=MMCM
|
||||
CSET primtype_sel=PLL_BASE
|
||||
CSET psclk_port=PSCLK
|
||||
CSET psdone_port=PSDONE
|
||||
CSET psen_port=PSEN
|
||||
CSET psincdec_port=PSINCDEC
|
||||
CSET relative_inclk=REL_PRIMARY
|
||||
CSET reset_port=RESET
|
||||
CSET secondary_in_freq=100.000
|
||||
CSET secondary_in_jitter=0.0033000033
|
||||
CSET secondary_port=CLK_IN2
|
||||
CSET secondary_source=Single_ended_clock_capable_pin
|
||||
CSET ss_mod_freq=250
|
||||
CSET ss_mode=CENTER_HIGH
|
||||
CSET status_port=STATUS
|
||||
CSET summary_strings=empty
|
||||
CSET use_clk_valid=false
|
||||
CSET use_clkfb_stopped=false
|
||||
CSET use_dyn_phase_shift=false
|
||||
CSET use_dyn_reconfig=false
|
||||
CSET use_freeze=false
|
||||
CSET use_freq_synth=true
|
||||
CSET use_inclk_stopped=false
|
||||
CSET use_inclk_switchover=false
|
||||
CSET use_locked=false
|
||||
CSET use_max_i_jitter=false
|
||||
CSET use_min_o_jitter=false
|
||||
CSET use_min_power=false
|
||||
CSET use_phase_alignment=true
|
||||
CSET use_power_down=false
|
||||
CSET use_reset=false
|
||||
CSET use_spread_spectrum=false
|
||||
CSET use_spread_spectrum_1=false
|
||||
CSET use_status=false
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-05-10T12:44:55Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 6c4dba5b
|
||||
66
fpga/ipcore_dir/CLK.xdc
Normal file
66
fpga/ipcore_dir/CLK.xdc
Normal file
@ -0,0 +1,66 @@
|
||||
# file: CLK.xdc
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
create_clock -name CLK_IN1 -period 30.0 [get_ports CLK_IN1]
|
||||
set_propagated_clock CLK_IN1
|
||||
set_input_jitter CLK_IN1 0.30302999999999997
|
||||
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
403
fpga/ipcore_dir/CLK.xise
Normal file
403
fpga/ipcore_dir/CLK.xise
Normal file
@ -0,0 +1,403 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="CLK.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="CLK.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|CLK" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="CLK.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/CLK" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="CLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ftg256" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="CLK_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="CLK_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="CLK_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="CLK_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="CLK" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-10-29T08:25:35" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="CB437BF50B554A6C887C126004DC024B" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/CLK" xil_pn:name="CLK.ucf"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
184
fpga/ipcore_dir/CLK/clk_wiz_v3_6_readme.txt
Normal file
184
fpga/ipcore_dir/CLK/clk_wiz_v3_6_readme.txt
Normal file
@ -0,0 +1,184 @@
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: June 19, 2013
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
|
||||
|
||||
................................................................................
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
|
||||
|
||||
Zynq-7000 devices
|
||||
Zynq-7000
|
||||
Defense Grade Zynq-7000Q (XQ)
|
||||
|
||||
|
||||
All Virtex-6 devices
|
||||
|
||||
|
||||
All Spartan-6 devices
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- Spread Spectrum support for 7 series MMCME2
|
||||
|
||||
- ISE 14.2 software support
|
||||
|
||||
................................................................................
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with example design becoming core top in planAhead
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
|
||||
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
|
||||
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
|
||||
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
|
||||
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
|
||||
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
|
||||
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
|
||||
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
184
fpga/ipcore_dir/CLK/doc/clk_wiz_v3_6_readme.txt
Normal file
184
fpga/ipcore_dir/CLK/doc/clk_wiz_v3_6_readme.txt
Normal file
@ -0,0 +1,184 @@
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: June 19, 2013
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
|
||||
|
||||
................................................................................
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
|
||||
|
||||
Zynq-7000 devices
|
||||
Zynq-7000
|
||||
Defense Grade Zynq-7000Q (XQ)
|
||||
|
||||
|
||||
All Virtex-6 devices
|
||||
|
||||
|
||||
All Spartan-6 devices
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- Spread Spectrum support for 7 series MMCME2
|
||||
|
||||
- ISE 14.2 software support
|
||||
|
||||
................................................................................
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with example design becoming core top in planAhead
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
|
||||
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
|
||||
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
|
||||
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
|
||||
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
|
||||
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
|
||||
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
|
||||
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
195
fpga/ipcore_dir/CLK/doc/clk_wiz_v3_6_vinfo.html
Normal file
195
fpga/ipcore_dir/CLK/doc/clk_wiz_v3_6_vinfo.html
Normal file
@ -0,0 +1,195 @@
|
||||
<HTML>
|
||||
<HEAD>
|
||||
<TITLE>clk_wiz_v3_6_vinfo</TITLE>
|
||||
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
|
||||
</HEAD>
|
||||
<BODY>
|
||||
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: June 19, 2013
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
|
||||
|
||||
For system requirements:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
<A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
|
||||
|
||||
Zynq-7000 devices
|
||||
Zynq-7000
|
||||
Defense Grade Zynq-7000Q (XQ)
|
||||
|
||||
|
||||
All Virtex-6 devices
|
||||
|
||||
|
||||
All Spartan-6 devices
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- Spread Spectrum support for 7 series MMCME2
|
||||
|
||||
- ISE 14.2 software support
|
||||
|
||||
................................................................................
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with example design becoming core top in planAhead
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes Guide
|
||||
located at
|
||||
|
||||
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
|
||||
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
|
||||
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
|
||||
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
|
||||
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
|
||||
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
|
||||
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
|
||||
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
|
||||
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
</FONT>
|
||||
</PRE>
|
||||
</BODY>
|
||||
</HTML>
|
||||
BIN
fpga/ipcore_dir/CLK/doc/pg065_clk_wiz.pdf
Normal file
BIN
fpga/ipcore_dir/CLK/doc/pg065_clk_wiz.pdf
Normal file
Binary file not shown.
64
fpga/ipcore_dir/CLK/example_design/CLK_exdes.ucf
Normal file
64
fpga/ipcore_dir/CLK/example_design/CLK_exdes.ucf
Normal file
@ -0,0 +1,64 @@
|
||||
# file: CLK_exdes.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 303.03ps;
|
||||
|
||||
|
||||
# Constraints for external feedback.
|
||||
# Change delay numbers as per requirement
|
||||
#-----------------------------------------------------------------
|
||||
NET "CLKFB_IN" FEEDBACK = 0.1 ns NET "CLKFB_OUT";
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "COUNTER_RESET" TIG;
|
||||
|
||||
173
fpga/ipcore_dir/CLK/example_design/CLK_exdes.v
Normal file
173
fpga/ipcore_dir/CLK/example_design/CLK_exdes.v
Normal file
@ -0,0 +1,173 @@
|
||||
// file: CLK_exdes.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clocking wizard example design
|
||||
//----------------------------------------------------------------------------
|
||||
// This example design instantiates the created clocking network, where each
|
||||
// output clock drives a counter. The high bit of each counter is ported.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module CLK_exdes
|
||||
#(
|
||||
parameter TCQ = 100
|
||||
)
|
||||
(// Clock in ports
|
||||
input CLK_IN1,
|
||||
input CLKFB_IN,
|
||||
// Reset that only drives logic in example design
|
||||
input COUNTER_RESET,
|
||||
output [2:1] CLK_OUT,
|
||||
// High bits of counters driven by clocks
|
||||
output [2:1] COUNT,
|
||||
output CLKFB_OUT
|
||||
);
|
||||
|
||||
// Parameters for the counters
|
||||
//-------------------------------
|
||||
// Counter width
|
||||
localparam C_W = 16;
|
||||
localparam NUM_C = 2;
|
||||
genvar count_gen;
|
||||
// Create reset for the counters
|
||||
wire reset_int = COUNTER_RESET;
|
||||
|
||||
reg [NUM_C:1] rst_sync;
|
||||
reg [NUM_C:1] rst_sync_int;
|
||||
reg [NUM_C:1] rst_sync_int1;
|
||||
reg [NUM_C:1] rst_sync_int2;
|
||||
|
||||
|
||||
// Declare the clocks and counters
|
||||
wire [NUM_C:1] clk_int;
|
||||
wire [NUM_C:1] clk_n;
|
||||
wire [NUM_C:1] clk;
|
||||
reg [C_W-1:0] counter [NUM_C:1];
|
||||
|
||||
// Instantiation of the clocking network
|
||||
//--------------------------------------
|
||||
CLK clknetwork
|
||||
(// Clock in ports
|
||||
.CLKIN (CLK_IN1),
|
||||
.CLKFB_IN (CLKFB_IN),
|
||||
// Clock out ports
|
||||
.FSBCLK (clk_int[1]),
|
||||
.CPUCLK (clk_int[2]),
|
||||
.CLKFB_OUT (CLKFB_OUT));
|
||||
|
||||
genvar clk_out_pins;
|
||||
|
||||
generate
|
||||
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
|
||||
begin: gen_outclk_oddr
|
||||
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
|
||||
|
||||
ODDR2 clkout_oddr
|
||||
(.Q (CLK_OUT[clk_out_pins]),
|
||||
.C0 (clk[clk_out_pins]),
|
||||
.C1 (clk_n[clk_out_pins]),
|
||||
.CE (1'b1),
|
||||
.D0 (1'b1),
|
||||
.D1 (1'b0),
|
||||
.R (1'b0),
|
||||
.S (1'b0));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Connect the output clocks to the design
|
||||
//-----------------------------------------
|
||||
assign clk[1] = clk_int[1];
|
||||
assign clk[2] = clk_int[2];
|
||||
|
||||
|
||||
// Reset synchronizer
|
||||
//-----------------------------------
|
||||
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
|
||||
always @(posedge reset_int or posedge clk[count_gen]) begin
|
||||
if (reset_int) begin
|
||||
rst_sync[count_gen] <= 1'b1;
|
||||
rst_sync_int[count_gen]<= 1'b1;
|
||||
rst_sync_int1[count_gen]<= 1'b1;
|
||||
rst_sync_int2[count_gen]<= 1'b1;
|
||||
end
|
||||
else begin
|
||||
rst_sync[count_gen] <= 1'b0;
|
||||
rst_sync_int[count_gen] <= rst_sync[count_gen];
|
||||
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
|
||||
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// Output clock sampling
|
||||
//-----------------------------------
|
||||
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
|
||||
|
||||
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
|
||||
if (rst_sync_int2[count_gen]) begin
|
||||
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
|
||||
end else begin
|
||||
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
|
||||
end
|
||||
end
|
||||
// alias the high bit of each counter to the corresponding
|
||||
// bit in the output bus
|
||||
assign COUNT[count_gen] = counter[count_gen][C_W-1];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
68
fpga/ipcore_dir/CLK/example_design/CLK_exdes.xdc
Normal file
68
fpga/ipcore_dir/CLK/example_design/CLK_exdes.xdc
Normal file
@ -0,0 +1,68 @@
|
||||
# file: CLK_exdes.xdc
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
create_clock -name CLK_IN1 -period 30.0 [get_ports CLK_IN1]
|
||||
set_propagated_clock CLK_IN1
|
||||
set_input_jitter CLK_IN1 0.30302999999999997
|
||||
|
||||
# FALSE PATH constraint added on COUNTER_RESET
|
||||
set_false_path -from [get_ports "COUNTER_RESET"]
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
90
fpga/ipcore_dir/CLK/implement/implement.bat
Normal file
90
fpga/ipcore_dir/CLK/implement/implement.bat
Normal file
@ -0,0 +1,90 @@
|
||||
REM file: implement.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM -----------------------------------------------------------------------------
|
||||
REM Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
REM -----------------------------------------------------------------------------
|
||||
|
||||
REM Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
REM Copy unisim_comp.v file to results directory
|
||||
copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
|
||||
|
||||
REM Synthesize the Verilog Wrapper Files
|
||||
echo 'Synthesizing Clocking Wizard design with XST'
|
||||
xst -ifn xst.scr
|
||||
move CLK_exdes.ngc results\
|
||||
|
||||
REM Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\CLK_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -uc CLK_exdes.ucf CLK_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map -timing -pr b CLK_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par -w mapped.ncd routed mapped.pcf
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed -o routed mapped.pcf
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level model for the clocking wizard example design'
|
||||
netgen -ofmt verilog -sim -sdf_anno false -tm CLK_exdes -w routed.ncd routed.v
|
||||
cd ..
|
||||
|
||||
91
fpga/ipcore_dir/CLK/implement/implement.sh
Normal file
91
fpga/ipcore_dir/CLK/implement/implement.sh
Normal file
@ -0,0 +1,91 @@
|
||||
#!/bin/sh
|
||||
# file: implement.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
# Clean up the results directory
|
||||
rm -rf results
|
||||
mkdir results
|
||||
|
||||
# Copy unisim_comp.v file to results directory
|
||||
cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
|
||||
|
||||
# Synthesize the Verilog Wrapper Files
|
||||
echo 'Synthesizing Clocking Wizard design with XST'
|
||||
xst -ifn xst.scr
|
||||
mv CLK_exdes.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/CLK_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -uc CLK_exdes.ucf CLK_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map -timing CLK_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par -w mapped.ncd routed mapped.pcf
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed -o routed mapped.pcf
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level model for the clocking wizard example design'
|
||||
netgen -ofmt verilog -sim -sdf_anno false -tm CLK_exdes -w routed.ncd routed.v
|
||||
|
||||
cd ..
|
||||
58
fpga/ipcore_dir/CLK/implement/planAhead_ise.bat
Normal file
58
fpga/ipcore_dir/CLK/implement/planAhead_ise.bat
Normal file
@ -0,0 +1,58 @@
|
||||
REM file: planAhead_ise.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM-----------------------------------------------------------------------------
|
||||
REM Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
REM-----------------------------------------------------------------------------
|
||||
|
||||
del \f results
|
||||
mkdir results
|
||||
cd results
|
||||
|
||||
planAhead -mode batch -source ..\planAhead_ise.tcl
|
||||
59
fpga/ipcore_dir/CLK/implement/planAhead_ise.sh
Normal file
59
fpga/ipcore_dir/CLK/implement/planAhead_ise.sh
Normal file
@ -0,0 +1,59 @@
|
||||
#!/bin/sh
|
||||
# file: planAhead_ise.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
|
||||
planAhead -mode batch -source ../planAhead_ise.tcl
|
||||
78
fpga/ipcore_dir/CLK/implement/planAhead_ise.tcl
Normal file
78
fpga/ipcore_dir/CLK/implement/planAhead_ise.tcl
Normal file
@ -0,0 +1,78 @@
|
||||
# file: planAhead_ise.tcl
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
set projDir [file dirname [info script]]
|
||||
set projName CLK
|
||||
set topName CLK_exdes
|
||||
set device xc6slx9ftg256-2
|
||||
|
||||
create_project $projName $projDir/results/$projName -part $device
|
||||
|
||||
set_property design_mode RTL [get_filesets sources_1]
|
||||
|
||||
## Source files
|
||||
#set verilogSources [glob $srcDir/*.v]
|
||||
import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/CLK_exdes.v
|
||||
import_files -fileset [get_filesets sources_1] -force -norecurse ../../../CLK.v
|
||||
|
||||
|
||||
#UCF file
|
||||
import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/CLK_exdes.ucf
|
||||
|
||||
set_property top $topName [get_property srcset [current_run]]
|
||||
|
||||
launch_runs -runs synth_1
|
||||
wait_on_run synth_1
|
||||
|
||||
set_property add_step Bitgen [get_runs impl_1]
|
||||
launch_runs -runs impl_1
|
||||
wait_on_run impl_1
|
||||
|
||||
|
||||
|
||||
58
fpga/ipcore_dir/CLK/implement/planAhead_rdn.bat
Normal file
58
fpga/ipcore_dir/CLK/implement/planAhead_rdn.bat
Normal file
@ -0,0 +1,58 @@
|
||||
REM file: planAhead_rdn.sh
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM-----------------------------------------------------------------------------
|
||||
REM Script to synthesize and implement the RTL provided for the XADC wizard
|
||||
REM-----------------------------------------------------------------------------
|
||||
|
||||
del \f results
|
||||
mkdir results
|
||||
cd results
|
||||
|
||||
planAhead -mode batch -source ..\planAhead_rdn.tcl
|
||||
57
fpga/ipcore_dir/CLK/implement/planAhead_rdn.sh
Normal file
57
fpga/ipcore_dir/CLK/implement/planAhead_rdn.sh
Normal file
@ -0,0 +1,57 @@
|
||||
#!/bin/sh
|
||||
# file: planAhead_rdn.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the RTL provided for the XADC wizard
|
||||
#-----------------------------------------------------------------------------
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
planAhead -mode batch -source ../planAhead_rdn.tcl
|
||||
69
fpga/ipcore_dir/CLK/implement/planAhead_rdn.tcl
Normal file
69
fpga/ipcore_dir/CLK/implement/planAhead_rdn.tcl
Normal file
@ -0,0 +1,69 @@
|
||||
# file : planAhead_rdn.tcl
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
set device xc6slx9ftg256-2
|
||||
set projName CLK
|
||||
set design CLK
|
||||
set projDir [file dirname [info script]]
|
||||
create_project $projName $projDir/results/$projName -part $device -force
|
||||
set_property design_mode RTL [current_fileset -srcset]
|
||||
set top_module CLK_exdes
|
||||
set_property top CLK_exdes [get_property srcset [current_run]]
|
||||
add_files -norecurse {../../../CLK.v}
|
||||
add_files -norecurse {../../example_design/CLK_exdes.v}
|
||||
import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/CLK_exdes.xdc}
|
||||
synth_design
|
||||
opt_design
|
||||
place_design
|
||||
route_design
|
||||
write_sdf -rename_top_module CLK_exdes -file routed.sdf
|
||||
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module CLK_exdes -file routed.v
|
||||
report_timing -nworst 30 -path_type full -file routed.twr
|
||||
report_drc -file report.drc
|
||||
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
|
||||
2
fpga/ipcore_dir/CLK/implement/xst.prj
Normal file
2
fpga/ipcore_dir/CLK/implement/xst.prj
Normal file
@ -0,0 +1,2 @@
|
||||
verilog work ../../CLK.v
|
||||
verilog work ../example_design/CLK_exdes.v
|
||||
9
fpga/ipcore_dir/CLK/implement/xst.scr
Normal file
9
fpga/ipcore_dir/CLK/implement/xst.scr
Normal file
@ -0,0 +1,9 @@
|
||||
run
|
||||
-ifmt MIXED
|
||||
-top CLK_exdes
|
||||
-p xc6slx9-ftg256-2
|
||||
-ifn xst.prj
|
||||
-ofn CLK_exdes
|
||||
-keep_hierarchy soft
|
||||
-equivalent_register_removal no
|
||||
-max_fanout 65535
|
||||
138
fpga/ipcore_dir/CLK/simulation/CLK_tb.v
Normal file
138
fpga/ipcore_dir/CLK/simulation/CLK_tb.v
Normal file
@ -0,0 +1,138 @@
|
||||
// file: CLK_tb.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clocking wizard demonstration testbench
|
||||
//----------------------------------------------------------------------------
|
||||
// This demonstration testbench instantiates the example design for the
|
||||
// clocking wizard. Input clocks are toggled, which cause the clocking
|
||||
// network to lock and the counters to increment.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`define wait_lock @(posedge dut.clknetwork.pll_base_inst.LOCKED)
|
||||
|
||||
module CLK_tb ();
|
||||
|
||||
// Clock to Q delay of 100ps
|
||||
localparam TCQ = 100;
|
||||
|
||||
|
||||
// timescale is 1ps/1ps
|
||||
localparam ONE_NS = 1000;
|
||||
localparam PHASE_ERR_MARGIN = 100; // 100ps
|
||||
// how many cycles to run
|
||||
localparam COUNT_PHASE = 1024;
|
||||
// we'll be using the period in many locations
|
||||
localparam time PER1 = 30.0*ONE_NS;
|
||||
localparam time PER1_1 = PER1/2;
|
||||
localparam time PER1_2 = PER1 - PER1/2;
|
||||
|
||||
// Declare the input clock signals
|
||||
reg CLK_IN1 = 1;
|
||||
|
||||
// The high bits of the sampling counters
|
||||
wire [2:1] COUNT;
|
||||
// Connect the feedback
|
||||
wire CLKFB_OUT;
|
||||
wire CLKFB_IN = CLKFB_OUT;
|
||||
reg COUNTER_RESET = 0;
|
||||
wire [2:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
|
||||
// Input clock generation
|
||||
//------------------------------------
|
||||
always begin
|
||||
CLK_IN1 = #PER1_1 ~CLK_IN1;
|
||||
CLK_IN1 = #PER1_2 ~CLK_IN1;
|
||||
end
|
||||
|
||||
// Test sequence
|
||||
reg [15*8-1:0] test_phase = "";
|
||||
initial begin
|
||||
// Set up any display statements using time to be readable
|
||||
$timeformat(-12, 2, "ps", 10);
|
||||
COUNTER_RESET = 0;
|
||||
test_phase = "wait lock";
|
||||
`wait_lock;
|
||||
#(PER1*6);
|
||||
COUNTER_RESET = 1;
|
||||
#(PER1*20)
|
||||
COUNTER_RESET = 0;
|
||||
|
||||
test_phase = "counting";
|
||||
#(PER1*COUNT_PHASE);
|
||||
|
||||
$display("SIMULATION PASSED");
|
||||
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Instantiation of the example design containing the clock
|
||||
// network and sampling counters
|
||||
//---------------------------------------------------------
|
||||
CLK_exdes
|
||||
#(
|
||||
.TCQ (TCQ)
|
||||
) dut
|
||||
(// Clock in ports
|
||||
.CLK_IN1 (CLK_IN1),
|
||||
.CLKFB_IN (CLKFB_IN),
|
||||
// Reset for logic in example design
|
||||
.COUNTER_RESET (COUNTER_RESET),
|
||||
.CLK_OUT (CLK_OUT),
|
||||
// High bits of the counters
|
||||
.COUNT (COUNT),
|
||||
.CLKFB_OUT (CLKFB_OUT));
|
||||
|
||||
// Freq Check
|
||||
|
||||
endmodule
|
||||
8
fpga/ipcore_dir/CLK/simulation/functional/simcmds.tcl
Normal file
8
fpga/ipcore_dir/CLK/simulation/functional/simcmds.tcl
Normal file
@ -0,0 +1,8 @@
|
||||
# file: simcmds.tcl
|
||||
|
||||
# create the simulation script
|
||||
vcd dumpfile isim.vcd
|
||||
vcd dumpvars -m /CLK_tb -l 0
|
||||
wave add /
|
||||
run 50000ns
|
||||
quit
|
||||
59
fpga/ipcore_dir/CLK/simulation/functional/simulate_isim.bat
Normal file
59
fpga/ipcore_dir/CLK/simulation/functional/simulate_isim.bat
Normal file
@ -0,0 +1,59 @@
|
||||
REM file: simulate_isim.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
vlogcomp -work work %XILINX%\verilog\src\glbl.v
|
||||
vlogcomp -work work ..\..\..\CLK.v
|
||||
vlogcomp -work work ..\..\example_design\CLK_exdes.v
|
||||
vlogcomp -work work ..\CLK_tb.v
|
||||
|
||||
REM compile the project
|
||||
fuse work.CLK_tb work.glbl -L unisims_ver -o CLK_isim.exe
|
||||
|
||||
REM run the simulation script
|
||||
.\CLK_isim.exe -gui -tclbatch simcmds.tcl
|
||||
61
fpga/ipcore_dir/CLK/simulation/functional/simulate_isim.sh
Normal file
61
fpga/ipcore_dir/CLK/simulation/functional/simulate_isim.sh
Normal file
@ -0,0 +1,61 @@
|
||||
# file: simulate_isim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# nt
|
||||
# create the project
|
||||
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
|
||||
vlogcomp -work work ../../../CLK.v
|
||||
vlogcomp -work work ../../example_design/CLK_exdes.v
|
||||
vlogcomp -work work ../CLK_tb.v
|
||||
|
||||
# compile the project
|
||||
fuse work.CLK_tb work.glbl -L unisims_ver -o CLK_isim.exe
|
||||
|
||||
# run the simulation script
|
||||
./CLK_isim.exe -gui -tclbatch simcmds.tcl
|
||||
61
fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.bat
Normal file
61
fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.bat
Normal file
@ -0,0 +1,61 @@
|
||||
REM file: simulate_mti.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM set up the working directory
|
||||
vlib work
|
||||
|
||||
REM compile all of the files
|
||||
vlog -work work %XILINX%\verilog\src\glbl.v
|
||||
vlog -work work ..\..\..\CLK.v
|
||||
vlog -work work ..\..\example_design\CLK_exdes.v
|
||||
vlog -work work ..\CLK_tb.v
|
||||
|
||||
REM run the simulation
|
||||
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.CLK_tb work.glbl
|
||||
|
||||
65
fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.do
Normal file
65
fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.do
Normal file
@ -0,0 +1,65 @@
|
||||
# file: simulate_mti.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $env(XILINX)/verilog/src/glbl.v
|
||||
vlog -work work ../../../CLK.v
|
||||
vlog -work work ../../example_design/CLK_exdes.v
|
||||
vlog -work work ../CLK_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -t ps -voptargs="+acc" -L unisims_ver work.CLK_tb work.glbl
|
||||
do wave.do
|
||||
log CLK_tb/dut/counter
|
||||
log -r /*
|
||||
run 50000ns
|
||||
61
fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.sh
Normal file
61
fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.sh
Normal file
@ -0,0 +1,61 @@
|
||||
#/bin/sh
|
||||
# file: simulate_mti.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $XILINX/verilog/src/glbl.v
|
||||
vlog -work work ../../../CLK.v
|
||||
vlog -work work ../../example_design/CLK_exdes.v
|
||||
vlog -work work ../CLK_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.CLK_tb work.glbl
|
||||
62
fpga/ipcore_dir/CLK/simulation/functional/simulate_ncsim.sh
Normal file
62
fpga/ipcore_dir/CLK/simulation/functional/simulate_ncsim.sh
Normal file
@ -0,0 +1,62 @@
|
||||
#/bin/sh
|
||||
# file: simulate_ncsim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
mkdir work
|
||||
|
||||
# compile all of the files
|
||||
ncvlog -work work ${XILINX}/verilog/src/glbl.v
|
||||
ncvlog -work work ../../../CLK.v
|
||||
ncvlog -work work ../../example_design/CLK_exdes.v
|
||||
ncvlog -work work ../CLK_tb.v
|
||||
|
||||
# elaborate and run the simulation
|
||||
ncelab -work work -access +wc work.CLK_tb work.glbl
|
||||
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.CLK_tb
|
||||
72
fpga/ipcore_dir/CLK/simulation/functional/simulate_vcs.sh
Normal file
72
fpga/ipcore_dir/CLK/simulation/functional/simulate_vcs.sh
Normal file
@ -0,0 +1,72 @@
|
||||
#!/bin/sh
|
||||
# file: simulate_vcs.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# remove old files
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
# compile all of the files
|
||||
# Note that -sverilog is not strictly required- You can
|
||||
# remove the -sverilog if you change the type of the
|
||||
# localparam for the periods in the testbench file to
|
||||
# [63:0] from time
|
||||
vlogan -sverilog \
|
||||
${XILINX}/verilog/src/glbl.v \
|
||||
../../../CLK.v \
|
||||
../../example_design/CLK_exdes.v \
|
||||
../CLK_tb.v
|
||||
|
||||
# prepare the simulation
|
||||
vcs +vcs+lic+wait -debug CLK_tb glbl
|
||||
|
||||
# run the simulation
|
||||
./simv -ucli -i ucli_commands.key
|
||||
|
||||
# launch the viewer
|
||||
dve -vpd vcdplus.vpd -session vcs_session.tcl
|
||||
@ -0,0 +1,5 @@
|
||||
call {$vcdpluson}
|
||||
call {$vcdplusmemon(CLK_tb.dut.counter)}
|
||||
run
|
||||
call {$vcdplusclose}
|
||||
quit
|
||||
15
fpga/ipcore_dir/CLK/simulation/functional/vcs_session.tcl
Normal file
15
fpga/ipcore_dir/CLK/simulation/functional/vcs_session.tcl
Normal file
@ -0,0 +1,15 @@
|
||||
gui_open_window Wave
|
||||
gui_sg_create CLK_group
|
||||
gui_list_add_group -id Wave.1 {CLK_group}
|
||||
gui_sg_addsignal -group CLK_group {CLK_tb.test_phase}
|
||||
gui_set_radix -radix {ascii} -signals {CLK_tb.test_phase}
|
||||
gui_sg_addsignal -group CLK_group {{Input_clocks}} -divider
|
||||
gui_sg_addsignal -group CLK_group {CLK_tb.CLK_IN1}
|
||||
gui_sg_addsignal -group CLK_group {{Output_clocks}} -divider
|
||||
gui_sg_addsignal -group CLK_group {CLK_tb.dut.clk}
|
||||
gui_list_expand -id Wave.1 CLK_tb.dut.clk
|
||||
gui_sg_addsignal -group CLK_group {{Counters}} -divider
|
||||
gui_sg_addsignal -group CLK_group {CLK_tb.COUNT}
|
||||
gui_sg_addsignal -group CLK_group {CLK_tb.dut.counter}
|
||||
gui_list_expand -id Wave.1 CLK_tb.dut.counter
|
||||
gui_zoom -window Wave.1 -full
|
||||
57
fpga/ipcore_dir/CLK/simulation/functional/wave.do
Normal file
57
fpga/ipcore_dir/CLK/simulation/functional/wave.do
Normal file
@ -0,0 +1,57 @@
|
||||
# file: wave.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
add wave -noupdate -format Literal -radix ascii /CLK_tb/test_phase
|
||||
add wave -noupdate -divider {Input clocks}
|
||||
add wave -noupdate -format Logic /CLK_tb/CLK_IN1
|
||||
add wave -noupdate -divider {Output clocks}
|
||||
add wave -noupdate -format Literal -expand /CLK_tb/dut/clk
|
||||
add wave -noupdate -divider Counters
|
||||
add wave -noupdate -format Literal -radix hexadecimal /CLK_tb/COUNT
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /CLK_tb/dut/counter
|
||||
111
fpga/ipcore_dir/CLK/simulation/functional/wave.sv
Normal file
111
fpga/ipcore_dir/CLK/simulation/functional/wave.sv
Normal file
@ -0,0 +1,111 @@
|
||||
# file: wave.sv
|
||||
#
|
||||
# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# Get the windows set up
|
||||
#
|
||||
if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
|
||||
window geometry "Design Browser 1" 1054x819+536+322
|
||||
}
|
||||
window target "Design Browser 1" on
|
||||
browser using {Design Browser 1}
|
||||
browser set \
|
||||
-scope nc::CLK_tb
|
||||
browser yview see nc::CLK_tb
|
||||
browser timecontrol set -lock 0
|
||||
|
||||
if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
|
||||
window geometry "Waveform 1" 1010x600+0+541
|
||||
}
|
||||
window target "Waveform 1" on
|
||||
waveform using {Waveform 1}
|
||||
waveform sidebar visibility partial
|
||||
waveform set \
|
||||
-primarycursor TimeA \
|
||||
-signalnames name \
|
||||
-signalwidth 175 \
|
||||
-units ns \
|
||||
-valuewidth 75
|
||||
cursor set -using TimeA -time 0
|
||||
waveform baseline set -time 0
|
||||
waveform xview limits 0 20000n
|
||||
|
||||
#
|
||||
# Define signal groups
|
||||
#
|
||||
catch {group new -name {Output clocks} -overlay 0}
|
||||
catch {group new -name {Status/control} -overlay 0}
|
||||
catch {group new -name {Counters} -overlay 0}
|
||||
|
||||
set id [waveform add -signals [list {nc::CLK_tb.CLK_IN1}]]
|
||||
|
||||
group using {Output clocks}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{CLK_tb.dut.clk[1]} \
|
||||
{CLK_tb.dut.clk[2]}
|
||||
group using {Counters}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{CLK_tb.dut.counter[1]} \
|
||||
{CLK_tb.dut.counter[2]}
|
||||
|
||||
set id [waveform add -signals [list {nc::CLK_tb.COUNT} ]]
|
||||
|
||||
set id [waveform add -signals [list {nc::CLK_tb.test_phase} ]]
|
||||
waveform format $id -radix %a
|
||||
|
||||
set groupId [waveform add -groups {{Input clocks}}]
|
||||
set groupId [waveform add -groups {{Output clocks}}]
|
||||
set groupId [waveform add -groups {{Status/control}}]
|
||||
set groupId [waveform add -groups {{Counters}}]
|
||||
141
fpga/ipcore_dir/CLK/simulation/timing/CLK_tb.v
Normal file
141
fpga/ipcore_dir/CLK/simulation/timing/CLK_tb.v
Normal file
@ -0,0 +1,141 @@
|
||||
// file: CLK_tb.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clocking wizard demonstration testbench
|
||||
//----------------------------------------------------------------------------
|
||||
// This demonstration testbench instantiates the example design for the
|
||||
// clocking wizard. Input clocks are toggled, which cause the clocking
|
||||
// network to lock and the counters to increment.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module CLK_tb ();
|
||||
|
||||
// Clock to Q delay of 100ps
|
||||
localparam TCQ = 100;
|
||||
|
||||
|
||||
// timescale is 1ps/1ps
|
||||
localparam ONE_NS = 1000;
|
||||
localparam PHASE_ERR_MARGIN = 100; // 100ps
|
||||
// how many cycles to run
|
||||
localparam COUNT_PHASE = 1024;
|
||||
// we'll be using the period in many locations
|
||||
localparam time PER1 = 30.0*ONE_NS;
|
||||
localparam time PER1_1 = PER1/2;
|
||||
localparam time PER1_2 = PER1 - PER1/2;
|
||||
|
||||
// Declare the input clock signals
|
||||
reg CLK_IN1 = 1;
|
||||
|
||||
// The high bits of the sampling counters
|
||||
wire [2:1] COUNT;
|
||||
// Connect the feedback
|
||||
wire CLKFB_OUT;
|
||||
wire CLKFB_IN = CLKFB_OUT;
|
||||
reg COUNTER_RESET = 0;
|
||||
wire [2:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
reg [13:0] timeout_counter = 14'b00000000000000;
|
||||
|
||||
// Input clock generation
|
||||
//------------------------------------
|
||||
always begin
|
||||
CLK_IN1 = #PER1_1 ~CLK_IN1;
|
||||
CLK_IN1 = #PER1_2 ~CLK_IN1;
|
||||
end
|
||||
|
||||
// Test sequence
|
||||
reg [15*8-1:0] test_phase = "";
|
||||
initial begin
|
||||
// Set up any display statements using time to be readable
|
||||
$timeformat(-12, 2, "ps", 10);
|
||||
$display ("Timing checks are not valid");
|
||||
COUNTER_RESET = 0;
|
||||
test_phase = "wait lock";
|
||||
#(PER1*50);
|
||||
#(PER1*6);
|
||||
COUNTER_RESET = 1;
|
||||
#(PER1*19.5)
|
||||
COUNTER_RESET = 0;
|
||||
#(PER1*1)
|
||||
$display ("Timing checks are valid");
|
||||
test_phase = "counting";
|
||||
#(PER1*COUNT_PHASE);
|
||||
|
||||
$display("SIMULATION PASSED");
|
||||
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
|
||||
// Instantiation of the example design containing the clock
|
||||
// network and sampling counters
|
||||
//---------------------------------------------------------
|
||||
CLK_exdes
|
||||
dut
|
||||
(// Clock in ports
|
||||
.CLK_IN1 (CLK_IN1),
|
||||
.CLKFB_IN (CLKFB_IN),
|
||||
// Reset for logic in example design
|
||||
.COUNTER_RESET (COUNTER_RESET),
|
||||
.CLK_OUT (CLK_OUT),
|
||||
// High bits of the counters
|
||||
.COUNT (COUNT),
|
||||
.CLKFB_OUT (CLKFB_OUT));
|
||||
|
||||
|
||||
// Freq Check
|
||||
|
||||
endmodule
|
||||
2
fpga/ipcore_dir/CLK/simulation/timing/sdf_cmd_file
Normal file
2
fpga/ipcore_dir/CLK/simulation/timing/sdf_cmd_file
Normal file
@ -0,0 +1,2 @@
|
||||
COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
|
||||
SCOPE = CLK_tb.dut;
|
||||
9
fpga/ipcore_dir/CLK/simulation/timing/simcmds.tcl
Normal file
9
fpga/ipcore_dir/CLK/simulation/timing/simcmds.tcl
Normal file
@ -0,0 +1,9 @@
|
||||
# file: simcmds.tcl
|
||||
|
||||
# create the simulation script
|
||||
vcd dumpfile isim.vcd
|
||||
vcd dumpvars -m /CLK_tb -l 0
|
||||
wave add /
|
||||
run 50000ns
|
||||
quit
|
||||
|
||||
62
fpga/ipcore_dir/CLK/simulation/timing/simulate_isim.sh
Normal file
62
fpga/ipcore_dir/CLK/simulation/timing/simulate_isim.sh
Normal file
@ -0,0 +1,62 @@
|
||||
# file: simulate_isim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# create the project
|
||||
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
|
||||
vlogcomp -work work ../../implement/results/routed.v
|
||||
vlogcomp -work work CLK_tb.v
|
||||
|
||||
# compile the project
|
||||
fuse work.CLK_tb work.glbl -L secureip -L simprims_ver -o CLK_isim.exe
|
||||
|
||||
# run the simulation script
|
||||
./CLK_isim.exe -tclbatch simcmds.tcl -sdfmax /CLK_tb/dut=../../implement/results/routed.sdf
|
||||
|
||||
# run the simulation script
|
||||
#./CLK_isim.exe -gui -tclbatch simcmds.tcl
|
||||
59
fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.bat
Normal file
59
fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.bat
Normal file
@ -0,0 +1,59 @@
|
||||
REM file: simulate_mti.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
REM compile all of the files
|
||||
vlog -work work %XILINX%\verilog\src\glbl.v
|
||||
vlog -work work ..\..\implement\results\routed.v
|
||||
vlog -work work CLK_tb.v
|
||||
|
||||
REM run the simulation
|
||||
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax CLK_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.CLK_tb work.glbl
|
||||
65
fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.do
Normal file
65
fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.do
Normal file
@ -0,0 +1,65 @@
|
||||
# file: simulate_mti.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $env(XILINX)/verilog/src/glbl.v
|
||||
vlog -work work ../../implement/results/routed.v
|
||||
vlog -work work CLK_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax CLK_tb/dut=../../implement/results/routed.sdf +no_notifier work.CLK_tb work.glbl
|
||||
#do wave.do
|
||||
#log -r /*
|
||||
run 50000ns
|
||||
|
||||
|
||||
61
fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.sh
Normal file
61
fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.sh
Normal file
@ -0,0 +1,61 @@
|
||||
#/bin/sh
|
||||
# file: simulate_mti.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $XILINX/verilog/src/glbl.v
|
||||
vlog -work work ../../implement/results/routed.v
|
||||
vlog -work work CLK_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax CLK_tb/dut=../../implement/results/routed.sdf +no_notifier work.CLK_tb work.glbl
|
||||
64
fpga/ipcore_dir/CLK/simulation/timing/simulate_ncsim.sh
Normal file
64
fpga/ipcore_dir/CLK/simulation/timing/simulate_ncsim.sh
Normal file
@ -0,0 +1,64 @@
|
||||
#!/bin/sh
|
||||
# file: simulate_ncsim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
mkdir work
|
||||
|
||||
# compile all of the files
|
||||
ncvlog -work work ${XILINX}/verilog/src/glbl.v
|
||||
ncvlog -work work ../../implement/results/routed.v
|
||||
ncvlog -work work CLK_tb.v
|
||||
|
||||
# elaborate and run the simulation
|
||||
ncsdfc ../../implement/results/routed.sdf
|
||||
|
||||
ncelab -work work -access +wc -pulse_r 10 -nonotifier work.CLK_tb work.glbl -sdf_cmd_file sdf_cmd_file
|
||||
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.CLK_tb
|
||||
|
||||
72
fpga/ipcore_dir/CLK/simulation/timing/simulate_vcs.sh
Normal file
72
fpga/ipcore_dir/CLK/simulation/timing/simulate_vcs.sh
Normal file
@ -0,0 +1,72 @@
|
||||
#!/bin/sh
|
||||
# file: simulate_vcs.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# remove old files
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
# compile all of the files
|
||||
# Note that -sverilog is not strictly required- You can
|
||||
# remove the -sverilog if you change the type of the
|
||||
# localparam for the periods in the testbench file to
|
||||
# [63:0] from time
|
||||
vlogan -sverilog \
|
||||
CLK_tb.v \
|
||||
../../implement/results/routed.v
|
||||
|
||||
|
||||
# prepare the simulation
|
||||
vcs -sdf max:CLK_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
|
||||
+libext+.v -debug CLK_tb.v ../../implement/results/routed.v
|
||||
|
||||
# run the simulation
|
||||
./simv -ucli -i ucli_commands.key
|
||||
|
||||
# launch the viewer
|
||||
#dve -vpd vcdplus.vpd -session vcs_session.tcl
|
||||
5
fpga/ipcore_dir/CLK/simulation/timing/ucli_commands.key
Normal file
5
fpga/ipcore_dir/CLK/simulation/timing/ucli_commands.key
Normal file
@ -0,0 +1,5 @@
|
||||
|
||||
call {$vcdpluson}
|
||||
run 50000ns
|
||||
call {$vcdplusclose}
|
||||
quit
|
||||
1
fpga/ipcore_dir/CLK/simulation/timing/vcs_session.tcl
Normal file
1
fpga/ipcore_dir/CLK/simulation/timing/vcs_session.tcl
Normal file
@ -0,0 +1 @@
|
||||
gui_open_window Wave
|
||||
70
fpga/ipcore_dir/CLK/simulation/timing/wave.do
Normal file
70
fpga/ipcore_dir/CLK/simulation/timing/wave.do
Normal file
@ -0,0 +1,70 @@
|
||||
# file: wave.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /CLK_tb/CLK_IN1
|
||||
add wave -noupdate /CLK_tb/COUNT
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
|
||||
configure wave -namecolwidth 238
|
||||
configure wave -valuecolwidth 107
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {74848022 ps}
|
||||
55
fpga/ipcore_dir/CLK_flist.txt
Normal file
55
fpga/ipcore_dir/CLK_flist.txt
Normal file
@ -0,0 +1,55 @@
|
||||
# Output products list for <CLK>
|
||||
CLK.asy
|
||||
CLK.gise
|
||||
CLK.sym
|
||||
CLK.ucf
|
||||
CLK.v
|
||||
CLK.veo
|
||||
CLK.xco
|
||||
CLK.xdc
|
||||
CLK.xise
|
||||
CLK\clk_wiz_v3_6_readme.txt
|
||||
CLK\doc\clk_wiz_v3_6_readme.txt
|
||||
CLK\doc\clk_wiz_v3_6_vinfo.html
|
||||
CLK\doc\pg065_clk_wiz.pdf
|
||||
CLK\example_design\CLK_exdes.ucf
|
||||
CLK\example_design\CLK_exdes.v
|
||||
CLK\example_design\CLK_exdes.xdc
|
||||
CLK\implement\implement.bat
|
||||
CLK\implement\implement.sh
|
||||
CLK\implement\planAhead_ise.bat
|
||||
CLK\implement\planAhead_ise.sh
|
||||
CLK\implement\planAhead_ise.tcl
|
||||
CLK\implement\planAhead_rdn.bat
|
||||
CLK\implement\planAhead_rdn.sh
|
||||
CLK\implement\planAhead_rdn.tcl
|
||||
CLK\implement\xst.prj
|
||||
CLK\implement\xst.scr
|
||||
CLK\simulation\CLK_tb.v
|
||||
CLK\simulation\functional\simcmds.tcl
|
||||
CLK\simulation\functional\simulate_isim.bat
|
||||
CLK\simulation\functional\simulate_isim.sh
|
||||
CLK\simulation\functional\simulate_mti.bat
|
||||
CLK\simulation\functional\simulate_mti.do
|
||||
CLK\simulation\functional\simulate_mti.sh
|
||||
CLK\simulation\functional\simulate_ncsim.sh
|
||||
CLK\simulation\functional\simulate_vcs.sh
|
||||
CLK\simulation\functional\ucli_commands.key
|
||||
CLK\simulation\functional\vcs_session.tcl
|
||||
CLK\simulation\functional\wave.do
|
||||
CLK\simulation\functional\wave.sv
|
||||
CLK\simulation\timing\CLK_tb.v
|
||||
CLK\simulation\timing\sdf_cmd_file
|
||||
CLK\simulation\timing\simcmds.tcl
|
||||
CLK\simulation\timing\simulate_isim.sh
|
||||
CLK\simulation\timing\simulate_mti.bat
|
||||
CLK\simulation\timing\simulate_mti.do
|
||||
CLK\simulation\timing\simulate_mti.sh
|
||||
CLK\simulation\timing\simulate_ncsim.sh
|
||||
CLK\simulation\timing\simulate_vcs.sh
|
||||
CLK\simulation\timing\ucli_commands.key
|
||||
CLK\simulation\timing\vcs_session.tcl
|
||||
CLK\simulation\timing\wave.do
|
||||
CLK_flist.txt
|
||||
CLK_xmdf.tcl
|
||||
_xmsgs\pn_parser.xmsgs
|
||||
140
fpga/ipcore_dir/CLK_xmdf.tcl
Normal file
140
fpga/ipcore_dir/CLK_xmdf.tcl
Normal file
@ -0,0 +1,140 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide CLK_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::CLK_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::CLK_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name CLK
|
||||
}
|
||||
# ::CLK_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::CLK_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/clk_wiz_readme.txt
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/doc/clk_wiz_ds709.pdf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/doc/clk_wiz_gsg521.pdf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/implement/implement.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/implement/implement.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/implement/xst.prj
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/implement/xst.scr
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/CLK_tb.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/simcmds.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/simulate_isim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/simulate_mti.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/simulate_ncsim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/simulate_vcs.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/ucli_commands.key
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/vcs_session.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/wave.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/wave.sv
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK.ejp
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module CLK
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
27
fpga/ipcore_dir/_xmsgs/cg.xmsgs
Normal file
27
fpga/ipcore_dir/_xmsgs/cg.xmsgs
Normal file
@ -0,0 +1,27 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="sim" num="172" delta="old" >Generating IP...
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'CLK' already exists in the project. Output products for this core may be overwritten.</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'CLK' already exists in the project. Output products for this core may be overwritten.</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user