mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2025-04-11 17:39:34 +00:00
More cache stuff
This commit is contained in:
Zane Kaminski
parent
22482ee4e4
commit
32019a34ee
@ -1,5 +1,5 @@
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module CS(
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input [31:8] A
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input [31:0] A,
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output RAMCS,
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output ROMCS,
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output VRAMCS,
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@ -17,6 +17,6 @@ module CS(
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assign CA[27] = A[30];
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assign CA[26] = A[28];
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assign CA[25:0] = A[25:0];
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assign CA[25:2] = A[25:2];
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endmodule
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1
fpga/L2Cache.cmd_log
Normal file
1
fpga/L2Cache.cmd_log
Normal file
@ -0,0 +1 @@
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vhdtdtfi -lang verilog -prj WarpLC -o C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/L2Cache.tfi -lib work C:/Users/Dog/Documents/GitHub/Warp-LC/fpga//L2Cache.v -module L2Cache -template C:/Xilinx/14.7/ISE_DS/ISE//data/tfi.tft -deleteonerror
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20
fpga/L2Cache.tfi
Normal file
20
fpga/L2Cache.tfi
Normal file
@ -0,0 +1,20 @@
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// Instantiate the module
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L2Cache instance_name (
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.CLK(CLK),
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.CPUCLKr(CPUCLKr),
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.RDA(RDA),
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.RDD(RDD),
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.Match(Match),
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.WRA(WRA),
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.WRD(WRD),
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.WRM(WRM),
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.TS(TS),
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.WR(WR),
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.CLR(CLR),
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.ALL(ALL)
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);
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@ -15,8 +15,8 @@ module L2Cache(
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input ALL);
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/* Cache ways */
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wire [31:0] WayRDD[7:0];
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wire WayRDMatch[7:0];
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wire [255:0] WayRDD;
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wire [7:0] WayRDMatch;
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L2CacheWay Way[7:0] (
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.CLK(CLK),
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.CPUCLKr(CPUCLKr),
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@ -31,18 +31,18 @@ module L2Cache(
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.CLR(CLR),
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.ALL(ALL));
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assign Match == WayRDMatch[0] || WayRDMatch[1] ||
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WayRDMatch[2] || WayRDMatch[3] ||
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WayRDMatch[4] || WayRDMatch[5] ||
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WayRDMatch[6] || WayRDMatch[7];
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assign Match = WayRDMatch[0] || WayRDMatch[1] ||
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WayRDMatch[2] || WayRDMatch[3] ||
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WayRDMatch[4] || WayRDMatch[5] ||
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WayRDMatch[6] || WayRDMatch[7];
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assign RDD[31:0] = WayRDMatch[0] ? WayRDD[0] :
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WayRDMatch[1] ? WayRDD[1] :
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WayRDMatch[2] ? WayRDD[2] :
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WayRDMatch[3] ? WayRDD[3] :
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WayRDMatch[4] ? WayRDD[4] :
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WayRDMatch[5] ? WayRDD[5] :
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WayRDMatch[6] ? WayRDD[6] :
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WayRDMatch[7] ? WayRDD[7] : 0;
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assign RDD[31:0] = WayRDMatch[0] ? WayRDD[31:00] :
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WayRDMatch[1] ? WayRDD[63:32] :
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WayRDMatch[2] ? WayRDD[95:64] :
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WayRDMatch[3] ? WayRDD[127:96] :
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WayRDMatch[4] ? WayRDD[159:128] :
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WayRDMatch[5] ? WayRDD[191:160] :
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WayRDMatch[6] ? WayRDD[223:192] :
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WayRDMatch[7] ? WayRDD[255:224] : 0;
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endmodule
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@ -1,7 +1,7 @@
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/* L2 Cache Way
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* 1024 x 49 bits
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* 1024 x 47 bits
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* (1) Valid
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* (16) Tag - {A[30], A[28], A[25:0]}
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* (14) Tag - {A[30], A[28], A[25:2]}
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* (32) Data
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*/
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module L2CacheWay(
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@ -29,7 +29,6 @@ module L2CacheWay(
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wire [11:0] WRAIndex = WRA[11:2];
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/* Cache way RAM */
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wire [31:0] RDD;
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wire [31:0] TSD;
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wire [15:0] RDTag;
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wire [15:0] TSTag;
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@ -1,7 +1,7 @@
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/* L2 Prefetch Buffer
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* Prefetch tag RAM - 128 x 22s bits
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* Prefetch tag RAM - 128 x 20 bits
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* (1) Valid
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* (21) Tag - {A[30], A[28], A[25:0]}
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* (19) Tag - {A[30], A[28], A[25:2]}
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* Prefetch data RAM -
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*/
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module L2Prefetch(
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@ -9,6 +9,7 @@ module L2Prefetch(
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input CPUCLKr,
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input [27:2] RDA,
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input RDFixed7k5SEL,
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output [31:0] RDD,
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output Match,
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@ -33,7 +34,7 @@ module L2Prefetch(
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wire TSValid;
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wire RDMatch = RDValid && RDTag==RDATag;
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wire TSMatch = TSValid && TSTag==WRATag;
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PrefetchTagRAM Tag (
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PrefetchTagRAM tag (
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.clk(CLK),
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.we(WR && (WRM[3:0]==4'b1111 || TSMatch)),
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.a(WRAIndex),
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@ -42,21 +43,21 @@ module L2Prefetch(
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.dpra(RDAIndex),
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.dpo({RDValid, RDTag}));
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assign Match = RDMatch;
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assign Match = RDMatch || RDFixed7k5SEL;
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/* Data */
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PrefetchDataRAM your_instance_name (
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PrefetchDataRAM data (
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.clka(CLK),
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.ena(~CPUCLKr),
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.wea(1'b0),
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.addra(addra), // input [8 : 0] addra
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.dina(dina), // input [31 : 0] dina
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.douta(douta), // output [31 : 0] douta
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.clkb(clkb), // input clkb
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.enb(enb), // input enb
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.web(web), // input [0 : 0] web
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.addrb(addrb), // input [8 : 0] addrb
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.dinb(dinb), // input [31 : 0] dinb
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.doutb(doutb)); // output [31 : 0] doutb
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.wea(4'b0),
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.addra({RDFixed7k5SEL ? RDA[12:9] : 4'hF , RDAIndex[6:0]}),
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.dina(32'b0),
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.douta(RDD[31:0]),
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.clkb(CLK),
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.enb(1'b0),
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.web(WRM[3:0]),
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.addrb({RDFixed7k5SEL ? WRA[12:9] : 4'hF , WRAIndex[6:0]}),
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.dinb(WRD[31:0]));
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endmodule
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234
fpga/WarpLC.bld
234
fpga/WarpLC.bld
@ -5,174 +5,16 @@ Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
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ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2
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WarpLC.ngc WarpLC.ngd
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Reading NGO file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.ngc" ...
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Reading NGO file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.ngc" ...
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Loading design module "ipcore_dir/PrefetchTagRAM.ngc"...
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Loading design module "ipcore_dir/PrefetchDataRAM.ngc"...
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Loading design module "ipcore_dir/L2WayRAM.ngc"...
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Gathering constraint information from source properties...
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Done.
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Annotating constraints to design from ucf file "PLL.ucf" ...
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Resolving constraint associations...
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Checking Constraint Associations...
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<0>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<0>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<1>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<1>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<2>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<2>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<3>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<3>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<4>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<4>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<5>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<5>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<6>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<6>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<7>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<7>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<8>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<8>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<9>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<9>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<10>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<10>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<11>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<11>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<12>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<12>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<13>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<13>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<14>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<14>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<15>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<15>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<16>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<16>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<17>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<17>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<18>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<18>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<19>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<19>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<20>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<20>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<21>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<21>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<22>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<22>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<23>" SLEW = SLOW>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<23>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<24>" SLEW = SLOW>: This
|
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constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/FSB_D<24>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<25>" SLEW = SLOW>: This
|
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<25>' because those design objects do not
|
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contain or drive any instances of the correct type.
|
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|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<26>" SLEW = SLOW>: This
|
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constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/FSB_D<26>' because those design objects do not
|
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contain or drive any instances of the correct type.
|
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|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<27>" SLEW = SLOW>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/FSB_D<27>' because those design objects do not
|
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contain or drive any instances of the correct type.
|
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|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<28>" SLEW = SLOW>: This
|
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constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/FSB_D<28>' because those design objects do not
|
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contain or drive any instances of the correct type.
|
||||
|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<29>" SLEW = SLOW>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<29>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<30>" SLEW = SLOW>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<30>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<31>" SLEW = SLOW>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<31>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nAS" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/CPU_nAS' because those design objects do not
|
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@ -198,9 +40,14 @@ WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<1>" IOBDELAY = NONE>: This
|
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UniqueName: /WarpLC/EXPANDED/FSB_A<1>' because those design objects do not
|
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contain or drive any instances of the correct type.
|
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|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<28>" IOBDELAY = NONE>:
|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<26>" IOBDELAY = NONE>:
|
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This constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/FSB_A<28>' because those design objects do not
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UniqueName: /WarpLC/EXPANDED/FSB_A<26>' because those design objects do not
|
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contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<27>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_A<27>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<29>" IOBDELAY = NONE>:
|
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@ -208,51 +55,30 @@ WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<29>" IOBDELAY = NONE>:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_A<29>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<30>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_A<30>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<31>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_A<31>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:137 - Constraint <NET "FSB_A[27]" TNM_NET = FSB_A;>
|
||||
[PLL.ucf(6)]: No appropriate instances for the TNM constraint are driven by
|
||||
"FSB_A<27>".
|
||||
|
||||
WARNING:ConstraintSystem:137 - Constraint <NET "FSB_A[26]" TNM_NET = FSB_A;>
|
||||
[PLL.ucf(7)]: No appropriate instances for the TNM constraint are driven by
|
||||
"FSB_A<26>".
|
||||
|
||||
WARNING:ConstraintSystem:194 - The TNM 'FSB_A', does not directly or indirectly
|
||||
drive any flip-flops, latches and/or RAMs and is not actively used by any
|
||||
referencing constraint.
|
||||
|
||||
WARNING:ConstraintSystem:194 - The TNM 'FSB_A', does not directly or indirectly
|
||||
drive any flip-flops, latches and/or RAMs and is not actively used by any
|
||||
referencing constraint.
|
||||
|
||||
Done...
|
||||
|
||||
Checking expanded design ...
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<31>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<30>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<29>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<28>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<27>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<26>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<25>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<24>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<23>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<22>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<21>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<20>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<19>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<18>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<17>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<16>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<15>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<14>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<13>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<12>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<11>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<10>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<9>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<8>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<7>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<6>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<5>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<4>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<3>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<2>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<0>' has no driver
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
@ -263,12 +89,12 @@ Partition Implementation Status
|
||||
|
||||
NGDBUILD Design Results Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 73
|
||||
Number of warnings: 13
|
||||
|
||||
Total memory usage is 134544 kilobytes
|
||||
Total memory usage is 139060 kilobytes
|
||||
|
||||
Writing NGD file "WarpLC.ngd" ...
|
||||
Total REAL time to NGDBUILD completion: 2 sec
|
||||
Total CPU time to NGDBUILD completion: 2 sec
|
||||
Total REAL time to NGDBUILD completion: 3 sec
|
||||
Total CPU time to NGDBUILD completion: 3 sec
|
||||
|
||||
Writing NGDBUILD log file "WarpLC.bld"...
|
||||
|
||||
@ -712,3 +712,23 @@ ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6s
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="WarpLC.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_VERILOG_INSTTEMPLATE" xil_pn:name="L2Cache.tfi"/>
|
||||
<file xil_pn:fileType="FILE_VERILOG_INSTTEMPLATE" xil_pn:name="L2CacheWay.tfi"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="WarpLC.bld"/>
|
||||
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="WarpLC.cmd_log"/>
|
||||
@ -74,55 +75,47 @@
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3515295135630071778" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3515295135630071778" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:in_ck="792064813085319307" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4864019295268560826" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:in_ck="792064813085319307" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4864019295268560826" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="ipcore_dir/L2WayRAM.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/L2WayRAM.v"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PLL.v"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PrefetchDataRAM.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PrefetchDataRAM.v"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PrefetchTagRAM.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PrefetchTagRAM.v"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:in_ck="8930453670915267207" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:in_ck="8930453670915267207" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6691162141195559328" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6691162141195559328" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:in_ck="8930453670915267207" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745411629038" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:in_ck="8930453670915267207" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745411629038" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="5917552782042024336" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="5917552782042024336" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761423" xil_pn:in_ck="-7378490581248552107" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1250938673410109993" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827583" xil_pn:in_ck="6037603080330662639" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1250938673410109993" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="WarpLC.lso"/>
|
||||
<outfile xil_pn:name="WarpLC.ngc"/>
|
||||
<outfile xil_pn:name="WarpLC.ngr"/>
|
||||
@ -135,25 +128,22 @@
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761423" xil_pn:in_ck="-7789573437496007849" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704523" xil_pn:start_ts="1635761423">
|
||||
<transform xil_pn:end_ts="1635827583" xil_pn:in_ck="-7789573437496007849" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704523" xil_pn:start_ts="1635827583">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761428" xil_pn:in_ck="1514068505672127241" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2511870374322119143" xil_pn:start_ts="1635761423">
|
||||
<transform xil_pn:end_ts="1635827589" xil_pn:in_ck="1514068505672127241" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2511870374322119143" xil_pn:start_ts="1635827583">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<outfile xil_pn:name="WarpLC.bld"/>
|
||||
<outfile xil_pn:name="WarpLC.ngd"/>
|
||||
<outfile xil_pn:name="WarpLC_ngdbuild.xrpt"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761440" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-5057403149233638808" xil_pn:start_ts="1635761428">
|
||||
<transform xil_pn:end_ts="1635827613" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-5057403149233638808" xil_pn:start_ts="1635827589">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
@ -168,11 +158,12 @@
|
||||
<outfile xil_pn:name="WarpLC_usage.xml"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761446" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-5338882351546597350" xil_pn:start_ts="1635761440">
|
||||
<transform xil_pn:end_ts="1635827357" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3071725558691267845" xil_pn:start_ts="1635827347">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForProperties"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<outfile xil_pn:name="WarpLC.ncd"/>
|
||||
<outfile xil_pn:name="WarpLC.pad"/>
|
||||
<outfile xil_pn:name="WarpLC.par"/>
|
||||
@ -193,23 +184,23 @@
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761449" xil_pn:in_ck="5584679923051828224" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-4489077157552092322" xil_pn:start_ts="1635761446">
|
||||
<transform xil_pn:end_ts="1635827362" xil_pn:in_ck="5584679923051828224" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-4489077157552092322" xil_pn:start_ts="1635827357">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="WarpLC.twr"/>
|
||||
<outfile xil_pn:name="WarpLC.twx"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635705655" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791352" xil_pn:start_ts="1635705650">
|
||||
<status xil_pn:value="AbortedRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<transform xil_pn:end_ts="1635827618" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791352" xil_pn:start_ts="1635827613">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<outfile xil_pn:name="WarpLC_preroute.twr"/>
|
||||
<outfile xil_pn:name="WarpLC_preroute.twx"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635705810" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1635705810">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
214
fpga/WarpLC.pad
214
fpga/WarpLC.pad
@ -1,7 +1,7 @@
|
||||
Release 14.7 - par P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Mon Nov 01 06:10:44 2021
|
||||
Tue Nov 02 00:29:15 2021
|
||||
|
||||
|
||||
# NOTE: This file is designed to be imported into a spreadsheet program
|
||||
@ -22,137 +22,137 @@ Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|D
|
||||
A1|||GND||||||||||||
|
||||
A2||IOBS|IO_L52N_M3A9_3|UNUSED||3|||||||||
|
||||
A3||IOBS|IO_L83N_VREF_3|UNUSED||3|||||||||
|
||||
A4||IOBS|IO_L1N_VREF_0|UNUSED||0|||||||||
|
||||
A5||IOBS|IO_L2N_0|UNUSED||0|||||||||
|
||||
A6||IOBS|IO_L4N_0|UNUSED||0|||||||||
|
||||
A7||IOBS|IO_L6N_0|UNUSED||0|||||||||
|
||||
A8||IOBS|IO_L33N_0|UNUSED||0|||||||||
|
||||
A9||IOBS|IO_L34N_GCLK18_0|UNUSED||0|||||||||
|
||||
A10||IOBS|IO_L35N_GCLK16_0|UNUSED||0|||||||||
|
||||
A11||IOBS|IO_L39N_0|UNUSED||0|||||||||
|
||||
A12||IOBS|IO_L62N_VREF_0|UNUSED||0|||||||||
|
||||
A13||IOBS|IO_L63N_SCP6_0|UNUSED||0|||||||||
|
||||
A14||IOBS|IO_L65N_SCP2_0|UNUSED||0|||||||||
|
||||
A4|RAMCLK0|IOB|IO_L1N_VREF_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
|
||||
A5|FSB_D<0>|IOB|IO_L2N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A6|FSB_D<4>|IOB|IO_L4N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A7|FSB_D<8>|IOB|IO_L6N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A8|FSB_D<12>|IOB|IO_L33N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A9|FSB_D<14>|IOB|IO_L34N_GCLK18_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A10|FSB_D<16>|IOB|IO_L35N_GCLK16_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A11|FSB_D<24>|IOB|IO_L39N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A12|FSB_D<28>|IOB|IO_L62N_VREF_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A13|CPU_nSTERM|IOB|IO_L63N_SCP6_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|NO|NONE|
|
||||
A14|RAMCLK1|IOB|IO_L65N_SCP2_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
|
||||
A15|||TMS||||||||||||
|
||||
A16|||GND||||||||||||
|
||||
B1||IOBS|IO_L50N_M3BA2_3|UNUSED||3|||||||||
|
||||
B2||IOBM|IO_L52P_M3A8_3|UNUSED||3|||||||||
|
||||
B3||IOBM|IO_L83P_3|UNUSED||3|||||||||
|
||||
B4|||VCCO_0|||0|||||any******||||
|
||||
B5||IOBM|IO_L2P_0|UNUSED||0|||||||||
|
||||
B6||IOBM|IO_L4P_0|UNUSED||0|||||||||
|
||||
B4|||VCCO_0|||0|||||3.30||||
|
||||
B5|FPUCLK|IOB|IO_L2P_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
|
||||
B6|FSB_D<3>|IOB|IO_L4P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
B7|||GND||||||||||||
|
||||
B8||IOBM|IO_L33P_0|UNUSED||0|||||||||
|
||||
B9|||VCCO_0|||0|||||any******||||
|
||||
B10||IOBM|IO_L35P_GCLK17_0|UNUSED||0|||||||||
|
||||
B8|FSB_D<11>|IOB|IO_L33P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
B9|||VCCO_0|||0|||||3.30||||
|
||||
B10|FSB_D<19>|IOB|IO_L35P_GCLK17_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
B11|||GND||||||||||||
|
||||
B12||IOBM|IO_L62P_0|UNUSED||0|||||||||
|
||||
B13|||VCCO_0|||0|||||any******||||
|
||||
B14||IOBM|IO_L65P_SCP3_0|UNUSED||0|||||||||
|
||||
B15||IOBM|IO_L29P_A23_M1A13_1|UNUSED||1|||||||||
|
||||
B16||IOBS|IO_L29N_A22_M1A14_1|UNUSED||1|||||||||
|
||||
B12|FSB_D<27>|IOB|IO_L62P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
B13|||VCCO_0|||0|||||3.30||||
|
||||
B14|FSB_A<2>|IOB|IO_L65P_SCP3_0|INPUT|LVCMOS33|0||||NONE||UNLOCATED|NO|NONE|
|
||||
B15|FSB_A<6>|IOB|IO_L29P_A23_M1A13_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
B16|FSB_A<7>|IOB|IO_L29N_A22_M1A14_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
C1||IOBM|IO_L50P_M3WE_3|UNUSED||3|||||||||
|
||||
C2||IOBS|IO_L48N_M3BA1_3|UNUSED||3|||||||||
|
||||
C3||IOBM|IO_L48P_M3BA0_3|UNUSED||3|||||||||
|
||||
C4||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0|||||||||
|
||||
C5||IOBS|IO_L3N_0|UNUSED||0|||||||||
|
||||
C6||IOBS|IO_L7N_0|UNUSED||0|||||||||
|
||||
C7||IOBM|IO_L6P_0|UNUSED||0|||||||||
|
||||
C8||IOBS|IO_L38N_VREF_0|UNUSED||0|||||||||
|
||||
C9||IOBM|IO_L34P_GCLK19_0|UNUSED||0|||||||||
|
||||
C10||IOBS|IO_L37N_GCLK12_0|UNUSED||0|||||||||
|
||||
C11||IOBM|IO_L39P_0|UNUSED||0|||||||||
|
||||
C4|CLKFB_OUT|IOB|IO_L1P_HSWAPEN_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
|
||||
C5|FSB_D<2>|IOB|IO_L3N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C6|FSB_D<10>|IOB|IO_L7N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C7|FSB_D<7>|IOB|IO_L6P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C8|FSB_D<18>|IOB|IO_L38N_VREF_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C9|FSB_D<13>|IOB|IO_L34P_GCLK19_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C10|FSB_D<20>|IOB|IO_L37N_GCLK12_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C11|FSB_D<23>|IOB|IO_L39P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C12|||TDI||||||||||||
|
||||
C13||IOBM|IO_L63P_SCP7_0|UNUSED||0|||||||||
|
||||
C13|FSB_D<21>|IOB|IO_L63P_SCP7_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C14|||TCK||||||||||||
|
||||
C15||IOBM|IO_L33P_A15_M1A10_1|UNUSED||1|||||||||
|
||||
C16||IOBS|IO_L33N_A14_M1A4_1|UNUSED||1|||||||||
|
||||
C15|FSB_A<14>|IOB|IO_L33P_A15_M1A10_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
C16|FSB_A<15>|IOB|IO_L33N_A14_M1A4_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
D1||IOBS|IO_L49N_M3A2_3|UNUSED||3|||||||||
|
||||
D2|||VCCO_3|||3|||||3.30||||
|
||||
D2|||VCCO_3|||3|||||any******||||
|
||||
D3||IOBM|IO_L49P_M3A7_3|UNUSED||3|||||||||
|
||||
D4|||GND||||||||||||
|
||||
D5||IOBM|IO_L3P_0|UNUSED||0|||||||||
|
||||
D6||IOBM|IO_L7P_0|UNUSED||0|||||||||
|
||||
D7|||VCCO_0|||0|||||any******||||
|
||||
D8||IOBM|IO_L38P_0|UNUSED||0|||||||||
|
||||
D9||IOBS|IO_L40N_0|UNUSED||0|||||||||
|
||||
D10|||VCCO_0|||0|||||any******||||
|
||||
D11||IOBM|IO_L66P_SCP1_0|UNUSED||0|||||||||
|
||||
D12||IOBS|IO_L66N_SCP0_0|UNUSED||0|||||||||
|
||||
D5|FSB_D<1>|IOB|IO_L3P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
D6|FSB_D<9>|IOB|IO_L7P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
D7|||VCCO_0|||0|||||3.30||||
|
||||
D8|FSB_D<25>|IOB|IO_L38P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
D9|FSB_D<22>|IOB|IO_L40N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
D10|||VCCO_0|||0|||||3.30||||
|
||||
D11|FSB_D<29>|IOB|IO_L66P_SCP1_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
D12|FSB_A<3>|IOB|IO_L66N_SCP0_0|INPUT|LVCMOS33|0||||NONE||UNLOCATED|NO|NONE|
|
||||
D13|||GND||||||||||||
|
||||
D14||IOBM|IO_L31P_A19_M1CKE_1|UNUSED||1|||||||||
|
||||
D14|FSB_A<10>|IOB|IO_L31P_A19_M1CKE_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
D15|||VCCO_1|||1|||||any******||||
|
||||
D16||IOBS|IO_L31N_A18_M1A12_1|UNUSED||1|||||||||
|
||||
E1|FPUCLK|IOB|IO_L46N_M3CLKN_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
E2|CPUCLK|IOB|IO_L46P_M3CLK_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
D16|FSB_A<11>|IOB|IO_L31N_A18_M1A12_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
E1||IOBS|IO_L46N_M3CLKN_3|UNUSED||3|||||||||
|
||||
E2||IOBM|IO_L46P_M3CLK_3|UNUSED||3|||||||||
|
||||
E3||IOBS|IO_L54N_M3A11_3|UNUSED||3|||||||||
|
||||
E4||IOBM|IO_L54P_M3RESET_3|UNUSED||3|||||||||
|
||||
E5|||VCCAUX||||||||2.5||||
|
||||
E6||IOBS|IO_L5N_0|UNUSED||0|||||||||
|
||||
E7||IOBM|IO_L36P_GCLK15_0|UNUSED||0|||||||||
|
||||
E8||IOBS|IO_L36N_GCLK14_0|UNUSED||0|||||||||
|
||||
E6|FSB_D<6>|IOB|IO_L5N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
E7|FSB_D<17>|IOB|IO_L36P_GCLK15_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
E8|FSB_D<26>|IOB|IO_L36N_GCLK14_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
E9|||GND||||||||||||
|
||||
E10||IOBM|IO_L37P_GCLK13_0|UNUSED||0|||||||||
|
||||
E11||IOBS|IO_L64N_SCP4_0|UNUSED||0|||||||||
|
||||
E12||IOBS|IO_L1N_A24_VREF_1|UNUSED||1|||||||||
|
||||
E13||IOBM|IO_L1P_A25_1|UNUSED||1|||||||||
|
||||
E10|FSB_D<15>|IOB|IO_L37P_GCLK13_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
E11|FSB_D<30>|IOB|IO_L64N_SCP4_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
E12|FSB_A<5>|IOB|IO_L1N_A24_VREF_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
E13|FSB_A<4>|IOB|IO_L1P_A25_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
E14|||TDO||||||||||||
|
||||
E15||IOBM|IO_L34P_A13_M1WE_1|UNUSED||1|||||||||
|
||||
E16||IOBS|IO_L34N_A12_M1BA2_1|UNUSED||1|||||||||
|
||||
F1|FSB_A<25>|IOB|IO_L41N_GCLK26_M3DQ5_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
F2|FSB_A<24>|IOB|IO_L41P_GCLK27_M3DQ4_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
E15|FSB_A<16>|IOB|IO_L34P_A13_M1WE_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
E16|FSB_A<17>|IOB|IO_L34N_A12_M1BA2_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
F1||IOBS|IO_L41N_GCLK26_M3DQ5_3|UNUSED||3|||||||||
|
||||
F2||IOBM|IO_L41P_GCLK27_M3DQ4_3|UNUSED||3|||||||||
|
||||
F3||IOBS|IO_L53N_M3A12_3|UNUSED||3|||||||||
|
||||
F4||IOBM|IO_L53P_M3CKE_3|UNUSED||3|||||||||
|
||||
F5||IOBS|IO_L55N_M3A14_3|UNUSED||3|||||||||
|
||||
F6||IOBM|IO_L55P_M3A13_3|UNUSED||3|||||||||
|
||||
F7||IOBM|IO_L5P_0|UNUSED||0|||||||||
|
||||
F7|FSB_D<5>|IOB|IO_L5P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
F8|||VCCAUX||||||||2.5||||
|
||||
F9||IOBM|IO_L40P_0|UNUSED||0|||||||||
|
||||
F10||IOBM|IO_L64P_SCP5_0|UNUSED||0|||||||||
|
||||
F9|CPUCLK|IOB|IO_L40P_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
|
||||
F10|FSB_D<31>|IOB|IO_L64P_SCP5_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
F11|||VCCAUX||||||||2.5||||
|
||||
F12||IOBM|IO_L30P_A21_M1RESET_1|UNUSED||1|||||||||
|
||||
F13||IOBM|IO_L32P_A17_M1A8_1|UNUSED||1|||||||||
|
||||
F14||IOBS|IO_L32N_A16_M1A9_1|UNUSED||1|||||||||
|
||||
F15||IOBM|IO_L35P_A11_M1A7_1|UNUSED||1|||||||||
|
||||
F16||IOBS|IO_L35N_A10_M1A2_1|UNUSED||1|||||||||
|
||||
G1|FSB_A<23>|IOB|IO_L40N_M3DQ7_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
F12|FSB_A<8>|IOB|IO_L30P_A21_M1RESET_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
F13|FSB_A<12>|IOB|IO_L32P_A17_M1A8_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
F14|FSB_A<13>|IOB|IO_L32N_A16_M1A9_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
F15|FSB_A<18>|IOB|IO_L35P_A11_M1A7_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
F16|FSB_A<19>|IOB|IO_L35N_A10_M1A2_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
G1||IOBS|IO_L40N_M3DQ7_3|UNUSED||3|||||||||
|
||||
G2|||GND||||||||||||
|
||||
G3|FSB_A<22>|IOB|IO_L40P_M3DQ6_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
G4|||VCCO_3|||3|||||3.30||||
|
||||
G3||IOBM|IO_L40P_M3DQ6_3|UNUSED||3|||||||||
|
||||
G4|||VCCO_3|||3|||||any******||||
|
||||
G5||IOBS|IO_L51N_M3A4_3|UNUSED||3|||||||||
|
||||
G6||IOBM|IO_L51P_M3A10_3|UNUSED||3|||||||||
|
||||
G7|||VCCINT||||||||1.2||||
|
||||
G8|||GND||||||||||||
|
||||
G9|||VCCINT||||||||1.2||||
|
||||
G10|||VCCAUX||||||||2.5||||
|
||||
G11||IOBS|IO_L30N_A20_M1A11_1|UNUSED||1|||||||||
|
||||
G12||IOBM|IO_L38P_A5_M1CLK_1|UNUSED||1|||||||||
|
||||
G11|FSB_A<9>|IOB|IO_L30N_A20_M1A11_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
G12|FSB_A<24>|IOB|IO_L38P_A5_M1CLK_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
G13|||VCCO_1|||1|||||any******||||
|
||||
G14||IOBM|IO_L36P_A9_M1BA0_1|UNUSED||1|||||||||
|
||||
G14|FSB_A<20>|IOB|IO_L36P_A9_M1BA0_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
G15|||GND||||||||||||
|
||||
G16||IOBS|IO_L36N_A8_M1BA1_1|UNUSED||1|||||||||
|
||||
H1|FSB_A<21>|IOB|IO_L39N_M3LDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H2|FSB_A<20>|IOB|IO_L39P_M3LDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H3|RAMCLK0|IOB|IO_L44N_GCLK20_M3A6_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
G16|FSB_A<21>|IOB|IO_L36N_A8_M1BA1_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
H1||IOBS|IO_L39N_M3LDQSN_3|UNUSED||3|||||||||
|
||||
H2||IOBM|IO_L39P_M3LDQS_3|UNUSED||3|||||||||
|
||||
H3||IOBS|IO_L44N_GCLK20_M3A6_3|UNUSED||3|||||||||
|
||||
H4|CLKFB_IN|IOB|IO_L44P_GCLK21_M3A5_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H5|CPU_nSTERM|IOB|IO_L43N_GCLK22_IRDY2_M3CASN_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|NO|NONE|
|
||||
H5||IOBS|IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED||3|||||||||
|
||||
H6|||VCCAUX||||||||2.5||||
|
||||
H7|||GND||||||||||||
|
||||
H8|||VCCINT||||||||1.2||||
|
||||
H9|||GND||||||||||||
|
||||
H10|||VCCINT||||||||1.2||||
|
||||
H11||IOBS|IO_L38N_A4_M1CLKN_1|UNUSED||1|||||||||
|
||||
H11|FSB_A<25>|IOB|IO_L38N_A4_M1CLKN_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
H12|||GND||||||||||||
|
||||
H13||IOBM|IO_L39P_M1A3_1|UNUSED||1|||||||||
|
||||
H14||IOBS|IO_L39N_M1ODT_1|UNUSED||1|||||||||
|
||||
H15||IOBM|IO_L37P_A7_M1A0_1|UNUSED||1|||||||||
|
||||
H16||IOBS|IO_L37N_A6_M1A1_1|UNUSED||1|||||||||
|
||||
J1|FSB_A<19>|IOB|IO_L38N_M3DQ3_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J2|||VCCO_3|||3|||||3.30||||
|
||||
J3|FSB_A<18>|IOB|IO_L38P_M3DQ2_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H13|FSB_A<28>|IOB|IO_L39P_M1A3_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
H14|FSB_A<30>|IOB|IO_L39N_M1ODT_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
H15|FSB_A<22>|IOB|IO_L37P_A7_M1A0_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
H16|FSB_A<23>|IOB|IO_L37N_A6_M1A1_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
J1||IOBS|IO_L38N_M3DQ3_3|UNUSED||3|||||||||
|
||||
J2|||VCCO_3|||3|||||any******||||
|
||||
J3||IOBM|IO_L38P_M3DQ2_3|UNUSED||3|||||||||
|
||||
J4|CLKIN|IOB|IO_L42N_GCLK24_M3LDM_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J5|||GND||||||||||||
|
||||
J6|FSB_A<27>|IOB|IO_L43P_GCLK23_M3RASN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J6||IOBM|IO_L43P_GCLK23_M3RASN_3|UNUSED||3|||||||||
|
||||
J7|||VCCINT||||||||1.2||||
|
||||
J8|||GND||||||||||||
|
||||
J9|||VCCINT||||||||1.2||||
|
||||
@ -163,10 +163,10 @@ J13||IOBM|IO_L41P_GCLK9_IRDY1_M1RASN_1|UNUSED||1|||||||||
|
||||
J14||IOBM|IO_L43P_GCLK5_M1DQ4_1|UNUSED||1|||||||||
|
||||
J15|||VCCO_1|||1|||||any******||||
|
||||
J16||IOBS|IO_L43N_GCLK4_M1DQ5_1|UNUSED||1|||||||||
|
||||
K1|FSB_A<17>|IOB|IO_L37N_M3DQ1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K2|FSB_A<16>|IOB|IO_L37P_M3DQ0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K3|FSB_A<26>|IOB|IO_L42P_GCLK25_TRDY2_M3UDM_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K4|||VCCO_3|||3|||||3.30||||
|
||||
K1||IOBS|IO_L37N_M3DQ1_3|UNUSED||3|||||||||
|
||||
K2||IOBM|IO_L37P_M3DQ0_3|UNUSED||3|||||||||
|
||||
K3||IOBM|IO_L42P_GCLK25_TRDY2_M3UDM_3|UNUSED||3|||||||||
|
||||
K4|||VCCO_3|||3|||||any******||||
|
||||
K5||IOBM|IO_L47P_M3A0_3|UNUSED||3|||||||||
|
||||
K6||IOBS|IO_L47N_M3A1_3|UNUSED||3|||||||||
|
||||
K7|||GND||||||||||||
|
||||
@ -179,11 +179,11 @@ K13|||VCCO_1|||1|||||any******||||
|
||||
K14||IOBS|IO_L41N_GCLK8_M1CASN_1|UNUSED||1|||||||||
|
||||
K15||IOBM|IO_L44P_A3_M1DQ6_1|UNUSED||1|||||||||
|
||||
K16||IOBS|IO_L44N_A2_M1DQ7_1|UNUSED||1|||||||||
|
||||
L1|FSB_A<15>|IOB|IO_L36N_M3DQ9_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L1||IOBS|IO_L36N_M3DQ9_3|UNUSED||3|||||||||
|
||||
L2|||GND||||||||||||
|
||||
L3|FSB_A<14>|IOB|IO_L36P_M3DQ8_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L4|CLKFB_OUT|IOB|IO_L45P_M3A3_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
L5|RAMCLK1|IOB|IO_L45N_M3ODT_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
L3||IOBM|IO_L36P_M3DQ8_3|UNUSED||3|||||||||
|
||||
L4||IOBM|IO_L45P_M3A3_3|UNUSED||3|||||||||
|
||||
L5||IOBS|IO_L45N_M3ODT_3|UNUSED||3|||||||||
|
||||
L6|||VCCAUX||||||||2.5||||
|
||||
L7||IOBS|IO_L62N_D6_2|UNUSED||2|||||||||
|
||||
L8||IOBM|IO_L62P_D5_2|UNUSED||2|||||||||
|
||||
@ -195,11 +195,11 @@ L13||IOBS|IO_L53N_VREF_1|UNUSED||1|||||||||
|
||||
L14||IOBM|IO_L47P_FWE_B_M1DQ0_1|UNUSED||1|||||||||
|
||||
L15|||GND||||||||||||
|
||||
L16||IOBS|IO_L47N_LDC_M1DQ1_1|UNUSED||1|||||||||
|
||||
M1|FSB_A<13>|IOB|IO_L35N_M3DQ11_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M2|FSB_A<12>|IOB|IO_L35P_M3DQ10_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M3|FSB_A<3>|IOB|IO_L1N_VREF_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M4|FSB_A<2>|IOB|IO_L1P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M5|FSB_A<4>|IOB|IO_L2P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M1||IOBS|IO_L35N_M3DQ11_3|UNUSED||3|||||||||
|
||||
M2||IOBM|IO_L35P_M3DQ10_3|UNUSED||3|||||||||
|
||||
M3||IOBS|IO_L1N_VREF_3|UNUSED||3|||||||||
|
||||
M4||IOBM|IO_L1P_3|UNUSED||3|||||||||
|
||||
M5||IOBM|IO_L2P_3|UNUSED||3|||||||||
|
||||
M6||IOBM|IO_L64P_D8_2|UNUSED||2|||||||||
|
||||
M7||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2|||||||||
|
||||
M8|||GND||||||||||||
|
||||
@ -211,10 +211,10 @@ M13||IOBM|IO_L74P_AWAKE_1|UNUSED||1|||||||||
|
||||
M14||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1|||||||||
|
||||
M15||IOBM|IO_L46P_FCS_B_M1DQ2_1|UNUSED||1|||||||||
|
||||
M16||IOBS|IO_L46N_FOE_B_M1DQ3_1|UNUSED||1|||||||||
|
||||
N1|FSB_A<11>|IOB|IO_L34N_M3UDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N2|||VCCO_3|||3|||||3.30||||
|
||||
N3|FSB_A<10>|IOB|IO_L34P_M3UDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N4|FSB_A<5>|IOB|IO_L2N_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N1||IOBS|IO_L34N_M3UDQSN_3|UNUSED||3|||||||||
|
||||
N2|||VCCO_3|||3|||||any******||||
|
||||
N3||IOBM|IO_L34P_M3UDQS_3|UNUSED||3|||||||||
|
||||
N4||IOBS|IO_L2N_3|UNUSED||3|||||||||
|
||||
N5||IOBM|IO_L49P_D3_2|UNUSED||2|||||||||
|
||||
N6||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
|
||||
N7|||VCCO_2|||2|||||any******||||
|
||||
@ -227,8 +227,8 @@ N13|||GND||||||||||||
|
||||
N14||IOBM|IO_L45P_A1_M1LDQS_1|UNUSED||1|||||||||
|
||||
N15|||VCCO_1|||1|||||any******||||
|
||||
N16||IOBS|IO_L45N_A0_M1LDQSN_1|UNUSED||1|||||||||
|
||||
P1|FSB_A<9>|IOB|IO_L33N_M3DQ13_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
P2|FSB_A<8>|IOB|IO_L33P_M3DQ12_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
P1||IOBS|IO_L33N_M3DQ13_3|UNUSED||3|||||||||
|
||||
P2||IOBM|IO_L33P_M3DQ12_3|UNUSED||3|||||||||
|
||||
P3|||GND||||||||||||
|
||||
P4||IOBM|IO_L63P_2|UNUSED||2|||||||||
|
||||
P5||IOBS|IO_L49N_D4_2|UNUSED||2|||||||||
|
||||
@ -243,8 +243,8 @@ P13|||DONE_2||||||||||||
|
||||
P14|||SUSPEND||||||||||||
|
||||
P15||IOBM|IO_L48P_HDC_M1DQ8_1|UNUSED||1|||||||||
|
||||
P16||IOBS|IO_L48N_M1DQ9_1|UNUSED||1|||||||||
|
||||
R1|FSB_A<7>|IOB|IO_L32N_M3DQ15_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
R2|FSB_A<6>|IOB|IO_L32P_M3DQ14_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
R1||IOBS|IO_L32N_M3DQ15_3|UNUSED||3|||||||||
|
||||
R2||IOBM|IO_L32P_M3DQ14_3|UNUSED||3|||||||||
|
||||
R3||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
|
||||
R4|||VCCO_2|||2|||||any******||||
|
||||
R5||IOBM|IO_L48P_D7_2|UNUSED||2|||||||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
Release 14.7 par P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
ZANEPC:: Mon Nov 01 06:10:41 2021
|
||||
DOG-PC:: Tue Nov 02 00:29:08 2021
|
||||
|
||||
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
|
||||
@ -33,11 +33,11 @@ Slice Logic Utilization:
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 89 out of 5,720 1%
|
||||
Number used as logic: 9 out of 5,720 1%
|
||||
Number using O6 output only: 7
|
||||
Number using O5 output only: 1
|
||||
Number using O5 and O6: 1
|
||||
Number of Slice LUTs: 294 out of 5,720 5%
|
||||
Number used as logic: 214 out of 5,720 3%
|
||||
Number using O6 output only: 183
|
||||
Number using O5 output only: 5
|
||||
Number using O5 and O6: 26
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 80 out of 1,440 5%
|
||||
Number used as Dual Port RAM: 80
|
||||
@ -48,12 +48,12 @@ Slice Logic Utilization:
|
||||
Number used as Shift Register: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 23 out of 1,430 1%
|
||||
Number of MUXCYs used: 8 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 89
|
||||
Number with an unused Flip Flop: 88 out of 89 98%
|
||||
Number with an unused LUT: 0 out of 89 0%
|
||||
Number of fully used LUT-FF pairs: 1 out of 89 1%
|
||||
Number of occupied Slices: 113 out of 1,430 7%
|
||||
Number of MUXCYs used: 72 out of 2,860 2%
|
||||
Number of LUT Flip Flop pairs used: 295
|
||||
Number with an unused Flip Flop: 294 out of 295 99%
|
||||
Number with an unused LUT: 1 out of 295 1%
|
||||
Number of fully used LUT-FF pairs: 0 out of 295 0%
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 0 out of 11,440 0%
|
||||
|
||||
@ -64,11 +64,11 @@ Slice Logic Distribution:
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 34 out of 186 18%
|
||||
Number of bonded IOBs: 66 out of 186 35%
|
||||
IOB Flip Flops: 5
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 0 out of 32 0%
|
||||
Number of RAMB16BWERs: 28 out of 32 87%
|
||||
Number of RAMB8BWERs: 0 out of 64 0%
|
||||
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2s: 1
|
||||
@ -106,31 +106,31 @@ PAR will use up to 4 processors
|
||||
Starting Multi-threaded Router
|
||||
|
||||
|
||||
Phase 1 : 672 unrouted; REAL time: 2 secs
|
||||
Phase 1 : 5140 unrouted; REAL time: 3 secs
|
||||
|
||||
Phase 2 : 328 unrouted; REAL time: 2 secs
|
||||
Phase 2 : 1769 unrouted; REAL time: 3 secs
|
||||
|
||||
Phase 3 : 155 unrouted; REAL time: 2 secs
|
||||
Phase 3 : 1550 unrouted; REAL time: 4 secs
|
||||
|
||||
Phase 4 : 155 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
|
||||
Phase 4 : 1550 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs
|
||||
|
||||
Updating file: WarpLC.ncd with current fully routed design.
|
||||
|
||||
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
|
||||
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
|
||||
|
||||
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
|
||||
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
|
||||
|
||||
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
|
||||
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
|
||||
|
||||
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
|
||||
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
|
||||
|
||||
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
|
||||
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
|
||||
|
||||
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
|
||||
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
|
||||
|
||||
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
|
||||
Total REAL time to Router completion: 3 secs
|
||||
Total CPU time to Router completion (all processors): 3 secs
|
||||
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
|
||||
Total REAL time to Router completion: 6 secs
|
||||
Total CPU time to Router completion (all processors): 7 secs
|
||||
|
||||
Generating "PAR" statistics.
|
||||
|
||||
@ -141,10 +141,10 @@ Generating Clock Report
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| FSBCLK | BUFGMUX_X3Y13| No | 29 | 0.585 | 2.022 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
|cg/pll/clkfb_bufg_ou | | | | | |
|
||||
| t | BUFGMUX_X2Y3| No | 2 | 0.062 | 2.072 |
|
||||
| t | BUFGMUX_X2Y3| No | 2 | 0.062 | 2.139 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| FSBCLK | BUFGMUX_X3Y13| No | 37 | 0.652 | 2.088 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
|
||||
* Net Skew is the difference between the minimum and maximum routing
|
||||
@ -163,8 +163,8 @@ Generating Pad Report.
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
Total REAL time to PAR completion: 3 secs
|
||||
Total CPU time to PAR completion (all processors): 3 secs
|
||||
Total REAL time to PAR completion: 7 secs
|
||||
Total CPU time to PAR completion (all processors): 8 secs
|
||||
|
||||
Peak Memory Usage: 258 MB
|
||||
|
||||
|
||||
556
fpga/WarpLC.pcf
556
fpga/WarpLC.pcf
@ -1,8 +1,48 @@
|
||||
//! **************************************************************************
|
||||
// Written by: Map P.20131013 on Mon Nov 01 06:10:38 2021
|
||||
// Written by: Map P.20131013 on Tue Nov 02 00:33:32 2021
|
||||
//! **************************************************************************
|
||||
|
||||
SCHEMATIC START;
|
||||
PIN
|
||||
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>
|
||||
= BEL
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
|
||||
PINNAME CLKA;
|
||||
PIN
|
||||
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>
|
||||
= BEL
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
|
||||
PINNAME CLKB;
|
||||
PIN
|
||||
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>
|
||||
= BEL
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
|
||||
PINNAME CLKA;
|
||||
PIN
|
||||
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>
|
||||
= BEL
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
|
||||
PINNAME CLKB;
|
||||
PIN
|
||||
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>
|
||||
= BEL
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
|
||||
PINNAME CLKA;
|
||||
PIN
|
||||
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>
|
||||
= BEL
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
|
||||
PINNAME CLKB;
|
||||
PIN
|
||||
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>
|
||||
= BEL
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
|
||||
PINNAME CLKA;
|
||||
PIN
|
||||
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>
|
||||
= BEL
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
|
||||
PINNAME CLKB;
|
||||
PIN cg/CPUCLK_inst_pins<1> = BEL "cg/CPUCLK_inst" PINNAME CK0;
|
||||
PIN cg/CPUCLK_inst_pins<2> = BEL "cg/CPUCLK_inst" PINNAME CK1;
|
||||
PIN cg/FPUCLK_inst_pins<1> = BEL "cg/FPUCLK_inst" PINNAME CK0;
|
||||
@ -11,166 +51,182 @@ PIN cg/RAMCLK0_inst_pins<1> = BEL "cg/RAMCLK0_inst" PINNAME CK0;
|
||||
PIN cg/RAMCLK0_inst_pins<2> = BEL "cg/RAMCLK0_inst" PINNAME CK1;
|
||||
PIN cg/RAMCLK1_inst_pins<1> = BEL "cg/RAMCLK1_inst" PINNAME CK0;
|
||||
PIN cg/RAMCLK1_inst_pins<2> = BEL "cg/RAMCLK1_inst" PINNAME CK1;
|
||||
TIMEGRP cg_pll_clkout0 = BEL "cg/pll/clkout1_buf" BEL "cg/CPUCLKr" BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.HIGH"
|
||||
TIMEGRP cg_pll_clkout0 = BEL "cg/CPUCLKr" BEL "cg/pll/clkout1_buf" PIN
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>"
|
||||
PIN
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>"
|
||||
PIN
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>"
|
||||
PIN
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>"
|
||||
PIN
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>"
|
||||
PIN
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>"
|
||||
PIN
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>"
|
||||
PIN
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.HIGH"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.LOW"
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.LOW"
|
||||
PIN "cg/CPUCLK_inst_pins<1>" PIN "cg/CPUCLK_inst_pins<2>" PIN
|
||||
"cg/CPUCLK_inst_pins<1>" PIN "cg/CPUCLK_inst_pins<2>" PIN
|
||||
"cg/FPUCLK_inst_pins<1>" PIN "cg/FPUCLK_inst_pins<2>" PIN
|
||||
@ -184,167 +240,183 @@ PIN cg/pll/clkfbout_oddr_pins<2> = BEL "cg/pll/clkfbout_oddr" PINNAME CK1;
|
||||
TIMEGRP cg_pll_clkfbout = BEL "cg/pll/clkfbout_bufg" PIN
|
||||
"cg/pll/clkfbout_oddr_pins<1>" PIN "cg/pll/clkfbout_oddr_pins<2>" PIN
|
||||
"cg/pll/clkfbout_oddr_pins<1>" PIN "cg/pll/clkfbout_oddr_pins<2>";
|
||||
TIMEGRP FSB_A = BEL "FSB_D<31>" BEL "FSB_D<30>" BEL "FSB_D<29>" BEL
|
||||
"FSB_D<28>" BEL "FSB_D<27>" BEL "FSB_D<26>" BEL "FSB_D<25>" BEL
|
||||
"FSB_D<24>" BEL "FSB_D<23>" BEL "FSB_D<22>" BEL "FSB_D<21>" BEL
|
||||
"FSB_D<20>" BEL "FSB_D<19>" BEL "FSB_D<18>" BEL "FSB_D<17>" BEL
|
||||
"FSB_D<16>" BEL "FSB_D<15>" BEL "FSB_D<14>" BEL "FSB_D<13>" BEL
|
||||
"FSB_D<12>" BEL "FSB_D<11>" BEL "FSB_D<10>" BEL "FSB_D<9>" BEL
|
||||
"FSB_D<8>" BEL "FSB_D<7>" BEL "FSB_D<6>" BEL "FSB_D<5>" BEL "FSB_D<4>"
|
||||
BEL "FSB_D<3>" BEL "FSB_D<2>" BEL "FSB_D<1>" BEL "FSB_D<0>" BEL
|
||||
"CPU_nSTERM" BEL
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
|
||||
BEL
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
|
||||
BEL
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
|
||||
BEL
|
||||
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.LOW"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.HIGH"
|
||||
BEL
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.LOW";
|
||||
TIMEGRP CPU_nSTERM = BEL "CPU_nSTERM";
|
||||
TIMEGRP FSB_A = BEL "CPU_nSTERM" BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.LOW"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.HIGH"
|
||||
BEL
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.LOW";
|
||||
PIN SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0_pins<0> = BEL
|
||||
"SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0" PINNAME DIVCLK;
|
||||
PIN cg/pll/pll_base_inst/PLL_ADV_pins<2> = BEL "cg/pll/pll_base_inst/PLL_ADV"
|
||||
|
||||
@ -1,6 +1,11 @@
|
||||
verilog work "ipcore_dir/PLL.v"
|
||||
verilog work "ipcore_dir/L2WayRAM.v"
|
||||
verilog work "L2CacheWay.v"
|
||||
verilog work "ipcore_dir/PrefetchTagRAM.v"
|
||||
verilog work "ipcore_dir/PrefetchDataRAM.v"
|
||||
verilog work "SizeDecode.v"
|
||||
verilog work "Prefetch.v"
|
||||
verilog work "L2Cache.v"
|
||||
verilog work "CS.v"
|
||||
verilog work "ClkGen.v"
|
||||
verilog work "WarpLC.v"
|
||||
|
||||
393
fpga/WarpLC.syr
393
fpga/WarpLC.syr
@ -108,25 +108,37 @@ Cores Search Directories : {"ipcore_dir" }
|
||||
=========================================================================
|
||||
* HDL Parsing *
|
||||
=========================================================================
|
||||
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" into library work
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" into library work
|
||||
Parsing module <PLL>.
|
||||
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" into library work
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\L2WayRAM.v" into library work
|
||||
Parsing module <L2WayRAM>.
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" into library work
|
||||
Parsing module <L2CacheWay>.
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" into library work
|
||||
Parsing module <PrefetchTagRAM>.
|
||||
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\SizeDecode.v" into library work
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" into library work
|
||||
Parsing module <PrefetchDataRAM>.
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\SizeDecode.v" into library work
|
||||
Parsing module <SizeDecode>.
|
||||
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" into library work
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v" into library work
|
||||
Parsing module <L2Prefetch>.
|
||||
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ClkGen.v" into library work
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2Cache.v" into library work
|
||||
Parsing module <L2Cache>.
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\CS.v" into library work
|
||||
Parsing module <CS>.
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" into library work
|
||||
Parsing module <ClkGen>.
|
||||
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" into library work
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" into library work
|
||||
Parsing module <WarpLC>.
|
||||
|
||||
=========================================================================
|
||||
* HDL Elaboration *
|
||||
=========================================================================
|
||||
WARNING:HDLCompiler:1016 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 92: Port LoMemCacheCS is not connected to this instance
|
||||
WARNING:HDLCompiler:1016 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 108: Port RDFixed7k5SEL is not connected to this instance
|
||||
|
||||
Elaborating module <WarpLC>.
|
||||
WARNING:HDLCompiler:1016 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port LOCKED is not connected to this instance
|
||||
WARNING:HDLCompiler:1016 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port LOCKED is not connected to this instance
|
||||
|
||||
Elaborating module <ClkGen>.
|
||||
|
||||
@ -137,11 +149,11 @@ Elaborating module <IBUFG>.
|
||||
Elaborating module <BUFIO2FB(DIVIDE_BYPASS="TRUE")>.
|
||||
|
||||
Elaborating module <PLL_BASE(BANDWIDTH="HIGH",CLK_FEEDBACK="CLKFBOUT",COMPENSATION="EXTERNAL",DIVCLK_DIVIDE=1,CLKFBOUT_MULT=28,CLKFBOUT_PHASE=0.0,CLKOUT0_DIVIDE=14,CLKOUT0_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,CLKIN_PERIOD=30.0,REF_JITTER=0.01)>.
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to clkout1_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to clkout2_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to clkout3_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to clkout4_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to clkout5_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to clkout1_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to clkout2_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to clkout3_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to clkout4_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to clkout5_unused ignored, since the identifier is never used
|
||||
|
||||
Elaborating module <BUFG>.
|
||||
|
||||
@ -149,24 +161,51 @@ Elaborating module <ODDR2>.
|
||||
|
||||
Elaborating module <ODDR2(DDR_ALIGNMENT="C0",INIT=1'b0,SRTYPE="ASYNC")>.
|
||||
|
||||
Elaborating module <CS>.
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to FSB_SEL_RAM ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 95: Assignment to FSB_SEL_ROM ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 96: Assignment to FSB_VRAM ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 97: Assignment to FSB_SEL_Cache ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 98: Assignment to FSB_CA ignored, since the identifier is never used
|
||||
|
||||
Elaborating module <SizeDecode>.
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to FSB_B ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 104: Assignment to FSB_B ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1016 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 49: Port doutb is not connected to this instance
|
||||
|
||||
Elaborating module <L2Prefetch>.
|
||||
|
||||
Elaborating module <PrefetchTagRAM>.
|
||||
WARNING:HDLCompiler:1499 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module <PrefetchTagRAM> remains a black box.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 40: Size mismatch in connection of port <d>. Formal port size is 22-bit while actual signal size is 20-bit.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 41: Size mismatch in connection of port <spo>. Formal port size is 22-bit while actual signal size is 20-bit.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 43: Size mismatch in connection of port <dpo>. Formal port size is 22-bit while actual signal size is 20-bit.
|
||||
WARNING:Xst:2972 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 91. All outputs of instance <sd> of block <SizeDecode> are unconnected in block <WarpLC>. Underlying logic will be removed.
|
||||
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module <PrefetchTagRAM> remains a black box.
|
||||
|
||||
Elaborating module <PrefetchDataRAM>.
|
||||
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" Line 39: Empty module <PrefetchDataRAM> remains a black box.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 116: Size mismatch in connection of port <WRA>. Formal port size is 26-bit while actual signal size is 28-bit.
|
||||
|
||||
Elaborating module <L2Cache>.
|
||||
|
||||
Elaborating module <L2CacheWay>.
|
||||
|
||||
Elaborating module <L2WayRAM>.
|
||||
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\L2WayRAM.v" Line 39: Empty module <L2WayRAM> remains a black box.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 43: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 12-bit.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 44: Size mismatch in connection of port <dina>. Formal port size is 47-bit while actual signal size is 50-bit.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 45: Size mismatch in connection of port <douta>. Formal port size is 47-bit while actual signal size is 49-bit.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 49: Size mismatch in connection of port <addrb>. Formal port size is 10-bit while actual signal size is 12-bit.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 50: Size mismatch in connection of port <dinb>. Formal port size is 47-bit while actual signal size is 49-bit.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 51: Size mismatch in connection of port <doutb>. Formal port size is 47-bit while actual signal size is 49-bit.
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 51: Assignment to TSD ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 132: Size mismatch in connection of port <WRA>. Formal port size is 26-bit while actual signal size is 28-bit.
|
||||
WARNING:HDLCompiler:634 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 125: Net <CLK> does not have a driver.
|
||||
WARNING:HDLCompiler:552 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 108: Input port RDFixed7k5SEL is not connected on this instance
|
||||
WARNING:Xst:2972 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92. All outputs of instance <cs> of block <CS> are unconnected in block <WarpLC>. Underlying logic will be removed.
|
||||
WARNING:Xst:2972 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 101. All outputs of instance <sd> of block <SizeDecode> are unconnected in block <WarpLC>. Underlying logic will be removed.
|
||||
|
||||
=========================================================================
|
||||
* HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Synthesizing Unit <WarpLC>.
|
||||
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v".
|
||||
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v".
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <FSB_A>.
|
||||
Set property "IOBDELAY = NONE" for signal <FSB_A>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <FSB_SIZ>.
|
||||
@ -198,36 +237,61 @@ Synthesizing Unit <WarpLC>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CLKFB_OUT>.
|
||||
Set property "DRIVE = 24" for signal <CLKFB_OUT>.
|
||||
Set property "SLEW = FAST" for signal <CLKFB_OUT>.
|
||||
WARNING:Xst:647 - Input <FSB_A<31:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:2898 - Port 'RDFixed7k5SEL', unconnected in block instance 'prefetch', is tied to GND.
|
||||
WARNING:Xst:647 - Input <CPU_nAS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
INFO:Xst:3210 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 91: Output port <B> of the instance <sd> is unconnected or connected to loadless signal.
|
||||
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <CA> of the instance <cs> is unconnected or connected to loadless signal.
|
||||
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <RAMCS> of the instance <cs> is unconnected or connected to loadless signal.
|
||||
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <ROMCS> of the instance <cs> is unconnected or connected to loadless signal.
|
||||
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <VRAMCS> of the instance <cs> is unconnected or connected to loadless signal.
|
||||
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <CacheCS> of the instance <cs> is unconnected or connected to loadless signal.
|
||||
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <LoMemCacheCS> of the instance <cs> is unconnected or connected to loadless signal.
|
||||
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 101: Output port <B> of the instance <sd> is unconnected or connected to loadless signal.
|
||||
WARNING:Xst:653 - Signal <CLK> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
||||
Summary:
|
||||
no macro.
|
||||
inferred 2 Multiplexer(s).
|
||||
Unit <WarpLC> synthesized.
|
||||
|
||||
Synthesizing Unit <ClkGen>.
|
||||
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ClkGen.v".
|
||||
INFO:Xst:3210 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ClkGen.v" line 32: Output port <LOCKED> of the instance <pll> is unconnected or connected to loadless signal.
|
||||
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v".
|
||||
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" line 32: Output port <LOCKED> of the instance <pll> is unconnected or connected to loadless signal.
|
||||
Found 1-bit register for signal <CPUCLKr>.
|
||||
Summary:
|
||||
inferred 1 D-type flip-flop(s).
|
||||
Unit <ClkGen> synthesized.
|
||||
|
||||
Synthesizing Unit <PLL>.
|
||||
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v".
|
||||
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v".
|
||||
Summary:
|
||||
no macro.
|
||||
Unit <PLL> synthesized.
|
||||
|
||||
Synthesizing Unit <L2Prefetch>.
|
||||
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v".
|
||||
WARNING:Xst:647 - Input <WRD> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <CPUCLKr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
Found 19-bit comparator equal for signal <RDTag[18]_RDATag[18]_equal_5_o> created at line 34
|
||||
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v".
|
||||
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v" line 49: Output port <doutb> of the instance <data> is unconnected or connected to loadless signal.
|
||||
Found 19-bit comparator equal for signal <RDTag[18]_RDATag[18]_equal_5_o> created at line 35
|
||||
Summary:
|
||||
inferred 1 Comparator(s).
|
||||
Unit <L2Prefetch> synthesized.
|
||||
|
||||
Synthesizing Unit <L2Cache>.
|
||||
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2Cache.v".
|
||||
Summary:
|
||||
inferred 8 Multiplexer(s).
|
||||
Unit <L2Cache> synthesized.
|
||||
|
||||
Synthesizing Unit <L2CacheWay>.
|
||||
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v".
|
||||
WARNING:Xst:647 - Input <RDA<27:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <WRM> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <TS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <WR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <CLR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <ALL> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" line 39: Output port <doutb> of the instance <way> is unconnected or connected to loadless signal.
|
||||
Summary:
|
||||
no macro.
|
||||
Unit <L2CacheWay> synthesized.
|
||||
|
||||
=========================================================================
|
||||
HDL Synthesis Report
|
||||
|
||||
@ -236,6 +300,8 @@ Macro Statistics
|
||||
1-bit register : 1
|
||||
# Comparators : 1
|
||||
19-bit comparator equal : 1
|
||||
# Multiplexers : 10
|
||||
32-bit 2-to-1 multiplexer : 10
|
||||
|
||||
=========================================================================
|
||||
|
||||
@ -244,7 +310,11 @@ Macro Statistics
|
||||
=========================================================================
|
||||
|
||||
Reading core <ipcore_dir/PrefetchTagRAM.ngc>.
|
||||
Loading core <PrefetchTagRAM> for timing and area information for instance <Tag>.
|
||||
Reading core <ipcore_dir/PrefetchDataRAM.ngc>.
|
||||
Reading core <ipcore_dir/L2WayRAM.ngc>.
|
||||
Loading core <PrefetchTagRAM> for timing and area information for instance <tag>.
|
||||
Loading core <PrefetchDataRAM> for timing and area information for instance <data>.
|
||||
Loading core <L2WayRAM> for timing and area information for instance <way>.
|
||||
|
||||
=========================================================================
|
||||
Advanced HDL Synthesis Report
|
||||
@ -254,6 +324,8 @@ Macro Statistics
|
||||
Flip-Flops : 1
|
||||
# Comparators : 1
|
||||
19-bit comparator equal : 1
|
||||
# Multiplexers : 10
|
||||
32-bit 2-to-1 multiplexer : 10
|
||||
|
||||
=========================================================================
|
||||
|
||||
@ -268,9 +340,11 @@ Optimizing unit <ClkGen> ...
|
||||
|
||||
Optimizing unit <PLL> ...
|
||||
|
||||
Optimizing unit <L2Cache> ...
|
||||
|
||||
Mapping all equations...
|
||||
Building and optimizing final netlist ...
|
||||
Found area constraint ratio of 100 (+ 5) on block WarpLC, actual ratio is 0.
|
||||
Found area constraint ratio of 100 (+ 5) on block WarpLC, actual ratio is 1.
|
||||
|
||||
Final Macro Processing ...
|
||||
|
||||
@ -302,26 +376,28 @@ Top Level Output File Name : WarpLC.ngc
|
||||
|
||||
Primitive and Black Box Usage:
|
||||
------------------------------
|
||||
# BELS : 21
|
||||
# GND : 1
|
||||
# BELS : 62
|
||||
# GND : 10
|
||||
# INV : 3
|
||||
# LUT1 : 1
|
||||
# LUT2 : 1
|
||||
# LUT3 : 32
|
||||
# LUT6 : 6
|
||||
# MUXCY : 8
|
||||
# VCC : 1
|
||||
# FlipFlops/Latches : 50
|
||||
# FD : 44
|
||||
# FlipFlops/Latches : 46
|
||||
# FD : 40
|
||||
# FDR : 1
|
||||
# ODDR2 : 5
|
||||
# RAMS : 22
|
||||
# RAM128X1D : 22
|
||||
# RAMS : 48
|
||||
# RAM128X1D : 20
|
||||
# RAMB16BWER : 28
|
||||
# Clock Buffers : 2
|
||||
# BUFG : 2
|
||||
# IO Buffers : 34
|
||||
# IO Buffers : 66
|
||||
# IBUF : 26
|
||||
# IBUFG : 2
|
||||
# OBUF : 6
|
||||
# OBUF : 38
|
||||
# Others : 2
|
||||
# BUFIO2FB : 1
|
||||
# PLL_ADV : 1
|
||||
@ -333,24 +409,26 @@ Selected Device : 6slx9ftg256-2
|
||||
|
||||
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 50 out of 11440 0%
|
||||
Number of Slice LUTs: 99 out of 5720 1%
|
||||
Number used as Logic: 11 out of 5720 0%
|
||||
Number used as Memory: 88 out of 1440 6%
|
||||
Number used as RAM: 88
|
||||
Number of Slice Registers: 46 out of 11440 0%
|
||||
Number of Slice LUTs: 123 out of 5720 2%
|
||||
Number used as Logic: 43 out of 5720 0%
|
||||
Number used as Memory: 80 out of 1440 5%
|
||||
Number used as RAM: 80
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of LUT Flip Flop pairs used: 149
|
||||
Number with an unused Flip Flop: 99 out of 149 66%
|
||||
Number with an unused LUT: 50 out of 149 33%
|
||||
Number of fully used LUT-FF pairs: 0 out of 149 0%
|
||||
Number of LUT Flip Flop pairs used: 169
|
||||
Number with an unused Flip Flop: 123 out of 169 72%
|
||||
Number with an unused LUT: 46 out of 169 27%
|
||||
Number of fully used LUT-FF pairs: 0 out of 169 0%
|
||||
Number of unique control sets: 2
|
||||
|
||||
IO Utilization:
|
||||
Number of IOs: 75
|
||||
Number of bonded IOBs: 34 out of 186 18%
|
||||
Number of bonded IOBs: 66 out of 186 35%
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of Block RAM/FIFO: 28 out of 32 87%
|
||||
Number using Block RAM only: 28
|
||||
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
|
||||
Number of PLL_ADVs: 1 out of 2 50%
|
||||
|
||||
@ -372,12 +450,14 @@ NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
||||
|
||||
Clock Information:
|
||||
------------------
|
||||
-----------------------------------+------------------------+-------+
|
||||
Clock Signal | Clock buffer(FF name) | Load |
|
||||
-----------------------------------+------------------------+-------+
|
||||
cg/pll/pll_base_inst/CLKOUT0 | BUFG | 75 |
|
||||
cg/pll/pll_base_inst/CLKFBOUT | BUFG | 2 |
|
||||
-----------------------------------+------------------------+-------+
|
||||
-----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-------+
|
||||
Clock Signal | Clock buffer(FF name) | Load |
|
||||
-----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-------+
|
||||
cg/pll/pll_base_inst/CLKOUT0 | BUFG | 73 |
|
||||
cg/pll/pll_base_inst/CLKFBOUT | BUFG | 2 |
|
||||
CLK | NONE(cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram)| 24 |
|
||||
-----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-------+
|
||||
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
||||
|
||||
Asynchronous Control Signals Information:
|
||||
----------------------------------------
|
||||
@ -387,10 +467,10 @@ Timing Summary:
|
||||
---------------
|
||||
Speed Grade: -2
|
||||
|
||||
Minimum period: 4.616ns (Maximum Frequency: 216.638MHz)
|
||||
Minimum input arrival time before clock: No path found
|
||||
Maximum output required time after clock: No path found
|
||||
Maximum combinational path delay: 6.656ns
|
||||
Minimum period: 6.137ns (Maximum Frequency: 162.941MHz)
|
||||
Minimum input arrival time before clock: 3.180ns
|
||||
Maximum output required time after clock: 6.838ns
|
||||
Maximum combinational path delay: 8.932ns
|
||||
|
||||
Timing Details:
|
||||
---------------
|
||||
@ -398,10 +478,10 @@ All values displayed in nanoseconds (ns)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default period analysis for Clock 'cg/pll/pll_base_inst/CLKOUT0'
|
||||
Clock period: 4.616ns (frequency: 216.638MHz)
|
||||
Total number of paths / destination ports: 5 / 5
|
||||
Clock period: 6.137ns (frequency: 162.941MHz)
|
||||
Total number of paths / destination ports: 9 / 9
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 2.308ns (Levels of Logic = 1)
|
||||
Delay: 3.069ns (Levels of Logic = 1)
|
||||
Source: cg/CPUCLKr (FF)
|
||||
Destination: cg/CPUCLK_inst (FF)
|
||||
Source Clock: cg/pll/pll_base_inst/CLKOUT0 rising
|
||||
@ -412,127 +492,132 @@ Delay: 2.308ns (Levels of Logic = 1)
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FDR:C->Q 4 0.525 0.803 cg/CPUCLKr (cg/CPUCLKr)
|
||||
INV:I->O 2 0.255 0.725 cg/CPUCLKr_INV_2_o1_INV_0 (cg/CPUCLKr_INV_2_o)
|
||||
INV:I->O 30 0.255 1.486 prefetch/CPUCLKr_INV_17_o1_INV_0 (prefetch/CPUCLKr_INV_17_o)
|
||||
ODDR2:D1 0.000 cg/CPUCLK_inst
|
||||
----------------------------------------
|
||||
Total 2.308ns (0.780ns logic, 1.528ns route)
|
||||
(33.8% logic, 66.2% route)
|
||||
Total 3.069ns (0.780ns logic, 2.289ns route)
|
||||
(25.4% logic, 74.6% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default path analysis
|
||||
Total number of paths / destination ports: 20 / 2
|
||||
Timing constraint: Default OFFSET IN BEFORE for Clock 'cg/pll/pll_base_inst/CLKOUT0'
|
||||
Total number of paths / destination ports: 28 / 28
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 6.656ns (Levels of Logic = 11)
|
||||
Source: FSB_A<11> (PAD)
|
||||
Destination: CPU_nSTERM (PAD)
|
||||
Offset: 3.180ns (Levels of Logic = 2)
|
||||
Source: FSB_A<8> (PAD)
|
||||
Destination: prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
|
||||
Destination Clock: cg/pll/pll_base_inst/CLKOUT0 rising
|
||||
|
||||
Data Path: FSB_A<11> to CPU_nSTERM
|
||||
Data Path: FSB_A<8> to prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 1 1.328 0.910 FSB_A_11_IBUF (FSB_A_11_IBUF)
|
||||
LUT6:I3->O 1 0.235 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_lut<0> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_lut<0>)
|
||||
MUXCY:S->O 1 0.215 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<0> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<0>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<1> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<1>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<2> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<2>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<3> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<3>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<4> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<4>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<5> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<5>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<6> (l2pre/RDTag[18]_RDATag[18]_equal_5_o)
|
||||
MUXCY:CI->O 1 0.235 0.681 CPU_nSTERM1_cy (CPU_nSTERM_OBUF)
|
||||
OBUF:I->O 2.912 CPU_nSTERM_OBUF (CPU_nSTERM)
|
||||
IBUF:I->O 28 1.328 1.452 FSB_A_8_IBUF (FSB_A_8_IBUF)
|
||||
begin scope: 'prefetch/data:addra<6>'
|
||||
RAMB16BWER:ADDRA9 0.400 U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
|
||||
----------------------------------------
|
||||
Total 6.656ns (5.065ns logic, 1.591ns route)
|
||||
(76.1% logic, 23.9% route)
|
||||
Total 3.180ns (1.728ns logic, 1.452ns route)
|
||||
(54.3% logic, 45.7% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
|
||||
Total number of paths / destination ports: 240 / 240
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 3.180ns (Levels of Logic = 2)
|
||||
Source: FSB_A<8> (PAD)
|
||||
Destination: cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
|
||||
Destination Clock: CLK rising
|
||||
|
||||
Data Path: FSB_A<8> to cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 28 1.328 1.452 FSB_A_8_IBUF (FSB_A_8_IBUF)
|
||||
begin scope: 'cache/Way<0>/way:addra<6>'
|
||||
RAMB16BWER:ADDRA10 0.400 U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
|
||||
----------------------------------------
|
||||
Total 3.180ns (1.728ns logic, 1.452ns route)
|
||||
(54.3% logic, 45.7% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET OUT AFTER for Clock 'cg/pll/pll_base_inst/CLKOUT0'
|
||||
Total number of paths / destination ports: 32 / 32
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 6.838ns (Levels of Logic = 3)
|
||||
Source: prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
|
||||
Destination: FSB_D<31> (PAD)
|
||||
Source Clock: cg/pll/pll_base_inst/CLKOUT0 rising
|
||||
|
||||
Data Path: prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram to FSB_D<31>
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
RAMB16BWER:CLKA->DOA7 1 2.100 0.910 U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (douta<31>)
|
||||
end scope: 'prefetch/data:douta<31>'
|
||||
LUT3:I0->O 1 0.235 0.681 Mmux_FSB_D251 (FSB_D_31_OBUF)
|
||||
OBUF:I->O 2.912 FSB_D_31_OBUF (FSB_D<31>)
|
||||
----------------------------------------
|
||||
Total 6.838ns (5.247ns logic, 1.591ns route)
|
||||
(76.7% logic, 23.3% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default path analysis
|
||||
Total number of paths / destination ports: 628 / 34
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 8.932ns (Levels of Logic = 11)
|
||||
Source: FSB_A<11> (PAD)
|
||||
Destination: FSB_D<31> (PAD)
|
||||
|
||||
Data Path: FSB_A<11> to FSB_D<31>
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 25 1.328 1.631 FSB_A_11_IBUF (FSB_A_11_IBUF)
|
||||
LUT6:I3->O 1 0.235 0.000 prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_lut<0> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_lut<0>)
|
||||
MUXCY:S->O 1 0.215 0.000 prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<0> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<0>)
|
||||
MUXCY:CI->O 1 0.023 0.000 prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<1> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<1>)
|
||||
MUXCY:CI->O 1 0.023 0.000 prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<2> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<2>)
|
||||
MUXCY:CI->O 1 0.023 0.000 prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<3> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<3>)
|
||||
MUXCY:CI->O 1 0.023 0.000 prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<4> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<4>)
|
||||
MUXCY:CI->O 1 0.023 0.000 prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<5> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<5>)
|
||||
MUXCY:CI->O 33 0.023 1.537 prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<6> (prefetch/RDTag[18]_RDATag[18]_equal_5_o)
|
||||
LUT3:I2->O 1 0.254 0.681 Mmux_FSB_D321 (FSB_D_9_OBUF)
|
||||
OBUF:I->O 2.912 FSB_D_9_OBUF (FSB_D<9>)
|
||||
----------------------------------------
|
||||
Total 8.932ns (5.084ns logic, 3.849ns route)
|
||||
(56.9% logic, 43.1% route)
|
||||
|
||||
=========================================================================
|
||||
|
||||
Cross Clock Domains Report:
|
||||
--------------------------
|
||||
|
||||
Clock to Setup on destination clock CLK
|
||||
----------------------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
----------------------------+---------+---------+---------+---------+
|
||||
cg/pll/pll_base_inst/CLKOUT0| 3.289| | | |
|
||||
----------------------------+---------+---------+---------+---------+
|
||||
|
||||
Clock to Setup on destination clock cg/pll/pll_base_inst/CLKOUT0
|
||||
----------------------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
----------------------------+---------+---------+---------+---------+
|
||||
cg/pll/pll_base_inst/CLKOUT0| 2.308| | 2.308| |
|
||||
cg/pll/pll_base_inst/CLKOUT0| 3.289| | 3.069| |
|
||||
----------------------------+---------+---------+---------+---------+
|
||||
|
||||
=========================================================================
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<31> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<31> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<30> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<30> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<29> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<29> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<28> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<28> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<27> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<27> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<26> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<26> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<25> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<25> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<24> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<24> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<23> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<23> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<22> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<22> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<21> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<21> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<20> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<20> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<19> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<19> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<18> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<18> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<17> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<17> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<16> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<16> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<15> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<15> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<14> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<14> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<13> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<13> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<12> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<12> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<11> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<11> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<10> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<10> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<9> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<9> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<8> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<8> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<7> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<7> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<6> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<6> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<5> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<5> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<4> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<4> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<3> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<3> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<2> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<2> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<1> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<1> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<0> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<0> not found, property DRIVE not attached.
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 3.00 secs
|
||||
Total CPU time to Xst completion: 3.42 secs
|
||||
Total REAL time to Xst completion: 6.00 secs
|
||||
Total CPU time to Xst completion: 6.14 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 224828 kilobytes
|
||||
Total memory usage is 216628 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 80 ( 0 filtered)
|
||||
Number of infos : 3 ( 0 filtered)
|
||||
Number of warnings : 40 ( 0 filtered)
|
||||
Number of infos : 12 ( 0 filtered)
|
||||
|
||||
|
||||
1355
fpga/WarpLC.twr
1355
fpga/WarpLC.twr
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@ -1,7 +1,7 @@
|
||||
Release 14.7 - par P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Mon Nov 01 06:10:44 2021
|
||||
Tue Nov 02 00:29:15 2021
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
@ -104,21 +104,45 @@ module WarpLC(
|
||||
.B(FSB_B[3:0]));
|
||||
|
||||
wire L2PrefetchMatch;
|
||||
L2Prefetch l2pre (
|
||||
wire [31:0] L2PrefetchRDD;
|
||||
L2Prefetch prefetch (
|
||||
.CLK(FSBCLK),
|
||||
.CPUCLKr(CPUCLKr),
|
||||
|
||||
.RDA(FSB_A[27:2]),
|
||||
.RDD(FSB_D[31:0]),
|
||||
.RDA({FSB_A[30], FSB_A[28], FSB_A[25:2]}),
|
||||
.RDD(L2PrefetchRDD),
|
||||
.Match(L2PrefetchMatch),
|
||||
|
||||
.WRA(26'b0),
|
||||
.WRA(28'b0),
|
||||
.WRD(32'b0),
|
||||
.WR(1'b0),
|
||||
.WRM(4'b0),
|
||||
.CLR(1'b0));
|
||||
|
||||
assign CPU_nSTERM = ~(L2PrefetchMatch);
|
||||
wire L2CacheMatch;
|
||||
wire [31:0] L2CacheRDD;
|
||||
L2Cache cache (
|
||||
.CLK(CLK),
|
||||
.CPUCLKr(CPUCLKr),
|
||||
|
||||
.RDA({FSB_A[30], FSB_A[28], FSB_A[25:2]}),
|
||||
.RDD(L2CacheRDD),
|
||||
.Match(L2CacheMatch),
|
||||
|
||||
.WRA(28'b0),
|
||||
.WRD(32'b0),
|
||||
.WRM(4'b0),
|
||||
.TS(1'b0),
|
||||
.WR(1'b0),
|
||||
.CLR(1'b0),
|
||||
.ALL(1'b0));
|
||||
|
||||
assign FSB_D[31:0] = L2PrefetchMatch ? L2PrefetchRDD[31:0] :
|
||||
L2CacheMatch ? L2CacheRDD[31:0] : 0;
|
||||
|
||||
reg STERMEN = 0;
|
||||
reg STERM = 0;
|
||||
assign CPU_nSTERM = ~((L2PrefetchMatch && STERMEN) || STERM);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -17,50 +17,50 @@
|
||||
<files>
|
||||
<file xil_pn:name="WarpLC.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
|
||||
</file>
|
||||
<file xil_pn:name="PLL.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PrefetchTagRAM.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PrefetchDataRAM.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="ClkGen.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="L2Cache.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
|
||||
</file>
|
||||
<file xil_pn:name="SizeDecode.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/L2WayRAM.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="L2CacheWay.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="Prefetch.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="CS.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PrefetchTagRAM.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
|
||||
@ -18,42 +18,42 @@
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Path</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\PuTTY\;<br>C:\Program Files (x86)\WinMerge;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Dog\AppData\Local\GitHubDesktop\bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\PuTTY\;<br>C:\Program Files (x86)\WinMerge;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Dog\AppData\Local\GitHubDesktop\bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\PuTTY\;<br>C:\Program Files (x86)\WinMerge;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Dog\AppData\Local\GitHubDesktop\bin</td>
|
||||
<td><font color=gray>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\PuTTY\;<br>C:\Program Files (x86)\WinMerge;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Dog\AppData\Local\GitHubDesktop\bin</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
<td><font color=gray>C:\Xilinx\14.7\ISE_DS\ISE\</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_DSP</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
<td><font color=gray>C:\Xilinx\14.7\ISE_DS\ISE</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
<td><font color=gray>C:\Xilinx\14.7\ISE_DS\EDK</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_PLANAHEAD</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
<td><font color=gray>C:\Xilinx\14.7\ISE_DS\PlanAhead</font></td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Synthesis Property Settings"></A>
|
||||
@ -512,34 +512,34 @@
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-xe</td>
|
||||
<td> </td>
|
||||
<td>c</td>
|
||||
<td>None</td>
|
||||
<td><font color=gray>-xe</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
<td><font color=gray>c</font></td>
|
||||
<td><font color=gray>None</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
<td> </td>
|
||||
<td><font color=gray>-intstyle</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
<td><font color=gray>ise</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-mt</td>
|
||||
<td>Enable Multi-Threading</td>
|
||||
<td>4</td>
|
||||
<td>off</td>
|
||||
<td><font color=gray>-mt</font></td>
|
||||
<td><font color=gray>Enable Multi-Threading</font></td>
|
||||
<td><font color=gray>4</font></td>
|
||||
<td><font color=gray>off</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ol</td>
|
||||
<td>Place & Route Effort Level (Overall)</td>
|
||||
<td>high</td>
|
||||
<td>std</td>
|
||||
<td><font color=gray>-ol</font></td>
|
||||
<td><font color=gray>Place & Route Effort Level (Overall)</font></td>
|
||||
<td><font color=gray>high</font></td>
|
||||
<td><font color=gray>std</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-w</td>
|
||||
<td> </td>
|
||||
<td>true</td>
|
||||
<td>false</td>
|
||||
<td><font color=gray>-w</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
<td><font color=gray>true</font></td>
|
||||
<td><font color=gray>false</font></td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Operating System Information"></A>
|
||||
@ -556,31 +556,31 @@
|
||||
</tr>
|
||||
<tr>
|
||||
<td>CPU Architecture/Speed</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
<td>Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz</td>
|
||||
<td>Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz</td>
|
||||
<td>Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz</td>
|
||||
<td><font color=gray>Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Host</td>
|
||||
<td>ZanePC</td>
|
||||
<td>ZanePC</td>
|
||||
<td>ZanePC</td>
|
||||
<td>ZanePC</td>
|
||||
<td>Dog-PC</td>
|
||||
<td>Dog-PC</td>
|
||||
<td>Dog-PC</td>
|
||||
<td><font color=gray>Dog-PC</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Name</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
<td><font color=gray>Microsoft Windows 7 , 64-bit</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Release</td>
|
||||
<td>major release (build 9200)</td>
|
||||
<td>major release (build 9200)</td>
|
||||
<td>major release (build 9200)</td>
|
||||
<td>major release (build 9200)</td>
|
||||
<td>Service Pack 1 (build 7601)</td>
|
||||
<td>Service Pack 1 (build 7601)</td>
|
||||
<td>Service Pack 1 (build 7601)</td>
|
||||
<td><font color=gray>Service Pack 1 (build 7601)</font></td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
</BODY> </HTML>
|
||||
File diff suppressed because one or more lines are too long
@ -10,7 +10,7 @@ Target Device : xc6slx9
|
||||
Target Package : ftg256
|
||||
Target Speed : -2
|
||||
Mapper Version : spartan6 -- $Revision: 1.55 $
|
||||
Mapped Date : Mon Nov 01 06:10:29 2021
|
||||
Mapped Date : Tue Nov 02 00:33:09 2021
|
||||
|
||||
Running global optimization...
|
||||
Mapping design into LUTs...
|
||||
@ -20,55 +20,57 @@ Updating timing models...
|
||||
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
|
||||
(.mrp).
|
||||
Running timing-driven placement...
|
||||
Total REAL time at the beginning of Placer: 7 secs
|
||||
Total CPU time at the beginning of Placer: 6 secs
|
||||
Total REAL time at the beginning of Placer: 9 secs
|
||||
Total CPU time at the beginning of Placer: 9 secs
|
||||
|
||||
Phase 1.1 Initial Placement Analysis
|
||||
Phase 1.1 Initial Placement Analysis (Checksum:60b6) REAL time: 8 secs
|
||||
Phase 1.1 Initial Placement Analysis (Checksum:a4d8) REAL time: 10 secs
|
||||
|
||||
Phase 2.7 Design Feasibility Check
|
||||
Phase 2.7 Design Feasibility Check (Checksum:60b6) REAL time: 8 secs
|
||||
Phase 2.7 Design Feasibility Check (Checksum:a4d8) REAL time: 10 secs
|
||||
|
||||
Phase 3.31 Local Placement Optimization
|
||||
Phase 3.31 Local Placement Optimization (Checksum:60b6) REAL time: 8 secs
|
||||
Phase 3.31 Local Placement Optimization (Checksum:a4d8) REAL time: 10 secs
|
||||
|
||||
Phase 4.2 Initial Placement for Architecture Specific Features
|
||||
...
|
||||
....
|
||||
Phase 4.2 Initial Placement for Architecture Specific Features
|
||||
(Checksum:11959966) REAL time: 8 secs
|
||||
(Checksum:2d53f6ff) REAL time: 14 secs
|
||||
|
||||
Phase 5.36 Local Placement Optimization
|
||||
Phase 5.36 Local Placement Optimization (Checksum:11959966) REAL time: 8 secs
|
||||
Phase 5.36 Local Placement Optimization (Checksum:2d53f6ff) REAL time: 14 secs
|
||||
|
||||
Phase 6.30 Global Clock Region Assignment
|
||||
Phase 6.30 Global Clock Region Assignment (Checksum:11959966) REAL time: 8 secs
|
||||
Phase 6.30 Global Clock Region Assignment (Checksum:2d53f6ff) REAL time: 14 secs
|
||||
|
||||
Phase 7.3 Local Placement Optimization
|
||||
...
|
||||
....
|
||||
Phase 7.3 Local Placement Optimization (Checksum:1284e9e0) REAL time: 8 secs
|
||||
Phase 7.3 Local Placement Optimization (Checksum:615a33f3) REAL time: 19 secs
|
||||
|
||||
Phase 8.5 Local Placement Optimization
|
||||
Phase 8.5 Local Placement Optimization (Checksum:1284e9e0) REAL time: 8 secs
|
||||
Phase 8.5 Local Placement Optimization (Checksum:615a33f3) REAL time: 19 secs
|
||||
|
||||
Phase 9.8 Global Placement
|
||||
................................................................
|
||||
..................
|
||||
Phase 9.8 Global Placement (Checksum:f7b99523) REAL time: 8 secs
|
||||
...................................................
|
||||
.......................
|
||||
Phase 9.8 Global Placement (Checksum:b18754dd) REAL time: 19 secs
|
||||
|
||||
Phase 10.5 Local Placement Optimization
|
||||
Phase 10.5 Local Placement Optimization (Checksum:f7b99523) REAL time: 8 secs
|
||||
Phase 10.5 Local Placement Optimization (Checksum:b18754dd) REAL time: 19 secs
|
||||
|
||||
Phase 11.18 Placement Optimization
|
||||
Phase 11.18 Placement Optimization (Checksum:6614d61e) REAL time: 9 secs
|
||||
Phase 11.18 Placement Optimization (Checksum:58c2ff74) REAL time: 20 secs
|
||||
|
||||
Phase 12.5 Local Placement Optimization
|
||||
Phase 12.5 Local Placement Optimization (Checksum:6614d61e) REAL time: 9 secs
|
||||
Phase 12.5 Local Placement Optimization (Checksum:58c2ff74) REAL time: 20 secs
|
||||
|
||||
Phase 13.34 Placement Validation
|
||||
Phase 13.34 Placement Validation (Checksum:6614d61e) REAL time: 9 secs
|
||||
Phase 13.34 Placement Validation (Checksum:58c2ff74) REAL time: 20 secs
|
||||
|
||||
Total REAL time to Placer completion: 9 secs
|
||||
Total CPU time to Placer completion: 6 secs
|
||||
Total REAL time to Placer completion: 20 secs
|
||||
Total CPU time to Placer completion: 20 secs
|
||||
Running physical synthesis...
|
||||
|
||||
Physical synthesis completed.
|
||||
@ -87,11 +89,11 @@ Slice Logic Utilization:
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 89 out of 5,720 1%
|
||||
Number used as logic: 9 out of 5,720 1%
|
||||
Number of Slice LUTs: 105 out of 5,720 1%
|
||||
Number used as logic: 25 out of 5,720 1%
|
||||
Number using O6 output only: 7
|
||||
Number using O5 output only: 1
|
||||
Number using O5 and O6: 1
|
||||
Number using O5 and O6: 17
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 80 out of 1,440 5%
|
||||
Number used as Dual Port RAM: 80
|
||||
@ -102,12 +104,12 @@ Slice Logic Utilization:
|
||||
Number used as Shift Register: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 23 out of 1,430 1%
|
||||
Number of occupied Slices: 35 out of 1,430 2%
|
||||
Number of MUXCYs used: 8 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 89
|
||||
Number with an unused Flip Flop: 88 out of 89 98%
|
||||
Number with an unused LUT: 0 out of 89 0%
|
||||
Number of fully used LUT-FF pairs: 1 out of 89 1%
|
||||
Number of LUT Flip Flop pairs used: 106
|
||||
Number with an unused Flip Flop: 105 out of 106 99%
|
||||
Number with an unused LUT: 1 out of 106 1%
|
||||
Number of fully used LUT-FF pairs: 0 out of 106 0%
|
||||
Number of unique control sets: 2
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 7 out of 11,440 1%
|
||||
@ -119,11 +121,11 @@ Slice Logic Distribution:
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 34 out of 186 18%
|
||||
Number of bonded IOBs: 66 out of 186 35%
|
||||
IOB Flip Flops: 5
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 0 out of 32 0%
|
||||
Number of RAMB16BWERs: 4 out of 32 12%
|
||||
Number of RAMB8BWERs: 0 out of 64 0%
|
||||
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2s: 1
|
||||
@ -153,11 +155,11 @@ Specific Feature Utilization:
|
||||
Number of STARTUPs: 0 out of 1 0%
|
||||
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 5.20
|
||||
Average Fanout of Non-Clock Nets: 3.54
|
||||
|
||||
Peak Memory Usage: 287 MB
|
||||
Total REAL time to MAP completion: 10 secs
|
||||
Total CPU time to MAP completion (all processors): 8 secs
|
||||
Peak Memory Usage: 283 MB
|
||||
Total REAL time to MAP completion: 22 secs
|
||||
Total CPU time to MAP completion (all processors): 22 secs
|
||||
|
||||
Mapping completed.
|
||||
See MAP report file "WarpLC_map.mrp" for details.
|
||||
|
||||
@ -10,7 +10,7 @@ Target Device : xc6slx9
|
||||
Target Package : ftg256
|
||||
Target Speed : -2
|
||||
Mapper Version : spartan6 -- $Revision: 1.55 $
|
||||
Mapped Date : Mon Nov 01 06:10:29 2021
|
||||
Mapped Date : Tue Nov 02 00:33:09 2021
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
@ -22,11 +22,11 @@ Slice Logic Utilization:
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 89 out of 5,720 1%
|
||||
Number used as logic: 9 out of 5,720 1%
|
||||
Number of Slice LUTs: 105 out of 5,720 1%
|
||||
Number used as logic: 25 out of 5,720 1%
|
||||
Number using O6 output only: 7
|
||||
Number using O5 output only: 1
|
||||
Number using O5 and O6: 1
|
||||
Number using O5 and O6: 17
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 80 out of 1,440 5%
|
||||
Number used as Dual Port RAM: 80
|
||||
@ -37,12 +37,12 @@ Slice Logic Utilization:
|
||||
Number used as Shift Register: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 23 out of 1,430 1%
|
||||
Number of occupied Slices: 35 out of 1,430 2%
|
||||
Number of MUXCYs used: 8 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 89
|
||||
Number with an unused Flip Flop: 88 out of 89 98%
|
||||
Number with an unused LUT: 0 out of 89 0%
|
||||
Number of fully used LUT-FF pairs: 1 out of 89 1%
|
||||
Number of LUT Flip Flop pairs used: 106
|
||||
Number with an unused Flip Flop: 105 out of 106 99%
|
||||
Number with an unused LUT: 1 out of 106 1%
|
||||
Number of fully used LUT-FF pairs: 0 out of 106 0%
|
||||
Number of unique control sets: 2
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 7 out of 11,440 1%
|
||||
@ -54,11 +54,11 @@ Slice Logic Distribution:
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 34 out of 186 18%
|
||||
Number of bonded IOBs: 66 out of 186 35%
|
||||
IOB Flip Flops: 5
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 0 out of 32 0%
|
||||
Number of RAMB16BWERs: 4 out of 32 12%
|
||||
Number of RAMB8BWERs: 0 out of 64 0%
|
||||
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2s: 1
|
||||
@ -88,11 +88,11 @@ Specific Feature Utilization:
|
||||
Number of STARTUPs: 0 out of 1 0%
|
||||
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 5.20
|
||||
Average Fanout of Non-Clock Nets: 3.54
|
||||
|
||||
Peak Memory Usage: 287 MB
|
||||
Total REAL time to MAP completion: 10 secs
|
||||
Total CPU time to MAP completion (all processors): 8 secs
|
||||
Peak Memory Usage: 283 MB
|
||||
Total REAL time to MAP completion: 22 secs
|
||||
Total CPU time to MAP completion (all processors): 22 secs
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
@ -122,11 +122,11 @@ INFO:Map:284 - Map is running with the multi-threading option on. Map currently
|
||||
supports the use of up to 2 processors. Based on the the user options and
|
||||
machine load, Map will use 2 processors during this run.
|
||||
INFO:LIT:243 - Logical network FSB_A<31> has no load.
|
||||
INFO:LIT:395 - The above info message is repeated 86 more times for the
|
||||
INFO:LIT:395 - The above info message is repeated 50 more times for the
|
||||
following (max. 5 shown):
|
||||
FSB_A<30>,
|
||||
FSB_A<29>,
|
||||
FSB_A<28>,
|
||||
FSB_A<27>,
|
||||
FSB_A<26>,
|
||||
FSB_A<1>,
|
||||
FSB_A<0>
|
||||
To see the details of these info messages, please use the -detail switch.
|
||||
@ -141,9 +141,9 @@ INFO:Pack:1650 - Map created a placed design.
|
||||
|
||||
Section 4 - Removed Logic Summary
|
||||
---------------------------------
|
||||
48 block(s) removed
|
||||
42 block(s) removed
|
||||
2 block(s) optimized away
|
||||
70 signal(s) removed
|
||||
62 signal(s) removed
|
||||
|
||||
Section 5 - Removed Logic
|
||||
-------------------------
|
||||
@ -159,303 +159,269 @@ above the place where that logic is listed in the trimming report, then locate
|
||||
the lines that are least indented (begin at the leftmost edge).
|
||||
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<0>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<0>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_0" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_0"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<1>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<1>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_1" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_1"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<2>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<2>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_2" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_2"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<3>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<3>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_3" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_3"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<4>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<4>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_4" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_4"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<5>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<5>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_5" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_5"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<6>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<6>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_6" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_6"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<7>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<7>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_7" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_7"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<8>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<8>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_8" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_8"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<9>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<9>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_9" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_9"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<10>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<10>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_10" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_10"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<11>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<11>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_11" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_11"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<12>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<12>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_12" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_12"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<13>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<13>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_13" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_13"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<14>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<14>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_14" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_14"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<15>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<15>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_15" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_15"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<16>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<16>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_16" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_16"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<17>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<17>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_17" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_17"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<18>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<18>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_18" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_18"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<19>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<19>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_19" (FF)
|
||||
removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_19"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<20>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<0>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_20" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/dpo<20>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_0"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<0>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<21>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<1>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_21" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/dpo<21>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_1"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<1>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<0>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<2>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_0" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<0>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_2"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<2>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<1>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<3>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_1" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<1>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_3"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<3>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<2>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<4>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_2" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<2>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_4"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<4>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<3>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<5>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_3" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<3>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_5"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<5>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<4>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<6>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_4" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<4>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_6"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<6>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<5>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<7>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_5" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<5>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_7"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<7>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<6>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<8>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_6" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<6>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_8"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<8>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<7>" is
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<9>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_7" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<7>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_9"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<9>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<8>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<10>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_8" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<8>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_10"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<10>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<9>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<11>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_9" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<9>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_11"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<11>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<10>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<12>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_10" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<10>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_12"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<12>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<11>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<13>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_11" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<11>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_13"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<13>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<12>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<14>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_12" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<12>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_14"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<14>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<13>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<15>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_13" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<13>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_15"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<15>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<14>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<16>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_14" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<14>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_16"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<16>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<15>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<17>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_15" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<15>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_17"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<17>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<16>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<18>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_16" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<16>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_18"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<18>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<17>" is
|
||||
loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<19>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_17" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<17>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<18>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_18" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<18>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<19>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_19" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<19>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<20>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_20" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<20>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<21>" is
|
||||
loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_21" (FF)
|
||||
removed.
|
||||
The signal "l2pre/Tag/spo<21>" is loadless and has been removed.
|
||||
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_19"
|
||||
(FF) removed.
|
||||
The signal "prefetch/tag/spo<19>" is loadless and has been removed.
|
||||
The signal "cg/pll/pll_base_inst/N2" is sourceless and has been removed.
|
||||
The signal "cg/pll/pll_base_inst/N3" is sourceless and has been removed.
|
||||
Unused block "cg/pll/pll_base_inst/XST_GND" (ZERO) removed.
|
||||
Unused block "cg/pll/pll_base_inst/XST_VCC" (ONE) removed.
|
||||
Unused block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21"
|
||||
(RAM128X1D) removed.
|
||||
Unused block
|
||||
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22"
|
||||
(RAM128X1D) removed.
|
||||
|
||||
Optimized Block(s):
|
||||
TYPE BLOCK
|
||||
@ -502,8 +468,40 @@ Section 6 - IOB Properties
|
||||
| FSB_A<23> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<24> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<25> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<26> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<27> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<28> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<30> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_D<0> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<1> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<2> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<3> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<4> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<5> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<6> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<7> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<8> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<9> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<10> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<11> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<12> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<13> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<14> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<15> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<16> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<17> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<18> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<19> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<20> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<21> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<22> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<23> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<24> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<25> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<26> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<27> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<28> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<29> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<30> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<31> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| RAMCLK0 | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
| RAMCLK1 | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -29,115 +29,107 @@ Target Device : 6slx9ftg256-2
|
||||
* Optimizations *
|
||||
=========================================================================
|
||||
---- Statistics
|
||||
Number of registers added by Synchronous Optimization | 1
|
||||
Number of LUTs removed by SmartOpt Trimming | 94
|
||||
Number of LUTs removed by SmartOpt Trimming | 90
|
||||
|
||||
Overall change in number of design objects | -93
|
||||
Overall change in number of design objects | -90
|
||||
|
||||
|
||||
---- Details
|
||||
|
||||
New or modified components | Optimization | Objective
|
||||
-------------------------------------------------------|--------------------------|----------------------
|
||||
cg/CPUCLKr | Synchronous Optimization | Performance
|
||||
|
||||
|
||||
Removed components | Optimization
|
||||
-------------------------------------------------------|--------------------------
|
||||
][282_1 | SmartOpt Trimming
|
||||
][285_2 | SmartOpt Trimming
|
||||
][287_4 | SmartOpt Trimming
|
||||
][288_5 | SmartOpt Trimming
|
||||
][69_7 | SmartOpt Trimming
|
||||
][const_101_65 | SmartOpt Trimming
|
||||
][const_102_66 | SmartOpt Trimming
|
||||
][const_104_67 | SmartOpt Trimming
|
||||
][const_105_68 | SmartOpt Trimming
|
||||
][const_107_69 | SmartOpt Trimming
|
||||
][const_108_70 | SmartOpt Trimming
|
||||
][const_110_71 | SmartOpt Trimming
|
||||
][const_111_72 | SmartOpt Trimming
|
||||
][const_113_73 | SmartOpt Trimming
|
||||
][const_114_74 | SmartOpt Trimming
|
||||
][const_116_75 | SmartOpt Trimming
|
||||
][const_117_76 | SmartOpt Trimming
|
||||
][const_119_77 | SmartOpt Trimming
|
||||
][const_120_78 | SmartOpt Trimming
|
||||
][const_122_79 | SmartOpt Trimming
|
||||
][const_123_80 | SmartOpt Trimming
|
||||
][const_125_81 | SmartOpt Trimming
|
||||
][const_126_82 | SmartOpt Trimming
|
||||
][const_128_83 | SmartOpt Trimming
|
||||
][const_129_84 | SmartOpt Trimming
|
||||
][const_131_85 | SmartOpt Trimming
|
||||
][const_132_86 | SmartOpt Trimming
|
||||
][const_134_87 | SmartOpt Trimming
|
||||
][const_135_88 | SmartOpt Trimming
|
||||
][const_137_89 | SmartOpt Trimming
|
||||
][const_138_90 | SmartOpt Trimming
|
||||
][const_140_91 | SmartOpt Trimming
|
||||
][const_141_92 | SmartOpt Trimming
|
||||
][const_143_93 | SmartOpt Trimming
|
||||
][const_144_94 | SmartOpt Trimming
|
||||
][const_146_95 | SmartOpt Trimming
|
||||
][const_147_96 | SmartOpt Trimming
|
||||
][const_15_8 | SmartOpt Trimming
|
||||
][const_17_9 | SmartOpt Trimming
|
||||
][const_18_10 | SmartOpt Trimming
|
||||
][const_20_11 | SmartOpt Trimming
|
||||
][const_21_12 | SmartOpt Trimming
|
||||
][const_23_13 | SmartOpt Trimming
|
||||
][const_24_14 | SmartOpt Trimming
|
||||
][const_26_15 | SmartOpt Trimming
|
||||
][const_27_16 | SmartOpt Trimming
|
||||
][const_29_17 | SmartOpt Trimming
|
||||
][const_30_18 | SmartOpt Trimming
|
||||
][const_32_19 | SmartOpt Trimming
|
||||
][const_33_20 | SmartOpt Trimming
|
||||
][const_35_21 | SmartOpt Trimming
|
||||
][const_36_22 | SmartOpt Trimming
|
||||
][const_38_23 | SmartOpt Trimming
|
||||
][const_39_24 | SmartOpt Trimming
|
||||
][const_41_25 | SmartOpt Trimming
|
||||
][const_42_26 | SmartOpt Trimming
|
||||
][const_44_27 | SmartOpt Trimming
|
||||
][const_45_28 | SmartOpt Trimming
|
||||
][const_47_29 | SmartOpt Trimming
|
||||
][const_48_30 | SmartOpt Trimming
|
||||
][const_50_31 | SmartOpt Trimming
|
||||
][const_51_32 | SmartOpt Trimming
|
||||
][const_53_33 | SmartOpt Trimming
|
||||
][const_54_34 | SmartOpt Trimming
|
||||
][const_56_35 | SmartOpt Trimming
|
||||
][const_57_36 | SmartOpt Trimming
|
||||
][const_59_37 | SmartOpt Trimming
|
||||
][const_60_38 | SmartOpt Trimming
|
||||
][const_62_39 | SmartOpt Trimming
|
||||
][const_63_40 | SmartOpt Trimming
|
||||
][const_65_41 | SmartOpt Trimming
|
||||
][const_66_42 | SmartOpt Trimming
|
||||
][const_68_43 | SmartOpt Trimming
|
||||
][const_69_44 | SmartOpt Trimming
|
||||
][const_71_45 | SmartOpt Trimming
|
||||
][const_72_46 | SmartOpt Trimming
|
||||
][const_74_47 | SmartOpt Trimming
|
||||
][const_75_48 | SmartOpt Trimming
|
||||
][const_77_49 | SmartOpt Trimming
|
||||
][const_78_50 | SmartOpt Trimming
|
||||
][const_80_51 | SmartOpt Trimming
|
||||
][const_81_52 | SmartOpt Trimming
|
||||
][const_83_53 | SmartOpt Trimming
|
||||
][const_84_54 | SmartOpt Trimming
|
||||
][const_86_55 | SmartOpt Trimming
|
||||
][const_87_56 | SmartOpt Trimming
|
||||
][const_89_57 | SmartOpt Trimming
|
||||
][const_90_58 | SmartOpt Trimming
|
||||
][const_92_59 | SmartOpt Trimming
|
||||
][const_93_60 | SmartOpt Trimming
|
||||
][const_95_61 | SmartOpt Trimming
|
||||
][const_96_62 | SmartOpt Trimming
|
||||
][const_98_63 | SmartOpt Trimming
|
||||
][const_99_64 | SmartOpt Trimming
|
||||
][298_1 | SmartOpt Trimming
|
||||
][301_2 | SmartOpt Trimming
|
||||
][303_4 | SmartOpt Trimming
|
||||
][304_5 | SmartOpt Trimming
|
||||
][339_39 | SmartOpt Trimming
|
||||
][340_40 | SmartOpt Trimming
|
||||
][341_41 | SmartOpt Trimming
|
||||
][342_42 | SmartOpt Trimming
|
||||
][69_43 | SmartOpt Trimming
|
||||
][const_100_101 | SmartOpt Trimming
|
||||
][const_101_102 | SmartOpt Trimming
|
||||
][const_103_103 | SmartOpt Trimming
|
||||
][const_104_104 | SmartOpt Trimming
|
||||
][const_106_105 | SmartOpt Trimming
|
||||
][const_107_106 | SmartOpt Trimming
|
||||
][const_109_107 | SmartOpt Trimming
|
||||
][const_110_108 | SmartOpt Trimming
|
||||
][const_112_109 | SmartOpt Trimming
|
||||
][const_113_110 | SmartOpt Trimming
|
||||
][const_115_111 | SmartOpt Trimming
|
||||
][const_116_112 | SmartOpt Trimming
|
||||
][const_118_113 | SmartOpt Trimming
|
||||
][const_119_114 | SmartOpt Trimming
|
||||
][const_121_115 | SmartOpt Trimming
|
||||
][const_122_116 | SmartOpt Trimming
|
||||
][const_124_117 | SmartOpt Trimming
|
||||
][const_125_118 | SmartOpt Trimming
|
||||
][const_127_119 | SmartOpt Trimming
|
||||
][const_128_120 | SmartOpt Trimming
|
||||
][const_130_121 | SmartOpt Trimming
|
||||
][const_131_122 | SmartOpt Trimming
|
||||
][const_133_123 | SmartOpt Trimming
|
||||
][const_134_124 | SmartOpt Trimming
|
||||
][const_14_44 | SmartOpt Trimming
|
||||
][const_16_45 | SmartOpt Trimming
|
||||
][const_17_46 | SmartOpt Trimming
|
||||
][const_19_47 | SmartOpt Trimming
|
||||
][const_20_48 | SmartOpt Trimming
|
||||
][const_22_49 | SmartOpt Trimming
|
||||
][const_23_50 | SmartOpt Trimming
|
||||
][const_25_51 | SmartOpt Trimming
|
||||
][const_26_52 | SmartOpt Trimming
|
||||
][const_28_53 | SmartOpt Trimming
|
||||
][const_29_54 | SmartOpt Trimming
|
||||
][const_31_55 | SmartOpt Trimming
|
||||
][const_32_56 | SmartOpt Trimming
|
||||
][const_34_57 | SmartOpt Trimming
|
||||
][const_35_58 | SmartOpt Trimming
|
||||
][const_37_59 | SmartOpt Trimming
|
||||
][const_38_60 | SmartOpt Trimming
|
||||
][const_40_61 | SmartOpt Trimming
|
||||
][const_41_62 | SmartOpt Trimming
|
||||
][const_43_63 | SmartOpt Trimming
|
||||
][const_44_64 | SmartOpt Trimming
|
||||
][const_46_65 | SmartOpt Trimming
|
||||
][const_47_66 | SmartOpt Trimming
|
||||
][const_49_67 | SmartOpt Trimming
|
||||
][const_50_68 | SmartOpt Trimming
|
||||
][const_52_69 | SmartOpt Trimming
|
||||
][const_53_70 | SmartOpt Trimming
|
||||
][const_55_71 | SmartOpt Trimming
|
||||
][const_56_72 | SmartOpt Trimming
|
||||
][const_58_73 | SmartOpt Trimming
|
||||
][const_59_74 | SmartOpt Trimming
|
||||
][const_61_75 | SmartOpt Trimming
|
||||
][const_62_76 | SmartOpt Trimming
|
||||
][const_64_77 | SmartOpt Trimming
|
||||
][const_65_78 | SmartOpt Trimming
|
||||
][const_67_79 | SmartOpt Trimming
|
||||
][const_68_80 | SmartOpt Trimming
|
||||
][const_70_81 | SmartOpt Trimming
|
||||
][const_71_82 | SmartOpt Trimming
|
||||
][const_73_83 | SmartOpt Trimming
|
||||
][const_74_84 | SmartOpt Trimming
|
||||
][const_76_85 | SmartOpt Trimming
|
||||
][const_77_86 | SmartOpt Trimming
|
||||
][const_79_87 | SmartOpt Trimming
|
||||
][const_80_88 | SmartOpt Trimming
|
||||
][const_82_89 | SmartOpt Trimming
|
||||
][const_83_90 | SmartOpt Trimming
|
||||
][const_85_91 | SmartOpt Trimming
|
||||
][const_86_92 | SmartOpt Trimming
|
||||
][const_88_93 | SmartOpt Trimming
|
||||
][const_89_94 | SmartOpt Trimming
|
||||
][const_91_95 | SmartOpt Trimming
|
||||
][const_92_96 | SmartOpt Trimming
|
||||
][const_94_97 | SmartOpt Trimming
|
||||
][const_95_98 | SmartOpt Trimming
|
||||
][const_97_99 | SmartOpt Trimming
|
||||
][const_98_100 | SmartOpt Trimming
|
||||
|
||||
|
||||
Flops added for Enable Generation
|
||||
|
||||
@ -5,14 +5,14 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Map" timeStamp="Mon Nov 01 06:10:39 2021">
|
||||
<application stringID="Map" timeStamp="Tue Nov 02 00:33:32 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files\Microchip\xc8\v2.31\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\PuTTY\;C:\Program Files\WinMerge;C:\Program Files\dotnet\;C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;C:\Users\zanek\AppData\Local\GitHubDesktop\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\zanek\.dotnet\tools;C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt;C:\Xilinx\14.7\ISE_DS\common\lib\nt;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\PuTTY\;C:\Program Files (x86)\WinMerge;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\Microchip\xc8\v2.31\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\Dog\AppData\Local\GitHubDesktop\bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
@ -36,16 +36,16 @@
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
|
||||
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="ZanePC"/>
|
||||
<item stringID="User_EnvHost" value="Dog-PC"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz"/>
|
||||
<item stringID="speed" value="3500 MHz"/>
|
||||
<item stringID="arch" value="Intel(R) Xeon(R) CPU W3680 @ 3.33GHz"/>
|
||||
<item stringID="speed" value="3316 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
@ -76,10 +76,10 @@
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="89">
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="105">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="1"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="7"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="1"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="17"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
|
||||
@ -99,7 +99,7 @@
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="34"/>
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="66"/>
|
||||
<item AVAILABLE="14" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="5"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
|
||||
@ -122,9 +122,9 @@
|
||||
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
|
||||
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="293380"/>
|
||||
<item stringID="MAP_TOTAL_REAL_TIME" value="10 secs "/>
|
||||
<item stringID="MAP_TOTAL_CPU_TIME" value="8 secs "/>
|
||||
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="290188"/>
|
||||
<item stringID="MAP_TOTAL_REAL_TIME" value="22 secs "/>
|
||||
<item stringID="MAP_TOTAL_CPU_TIME" value="22 secs "/>
|
||||
</section>
|
||||
<section stringID="MAP_SLICE_REPORTING">
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="1">
|
||||
@ -133,10 +133,10 @@
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="89">
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="105">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="1"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="7"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="1"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="17"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
|
||||
@ -156,19 +156,19 @@
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="23">
|
||||
<item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="35">
|
||||
<item AVAILABLE="355" dataType="int" stringID="MAP_NUM_SLICEL" value="2"/>
|
||||
<item AVAILABLE="360" dataType="int" stringID="MAP_NUM_SLICEM" value="20"/>
|
||||
<item AVAILABLE="715" dataType="int" stringID="MAP_NUM_SLICEX" value="1"/>
|
||||
<item AVAILABLE="715" dataType="int" stringID="MAP_NUM_SLICEX" value="13"/>
|
||||
</item>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="89">
|
||||
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="88"/>
|
||||
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="0"/>
|
||||
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="1"/>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="106">
|
||||
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="105"/>
|
||||
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="1"/>
|
||||
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="0"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="MAP_IOB_REPORTING">
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="34"/>
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="66"/>
|
||||
<item AVAILABLE="14" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="5"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
|
||||
@ -183,7 +183,7 @@
|
||||
</section>
|
||||
<section stringID="MAP_HARD_IP_REPORTING"/>
|
||||
<section stringID="MAP_RAM_FIFO_DATA">
|
||||
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
|
||||
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="4"/>
|
||||
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_IP_DATA">
|
||||
@ -415,18 +415,274 @@
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="31">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<26>"/>
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<28>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="32">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<27>"/>
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<30>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="33">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<0>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="34">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<1>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="35">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<2>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="36">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<3>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="37">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<4>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="38">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<5>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="39">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<6>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="40">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<7>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="41">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<8>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="42">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<9>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="43">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<10>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="44">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<11>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="45">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<12>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="46">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<13>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="47">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<14>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="48">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<15>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="49">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<16>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="50">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<17>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="51">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<18>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="52">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<19>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="53">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<20>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="54">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<21>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="55">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<22>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="56">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<23>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="57">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<24>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="58">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<25>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="59">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<26>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="60">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<27>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="61">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<28>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="62">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<29>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="63">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<30>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="64">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<31>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="65">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RAMCLK0"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
@ -435,7 +691,7 @@
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="ODDR"/>
|
||||
</row>
|
||||
<row stringID="row" value="34">
|
||||
<row stringID="row" value="66">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RAMCLK1"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
@ -494,7 +750,7 @@
|
||||
</section>
|
||||
</task>
|
||||
<section stringID="MAP_RAM_FIFO_DATA">
|
||||
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
|
||||
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="4"/>
|
||||
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_IP_DATA">
|
||||
|
||||
@ -5,14 +5,14 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Mon Nov 01 06:10:26 2021">
|
||||
<application stringID="NgdBuild" timeStamp="Tue Nov 02 00:33:07 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files\Microchip\xc8\v2.31\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\PuTTY\;C:\Program Files\WinMerge;C:\Program Files\dotnet\;C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;C:\Users\zanek\AppData\Local\GitHubDesktop\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\zanek\.dotnet\tools;C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt;C:\Xilinx\14.7\ISE_DS\common\lib\nt;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\PuTTY\;C:\Program Files (x86)\WinMerge;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\Microchip\xc8\v2.31\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\Dog\AppData\Local\GitHubDesktop\bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
@ -36,16 +36,16 @@
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
|
||||
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="ZanePC"/>
|
||||
<item stringID="User_EnvHost" value="Dog-PC"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz"/>
|
||||
<item stringID="speed" value="3500 MHz"/>
|
||||
<item stringID="arch" value="Intel(R) Xeon(R) CPU W3680 @ 3.33GHz"/>
|
||||
<item stringID="speed" value="3316 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
@ -62,57 +62,69 @@
|
||||
<section stringID="NGDBUILD_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="73"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="13"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFIO2FB" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="44"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="40"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="26"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="32"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="8"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="38"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ODDR2" value="5"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAM128X1D" value="22"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAM128X1D" value="20"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16BWER" value="28"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFIO2FB" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="44"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="40"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="26"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="32"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="8"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="38"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ODDR2" value="5"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_PLL_ADV" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16BWER" value="28"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_CORE_SUMMARY">
|
||||
<item COUNT="1" stringID="NGDBUILD_CORE" value="dist_mem_gen_v7_2, Xilinx CORE Generator 14.7"/>
|
||||
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
|
||||
<section stringID="NGDBUILD_CORE_INSTANCES">
|
||||
<scope stringID="NGDBUILD_CORE_INSTANCE" value="L2WayRAM">
|
||||
<item stringID="NGDBUILD_CORE_INFO" type="blk_mem_gen_v7_3" value="L2WayRAM"/>
|
||||
<item c_addra_width="10" c_addrb_width="10" c_algorithm="1" c_axi_id_width="4" c_axi_slave_type="0" c_axi_type="1" c_byte_size="9" c_common_clk="1" c_default_data="0" c_disable_warn_bhv_coll="0" c_disable_warn_bhv_range="0" c_elaboration_dir="masked_value" c_enable_32bit_address="0" c_family="spartan6" c_has_axi_id="0" c_has_ena="1" c_has_enb="1" c_has_injecterr="0" c_has_mem_output_regs_a="0" c_has_mem_output_regs_b="0" c_has_mux_output_regs_a="0" c_has_mux_output_regs_b="0" c_has_regcea="0" c_has_regceb="0" c_has_rsta="0" c_has_rstb="0" c_has_softecc_input_regs_a="0" c_has_softecc_output_regs_b="0" c_init_file="BlankString" c_init_file_name="no_coe_file_loaded" c_inita_val="0" c_initb_val="0" c_interface_type="0" c_load_init_file="0" c_mem_type="2" c_mux_pipeline_stages="0" c_prim_type="1" c_read_depth_a="1024" c_read_depth_b="1024" c_read_width_a="47" c_read_width_b="47" c_rst_priority_a="CE" c_rst_priority_b="CE" c_rst_type="SYNC" c_rstram_a="0" c_rstram_b="0" c_sim_collision_check="ALL" c_use_bram_block="0" c_use_byte_wea="0" c_use_byte_web="0" c_use_default_data="0" c_use_ecc="0" c_use_softecc="0" c_wea_width="1" c_web_width="1" c_write_depth_a="1024" c_write_depth_b="1024" c_write_mode_a="READ_FIRST" c_write_mode_b="READ_FIRST" c_write_width_a="47" c_write_width_b="47" c_xdevicefamily="spartan6" stringID="NGDBUILD_CORE_PARAMETERS" value="L2WayRAM"/>
|
||||
</scope>
|
||||
<scope stringID="NGDBUILD_CORE_INSTANCE" value="PLL">
|
||||
<item stringID="NGDBUILD_CORE_INFO" type="clk_wiz_v3_6" value="PLL"/>
|
||||
<item clkin1_period="30.000" clkin2_period="30.000" clock_mgr_type="MANUAL" component_name="PLL" feedback_source="FDBK_AUTO_OFFCHIP" feedback_type="SINGLE" manual_override="false" num_out_clk="1" primtype_sel="PLL_BASE" stringID="NGDBUILD_CORE_PARAMETERS" use_clk_valid="false" use_dyn_phase_shift="false" use_dyn_reconfig="false" use_freeze="false" use_inclk_stopped="false" use_inclk_switchover="false" use_locked="true" use_max_i_jitter="false" use_min_o_jitter="true" use_phase_alignment="true" use_power_down="false" use_reset="false" use_status="false" value="PLL"/>
|
||||
</scope>
|
||||
<scope stringID="NGDBUILD_CORE_INSTANCE" value="PrefetchDataRAM">
|
||||
<item stringID="NGDBUILD_CORE_INFO" type="blk_mem_gen_v7_3" value="PrefetchDataRAM"/>
|
||||
<item c_addra_width="11" c_addrb_width="11" c_algorithm="1" c_axi_id_width="4" c_axi_slave_type="0" c_axi_type="1" c_byte_size="8" c_common_clk="1" c_default_data="0" c_disable_warn_bhv_coll="0" c_disable_warn_bhv_range="0" c_elaboration_dir="masked_value" c_enable_32bit_address="0" c_family="spartan6" c_has_axi_id="0" c_has_ena="1" c_has_enb="1" c_has_injecterr="0" c_has_mem_output_regs_a="0" c_has_mem_output_regs_b="0" c_has_mux_output_regs_a="0" c_has_mux_output_regs_b="0" c_has_regcea="0" c_has_regceb="0" c_has_rsta="0" c_has_rstb="0" c_has_softecc_input_regs_a="0" c_has_softecc_output_regs_b="0" c_init_file="BlankString" c_init_file_name="no_coe_file_loaded" c_inita_val="0" c_initb_val="0" c_interface_type="0" c_load_init_file="0" c_mem_type="2" c_mux_pipeline_stages="0" c_prim_type="1" c_read_depth_a="2048" c_read_depth_b="2048" c_read_width_a="32" c_read_width_b="32" c_rst_priority_a="CE" c_rst_priority_b="CE" c_rst_type="SYNC" c_rstram_a="0" c_rstram_b="0" c_sim_collision_check="ALL" c_use_bram_block="0" c_use_byte_wea="1" c_use_byte_web="1" c_use_default_data="0" c_use_ecc="0" c_use_softecc="0" c_wea_width="4" c_web_width="4" c_write_depth_a="2048" c_write_depth_b="2048" c_write_mode_a="READ_FIRST" c_write_mode_b="READ_FIRST" c_write_width_a="32" c_write_width_b="32" c_xdevicefamily="spartan6" stringID="NGDBUILD_CORE_PARAMETERS" value="PrefetchDataRAM"/>
|
||||
</scope>
|
||||
<scope stringID="NGDBUILD_CORE_INSTANCE" value="PrefetchTagRAM">
|
||||
<item stringID="NGDBUILD_CORE_INFO" type="dist_mem_gen_v7_2" value="PrefetchTagRAM"/>
|
||||
<item c_addr_width="7" c_default_data="0" c_depth="128" c_elaboration_dir="masked_value" c_family="spartan6" c_has_clk="1" c_has_d="1" c_has_dpo="1" c_has_dpra="1" c_has_i_ce="0" c_has_qdpo="0" c_has_qdpo_ce="0" c_has_qdpo_clk="0" c_has_qdpo_rst="0" c_has_qdpo_srst="0" c_has_qspo="0" c_has_qspo_ce="0" c_has_qspo_rst="0" c_has_qspo_srst="0" c_has_spo="1" c_has_spra="0" c_has_we="1" c_mem_init_file="no_coe_file_loaded" c_mem_type="2" c_parser_type="1" c_pipeline_stages="0" c_qce_joined="0" c_qualify_we="0" c_read_mif="0" c_reg_a_d_inputs="0" c_reg_dpra_input="0" c_sync_enable="1" c_width="22" stringID="NGDBUILD_CORE_PARAMETERS" value="PrefetchTagRAM"/>
|
||||
<item c_addr_width="7" c_default_data="0" c_depth="128" c_elaboration_dir="masked_value" c_family="spartan6" c_has_clk="1" c_has_d="1" c_has_dpo="1" c_has_dpra="1" c_has_i_ce="0" c_has_qdpo="0" c_has_qdpo_ce="0" c_has_qdpo_clk="0" c_has_qdpo_rst="0" c_has_qdpo_srst="0" c_has_qspo="0" c_has_qspo_ce="0" c_has_qspo_rst="0" c_has_qspo_srst="0" c_has_spo="1" c_has_spra="0" c_has_we="1" c_mem_init_file="no_coe_file_loaded" c_mem_type="2" c_parser_type="1" c_pipeline_stages="0" c_qce_joined="0" c_qualify_we="0" c_read_mif="0" c_reg_a_d_inputs="0" c_reg_dpra_input="0" c_sync_enable="1" c_width="20" stringID="NGDBUILD_CORE_PARAMETERS" value="PrefetchTagRAM"/>
|
||||
</scope>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
#Release 14.7 - par P.20131013 (nt)
|
||||
#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
#Mon Nov 01 06:10:44 2021
|
||||
#Tue Nov 02 00:29:15 2021
|
||||
|
||||
#
|
||||
## NOTE: This file is designed to be imported into a spreadsheet program
|
||||
@ -22,137 +22,137 @@ Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,D
|
||||
A1,,,GND,,,,,,,,,,,,
|
||||
A2,,IOBS,IO_L52N_M3A9_3,UNUSED,,3,,,,,,,,,
|
||||
A3,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,,
|
||||
A4,,IOBS,IO_L1N_VREF_0,UNUSED,,0,,,,,,,,,
|
||||
A5,,IOBS,IO_L2N_0,UNUSED,,0,,,,,,,,,
|
||||
A6,,IOBS,IO_L4N_0,UNUSED,,0,,,,,,,,,
|
||||
A7,,IOBS,IO_L6N_0,UNUSED,,0,,,,,,,,,
|
||||
A8,,IOBS,IO_L33N_0,UNUSED,,0,,,,,,,,,
|
||||
A9,,IOBS,IO_L34N_GCLK18_0,UNUSED,,0,,,,,,,,,
|
||||
A10,,IOBS,IO_L35N_GCLK16_0,UNUSED,,0,,,,,,,,,
|
||||
A11,,IOBS,IO_L39N_0,UNUSED,,0,,,,,,,,,
|
||||
A12,,IOBS,IO_L62N_VREF_0,UNUSED,,0,,,,,,,,,
|
||||
A13,,IOBS,IO_L63N_SCP6_0,UNUSED,,0,,,,,,,,,
|
||||
A14,,IOBS,IO_L65N_SCP2_0,UNUSED,,0,,,,,,,,,
|
||||
A4,RAMCLK0,IOB,IO_L1N_VREF_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
A5,FSB_D<0>,IOB,IO_L2N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A6,FSB_D<4>,IOB,IO_L4N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A7,FSB_D<8>,IOB,IO_L6N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A8,FSB_D<12>,IOB,IO_L33N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A9,FSB_D<14>,IOB,IO_L34N_GCLK18_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A10,FSB_D<16>,IOB,IO_L35N_GCLK16_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A11,FSB_D<24>,IOB,IO_L39N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A12,FSB_D<28>,IOB,IO_L62N_VREF_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A13,CPU_nSTERM,IOB,IO_L63N_SCP6_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,NO,NONE,
|
||||
A14,RAMCLK1,IOB,IO_L65N_SCP2_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
A15,,,TMS,,,,,,,,,,,,
|
||||
A16,,,GND,,,,,,,,,,,,
|
||||
B1,,IOBS,IO_L50N_M3BA2_3,UNUSED,,3,,,,,,,,,
|
||||
B2,,IOBM,IO_L52P_M3A8_3,UNUSED,,3,,,,,,,,,
|
||||
B3,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,,
|
||||
B4,,,VCCO_0,,,0,,,,,any******,,,,
|
||||
B5,,IOBM,IO_L2P_0,UNUSED,,0,,,,,,,,,
|
||||
B6,,IOBM,IO_L4P_0,UNUSED,,0,,,,,,,,,
|
||||
B4,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
B5,FPUCLK,IOB,IO_L2P_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
B6,FSB_D<3>,IOB,IO_L4P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
B7,,,GND,,,,,,,,,,,,
|
||||
B8,,IOBM,IO_L33P_0,UNUSED,,0,,,,,,,,,
|
||||
B9,,,VCCO_0,,,0,,,,,any******,,,,
|
||||
B10,,IOBM,IO_L35P_GCLK17_0,UNUSED,,0,,,,,,,,,
|
||||
B8,FSB_D<11>,IOB,IO_L33P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
B9,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
B10,FSB_D<19>,IOB,IO_L35P_GCLK17_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
B11,,,GND,,,,,,,,,,,,
|
||||
B12,,IOBM,IO_L62P_0,UNUSED,,0,,,,,,,,,
|
||||
B13,,,VCCO_0,,,0,,,,,any******,,,,
|
||||
B14,,IOBM,IO_L65P_SCP3_0,UNUSED,,0,,,,,,,,,
|
||||
B15,,IOBM,IO_L29P_A23_M1A13_1,UNUSED,,1,,,,,,,,,
|
||||
B16,,IOBS,IO_L29N_A22_M1A14_1,UNUSED,,1,,,,,,,,,
|
||||
B12,FSB_D<27>,IOB,IO_L62P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
B13,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
B14,FSB_A<2>,IOB,IO_L65P_SCP3_0,INPUT,LVCMOS33,0,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
B15,FSB_A<6>,IOB,IO_L29P_A23_M1A13_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
B16,FSB_A<7>,IOB,IO_L29N_A22_M1A14_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
C1,,IOBM,IO_L50P_M3WE_3,UNUSED,,3,,,,,,,,,
|
||||
C2,,IOBS,IO_L48N_M3BA1_3,UNUSED,,3,,,,,,,,,
|
||||
C3,,IOBM,IO_L48P_M3BA0_3,UNUSED,,3,,,,,,,,,
|
||||
C4,,IOBM,IO_L1P_HSWAPEN_0,UNUSED,,0,,,,,,,,,
|
||||
C5,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,,
|
||||
C6,,IOBS,IO_L7N_0,UNUSED,,0,,,,,,,,,
|
||||
C7,,IOBM,IO_L6P_0,UNUSED,,0,,,,,,,,,
|
||||
C8,,IOBS,IO_L38N_VREF_0,UNUSED,,0,,,,,,,,,
|
||||
C9,,IOBM,IO_L34P_GCLK19_0,UNUSED,,0,,,,,,,,,
|
||||
C10,,IOBS,IO_L37N_GCLK12_0,UNUSED,,0,,,,,,,,,
|
||||
C11,,IOBM,IO_L39P_0,UNUSED,,0,,,,,,,,,
|
||||
C4,CLKFB_OUT,IOB,IO_L1P_HSWAPEN_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
C5,FSB_D<2>,IOB,IO_L3N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C6,FSB_D<10>,IOB,IO_L7N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C7,FSB_D<7>,IOB,IO_L6P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C8,FSB_D<18>,IOB,IO_L38N_VREF_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C9,FSB_D<13>,IOB,IO_L34P_GCLK19_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C10,FSB_D<20>,IOB,IO_L37N_GCLK12_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C11,FSB_D<23>,IOB,IO_L39P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C12,,,TDI,,,,,,,,,,,,
|
||||
C13,,IOBM,IO_L63P_SCP7_0,UNUSED,,0,,,,,,,,,
|
||||
C13,FSB_D<21>,IOB,IO_L63P_SCP7_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C14,,,TCK,,,,,,,,,,,,
|
||||
C15,,IOBM,IO_L33P_A15_M1A10_1,UNUSED,,1,,,,,,,,,
|
||||
C16,,IOBS,IO_L33N_A14_M1A4_1,UNUSED,,1,,,,,,,,,
|
||||
C15,FSB_A<14>,IOB,IO_L33P_A15_M1A10_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
C16,FSB_A<15>,IOB,IO_L33N_A14_M1A4_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
D1,,IOBS,IO_L49N_M3A2_3,UNUSED,,3,,,,,,,,,
|
||||
D2,,,VCCO_3,,,3,,,,,3.30,,,,
|
||||
D2,,,VCCO_3,,,3,,,,,any******,,,,
|
||||
D3,,IOBM,IO_L49P_M3A7_3,UNUSED,,3,,,,,,,,,
|
||||
D4,,,GND,,,,,,,,,,,,
|
||||
D5,,IOBM,IO_L3P_0,UNUSED,,0,,,,,,,,,
|
||||
D6,,IOBM,IO_L7P_0,UNUSED,,0,,,,,,,,,
|
||||
D7,,,VCCO_0,,,0,,,,,any******,,,,
|
||||
D8,,IOBM,IO_L38P_0,UNUSED,,0,,,,,,,,,
|
||||
D9,,IOBS,IO_L40N_0,UNUSED,,0,,,,,,,,,
|
||||
D10,,,VCCO_0,,,0,,,,,any******,,,,
|
||||
D11,,IOBM,IO_L66P_SCP1_0,UNUSED,,0,,,,,,,,,
|
||||
D12,,IOBS,IO_L66N_SCP0_0,UNUSED,,0,,,,,,,,,
|
||||
D5,FSB_D<1>,IOB,IO_L3P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
D6,FSB_D<9>,IOB,IO_L7P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
D7,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
D8,FSB_D<25>,IOB,IO_L38P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
D9,FSB_D<22>,IOB,IO_L40N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
D10,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
D11,FSB_D<29>,IOB,IO_L66P_SCP1_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
D12,FSB_A<3>,IOB,IO_L66N_SCP0_0,INPUT,LVCMOS33,0,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
D13,,,GND,,,,,,,,,,,,
|
||||
D14,,IOBM,IO_L31P_A19_M1CKE_1,UNUSED,,1,,,,,,,,,
|
||||
D14,FSB_A<10>,IOB,IO_L31P_A19_M1CKE_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
D15,,,VCCO_1,,,1,,,,,any******,,,,
|
||||
D16,,IOBS,IO_L31N_A18_M1A12_1,UNUSED,,1,,,,,,,,,
|
||||
E1,FPUCLK,IOB,IO_L46N_M3CLKN_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
E2,CPUCLK,IOB,IO_L46P_M3CLK_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
D16,FSB_A<11>,IOB,IO_L31N_A18_M1A12_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
E1,,IOBS,IO_L46N_M3CLKN_3,UNUSED,,3,,,,,,,,,
|
||||
E2,,IOBM,IO_L46P_M3CLK_3,UNUSED,,3,,,,,,,,,
|
||||
E3,,IOBS,IO_L54N_M3A11_3,UNUSED,,3,,,,,,,,,
|
||||
E4,,IOBM,IO_L54P_M3RESET_3,UNUSED,,3,,,,,,,,,
|
||||
E5,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
E6,,IOBS,IO_L5N_0,UNUSED,,0,,,,,,,,,
|
||||
E7,,IOBM,IO_L36P_GCLK15_0,UNUSED,,0,,,,,,,,,
|
||||
E8,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,,
|
||||
E6,FSB_D<6>,IOB,IO_L5N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
E7,FSB_D<17>,IOB,IO_L36P_GCLK15_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
E8,FSB_D<26>,IOB,IO_L36N_GCLK14_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
E9,,,GND,,,,,,,,,,,,
|
||||
E10,,IOBM,IO_L37P_GCLK13_0,UNUSED,,0,,,,,,,,,
|
||||
E11,,IOBS,IO_L64N_SCP4_0,UNUSED,,0,,,,,,,,,
|
||||
E12,,IOBS,IO_L1N_A24_VREF_1,UNUSED,,1,,,,,,,,,
|
||||
E13,,IOBM,IO_L1P_A25_1,UNUSED,,1,,,,,,,,,
|
||||
E10,FSB_D<15>,IOB,IO_L37P_GCLK13_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
E11,FSB_D<30>,IOB,IO_L64N_SCP4_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
E12,FSB_A<5>,IOB,IO_L1N_A24_VREF_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
E13,FSB_A<4>,IOB,IO_L1P_A25_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
E14,,,TDO,,,,,,,,,,,,
|
||||
E15,,IOBM,IO_L34P_A13_M1WE_1,UNUSED,,1,,,,,,,,,
|
||||
E16,,IOBS,IO_L34N_A12_M1BA2_1,UNUSED,,1,,,,,,,,,
|
||||
F1,FSB_A<25>,IOB,IO_L41N_GCLK26_M3DQ5_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
F2,FSB_A<24>,IOB,IO_L41P_GCLK27_M3DQ4_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
E15,FSB_A<16>,IOB,IO_L34P_A13_M1WE_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
E16,FSB_A<17>,IOB,IO_L34N_A12_M1BA2_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
F1,,IOBS,IO_L41N_GCLK26_M3DQ5_3,UNUSED,,3,,,,,,,,,
|
||||
F2,,IOBM,IO_L41P_GCLK27_M3DQ4_3,UNUSED,,3,,,,,,,,,
|
||||
F3,,IOBS,IO_L53N_M3A12_3,UNUSED,,3,,,,,,,,,
|
||||
F4,,IOBM,IO_L53P_M3CKE_3,UNUSED,,3,,,,,,,,,
|
||||
F5,,IOBS,IO_L55N_M3A14_3,UNUSED,,3,,,,,,,,,
|
||||
F6,,IOBM,IO_L55P_M3A13_3,UNUSED,,3,,,,,,,,,
|
||||
F7,,IOBM,IO_L5P_0,UNUSED,,0,,,,,,,,,
|
||||
F7,FSB_D<5>,IOB,IO_L5P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
F8,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
F9,,IOBM,IO_L40P_0,UNUSED,,0,,,,,,,,,
|
||||
F10,,IOBM,IO_L64P_SCP5_0,UNUSED,,0,,,,,,,,,
|
||||
F9,CPUCLK,IOB,IO_L40P_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
F10,FSB_D<31>,IOB,IO_L64P_SCP5_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
F11,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
F12,,IOBM,IO_L30P_A21_M1RESET_1,UNUSED,,1,,,,,,,,,
|
||||
F13,,IOBM,IO_L32P_A17_M1A8_1,UNUSED,,1,,,,,,,,,
|
||||
F14,,IOBS,IO_L32N_A16_M1A9_1,UNUSED,,1,,,,,,,,,
|
||||
F15,,IOBM,IO_L35P_A11_M1A7_1,UNUSED,,1,,,,,,,,,
|
||||
F16,,IOBS,IO_L35N_A10_M1A2_1,UNUSED,,1,,,,,,,,,
|
||||
G1,FSB_A<23>,IOB,IO_L40N_M3DQ7_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
F12,FSB_A<8>,IOB,IO_L30P_A21_M1RESET_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
F13,FSB_A<12>,IOB,IO_L32P_A17_M1A8_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
F14,FSB_A<13>,IOB,IO_L32N_A16_M1A9_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
F15,FSB_A<18>,IOB,IO_L35P_A11_M1A7_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
F16,FSB_A<19>,IOB,IO_L35N_A10_M1A2_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
G1,,IOBS,IO_L40N_M3DQ7_3,UNUSED,,3,,,,,,,,,
|
||||
G2,,,GND,,,,,,,,,,,,
|
||||
G3,FSB_A<22>,IOB,IO_L40P_M3DQ6_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
G4,,,VCCO_3,,,3,,,,,3.30,,,,
|
||||
G3,,IOBM,IO_L40P_M3DQ6_3,UNUSED,,3,,,,,,,,,
|
||||
G4,,,VCCO_3,,,3,,,,,any******,,,,
|
||||
G5,,IOBS,IO_L51N_M3A4_3,UNUSED,,3,,,,,,,,,
|
||||
G6,,IOBM,IO_L51P_M3A10_3,UNUSED,,3,,,,,,,,,
|
||||
G7,,,VCCINT,,,,,,,,1.2,,,,
|
||||
G8,,,GND,,,,,,,,,,,,
|
||||
G9,,,VCCINT,,,,,,,,1.2,,,,
|
||||
G10,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
G11,,IOBS,IO_L30N_A20_M1A11_1,UNUSED,,1,,,,,,,,,
|
||||
G12,,IOBM,IO_L38P_A5_M1CLK_1,UNUSED,,1,,,,,,,,,
|
||||
G11,FSB_A<9>,IOB,IO_L30N_A20_M1A11_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
G12,FSB_A<24>,IOB,IO_L38P_A5_M1CLK_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
G13,,,VCCO_1,,,1,,,,,any******,,,,
|
||||
G14,,IOBM,IO_L36P_A9_M1BA0_1,UNUSED,,1,,,,,,,,,
|
||||
G14,FSB_A<20>,IOB,IO_L36P_A9_M1BA0_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
G15,,,GND,,,,,,,,,,,,
|
||||
G16,,IOBS,IO_L36N_A8_M1BA1_1,UNUSED,,1,,,,,,,,,
|
||||
H1,FSB_A<21>,IOB,IO_L39N_M3LDQSN_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H2,FSB_A<20>,IOB,IO_L39P_M3LDQS_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H3,RAMCLK0,IOB,IO_L44N_GCLK20_M3A6_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
G16,FSB_A<21>,IOB,IO_L36N_A8_M1BA1_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H1,,IOBS,IO_L39N_M3LDQSN_3,UNUSED,,3,,,,,,,,,
|
||||
H2,,IOBM,IO_L39P_M3LDQS_3,UNUSED,,3,,,,,,,,,
|
||||
H3,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,,
|
||||
H4,CLKFB_IN,IOB,IO_L44P_GCLK21_M3A5_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H5,CPU_nSTERM,IOB,IO_L43N_GCLK22_IRDY2_M3CASN_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,NO,NONE,
|
||||
H5,,IOBS,IO_L43N_GCLK22_IRDY2_M3CASN_3,UNUSED,,3,,,,,,,,,
|
||||
H6,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
H7,,,GND,,,,,,,,,,,,
|
||||
H8,,,VCCINT,,,,,,,,1.2,,,,
|
||||
H9,,,GND,,,,,,,,,,,,
|
||||
H10,,,VCCINT,,,,,,,,1.2,,,,
|
||||
H11,,IOBS,IO_L38N_A4_M1CLKN_1,UNUSED,,1,,,,,,,,,
|
||||
H11,FSB_A<25>,IOB,IO_L38N_A4_M1CLKN_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H12,,,GND,,,,,,,,,,,,
|
||||
H13,,IOBM,IO_L39P_M1A3_1,UNUSED,,1,,,,,,,,,
|
||||
H14,,IOBS,IO_L39N_M1ODT_1,UNUSED,,1,,,,,,,,,
|
||||
H15,,IOBM,IO_L37P_A7_M1A0_1,UNUSED,,1,,,,,,,,,
|
||||
H16,,IOBS,IO_L37N_A6_M1A1_1,UNUSED,,1,,,,,,,,,
|
||||
J1,FSB_A<19>,IOB,IO_L38N_M3DQ3_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
J2,,,VCCO_3,,,3,,,,,3.30,,,,
|
||||
J3,FSB_A<18>,IOB,IO_L38P_M3DQ2_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H13,FSB_A<28>,IOB,IO_L39P_M1A3_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H14,FSB_A<30>,IOB,IO_L39N_M1ODT_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H15,FSB_A<22>,IOB,IO_L37P_A7_M1A0_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H16,FSB_A<23>,IOB,IO_L37N_A6_M1A1_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
J1,,IOBS,IO_L38N_M3DQ3_3,UNUSED,,3,,,,,,,,,
|
||||
J2,,,VCCO_3,,,3,,,,,any******,,,,
|
||||
J3,,IOBM,IO_L38P_M3DQ2_3,UNUSED,,3,,,,,,,,,
|
||||
J4,CLKIN,IOB,IO_L42N_GCLK24_M3LDM_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
J5,,,GND,,,,,,,,,,,,
|
||||
J6,FSB_A<27>,IOB,IO_L43P_GCLK23_M3RASN_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
J6,,IOBM,IO_L43P_GCLK23_M3RASN_3,UNUSED,,3,,,,,,,,,
|
||||
J7,,,VCCINT,,,,,,,,1.2,,,,
|
||||
J8,,,GND,,,,,,,,,,,,
|
||||
J9,,,VCCINT,,,,,,,,1.2,,,,
|
||||
@ -163,10 +163,10 @@ J13,,IOBM,IO_L41P_GCLK9_IRDY1_M1RASN_1,UNUSED,,1,,,,,,,,,
|
||||
J14,,IOBM,IO_L43P_GCLK5_M1DQ4_1,UNUSED,,1,,,,,,,,,
|
||||
J15,,,VCCO_1,,,1,,,,,any******,,,,
|
||||
J16,,IOBS,IO_L43N_GCLK4_M1DQ5_1,UNUSED,,1,,,,,,,,,
|
||||
K1,FSB_A<17>,IOB,IO_L37N_M3DQ1_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
K2,FSB_A<16>,IOB,IO_L37P_M3DQ0_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
K3,FSB_A<26>,IOB,IO_L42P_GCLK25_TRDY2_M3UDM_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
K4,,,VCCO_3,,,3,,,,,3.30,,,,
|
||||
K1,,IOBS,IO_L37N_M3DQ1_3,UNUSED,,3,,,,,,,,,
|
||||
K2,,IOBM,IO_L37P_M3DQ0_3,UNUSED,,3,,,,,,,,,
|
||||
K3,,IOBM,IO_L42P_GCLK25_TRDY2_M3UDM_3,UNUSED,,3,,,,,,,,,
|
||||
K4,,,VCCO_3,,,3,,,,,any******,,,,
|
||||
K5,,IOBM,IO_L47P_M3A0_3,UNUSED,,3,,,,,,,,,
|
||||
K6,,IOBS,IO_L47N_M3A1_3,UNUSED,,3,,,,,,,,,
|
||||
K7,,,GND,,,,,,,,,,,,
|
||||
@ -179,11 +179,11 @@ K13,,,VCCO_1,,,1,,,,,any******,,,,
|
||||
K14,,IOBS,IO_L41N_GCLK8_M1CASN_1,UNUSED,,1,,,,,,,,,
|
||||
K15,,IOBM,IO_L44P_A3_M1DQ6_1,UNUSED,,1,,,,,,,,,
|
||||
K16,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,,
|
||||
L1,FSB_A<15>,IOB,IO_L36N_M3DQ9_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
L1,,IOBS,IO_L36N_M3DQ9_3,UNUSED,,3,,,,,,,,,
|
||||
L2,,,GND,,,,,,,,,,,,
|
||||
L3,FSB_A<14>,IOB,IO_L36P_M3DQ8_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
L4,CLKFB_OUT,IOB,IO_L45P_M3A3_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
L5,RAMCLK1,IOB,IO_L45N_M3ODT_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
L3,,IOBM,IO_L36P_M3DQ8_3,UNUSED,,3,,,,,,,,,
|
||||
L4,,IOBM,IO_L45P_M3A3_3,UNUSED,,3,,,,,,,,,
|
||||
L5,,IOBS,IO_L45N_M3ODT_3,UNUSED,,3,,,,,,,,,
|
||||
L6,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
L7,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,,
|
||||
L8,,IOBM,IO_L62P_D5_2,UNUSED,,2,,,,,,,,,
|
||||
@ -195,11 +195,11 @@ L13,,IOBS,IO_L53N_VREF_1,UNUSED,,1,,,,,,,,,
|
||||
L14,,IOBM,IO_L47P_FWE_B_M1DQ0_1,UNUSED,,1,,,,,,,,,
|
||||
L15,,,GND,,,,,,,,,,,,
|
||||
L16,,IOBS,IO_L47N_LDC_M1DQ1_1,UNUSED,,1,,,,,,,,,
|
||||
M1,FSB_A<13>,IOB,IO_L35N_M3DQ11_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
M2,FSB_A<12>,IOB,IO_L35P_M3DQ10_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
M3,FSB_A<3>,IOB,IO_L1N_VREF_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
M4,FSB_A<2>,IOB,IO_L1P_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
M5,FSB_A<4>,IOB,IO_L2P_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
M1,,IOBS,IO_L35N_M3DQ11_3,UNUSED,,3,,,,,,,,,
|
||||
M2,,IOBM,IO_L35P_M3DQ10_3,UNUSED,,3,,,,,,,,,
|
||||
M3,,IOBS,IO_L1N_VREF_3,UNUSED,,3,,,,,,,,,
|
||||
M4,,IOBM,IO_L1P_3,UNUSED,,3,,,,,,,,,
|
||||
M5,,IOBM,IO_L2P_3,UNUSED,,3,,,,,,,,,
|
||||
M6,,IOBM,IO_L64P_D8_2,UNUSED,,2,,,,,,,,,
|
||||
M7,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,,
|
||||
M8,,,GND,,,,,,,,,,,,
|
||||
@ -211,10 +211,10 @@ M13,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,,
|
||||
M14,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,,
|
||||
M15,,IOBM,IO_L46P_FCS_B_M1DQ2_1,UNUSED,,1,,,,,,,,,
|
||||
M16,,IOBS,IO_L46N_FOE_B_M1DQ3_1,UNUSED,,1,,,,,,,,,
|
||||
N1,FSB_A<11>,IOB,IO_L34N_M3UDQSN_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
N2,,,VCCO_3,,,3,,,,,3.30,,,,
|
||||
N3,FSB_A<10>,IOB,IO_L34P_M3UDQS_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
N4,FSB_A<5>,IOB,IO_L2N_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
N1,,IOBS,IO_L34N_M3UDQSN_3,UNUSED,,3,,,,,,,,,
|
||||
N2,,,VCCO_3,,,3,,,,,any******,,,,
|
||||
N3,,IOBM,IO_L34P_M3UDQS_3,UNUSED,,3,,,,,,,,,
|
||||
N4,,IOBS,IO_L2N_3,UNUSED,,3,,,,,,,,,
|
||||
N5,,IOBM,IO_L49P_D3_2,UNUSED,,2,,,,,,,,,
|
||||
N6,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,,
|
||||
N7,,,VCCO_2,,,2,,,,,any******,,,,
|
||||
@ -227,8 +227,8 @@ N13,,,GND,,,,,,,,,,,,
|
||||
N14,,IOBM,IO_L45P_A1_M1LDQS_1,UNUSED,,1,,,,,,,,,
|
||||
N15,,,VCCO_1,,,1,,,,,any******,,,,
|
||||
N16,,IOBS,IO_L45N_A0_M1LDQSN_1,UNUSED,,1,,,,,,,,,
|
||||
P1,FSB_A<9>,IOB,IO_L33N_M3DQ13_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
P2,FSB_A<8>,IOB,IO_L33P_M3DQ12_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
P1,,IOBS,IO_L33N_M3DQ13_3,UNUSED,,3,,,,,,,,,
|
||||
P2,,IOBM,IO_L33P_M3DQ12_3,UNUSED,,3,,,,,,,,,
|
||||
P3,,,GND,,,,,,,,,,,,
|
||||
P4,,IOBM,IO_L63P_2,UNUSED,,2,,,,,,,,,
|
||||
P5,,IOBS,IO_L49N_D4_2,UNUSED,,2,,,,,,,,,
|
||||
@ -243,8 +243,8 @@ P13,,,DONE_2,,,,,,,,,,,,
|
||||
P14,,,SUSPEND,,,,,,,,,,,,
|
||||
P15,,IOBM,IO_L48P_HDC_M1DQ8_1,UNUSED,,1,,,,,,,,,
|
||||
P16,,IOBS,IO_L48N_M1DQ9_1,UNUSED,,1,,,,,,,,,
|
||||
R1,FSB_A<7>,IOB,IO_L32N_M3DQ15_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
R2,FSB_A<6>,IOB,IO_L32P_M3DQ14_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
R1,,IOBS,IO_L32N_M3DQ15_3,UNUSED,,3,,,,,,,,,
|
||||
R2,,IOBM,IO_L32P_M3DQ14_3,UNUSED,,3,,,,,,,,,
|
||||
R3,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,,
|
||||
R4,,,VCCO_2,,,2,,,,,any******,,,,
|
||||
R5,,IOBM,IO_L48P_D7_2,UNUSED,,2,,,,,,,,,
|
||||
|
||||
|
@ -1,7 +1,7 @@
|
||||
Release 14.7 - par P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Mon Nov 01 06:10:44 2021
|
||||
Tue Nov 02 00:29:15 2021
|
||||
|
||||
|
||||
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
|
||||
@ -23,137 +23,137 @@ Pinout by Pin Number:
|
||||
|A1 | | |GND | | | | | | | | | | | |
|
||||
|A2 | |IOBS |IO_L52N_M3A9_3 |UNUSED | |3 | | | | | | | | |
|
||||
|A3 | |IOBS |IO_L83N_VREF_3 |UNUSED | |3 | | | | | | | | |
|
||||
|A4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A5 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A6 | |IOBS |IO_L4N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A7 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A8 | |IOBS |IO_L33N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A9 | |IOBS |IO_L34N_GCLK18_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A10 | |IOBS |IO_L35N_GCLK16_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A11 | |IOBS |IO_L39N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A12 | |IOBS |IO_L62N_VREF_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A13 | |IOBS |IO_L63N_SCP6_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A14 | |IOBS |IO_L65N_SCP2_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A4 |RAMCLK0 |IOB |IO_L1N_VREF_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|A5 |FSB_D<0> |IOB |IO_L2N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A6 |FSB_D<4> |IOB |IO_L4N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A7 |FSB_D<8> |IOB |IO_L6N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A8 |FSB_D<12> |IOB |IO_L33N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A9 |FSB_D<14> |IOB |IO_L34N_GCLK18_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A10 |FSB_D<16> |IOB |IO_L35N_GCLK16_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A11 |FSB_D<24> |IOB |IO_L39N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A12 |FSB_D<28> |IOB |IO_L62N_VREF_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A13 |CPU_nSTERM |IOB |IO_L63N_SCP6_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |NO |NONE |
|
||||
|A14 |RAMCLK1 |IOB |IO_L65N_SCP2_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|A15 | | |TMS | | | | | | | | | | | |
|
||||
|A16 | | |GND | | | | | | | | | | | |
|
||||
|B1 | |IOBS |IO_L50N_M3BA2_3 |UNUSED | |3 | | | | | | | | |
|
||||
|B2 | |IOBM |IO_L52P_M3A8_3 |UNUSED | |3 | | | | | | | | |
|
||||
|B3 | |IOBM |IO_L83P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|B4 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|B5 | |IOBM |IO_L2P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B6 | |IOBM |IO_L4P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B4 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|B5 |FPUCLK |IOB |IO_L2P_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|B6 |FSB_D<3> |IOB |IO_L4P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|B7 | | |GND | | | | | | | | | | | |
|
||||
|B8 | |IOBM |IO_L33P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B9 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|B10 | |IOBM |IO_L35P_GCLK17_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B8 |FSB_D<11> |IOB |IO_L33P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|B9 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|B10 |FSB_D<19> |IOB |IO_L35P_GCLK17_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|B11 | | |GND | | | | | | | | | | | |
|
||||
|B12 | |IOBM |IO_L62P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B13 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|B14 | |IOBM |IO_L65P_SCP3_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B15 | |IOBM |IO_L29P_A23_M1A13_1 |UNUSED | |1 | | | | | | | | |
|
||||
|B16 | |IOBS |IO_L29N_A22_M1A14_1 |UNUSED | |1 | | | | | | | | |
|
||||
|B12 |FSB_D<27> |IOB |IO_L62P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|B13 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|B14 |FSB_A<2> |IOB |IO_L65P_SCP3_0 |INPUT |LVCMOS33 |0 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|B15 |FSB_A<6> |IOB |IO_L29P_A23_M1A13_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|B16 |FSB_A<7> |IOB |IO_L29N_A22_M1A14_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|C1 | |IOBM |IO_L50P_M3WE_3 |UNUSED | |3 | | | | | | | | |
|
||||
|C2 | |IOBS |IO_L48N_M3BA1_3 |UNUSED | |3 | | | | | | | | |
|
||||
|C3 | |IOBM |IO_L48P_M3BA0_3 |UNUSED | |3 | | | | | | | | |
|
||||
|C4 | |IOBM |IO_L1P_HSWAPEN_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C5 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C6 | |IOBS |IO_L7N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C7 | |IOBM |IO_L6P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C8 | |IOBS |IO_L38N_VREF_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C9 | |IOBM |IO_L34P_GCLK19_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C10 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C11 | |IOBM |IO_L39P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C4 |CLKFB_OUT |IOB |IO_L1P_HSWAPEN_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|C5 |FSB_D<2> |IOB |IO_L3N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C6 |FSB_D<10> |IOB |IO_L7N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C7 |FSB_D<7> |IOB |IO_L6P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C8 |FSB_D<18> |IOB |IO_L38N_VREF_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C9 |FSB_D<13> |IOB |IO_L34P_GCLK19_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C10 |FSB_D<20> |IOB |IO_L37N_GCLK12_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C11 |FSB_D<23> |IOB |IO_L39P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C12 | | |TDI | | | | | | | | | | | |
|
||||
|C13 | |IOBM |IO_L63P_SCP7_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C13 |FSB_D<21> |IOB |IO_L63P_SCP7_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C14 | | |TCK | | | | | | | | | | | |
|
||||
|C15 | |IOBM |IO_L33P_A15_M1A10_1 |UNUSED | |1 | | | | | | | | |
|
||||
|C16 | |IOBS |IO_L33N_A14_M1A4_1 |UNUSED | |1 | | | | | | | | |
|
||||
|C15 |FSB_A<14> |IOB |IO_L33P_A15_M1A10_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|C16 |FSB_A<15> |IOB |IO_L33N_A14_M1A4_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|D1 | |IOBS |IO_L49N_M3A2_3 |UNUSED | |3 | | | | | | | | |
|
||||
|D2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|D2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|
||||
|D3 | |IOBM |IO_L49P_M3A7_3 |UNUSED | |3 | | | | | | | | |
|
||||
|D4 | | |GND | | | | | | | | | | | |
|
||||
|D5 | |IOBM |IO_L3P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D6 | |IOBM |IO_L7P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D7 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|D8 | |IOBM |IO_L38P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D9 | |IOBS |IO_L40N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D10 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|D11 | |IOBM |IO_L66P_SCP1_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D12 | |IOBS |IO_L66N_SCP0_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D5 |FSB_D<1> |IOB |IO_L3P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|D6 |FSB_D<9> |IOB |IO_L7P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|D7 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|D8 |FSB_D<25> |IOB |IO_L38P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|D9 |FSB_D<22> |IOB |IO_L40N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|D10 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|D11 |FSB_D<29> |IOB |IO_L66P_SCP1_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|D12 |FSB_A<3> |IOB |IO_L66N_SCP0_0 |INPUT |LVCMOS33 |0 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|D13 | | |GND | | | | | | | | | | | |
|
||||
|D14 | |IOBM |IO_L31P_A19_M1CKE_1 |UNUSED | |1 | | | | | | | | |
|
||||
|D14 |FSB_A<10> |IOB |IO_L31P_A19_M1CKE_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|D15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|D16 | |IOBS |IO_L31N_A18_M1A12_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E1 |FPUCLK |IOB |IO_L46N_M3CLKN_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|E2 |CPUCLK |IOB |IO_L46P_M3CLK_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|D16 |FSB_A<11> |IOB |IO_L31N_A18_M1A12_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E1 | |IOBS |IO_L46N_M3CLKN_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E2 | |IOBM |IO_L46P_M3CLK_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E3 | |IOBS |IO_L54N_M3A11_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E4 | |IOBM |IO_L54P_M3RESET_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E5 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|E6 | |IOBS |IO_L5N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E7 | |IOBM |IO_L36P_GCLK15_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E8 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E6 |FSB_D<6> |IOB |IO_L5N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|E7 |FSB_D<17> |IOB |IO_L36P_GCLK15_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|E8 |FSB_D<26> |IOB |IO_L36N_GCLK14_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|E9 | | |GND | | | | | | | | | | | |
|
||||
|E10 | |IOBM |IO_L37P_GCLK13_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E11 | |IOBS |IO_L64N_SCP4_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E12 | |IOBS |IO_L1N_A24_VREF_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E13 | |IOBM |IO_L1P_A25_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E10 |FSB_D<15> |IOB |IO_L37P_GCLK13_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|E11 |FSB_D<30> |IOB |IO_L64N_SCP4_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|E12 |FSB_A<5> |IOB |IO_L1N_A24_VREF_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E13 |FSB_A<4> |IOB |IO_L1P_A25_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E14 | | |TDO | | | | | | | | | | | |
|
||||
|E15 | |IOBM |IO_L34P_A13_M1WE_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E16 | |IOBS |IO_L34N_A12_M1BA2_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F1 |FSB_A<25> |IOB |IO_L41N_GCLK26_M3DQ5_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F2 |FSB_A<24> |IOB |IO_L41P_GCLK27_M3DQ4_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E15 |FSB_A<16> |IOB |IO_L34P_A13_M1WE_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E16 |FSB_A<17> |IOB |IO_L34N_A12_M1BA2_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F1 | |IOBS |IO_L41N_GCLK26_M3DQ5_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F2 | |IOBM |IO_L41P_GCLK27_M3DQ4_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F3 | |IOBS |IO_L53N_M3A12_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F4 | |IOBM |IO_L53P_M3CKE_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F5 | |IOBS |IO_L55N_M3A14_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F6 | |IOBM |IO_L55P_M3A13_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F7 | |IOBM |IO_L5P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|F7 |FSB_D<5> |IOB |IO_L5P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|F8 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|F9 | |IOBM |IO_L40P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|F10 | |IOBM |IO_L64P_SCP5_0 |UNUSED | |0 | | | | | | | | |
|
||||
|F9 |CPUCLK |IOB |IO_L40P_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|F10 |FSB_D<31> |IOB |IO_L64P_SCP5_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|F11 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|F12 | |IOBM |IO_L30P_A21_M1RESET_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F13 | |IOBM |IO_L32P_A17_M1A8_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F14 | |IOBS |IO_L32N_A16_M1A9_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F15 | |IOBM |IO_L35P_A11_M1A7_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F16 | |IOBS |IO_L35N_A10_M1A2_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G1 |FSB_A<23> |IOB |IO_L40N_M3DQ7_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F12 |FSB_A<8> |IOB |IO_L30P_A21_M1RESET_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F13 |FSB_A<12> |IOB |IO_L32P_A17_M1A8_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F14 |FSB_A<13> |IOB |IO_L32N_A16_M1A9_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F15 |FSB_A<18> |IOB |IO_L35P_A11_M1A7_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F16 |FSB_A<19> |IOB |IO_L35N_A10_M1A2_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G1 | |IOBS |IO_L40N_M3DQ7_3 |UNUSED | |3 | | | | | | | | |
|
||||
|G2 | | |GND | | | | | | | | | | | |
|
||||
|G3 |FSB_A<22> |IOB |IO_L40P_M3DQ6_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G4 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|G3 | |IOBM |IO_L40P_M3DQ6_3 |UNUSED | |3 | | | | | | | | |
|
||||
|G4 | | |VCCO_3 | | |3 | | | | |any******| | | |
|
||||
|G5 | |IOBS |IO_L51N_M3A4_3 |UNUSED | |3 | | | | | | | | |
|
||||
|G6 | |IOBM |IO_L51P_M3A10_3 |UNUSED | |3 | | | | | | | | |
|
||||
|G7 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|G8 | | |GND | | | | | | | | | | | |
|
||||
|G9 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|G10 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|G11 | |IOBS |IO_L30N_A20_M1A11_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G12 | |IOBM |IO_L38P_A5_M1CLK_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G11 |FSB_A<9> |IOB |IO_L30N_A20_M1A11_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G12 |FSB_A<24> |IOB |IO_L38P_A5_M1CLK_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G13 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|G14 | |IOBM |IO_L36P_A9_M1BA0_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G14 |FSB_A<20> |IOB |IO_L36P_A9_M1BA0_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G15 | | |GND | | | | | | | | | | | |
|
||||
|G16 | |IOBS |IO_L36N_A8_M1BA1_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H1 |FSB_A<21> |IOB |IO_L39N_M3LDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H2 |FSB_A<20> |IOB |IO_L39P_M3LDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H3 |RAMCLK0 |IOB |IO_L44N_GCLK20_M3A6_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|G16 |FSB_A<21> |IOB |IO_L36N_A8_M1BA1_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H1 | |IOBS |IO_L39N_M3LDQSN_3 |UNUSED | |3 | | | | | | | | |
|
||||
|H2 | |IOBM |IO_L39P_M3LDQS_3 |UNUSED | |3 | | | | | | | | |
|
||||
|H3 | |IOBS |IO_L44N_GCLK20_M3A6_3 |UNUSED | |3 | | | | | | | | |
|
||||
|H4 |CLKFB_IN |IOB |IO_L44P_GCLK21_M3A5_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H5 |CPU_nSTERM |IOB |IO_L43N_GCLK22_IRDY2_M3CASN_3|OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |NO |NONE |
|
||||
|H5 | |IOBS |IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED | |3 | | | | | | | | |
|
||||
|H6 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|H7 | | |GND | | | | | | | | | | | |
|
||||
|H8 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|H9 | | |GND | | | | | | | | | | | |
|
||||
|H10 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|H11 | |IOBS |IO_L38N_A4_M1CLKN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H11 |FSB_A<25> |IOB |IO_L38N_A4_M1CLKN_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H12 | | |GND | | | | | | | | | | | |
|
||||
|H13 | |IOBM |IO_L39P_M1A3_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H14 | |IOBS |IO_L39N_M1ODT_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H15 | |IOBM |IO_L37P_A7_M1A0_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H16 | |IOBS |IO_L37N_A6_M1A1_1 |UNUSED | |1 | | | | | | | | |
|
||||
|J1 |FSB_A<19> |IOB |IO_L38N_M3DQ3_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|J3 |FSB_A<18> |IOB |IO_L38P_M3DQ2_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H13 |FSB_A<28> |IOB |IO_L39P_M1A3_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H14 |FSB_A<30> |IOB |IO_L39N_M1ODT_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H15 |FSB_A<22> |IOB |IO_L37P_A7_M1A0_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H16 |FSB_A<23> |IOB |IO_L37N_A6_M1A1_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J1 | |IOBS |IO_L38N_M3DQ3_3 |UNUSED | |3 | | | | | | | | |
|
||||
|J2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|
||||
|J3 | |IOBM |IO_L38P_M3DQ2_3 |UNUSED | |3 | | | | | | | | |
|
||||
|J4 |CLKIN |IOB |IO_L42N_GCLK24_M3LDM_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J5 | | |GND | | | | | | | | | | | |
|
||||
|J6 |FSB_A<27> |IOB |IO_L43P_GCLK23_M3RASN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J6 | |IOBM |IO_L43P_GCLK23_M3RASN_3 |UNUSED | |3 | | | | | | | | |
|
||||
|J7 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|J8 | | |GND | | | | | | | | | | | |
|
||||
|J9 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
@ -164,10 +164,10 @@ Pinout by Pin Number:
|
||||
|J14 | |IOBM |IO_L43P_GCLK5_M1DQ4_1 |UNUSED | |1 | | | | | | | | |
|
||||
|J15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|J16 | |IOBS |IO_L43N_GCLK4_M1DQ5_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K1 |FSB_A<17> |IOB |IO_L37N_M3DQ1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K2 |FSB_A<16> |IOB |IO_L37P_M3DQ0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K3 |FSB_A<26> |IOB |IO_L42P_GCLK25_TRDY2_M3UDM_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K4 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|K1 | |IOBS |IO_L37N_M3DQ1_3 |UNUSED | |3 | | | | | | | | |
|
||||
|K2 | |IOBM |IO_L37P_M3DQ0_3 |UNUSED | |3 | | | | | | | | |
|
||||
|K3 | |IOBM |IO_L42P_GCLK25_TRDY2_M3UDM_3 |UNUSED | |3 | | | | | | | | |
|
||||
|K4 | | |VCCO_3 | | |3 | | | | |any******| | | |
|
||||
|K5 | |IOBM |IO_L47P_M3A0_3 |UNUSED | |3 | | | | | | | | |
|
||||
|K6 | |IOBS |IO_L47N_M3A1_3 |UNUSED | |3 | | | | | | | | |
|
||||
|K7 | | |GND | | | | | | | | | | | |
|
||||
@ -180,11 +180,11 @@ Pinout by Pin Number:
|
||||
|K14 | |IOBS |IO_L41N_GCLK8_M1CASN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K15 | |IOBM |IO_L44P_A3_M1DQ6_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K16 | |IOBS |IO_L44N_A2_M1DQ7_1 |UNUSED | |1 | | | | | | | | |
|
||||
|L1 |FSB_A<15> |IOB |IO_L36N_M3DQ9_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L1 | |IOBS |IO_L36N_M3DQ9_3 |UNUSED | |3 | | | | | | | | |
|
||||
|L2 | | |GND | | | | | | | | | | | |
|
||||
|L3 |FSB_A<14> |IOB |IO_L36P_M3DQ8_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L4 |CLKFB_OUT |IOB |IO_L45P_M3A3_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|L5 |RAMCLK1 |IOB |IO_L45N_M3ODT_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|L3 | |IOBM |IO_L36P_M3DQ8_3 |UNUSED | |3 | | | | | | | | |
|
||||
|L4 | |IOBM |IO_L45P_M3A3_3 |UNUSED | |3 | | | | | | | | |
|
||||
|L5 | |IOBS |IO_L45N_M3ODT_3 |UNUSED | |3 | | | | | | | | |
|
||||
|L6 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|L7 | |IOBS |IO_L62N_D6_2 |UNUSED | |2 | | | | | | | | |
|
||||
|L8 | |IOBM |IO_L62P_D5_2 |UNUSED | |2 | | | | | | | | |
|
||||
@ -196,11 +196,11 @@ Pinout by Pin Number:
|
||||
|L14 | |IOBM |IO_L47P_FWE_B_M1DQ0_1 |UNUSED | |1 | | | | | | | | |
|
||||
|L15 | | |GND | | | | | | | | | | | |
|
||||
|L16 | |IOBS |IO_L47N_LDC_M1DQ1_1 |UNUSED | |1 | | | | | | | | |
|
||||
|M1 |FSB_A<13> |IOB |IO_L35N_M3DQ11_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M2 |FSB_A<12> |IOB |IO_L35P_M3DQ10_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M3 |FSB_A<3> |IOB |IO_L1N_VREF_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M4 |FSB_A<2> |IOB |IO_L1P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M5 |FSB_A<4> |IOB |IO_L2P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M1 | |IOBS |IO_L35N_M3DQ11_3 |UNUSED | |3 | | | | | | | | |
|
||||
|M2 | |IOBM |IO_L35P_M3DQ10_3 |UNUSED | |3 | | | | | | | | |
|
||||
|M3 | |IOBS |IO_L1N_VREF_3 |UNUSED | |3 | | | | | | | | |
|
||||
|M4 | |IOBM |IO_L1P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|M5 | |IOBM |IO_L2P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|M6 | |IOBM |IO_L64P_D8_2 |UNUSED | |2 | | | | | | | | |
|
||||
|M7 | |IOBS |IO_L31N_GCLK30_D15_2 |UNUSED | |2 | | | | | | | | |
|
||||
|M8 | | |GND | | | | | | | | | | | |
|
||||
@ -212,10 +212,10 @@ Pinout by Pin Number:
|
||||
|M14 | |IOBS |IO_L74N_DOUT_BUSY_1 |UNUSED | |1 | | | | | | | | |
|
||||
|M15 | |IOBM |IO_L46P_FCS_B_M1DQ2_1 |UNUSED | |1 | | | | | | | | |
|
||||
|M16 | |IOBS |IO_L46N_FOE_B_M1DQ3_1 |UNUSED | |1 | | | | | | | | |
|
||||
|N1 |FSB_A<11> |IOB |IO_L34N_M3UDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|N3 |FSB_A<10> |IOB |IO_L34P_M3UDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N4 |FSB_A<5> |IOB |IO_L2N_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N1 | |IOBS |IO_L34N_M3UDQSN_3 |UNUSED | |3 | | | | | | | | |
|
||||
|N2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|
||||
|N3 | |IOBM |IO_L34P_M3UDQS_3 |UNUSED | |3 | | | | | | | | |
|
||||
|N4 | |IOBS |IO_L2N_3 |UNUSED | |3 | | | | | | | | |
|
||||
|N5 | |IOBM |IO_L49P_D3_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N6 | |IOBS |IO_L64N_D9_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N7 | | |VCCO_2 | | |2 | | | | |any******| | | |
|
||||
@ -228,8 +228,8 @@ Pinout by Pin Number:
|
||||
|N14 | |IOBM |IO_L45P_A1_M1LDQS_1 |UNUSED | |1 | | | | | | | | |
|
||||
|N15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|N16 | |IOBS |IO_L45N_A0_M1LDQSN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P1 |FSB_A<9> |IOB |IO_L33N_M3DQ13_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|P2 |FSB_A<8> |IOB |IO_L33P_M3DQ12_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|P1 | |IOBS |IO_L33N_M3DQ13_3 |UNUSED | |3 | | | | | | | | |
|
||||
|P2 | |IOBM |IO_L33P_M3DQ12_3 |UNUSED | |3 | | | | | | | | |
|
||||
|P3 | | |GND | | | | | | | | | | | |
|
||||
|P4 | |IOBM |IO_L63P_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P5 | |IOBS |IO_L49N_D4_2 |UNUSED | |2 | | | | | | | | |
|
||||
@ -244,8 +244,8 @@ Pinout by Pin Number:
|
||||
|P14 | | |SUSPEND | | | | | | | | | | | |
|
||||
|P15 | |IOBM |IO_L48P_HDC_M1DQ8_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P16 | |IOBS |IO_L48N_M1DQ9_1 |UNUSED | |1 | | | | | | | | |
|
||||
|R1 |FSB_A<7> |IOB |IO_L32N_M3DQ15_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|R2 |FSB_A<6> |IOB |IO_L32P_M3DQ14_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|R1 | |IOBS |IO_L32N_M3DQ15_3 |UNUSED | |3 | | | | | | | | |
|
||||
|R2 | |IOBM |IO_L32P_M3DQ14_3 |UNUSED | |3 | | | | | | | | |
|
||||
|R3 | |IOBM |IO_L65P_INIT_B_2 |UNUSED | |2 | | | | | | | | |
|
||||
|R4 | | |VCCO_2 | | |2 | | | | |any******| | | |
|
||||
|R5 | |IOBM |IO_L48P_D7_2 |UNUSED | |2 | | | | | | | | |
|
||||
|
||||
1176
fpga/WarpLC_par.xrpt
1176
fpga/WarpLC_par.xrpt
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@ -2,18 +2,18 @@
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>WarpLC Project Status (11/01/2021 - 06:10:50)</B></TD></TR>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>WarpLC Project Status (11/02/2021 - 00:33:38)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>WarpLC.xise</TD>
|
||||
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
|
||||
<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/pn_parser.xmsgs?&DataKey=Error'>2 Errors</A></TD>
|
||||
<TD> No Errors </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
|
||||
<TD>WarpLC</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
|
||||
<TD>Placed and Routed</TD>
|
||||
<TD>Mapped</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
|
||||
@ -25,14 +25,14 @@ No Errors</TD>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/*.xmsgs?&DataKey=Warning'>153 Warnings (53 new)</A></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/*.xmsgs?&DataKey=Warning'>53 Warnings (6 new)</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
<TD>Balanced</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.unroutes'>All Signals Completely Routed</A></TD>
|
||||
</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
|
||||
@ -43,11 +43,11 @@ No Errors</TD>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_envsettings.html'>
|
||||
<A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_envsettings.html'>
|
||||
System Settings</A>
|
||||
</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
|
||||
<TD>0 <A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
@ -89,13 +89,13 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
|
||||
<TD ALIGN=RIGHT>89</TD>
|
||||
<TD ALIGN=RIGHT>105</TD>
|
||||
<TD ALIGN=RIGHT>5,720</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
|
||||
<TD ALIGN=RIGHT>9</TD>
|
||||
<TD ALIGN=RIGHT>25</TD>
|
||||
<TD ALIGN=RIGHT>5,720</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
@ -113,7 +113,7 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>17</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
@ -167,9 +167,9 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
|
||||
<TD ALIGN=RIGHT>23</TD>
|
||||
<TD ALIGN=RIGHT>35</TD>
|
||||
<TD ALIGN=RIGHT>1,430</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD ALIGN=RIGHT>2%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
|
||||
@ -179,27 +179,27 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
|
||||
<TD ALIGN=RIGHT>89</TD>
|
||||
<TD ALIGN=RIGHT>106</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD>
|
||||
<TD ALIGN=RIGHT>88</TD>
|
||||
<TD ALIGN=RIGHT>89</TD>
|
||||
<TD ALIGN=RIGHT>98%</TD>
|
||||
<TD ALIGN=RIGHT>105</TD>
|
||||
<TD ALIGN=RIGHT>106</TD>
|
||||
<TD ALIGN=RIGHT>99%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>89</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>106</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>89</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>106</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD>
|
||||
@ -214,10 +214,10 @@ System Settings</A>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
|
||||
<TD ALIGN=RIGHT>34</TD>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
|
||||
<TD ALIGN=RIGHT>66</TD>
|
||||
<TD ALIGN=RIGHT>186</TD>
|
||||
<TD ALIGN=RIGHT>18%</TD>
|
||||
<TD ALIGN=RIGHT>35%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Flip Flops</TD>
|
||||
@ -227,9 +227,9 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD ALIGN=RIGHT>32</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD ALIGN=RIGHT>12%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
|
||||
@ -401,7 +401,7 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
|
||||
<TD ALIGN=RIGHT>5.20</TD>
|
||||
<TD ALIGN=RIGHT>3.54</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
@ -410,26 +410,7 @@ System Settings</A>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
|
||||
<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
|
||||
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
|
||||
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.unroutes'>All Signals Completely Routed</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
|
||||
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
|
||||
<TD> </TD>
|
||||
<TD BGCOLOR='#FFFF99'><B> </B></TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
|
||||
@ -437,21 +418,21 @@ System Settings</A>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon Nov 1 06:10:22 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>80 Warnings (53 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon Nov 1 06:10:26 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>73 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon Nov 1 06:10:39 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon Nov 1 06:10:44 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/par.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Tue Nov 2 00:33:02 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>40 Warnings (6 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Info'>12 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue Nov 2 00:33:08 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>13 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Tue Nov 2 00:33:32 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (1 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.par'>Place and Route Report</A></TD><TD>Out of Date</TD><TD>Tue Nov 2 00:29:15 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/par.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon Nov 1 06:10:48 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.twr'>Post-PAR Static Timing Report</A></TD><TD>Out of Date</TD><TD>Tue Nov 2 00:29:21 2021</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Nov 1 01:01:50 2021</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.psr'>Physical Synthesis Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon Nov 1 06:10:39 2021</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue Nov 2 00:33:37 2021</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue Nov 2 00:33:32 2021</TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 11/01/2021 - 12:11:55</center>
|
||||
<br><center><b>Date Generated:</b> 11/02/2021 - 00:35:21</center>
|
||||
</BODY></HTML>
|
||||
@ -4,7 +4,7 @@
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<DesignSummary rev="46">
|
||||
<DesignSummary rev="49">
|
||||
<CmdHistory>
|
||||
</CmdHistory>
|
||||
</DesignSummary>
|
||||
|
||||
@ -4,65 +4,69 @@
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<DeviceUsageSummary rev="46">
|
||||
<DesignStatistics TimeStamp="Mon Nov 01 06:10:39 2021"><group name="MiscellaneousStatistics">
|
||||
<item name="AGG_BONDED_IO" rev="46">
|
||||
<attrib name="value" value="34"/></item>
|
||||
<item name="AGG_IO" rev="46">
|
||||
<attrib name="value" value="34"/></item>
|
||||
<item name="AGG_SLICE" rev="46">
|
||||
<attrib name="value" value="23"/></item>
|
||||
<item name="NUM_BONDED_IOB" rev="46">
|
||||
<attrib name="value" value="34"/></item>
|
||||
<item name="NUM_BSFULL" rev="46">
|
||||
<DeviceUsageSummary rev="49">
|
||||
<DesignStatistics TimeStamp="Tue Nov 02 00:33:32 2021"><group name="MiscellaneousStatistics">
|
||||
<item name="AGG_BONDED_IO" rev="49">
|
||||
<attrib name="value" value="66"/></item>
|
||||
<item name="AGG_IO" rev="49">
|
||||
<attrib name="value" value="66"/></item>
|
||||
<item name="AGG_SLICE" rev="49">
|
||||
<attrib name="value" value="35"/></item>
|
||||
<item name="NUM_BONDED_IOB" rev="49">
|
||||
<attrib name="value" value="66"/></item>
|
||||
<item name="NUM_BSLUTONLY" rev="49">
|
||||
<attrib name="value" value="105"/></item>
|
||||
<item name="NUM_BSREGONLY" rev="49">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_BSLUTONLY" rev="46">
|
||||
<attrib name="value" value="88"/></item>
|
||||
<item name="NUM_BSUSED" rev="46">
|
||||
<attrib name="value" value="89"/></item>
|
||||
<item name="NUM_BUFG" rev="46">
|
||||
<item name="NUM_BSUSED" rev="49">
|
||||
<attrib name="value" value="106"/></item>
|
||||
<item name="NUM_BUFG" rev="49">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NUM_BUFIO2" rev="46">
|
||||
<item name="NUM_BUFIO2" rev="49">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_BUFIO2FB" rev="46">
|
||||
<item name="NUM_BUFIO2FB" rev="49">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_DPRAM_O6ONLY" rev="46">
|
||||
<item name="NUM_DPRAM_O6ONLY" rev="49">
|
||||
<attrib name="value" value="80"/></item>
|
||||
<item name="NUM_IOB_FF" rev="46">
|
||||
<item name="NUM_IOB_FF" rev="49">
|
||||
<attrib name="value" value="5"/></item>
|
||||
<item name="NUM_LOGIC_O5ANDO6" rev="46">
|
||||
<item name="NUM_LOGIC_O5ANDO6" rev="49">
|
||||
<attrib name="value" value="17"/></item>
|
||||
<item name="NUM_LOGIC_O5ONLY" rev="49">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_LOGIC_O5ONLY" rev="46">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_LOGIC_O6ONLY" rev="46">
|
||||
<item name="NUM_LOGIC_O6ONLY" rev="49">
|
||||
<attrib name="value" value="7"/></item>
|
||||
<item name="NUM_LUT_RT_O6" rev="46">
|
||||
<item name="NUM_LUT_RT_O6" rev="49">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_OLOGIC2" rev="46">
|
||||
<item name="NUM_OLOGIC2" rev="49">
|
||||
<attrib name="value" value="5"/></item>
|
||||
<item name="NUM_PLL_ADV" rev="46">
|
||||
<item name="NUM_PLL_ADV" rev="49">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_SLICEL" rev="46">
|
||||
<item name="NUM_RAMB16BWER" rev="49">
|
||||
<attrib name="value" value="4"/></item>
|
||||
<item name="NUM_SLICEL" rev="49">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NUM_SLICEM" rev="46">
|
||||
<item name="NUM_SLICEM" rev="49">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="NUM_SLICEX" rev="46">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_SLICE_CARRY4" rev="46">
|
||||
<item name="NUM_SLICEX" rev="49">
|
||||
<attrib name="value" value="13"/></item>
|
||||
<item name="NUM_SLICE_CARRY4" rev="49">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NUM_SLICE_CONTROLSET" rev="46">
|
||||
<item name="NUM_SLICE_CONTROLSET" rev="49">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NUM_SLICE_CYINIT" rev="46">
|
||||
<attrib name="value" value="92"/></item>
|
||||
<item name="NUM_SLICE_F7MUX" rev="46">
|
||||
<item name="NUM_SLICE_CYINIT" rev="49">
|
||||
<attrib name="value" value="124"/></item>
|
||||
<item name="NUM_SLICE_F7MUX" rev="49">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="NUM_SLICE_FF" rev="46">
|
||||
<item name="NUM_SLICE_FF" rev="49">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_SLICE_UNUSEDCTRL" rev="46">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NUM_UNUSABLE_FF_BELS" rev="46">
|
||||
<item name="NUM_SLICE_UNUSEDCTRL" rev="49">
|
||||
<attrib name="value" value="14"/></item>
|
||||
<item name="NUM_UNUSABLE_FF_BELS" rev="49">
|
||||
<attrib name="value" value="7"/></item>
|
||||
<item name="Xilinx Core dist_mem_gen_v7_2, Xilinx CORE Generator 14.7" rev="46">
|
||||
<item name="Xilinx Core blk_mem_gen_v7_3, Xilinx CORE Generator 14.7" rev="49">
|
||||
<attrib name="value" value="9"/></item>
|
||||
<item name="Xilinx Core dist_mem_gen_v7_2, Xilinx CORE Generator 14.7" rev="49">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
</DesignStatistics>
|
||||
|
||||
@ -5,14 +5,14 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Mon Nov 01 06:10:19 2021">
|
||||
<application stringID="Xst" timeStamp="Tue Nov 02 00:32:56 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files\Microchip\xc8\v2.31\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\PuTTY\;C:\Program Files\WinMerge;C:\Program Files\dotnet\;C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;C:\Users\zanek\AppData\Local\GitHubDesktop\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\zanek\.dotnet\tools;C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt;C:\Xilinx\14.7\ISE_DS\common\lib\nt;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\PuTTY\;C:\Program Files (x86)\WinMerge;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\Microchip\xc8\v2.31\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\Dog\AppData\Local\GitHubDesktop\bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
@ -36,16 +36,16 @@
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
|
||||
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="ZanePC"/>
|
||||
<item stringID="User_EnvHost" value="Dog-PC"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz"/>
|
||||
<item stringID="speed" value="3500 MHz"/>
|
||||
<item stringID="arch" value="Intel(R) Xeon(R) CPU W3680 @ 3.33GHz"/>
|
||||
<item stringID="speed" value="3316 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
@ -113,12 +113,18 @@
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="1"></item>
|
||||
<item dataType="int" stringID="XST_MULTIPLEXERS" value="10">
|
||||
<item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="10"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="1">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="1"></item>
|
||||
<item dataType="int" stringID="XST_MULTIPLEXERS" value="10">
|
||||
<item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="10"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_FINAL_REGISTER_REPORT">
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="1">
|
||||
@ -135,45 +141,50 @@
|
||||
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="WarpLC.ngc"/>
|
||||
</section>
|
||||
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="21">
|
||||
<item dataType="int" stringID="XST_GND" value="1"/>
|
||||
<item dataType="int" stringID="XST_BELS" value="62">
|
||||
<item dataType="int" stringID="XST_GND" value="10"/>
|
||||
<item dataType="int" stringID="XST_INV" value="3"/>
|
||||
<item dataType="int" stringID="XST_LUT1" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT2" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT3" value="32"/>
|
||||
<item dataType="int" stringID="XST_LUT6" value="6"/>
|
||||
<item dataType="int" stringID="XST_MUXCY" value="8"/>
|
||||
<item dataType="int" stringID="XST_VCC" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="50">
|
||||
<item dataType="int" stringID="XST_FD" value="44"/>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="46">
|
||||
<item dataType="int" stringID="XST_FD" value="40"/>
|
||||
<item dataType="int" stringID="XST_FDR" value="1"/>
|
||||
<item dataType="int" stringID="XST_ODDR2" value="5"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_RAMS" value="22"></item>
|
||||
<item dataType="int" stringID="XST_RAMS" value="48">
|
||||
<item dataType="int" stringID="XST_RAMB16BWER" value="28"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="2">
|
||||
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="2"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="34">
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="66">
|
||||
<item dataType="int" stringID="XST_IBUF" value="26"/>
|
||||
<item dataType="int" stringID="XST_IBUFG" value="2"/>
|
||||
<item dataType="int" stringID="XST_OBUF" value="6"/>
|
||||
<item dataType="int" stringID="XST_OBUF" value="38"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_OTHERS" value="2"></item>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
|
||||
<item stringID="XST_SELECTED_DEVICE" value="6slx9ftg256-2"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="50"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="99"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="11"/>
|
||||
<item AVAILABLE="1440" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="88"/>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="149"/>
|
||||
<item AVAILABLE="149" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="99"/>
|
||||
<item AVAILABLE="149" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="50"/>
|
||||
<item AVAILABLE="149" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="0"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="46"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="123"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="43"/>
|
||||
<item AVAILABLE="1440" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="80"/>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="169"/>
|
||||
<item AVAILABLE="169" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="123"/>
|
||||
<item AVAILABLE="169" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="46"/>
|
||||
<item AVAILABLE="169" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="0"/>
|
||||
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="2"/>
|
||||
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="75"/>
|
||||
<item AVAILABLE="186" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="34"/>
|
||||
<item AVAILABLE="186" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="66"/>
|
||||
<item AVAILABLE="32" dataType="int" label="Number of Block RAM/FIFO" stringID="XST_NUMBER_OF_BLOCK_RAMFIFO" value="28"/>
|
||||
<item dataType="int" label="Number using Block RAM only" stringID="XST_NUMBER_USING_BLOCK_RAM_ONLY" value="28"/>
|
||||
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="2"/>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
|
||||
@ -181,8 +192,8 @@
|
||||
</section>
|
||||
<section stringID="XST_ERRORS_STATISTICS">
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="80"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="3"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="40"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="12"/>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
|
||||
@ -1,3 +1,5 @@
|
||||
C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.ngc 1635761422
|
||||
ipcore_dir/PrefetchTagRAM.ngc 1635761393
|
||||
C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.ngc 1635827582
|
||||
ipcore_dir/PrefetchTagRAM.ngc 1635827546
|
||||
ipcore_dir/PrefetchDataRAM.ngc 1635786436
|
||||
ipcore_dir/L2WayRAM.ngc 1635827502
|
||||
OK
|
||||
|
||||
@ -11,10 +11,10 @@
|
||||
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">FSB_A<31></arg> has no load.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">86</arg> more times for the following (max. 5 shown):
|
||||
<arg fmt="%s" index="3">FSB_A<30>,
|
||||
FSB_A<29>,
|
||||
FSB_A<28>,
|
||||
<msg type="info" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">50</arg> more times for the following (max. 5 shown):
|
||||
<arg fmt="%s" index="3">FSB_A<29>,
|
||||
FSB_A<27>,
|
||||
FSB_A<26>,
|
||||
FSB_A<1>,
|
||||
FSB_A<0></arg>
|
||||
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
|
||||
|
||||
@ -5,102 +5,6 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<0>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<1>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<2>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<2></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<3>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<3></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<4>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<4></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<5>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<5></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<6>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<6></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<7>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<7></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<8>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<8></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<9>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<9></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<10>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<10></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<11>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<11></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<12>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<12></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<13>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<13></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<14>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<14></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<15>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<15></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<16>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<16></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<17>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<17></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<18>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<18></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<19>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<19></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<20>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<20></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<21>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<21></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<22>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<22></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<23>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<23></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<24>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<24></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<25>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<25></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<26>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<26></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<27>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<27></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<28>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<28></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<29>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<29></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<30>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<30></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<31>" SLEW = SLOW></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<31></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nAS" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nAS</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
@ -116,113 +20,29 @@
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<1>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<28>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<28></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<26>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<26></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<27>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<27></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<29>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<29></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<30>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<30></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<31>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<31></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<31></arg>' has no driver
|
||||
<msg type="warning" file="ConstraintSystem" num="137" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A[27]" TNM_NET = FSB_A;> [PLL.ucf(6)]</arg>: No appropriate instances for the TNM constraint are driven by "<arg fmt="%s" index="2">FSB_A<27></arg>".
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<30></arg>' has no driver
|
||||
<msg type="warning" file="ConstraintSystem" num="137" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A[26]" TNM_NET = FSB_A;> [PLL.ucf(7)]</arg>: No appropriate instances for the TNM constraint are driven by "<arg fmt="%s" index="2">FSB_A<26></arg>".
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<29></arg>' has no driver
|
||||
</msg>
|
||||
<msg type="warning" file="ConstraintSystem" num="194" delta="old" >The <arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">FSB_A</arg>', does not directly or indirectly drive any flip-flops, latches and/or RAMs and is not actively used by any referencing constraint.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<28></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<27></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<26></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<25></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<24></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<23></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<22></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<21></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<20></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<19></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<18></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<17></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<16></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<15></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<14></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<13></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<12></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<11></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<10></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<9></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<8></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<7></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<6></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<5></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<4></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<3></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<2></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<0></arg>' has no driver
|
||||
</msg>
|
||||
<msg type="warning" file="ConstraintSystem" num="194" delta="old" >The <arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">FSB_A</arg>', does not directly or indirectly drive any flip-flops, latches and/or RAMs and is not actively used by any referencing constraint.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
||||
@ -8,31 +8,7 @@
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<messages>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/CS.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="error" file="ProjectMgmt" num="806" >"<arg fmt="%s" index="1">C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/CS.v</arg>" Line <arg fmt="%d" index="2">3</arg>. <arg fmt="%s" index="3">Syntax error near "output".</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ClkGen.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/L2Cache.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="error" file="ProjectMgmt" num="806" >"<arg fmt="%s" index="1">C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/L2Cache.v</arg>" Line <arg fmt="%d" index="2">34</arg>. <arg fmt="%s" index="3">Syntax error near "==".</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/L2CacheWay.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/Prefetch.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/SizeDecode.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.v" into library work</arg>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
@ -9,6 +9,10 @@
|
||||
|
||||
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3284" delta="new" >This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
@ -5,253 +5,160 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="HDLCompiler" num="1016" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port <arg fmt="%s" index="1">LOCKED</arg> is not connected to this instance
|
||||
<msg type="warning" file="HDLCompiler" num="1016" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 92: Port <arg fmt="%s" index="1">LoMemCacheCS</arg> is not connected to this instance
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to <arg fmt="%s" index="1">clkout1_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1016" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 108: Port <arg fmt="%s" index="1">RDFixed7k5SEL</arg> is not connected to this instance
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to <arg fmt="%s" index="1">clkout2_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1016" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port <arg fmt="%s" index="1">LOCKED</arg> is not connected to this instance
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to <arg fmt="%s" index="1">clkout3_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to <arg fmt="%s" index="1">clkout1_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to <arg fmt="%s" index="1">clkout4_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to <arg fmt="%s" index="1">clkout2_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to <arg fmt="%s" index="1">clkout5_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to <arg fmt="%s" index="1">clkout3_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to <arg fmt="%s" index="1">FSB_B</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to <arg fmt="%s" index="1">clkout4_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1499" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module <<arg fmt="%s" index="1">PrefetchTagRAM</arg>> remains a black box.
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to <arg fmt="%s" index="1">clkout5_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 40: Size mismatch in connection of port <<arg fmt="%s" index="3">d</arg>>. Formal port size is <arg fmt="%d" index="2">22</arg>-bit while actual signal size is <arg fmt="%d" index="1">20</arg>-bit.
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to <arg fmt="%s" index="1">FSB_SEL_RAM</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 41: Size mismatch in connection of port <<arg fmt="%s" index="3">spo</arg>>. Formal port size is <arg fmt="%d" index="2">22</arg>-bit while actual signal size is <arg fmt="%d" index="1">20</arg>-bit.
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 95: Assignment to <arg fmt="%s" index="1">FSB_SEL_ROM</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 43: Size mismatch in connection of port <<arg fmt="%s" index="3">dpo</arg>>. Formal port size is <arg fmt="%d" index="2">22</arg>-bit while actual signal size is <arg fmt="%d" index="1">20</arg>-bit.
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 96: Assignment to <arg fmt="%s" index="1">FSB_VRAM</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2972" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%d" index="2">91</arg>. All outputs of instance <<arg fmt="%s" index="3">sd</arg>> of block <<arg fmt="%s" index="4">SizeDecode</arg>> are unconnected in block <<arg fmt="%s" index="5">WarpLC</arg>>. Underlying logic will be removed.
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 97: Assignment to <arg fmt="%s" index="1">FSB_SEL_Cache</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">FSB_A<31:28></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 98: Assignment to <arg fmt="%s" index="1">FSB_CA</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 104: Assignment to <arg fmt="%s" index="1">FSB_B</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1016" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 49: Port <arg fmt="%s" index="1">doutb</arg> is not connected to this instance
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1499" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module <<arg fmt="%s" index="1">PrefetchTagRAM</arg>> remains a black box.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1499" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" Line 39: Empty module <<arg fmt="%s" index="1">PrefetchDataRAM</arg>> remains a black box.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 116: Size mismatch in connection of port <<arg fmt="%s" index="3">WRA</arg>>. Formal port size is <arg fmt="%d" index="2">26</arg>-bit while actual signal size is <arg fmt="%d" index="1">28</arg>-bit.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1499" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\L2WayRAM.v" Line 39: Empty module <<arg fmt="%s" index="1">L2WayRAM</arg>> remains a black box.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 43: Size mismatch in connection of port <<arg fmt="%s" index="3">addra</arg>>. Formal port size is <arg fmt="%d" index="2">10</arg>-bit while actual signal size is <arg fmt="%d" index="1">12</arg>-bit.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="new" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 44: Size mismatch in connection of port <<arg fmt="%s" index="3">dina</arg>>. Formal port size is <arg fmt="%d" index="2">47</arg>-bit while actual signal size is <arg fmt="%d" index="1">50</arg>-bit.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="new" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 45: Size mismatch in connection of port <<arg fmt="%s" index="3">douta</arg>>. Formal port size is <arg fmt="%d" index="2">47</arg>-bit while actual signal size is <arg fmt="%d" index="1">49</arg>-bit.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 49: Size mismatch in connection of port <<arg fmt="%s" index="3">addrb</arg>>. Formal port size is <arg fmt="%d" index="2">10</arg>-bit while actual signal size is <arg fmt="%d" index="1">12</arg>-bit.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="new" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 50: Size mismatch in connection of port <<arg fmt="%s" index="3">dinb</arg>>. Formal port size is <arg fmt="%d" index="2">47</arg>-bit while actual signal size is <arg fmt="%d" index="1">49</arg>-bit.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="new" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 51: Size mismatch in connection of port <<arg fmt="%s" index="3">doutb</arg>>. Formal port size is <arg fmt="%d" index="2">47</arg>-bit while actual signal size is <arg fmt="%d" index="1">49</arg>-bit.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 51: Assignment to <arg fmt="%s" index="1">TSD</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 132: Size mismatch in connection of port <<arg fmt="%s" index="3">WRA</arg>>. Formal port size is <arg fmt="%d" index="2">26</arg>-bit while actual signal size is <arg fmt="%d" index="1">28</arg>-bit.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 125: Net <<arg fmt="%s" index="1">CLK</arg>> does not have a driver.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="552" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 108: Input port <arg fmt="%s" index="1">RDFixed7k5SEL</arg> is not connected on this instance
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2972" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%d" index="2">92</arg>. All outputs of instance <<arg fmt="%s" index="3">cs</arg>> of block <<arg fmt="%s" index="4">CS</arg>> are unconnected in block <<arg fmt="%s" index="5">WarpLC</arg>>. Underlying logic will be removed.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2972" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%d" index="2">101</arg>. All outputs of instance <<arg fmt="%s" index="3">sd</arg>> of block <<arg fmt="%s" index="4">SizeDecode</arg>> are unconnected in block <<arg fmt="%s" index="5">WarpLC</arg>>. Underlying logic will be removed.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2898" delta="old" >Port '<arg fmt="%s" index="1">RDFixed7k5SEL</arg>', unconnected in block instance '<arg fmt="%s" index="2">prefetch</arg>', is tied to GND.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CPU_nAS</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%s" index="2">91</arg>: Output port <<arg fmt="%s" index="3">B</arg>> of the instance <<arg fmt="%s" index="4">sd</arg>> is unconnected or connected to loadless signal.
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%s" index="2">92</arg>: Output port <<arg fmt="%s" index="3">CA</arg>> of the instance <<arg fmt="%s" index="4">cs</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ClkGen.v</arg>" line <arg fmt="%s" index="2">32</arg>: Output port <<arg fmt="%s" index="3">LOCKED</arg>> of the instance <<arg fmt="%s" index="4">pll</arg>> is unconnected or connected to loadless signal.
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%s" index="2">92</arg>: Output port <<arg fmt="%s" index="3">RAMCS</arg>> of the instance <<arg fmt="%s" index="4">cs</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">WRD</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%s" index="2">92</arg>: Output port <<arg fmt="%s" index="3">ROMCS</arg>> of the instance <<arg fmt="%s" index="4">cs</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CPUCLKr</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%s" index="2">92</arg>: Output port <<arg fmt="%s" index="3">VRAMCS</arg>> of the instance <<arg fmt="%s" index="4">cs</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%s" index="2">92</arg>: Output port <<arg fmt="%s" index="3">CacheCS</arg>> of the instance <<arg fmt="%s" index="4">cs</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%s" index="2">92</arg>: Output port <<arg fmt="%s" index="3">LoMemCacheCS</arg>> of the instance <<arg fmt="%s" index="4">cs</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%s" index="2">101</arg>: Output port <<arg fmt="%s" index="3">B</arg>> of the instance <<arg fmt="%s" index="4">sd</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">CLK</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v</arg>" line <arg fmt="%s" index="2">32</arg>: Output port <<arg fmt="%s" index="3">LOCKED</arg>> of the instance <<arg fmt="%s" index="4">pll</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v</arg>" line <arg fmt="%s" index="2">49</arg>: Output port <<arg fmt="%s" index="3">doutb</arg>> of the instance <<arg fmt="%s" index="4">data</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">RDA<27:12></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">WRM</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">TS</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">WR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">CLR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">ALL</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v</arg>" line <arg fmt="%s" index="2">39</arg>: Output port <<arg fmt="%s" index="3">doutb</arg>> of the instance <<arg fmt="%s" index="4">way</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="1901" delta="old" >Instance <arg fmt="%s" index="1">pll_base_inst</arg> in unit <arg fmt="%s" index="2">pll_base_inst</arg> of type <arg fmt="%s" index="3">PLL_BASE</arg> has been replaced by <arg fmt="%s" index="4">PLL_ADV</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<31></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<31></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<30></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<30></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<29></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<29></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<28></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<28></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<27></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<27></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<26></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<26></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<25></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<25></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<24></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<24></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<23></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<23></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<22></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<22></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<21></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<21></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<20></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<20></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<19></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<19></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<18></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<18></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<17></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<17></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<16></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<16></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<15></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<15></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<14></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<14></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<13></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<13></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<12></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<12></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<11></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<11></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<10></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<10></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<9></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<9></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<8></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<8></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<7></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<7></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<6></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<6></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<5></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<5></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<4></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<4></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<3></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<2></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
@ -8,7 +8,7 @@ PINATTR PinName addra[9:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 112 32 112
|
||||
PIN 0 112 LEFT 36
|
||||
PINATTR PinName dina[49:0]
|
||||
PINATTR PinName dina[46:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 144 32 144
|
||||
PIN 0 144 LEFT 36
|
||||
@ -28,7 +28,7 @@ PINATTR PinName addrb[9:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 464 32 464
|
||||
PIN 0 464 LEFT 36
|
||||
PINATTR PinName dinb[49:0]
|
||||
PINATTR PinName dinb[46:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 496 32 496
|
||||
PIN 0 496 LEFT 36
|
||||
@ -44,10 +44,10 @@ PINATTR PinName clkb
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 80 544 80
|
||||
PIN 576 80 RIGHT 36
|
||||
PINATTR PinName douta[49:0]
|
||||
PINATTR PinName douta[46:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 368 544 368
|
||||
PIN 576 368 RIGHT 36
|
||||
PINATTR PinName doutb[49:0]
|
||||
PINATTR PinName doutb[46:0]
|
||||
PINATTR Polarity OUT
|
||||
|
||||
|
||||
@ -32,19 +32,19 @@
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4291244256852075332" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4291244256852075332" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="740071792634416364" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="740071792634416364" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4263457726895274682" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4263457726895274682" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -1,26 +1,26 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<symbol version="7" name="L2WayRAM">
|
||||
<symboltype>BLOCK</symboltype>
|
||||
<timestamp>2021-11-1T9:40:30</timestamp>
|
||||
<timestamp>2021-11-2T4:31:47</timestamp>
|
||||
<pin polarity="Input" x="0" y="80" name="addra[9:0]" />
|
||||
<pin polarity="Input" x="0" y="112" name="dina[49:0]" />
|
||||
<pin polarity="Input" x="0" y="112" name="dina[46:0]" />
|
||||
<pin polarity="Input" x="0" y="144" name="ena" />
|
||||
<pin polarity="Input" x="0" y="208" name="wea[0:0]" />
|
||||
<pin polarity="Input" x="0" y="272" name="clka" />
|
||||
<pin polarity="Input" x="0" y="432" name="addrb[9:0]" />
|
||||
<pin polarity="Input" x="0" y="464" name="dinb[49:0]" />
|
||||
<pin polarity="Input" x="0" y="464" name="dinb[46:0]" />
|
||||
<pin polarity="Input" x="0" y="496" name="enb" />
|
||||
<pin polarity="Input" x="0" y="560" name="web[0:0]" />
|
||||
<pin polarity="Input" x="0" y="624" name="clkb" />
|
||||
<pin polarity="Output" x="576" y="80" name="douta[49:0]" />
|
||||
<pin polarity="Output" x="576" y="368" name="doutb[49:0]" />
|
||||
<pin polarity="Output" x="576" y="80" name="douta[46:0]" />
|
||||
<pin polarity="Output" x="576" y="368" name="doutb[46:0]" />
|
||||
<graph>
|
||||
<text style="fontsize:40;fontname:Arial" x="32" y="32">L2WayRAM</text>
|
||||
<rect width="512" x="32" y="32" height="1344" />
|
||||
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[9:0]" />
|
||||
<line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin dina[49:0]" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin dina[46:0]" />
|
||||
<line x2="32" y1="144" y2="144" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin ena" />
|
||||
<line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
|
||||
@ -30,7 +30,7 @@
|
||||
<line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[9:0]" />
|
||||
<line x2="32" y1="464" y2="464" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="464" type="pin dinb[49:0]" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="464" type="pin dinb[46:0]" />
|
||||
<line x2="32" y1="496" y2="496" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="496" type="pin enb" />
|
||||
<line x2="32" y1="560" y2="560" style="linewidth:W" x1="0" />
|
||||
@ -38,8 +38,8 @@
|
||||
<line x2="32" y1="624" y2="624" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
|
||||
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[49:0]" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[46:0]" />
|
||||
<line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[49:0]" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[46:0]" />
|
||||
</graph>
|
||||
</symbol>
|
||||
|
||||
@ -55,14 +55,14 @@ input clka;
|
||||
input ena;
|
||||
input [0 : 0] wea;
|
||||
input [9 : 0] addra;
|
||||
input [49 : 0] dina;
|
||||
output [49 : 0] douta;
|
||||
input [46 : 0] dina;
|
||||
output [46 : 0] douta;
|
||||
input clkb;
|
||||
input enb;
|
||||
input [0 : 0] web;
|
||||
input [9 : 0] addrb;
|
||||
input [49 : 0] dinb;
|
||||
output [49 : 0] doutb;
|
||||
input [46 : 0] dinb;
|
||||
output [46 : 0] doutb;
|
||||
|
||||
// synthesis translate_off
|
||||
|
||||
@ -105,8 +105,8 @@ output [49 : 0] doutb;
|
||||
.C_PRIM_TYPE(1),
|
||||
.C_READ_DEPTH_A(1024),
|
||||
.C_READ_DEPTH_B(1024),
|
||||
.C_READ_WIDTH_A(50),
|
||||
.C_READ_WIDTH_B(50),
|
||||
.C_READ_WIDTH_A(47),
|
||||
.C_READ_WIDTH_B(47),
|
||||
.C_RST_PRIORITY_A("CE"),
|
||||
.C_RST_PRIORITY_B("CE"),
|
||||
.C_RST_TYPE("SYNC"),
|
||||
@ -125,8 +125,8 @@ output [49 : 0] doutb;
|
||||
.C_WRITE_DEPTH_B(1024),
|
||||
.C_WRITE_MODE_A("READ_FIRST"),
|
||||
.C_WRITE_MODE_B("READ_FIRST"),
|
||||
.C_WRITE_WIDTH_A(50),
|
||||
.C_WRITE_WIDTH_B(50),
|
||||
.C_WRITE_WIDTH_A(47),
|
||||
.C_WRITE_WIDTH_B(47),
|
||||
.C_XDEVICEFAMILY("spartan6")
|
||||
)
|
||||
inst (
|
||||
|
||||
@ -52,14 +52,14 @@ L2WayRAM your_instance_name (
|
||||
.ena(ena), // input ena
|
||||
.wea(wea), // input [0 : 0] wea
|
||||
.addra(addra), // input [9 : 0] addra
|
||||
.dina(dina), // input [49 : 0] dina
|
||||
.douta(douta), // output [49 : 0] douta
|
||||
.dina(dina), // input [46 : 0] dina
|
||||
.douta(douta), // output [46 : 0] douta
|
||||
.clkb(clkb), // input clkb
|
||||
.enb(enb), // input enb
|
||||
.web(web), // input [0 : 0] web
|
||||
.addrb(addrb), // input [9 : 0] addrb
|
||||
.dinb(dinb), // input [49 : 0] dinb
|
||||
.doutb(doutb) // output [49 : 0] doutb
|
||||
.dinb(dinb), // input [46 : 0] dinb
|
||||
.doutb(doutb) // output [46 : 0] doutb
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.7
|
||||
# Date: Mon Nov 01 09:39:48 2021
|
||||
# Date: Tue Nov 02 04:31:03 2021
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
@ -74,8 +74,8 @@ CSET port_b_clock=100
|
||||
CSET port_b_enable_rate=100
|
||||
CSET port_b_write_rate=50
|
||||
CSET primitive=8kx2
|
||||
CSET read_width_a=50
|
||||
CSET read_width_b=50
|
||||
CSET read_width_a=47
|
||||
CSET read_width_b=47
|
||||
CSET register_porta_input_of_softecc=false
|
||||
CSET register_porta_output_of_memory_core=false
|
||||
CSET register_porta_output_of_memory_primitives=false
|
||||
@ -98,11 +98,11 @@ CSET use_regceb_pin=false
|
||||
CSET use_rsta_pin=false
|
||||
CSET use_rstb_pin=false
|
||||
CSET write_depth_a=1024
|
||||
CSET write_width_a=50
|
||||
CSET write_width_b=50
|
||||
CSET write_width_a=47
|
||||
CSET write_width_b=47
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-11-19T16:22:25Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 16400b8
|
||||
# CRC: f27df11b
|
||||
|
||||
@ -29,30 +29,359 @@
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|L2WayRAM" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="L2WayRAM.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/L2WayRAM" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="L2WayRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ftg256" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="L2WayRAM_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="L2WayRAM_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="L2WayRAM_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="L2WayRAM_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="L2WayRAM" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-11-01T05:40:35" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BCE6173C9B444AF498E2AE133C1C2EEF" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-11-02T00:31:51" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AC51AB601F0548EC9775FB075EB565ED" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
@ -93,9 +93,9 @@ ENTITY L2WayRAM_exdes IS
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
|
||||
DINA : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
|
||||
CLKA : IN STD_LOGIC;
|
||||
|
||||
@ -106,8 +106,8 @@ ENTITY L2WayRAM_exdes IS
|
||||
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
|
||||
DINB : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DINB : IN STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
CLKB : IN STD_LOGIC
|
||||
|
||||
);
|
||||
@ -132,9 +132,9 @@ ARCHITECTURE xilinx OF L2WayRAM_exdes IS
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
|
||||
DINA : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
|
||||
|
||||
CLKA : IN STD_LOGIC;
|
||||
@ -146,8 +146,8 @@ ARCHITECTURE xilinx OF L2WayRAM_exdes IS
|
||||
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
|
||||
DINB : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DINB : IN STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
CLKB : IN STD_LOGIC
|
||||
|
||||
|
||||
|
||||
@ -99,8 +99,8 @@
|
||||
-- C_USE_BYTE_WEA : 0
|
||||
-- C_WEA_WIDTH : 1
|
||||
-- C_WRITE_MODE_A : READ_FIRST
|
||||
-- C_WRITE_WIDTH_A : 50
|
||||
-- C_READ_WIDTH_A : 50
|
||||
-- C_WRITE_WIDTH_A : 47
|
||||
-- C_READ_WIDTH_A : 47
|
||||
-- C_WRITE_DEPTH_A : 1024
|
||||
-- C_READ_DEPTH_A : 1024
|
||||
-- C_ADDRA_WIDTH : 10
|
||||
@ -113,8 +113,8 @@
|
||||
-- C_USE_BYTE_WEB : 0
|
||||
-- C_WEB_WIDTH : 1
|
||||
-- C_WRITE_MODE_B : READ_FIRST
|
||||
-- C_WRITE_WIDTH_B : 50
|
||||
-- C_READ_WIDTH_B : 50
|
||||
-- C_WRITE_WIDTH_B : 47
|
||||
-- C_READ_WIDTH_B : 47
|
||||
-- C_WRITE_DEPTH_B : 1024
|
||||
-- C_READ_DEPTH_B : 1024
|
||||
-- C_ADDRB_WIDTH : 10
|
||||
@ -157,8 +157,8 @@ ENTITY L2WayRAM_prod IS
|
||||
REGCEA : IN STD_LOGIC; --optional port
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
|
||||
--Port B
|
||||
CLKB : IN STD_LOGIC;
|
||||
@ -167,8 +167,8 @@ ENTITY L2WayRAM_prod IS
|
||||
REGCEB : IN STD_LOGIC; --optional port
|
||||
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
DINB : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DINB : IN STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
|
||||
--ECC
|
||||
INJECTSBITERR : IN STD_LOGIC; --optional port
|
||||
@ -187,7 +187,7 @@ ENTITY L2WayRAM_prod IS
|
||||
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_WLAST : IN STD_LOGIC;
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
@ -206,7 +206,7 @@ ENTITY L2WayRAM_prod IS
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RLAST : OUT STD_LOGIC;
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
@ -236,9 +236,9 @@ ARCHITECTURE xilinx OF L2WayRAM_prod IS
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
|
||||
DINA : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
|
||||
|
||||
CLKA : IN STD_LOGIC;
|
||||
@ -250,8 +250,8 @@ ARCHITECTURE xilinx OF L2WayRAM_prod IS
|
||||
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
|
||||
DINB : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DINB : IN STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
CLKB : IN STD_LOGIC
|
||||
|
||||
|
||||
|
||||
@ -109,16 +109,16 @@ COMPONENT L2WayRAM_exdes
|
||||
ENA : IN STD_LOGIC; --opt port
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
CLKA : IN STD_LOGIC;
|
||||
|
||||
--Inputs - Port B
|
||||
ENB : IN STD_LOGIC; --opt port
|
||||
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
DINB : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
DINB : IN STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
CLKB : IN STD_LOGIC
|
||||
|
||||
);
|
||||
@ -134,9 +134,9 @@ END COMPONENT;
|
||||
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINA: STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINA_R: STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DOUTA: STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
SIGNAL DINA: STD_LOGIC_VECTOR(46 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINA_R: STD_LOGIC_VECTOR(46 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DOUTA: STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
SIGNAL CLKB: STD_LOGIC := '0';
|
||||
SIGNAL RSTB: STD_LOGIC := '0';
|
||||
SIGNAL ENB: STD_LOGIC := '0';
|
||||
@ -146,9 +146,9 @@ END COMPONENT;
|
||||
SIGNAL WEB_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ADDRB: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINB: STD_LOGIC_VECTOR( 49 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINB_R: STD_LOGIC_VECTOR( 49 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DOUTB: STD_LOGIC_VECTOR(49 DOWNTO 0);
|
||||
SIGNAL DINB: STD_LOGIC_VECTOR( 46 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINB_R: STD_LOGIC_VECTOR( 46 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DOUTB: STD_LOGIC_VECTOR(46 DOWNTO 0);
|
||||
SIGNAL CHECKER_EN : STD_LOGIC:='0';
|
||||
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
|
||||
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
|
||||
@ -227,8 +227,8 @@ STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
|
||||
|
||||
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
|
||||
GENERIC MAP (
|
||||
WRITE_WIDTH => 50,
|
||||
READ_WIDTH => 50 )
|
||||
WRITE_WIDTH => 47,
|
||||
READ_WIDTH => 47 )
|
||||
PORT MAP (
|
||||
CLK => CLKA,
|
||||
RST => RSTA,
|
||||
@ -249,8 +249,8 @@ STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
|
||||
|
||||
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
|
||||
GENERIC MAP (
|
||||
WRITE_WIDTH => 50,
|
||||
READ_WIDTH => 50 )
|
||||
WRITE_WIDTH => 47,
|
||||
READ_WIDTH => 47 )
|
||||
PORT MAP (
|
||||
CLK => CLKB,
|
||||
RST => RSTB,
|
||||
|
||||
@ -122,12 +122,12 @@ ENTITY BMG_STIM_GEN IS
|
||||
CLKB : IN STD_LOGIC;
|
||||
TB_RST : IN STD_LOGIC;
|
||||
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
|
||||
DINA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
|
||||
DINA : OUT STD_LOGIC_VECTOR(46 DOWNTO 0) := (OTHERS => '0');
|
||||
ENA : OUT STD_LOGIC :='0';
|
||||
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
|
||||
WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
|
||||
ADDRB : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
|
||||
DINB : OUT STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
|
||||
DINB : OUT STD_LOGIC_VECTOR(46 DOWNTO 0) := (OTHERS => '0');
|
||||
ENB : OUT STD_LOGIC :='0';
|
||||
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
|
||||
);
|
||||
@ -138,8 +138,8 @@ ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
|
||||
|
||||
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
|
||||
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(50,50);
|
||||
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(50,50);
|
||||
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(47,47);
|
||||
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(47,47);
|
||||
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
|
||||
@ -148,8 +148,8 @@ SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINA_INT : STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINB_INT : STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINA_INT : STD_LOGIC_VECTOR(46 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINB_INT : STD_LOGIC_VECTOR(46 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(1024,11);
|
||||
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
|
||||
SIGNAL DO_READ_A : STD_LOGIC := '0';
|
||||
@ -252,8 +252,8 @@ BEGIN
|
||||
);
|
||||
|
||||
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
|
||||
GENERIC MAP ( DATA_GEN_WIDTH =>50,
|
||||
DOUT_WIDTH => 50,
|
||||
GENERIC MAP ( DATA_GEN_WIDTH =>47,
|
||||
DOUT_WIDTH => 47,
|
||||
DATA_PART_CNT => 1,
|
||||
SEED => 2)
|
||||
|
||||
@ -265,8 +265,8 @@ BEGIN
|
||||
);
|
||||
|
||||
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
|
||||
GENERIC MAP ( DATA_GEN_WIDTH =>50,
|
||||
DOUT_WIDTH =>50 ,
|
||||
GENERIC MAP ( DATA_GEN_WIDTH =>47,
|
||||
DOUT_WIDTH =>47 ,
|
||||
DATA_PART_CNT =>1,
|
||||
SEED => 2)
|
||||
|
||||
|
||||
@ -31,19 +31,19 @@
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3888609537775819197" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3888609537775819197" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6060603849343674715" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6060603849343674715" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3791878364537811583" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3791878364537811583" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
|
||||
@ -32,19 +32,19 @@
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2412465949367085632" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2412465949367085632" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6843461273688002120" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6843461273688002120" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8592705777308130942" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8592705777308130942" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
|
||||
@ -17,11 +17,11 @@
|
||||
<files>
|
||||
<file xil_pn:name="PrefetchDataRAM.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="PrefetchDataRAM.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
|
||||
|
||||
@ -8,7 +8,7 @@ PINATTR PinName a[6:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 112 32 112
|
||||
PIN 0 112 LEFT 36
|
||||
PINATTR PinName d[21:0]
|
||||
PINATTR PinName d[19:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 144 32 144
|
||||
PIN 0 144 LEFT 36
|
||||
@ -24,10 +24,10 @@ PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 288 80 256 80
|
||||
PIN 288 80 RIGHT 36
|
||||
PINATTR PinName spo[21:0]
|
||||
PINATTR PinName spo[19:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 288 144 256 144
|
||||
PIN 288 144 RIGHT 36
|
||||
PINATTR PinName dpo[21:0]
|
||||
PINATTR PinName dpo[19:0]
|
||||
PINATTR Polarity OUT
|
||||
|
||||
|
||||
@ -32,19 +32,19 @@
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4471687479450306590" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4471687479450306590" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1159336514965820042" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1159336514965820042" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9130905431499320476" xil_pn:start_ts="1635761418">
|
||||
<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9130905431499320476" xil_pn:start_ts="1635827575">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -1,21 +1,21 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<symbol version="7" name="PrefetchTagRAM">
|
||||
<symboltype>BLOCK</symboltype>
|
||||
<timestamp>2021-11-1T10:9:55</timestamp>
|
||||
<timestamp>2021-11-2T4:32:27</timestamp>
|
||||
<pin polarity="Input" x="0" y="80" name="a[6:0]" />
|
||||
<pin polarity="Input" x="0" y="112" name="d[21:0]" />
|
||||
<pin polarity="Input" x="0" y="112" name="d[19:0]" />
|
||||
<pin polarity="Input" x="0" y="144" name="dpra[6:0]" />
|
||||
<pin polarity="Input" x="0" y="272" name="we" />
|
||||
<pin polarity="Input" x="0" y="304" name="clk" />
|
||||
<pin polarity="Output" x="288" y="80" name="spo[21:0]" />
|
||||
<pin polarity="Output" x="288" y="144" name="dpo[21:0]" />
|
||||
<pin polarity="Output" x="288" y="80" name="spo[19:0]" />
|
||||
<pin polarity="Output" x="288" y="144" name="dpo[19:0]" />
|
||||
<graph>
|
||||
<text style="fontsize:40;fontname:Arial" x="32" y="32">PrefetchTagRAM</text>
|
||||
<rect width="224" x="32" y="32" height="512" />
|
||||
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin a[6:0]" />
|
||||
<line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin d[21:0]" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin d[19:0]" />
|
||||
<line x2="32" y1="144" y2="144" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin dpra[6:0]" />
|
||||
<line x2="32" y1="272" y2="272" x1="0" />
|
||||
@ -23,8 +23,8 @@
|
||||
<line x2="32" y1="304" y2="304" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="304" type="pin clk" />
|
||||
<line x2="256" y1="80" y2="80" style="linewidth:W" x1="288" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="252" y="80" type="pin spo[21:0]" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="252" y="80" type="pin spo[19:0]" />
|
||||
<line x2="256" y1="144" y2="144" style="linewidth:W" x1="288" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="252" y="144" type="pin dpo[21:0]" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="252" y="144" type="pin dpo[19:0]" />
|
||||
</graph>
|
||||
</symbol>
|
||||
|
||||
@ -47,12 +47,12 @@ module PrefetchTagRAM(
|
||||
);
|
||||
|
||||
input [6 : 0] a;
|
||||
input [21 : 0] d;
|
||||
input [19 : 0] d;
|
||||
input [6 : 0] dpra;
|
||||
input clk;
|
||||
input we;
|
||||
output [21 : 0] spo;
|
||||
output [21 : 0] dpo;
|
||||
output [19 : 0] spo;
|
||||
output [19 : 0] dpo;
|
||||
|
||||
// synthesis translate_off
|
||||
|
||||
@ -88,7 +88,7 @@ output [21 : 0] dpo;
|
||||
.C_REG_A_D_INPUTS(0),
|
||||
.C_REG_DPRA_INPUT(0),
|
||||
.C_SYNC_ENABLE(1),
|
||||
.C_WIDTH(22)
|
||||
.C_WIDTH(20)
|
||||
)
|
||||
inst (
|
||||
.A(a),
|
||||
|
||||
@ -44,12 +44,12 @@
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
PrefetchTagRAM your_instance_name (
|
||||
.a(a), // input [6 : 0] a
|
||||
.d(d), // input [21 : 0] d
|
||||
.d(d), // input [19 : 0] d
|
||||
.dpra(dpra), // input [6 : 0] dpra
|
||||
.clk(clk), // input clk
|
||||
.we(we), // input we
|
||||
.spo(spo), // output [21 : 0] spo
|
||||
.dpo(dpo) // output [21 : 0] dpo
|
||||
.spo(spo), // output [19 : 0] spo
|
||||
.dpo(dpo) // output [19 : 0] dpo
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.7
|
||||
# Date: Mon Nov 01 10:09:33 2021
|
||||
# Date: Tue Nov 02 04:32:07 2021
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
@ -44,7 +44,7 @@ CSET coefficient_file=no_coe_file_loaded
|
||||
CSET common_output_ce=false
|
||||
CSET common_output_clk=false
|
||||
CSET component_name=PrefetchTagRAM
|
||||
CSET data_width=22
|
||||
CSET data_width=20
|
||||
CSET default_data=0
|
||||
CSET default_data_radix=16
|
||||
CSET depth=128
|
||||
@ -70,4 +70,4 @@ CSET sync_reset_qspo=false
|
||||
MISC pkg_timestamp=2012-11-21T20:07:40Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: ff3decec
|
||||
# CRC: c3055252
|
||||
|
||||
@ -29,30 +29,359 @@
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|PrefetchTagRAM" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="PrefetchTagRAM.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/PrefetchTagRAM" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="PrefetchTagRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ftg256" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="PrefetchTagRAM_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="PrefetchTagRAM_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="PrefetchTagRAM_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="PrefetchTagRAM_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="PrefetchTagRAM" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-11-01T06:10:00" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BE6DB839BC374125B3033C50E8C5E847" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-11-02T00:32:31" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="717B5E58B20940C0963F3478407C8E45" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
@ -78,11 +78,11 @@ entity PrefetchTagRAM_exdes is
|
||||
DPRA : IN STD_LOGIC_VECTOR(7-1 downto 0) := (OTHERS => '0');
|
||||
CLK : IN STD_LOGIC := '0';
|
||||
WE : IN STD_LOGIC := '0';
|
||||
SPO : OUT STD_LOGIC_VECTOR(22-1 downto 0);
|
||||
DPO : OUT STD_LOGIC_VECTOR(22-1 downto 0);
|
||||
SPO : OUT STD_LOGIC_VECTOR(20-1 downto 0);
|
||||
DPO : OUT STD_LOGIC_VECTOR(20-1 downto 0);
|
||||
A : IN STD_LOGIC_VECTOR(7-1-(4*0*boolean'pos(7>4)) downto 0)
|
||||
:= (OTHERS => '0');
|
||||
D : IN STD_LOGIC_VECTOR(22-1 downto 0) := (OTHERS => '0')
|
||||
D : IN STD_LOGIC_VECTOR(20-1 downto 0) := (OTHERS => '0')
|
||||
);
|
||||
|
||||
end PrefetchTagRAM_exdes;
|
||||
@ -99,11 +99,11 @@ architecture xilinx of PrefetchTagRAM_exdes is
|
||||
DPRA : IN STD_LOGIC_VECTOR(7-1 downto 0) := (OTHERS => '0');
|
||||
CLK : IN STD_LOGIC;
|
||||
WE : IN STD_LOGIC;
|
||||
SPO : OUT STD_LOGIC_VECTOR(22-1 downto 0);
|
||||
DPO : OUT STD_LOGIC_VECTOR(22-1 downto 0);
|
||||
SPO : OUT STD_LOGIC_VECTOR(20-1 downto 0);
|
||||
DPO : OUT STD_LOGIC_VECTOR(20-1 downto 0);
|
||||
A : IN STD_LOGIC_VECTOR(7-1-(4*0*boolean'pos(7>4)) downto 0)
|
||||
:= (OTHERS => '0');
|
||||
D : IN STD_LOGIC_VECTOR(22-1 downto 0) := (OTHERS => '0')
|
||||
D : IN STD_LOGIC_VECTOR(20-1 downto 0) := (OTHERS => '0')
|
||||
|
||||
);
|
||||
end component;
|
||||
|
||||
@ -77,7 +77,7 @@ entity PrefetchTagRAM_exdes is
|
||||
PORT (
|
||||
A : IN STD_LOGIC_VECTOR(7-1-(4*0*boolean'pos(7>4)) downto 0)
|
||||
:= (OTHERS => '0');
|
||||
D : IN STD_LOGIC_VECTOR(22-1 downto 0) := (OTHERS => '0');
|
||||
D : IN STD_LOGIC_VECTOR(20-1 downto 0) := (OTHERS => '0');
|
||||
DPRA : IN STD_LOGIC_VECTOR(7-1 downto 0) := (OTHERS => '0');
|
||||
SPRA : IN STD_LOGIC_VECTOR(7-1 downto 0) := (OTHERS => '0');
|
||||
CLK : IN STD_LOGIC := '0';
|
||||
@ -90,10 +90,10 @@ entity PrefetchTagRAM_exdes is
|
||||
QDPO_RST : IN STD_LOGIC := '0';
|
||||
QSPO_SRST : IN STD_LOGIC := '0';
|
||||
QDPO_SRST : IN STD_LOGIC := '0';
|
||||
SPO : OUT STD_LOGIC_VECTOR(22-1 downto 0);
|
||||
DPO : OUT STD_LOGIC_VECTOR(22-1 downto 0);
|
||||
QSPO : OUT STD_LOGIC_VECTOR(22-1 downto 0);
|
||||
QDPO : OUT STD_LOGIC_VECTOR(22-1 downto 0)
|
||||
SPO : OUT STD_LOGIC_VECTOR(20-1 downto 0);
|
||||
DPO : OUT STD_LOGIC_VECTOR(20-1 downto 0);
|
||||
QSPO : OUT STD_LOGIC_VECTOR(20-1 downto 0);
|
||||
QDPO : OUT STD_LOGIC_VECTOR(20-1 downto 0)
|
||||
);
|
||||
|
||||
end PrefetchTagRAM_exdes;
|
||||
@ -110,11 +110,11 @@ architecture xilinx of PrefetchTagRAM_exdes is
|
||||
DPRA : IN STD_LOGIC_VECTOR(7-1 downto 0) := (OTHERS => '0');
|
||||
CLK : IN STD_LOGIC;
|
||||
WE : IN STD_LOGIC;
|
||||
SPO : OUT STD_LOGIC_VECTOR(22-1 downto 0);
|
||||
DPO : OUT STD_LOGIC_VECTOR(22-1 downto 0);
|
||||
SPO : OUT STD_LOGIC_VECTOR(20-1 downto 0);
|
||||
DPO : OUT STD_LOGIC_VECTOR(20-1 downto 0);
|
||||
A : IN STD_LOGIC_VECTOR(7-1-(4*0*boolean'pos(7>4)) downto 0)
|
||||
:= (OTHERS => '0');
|
||||
D : IN STD_LOGIC_VECTOR(22-1 downto 0) := (OTHERS => '0')
|
||||
D : IN STD_LOGIC_VECTOR(20-1 downto 0) := (OTHERS => '0')
|
||||
|
||||
);
|
||||
end component;
|
||||
|
||||
@ -118,11 +118,11 @@ ENTITY PrefetchTagRAM_TB_STIM_GEN IS
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
A : OUT STD_LOGIC_VECTOR(7-1 downto 0) := (OTHERS => '0');
|
||||
D : OUT STD_LOGIC_VECTOR(22-1 downto 0) := (OTHERS => '0');
|
||||
D : OUT STD_LOGIC_VECTOR(20-1 downto 0) := (OTHERS => '0');
|
||||
DPRA : OUT STD_LOGIC_VECTOR(7-1 downto 0) := (OTHERS => '0');
|
||||
WE : OUT STD_LOGIC := '0';
|
||||
DATA_IN : IN STD_LOGIC_VECTOR (21 DOWNTO 0); --OUTPUT VECTOR
|
||||
DATA_IN_B : IN STD_LOGIC_VECTOR (21 DOWNTO 0); --OUTPUT VECTOR
|
||||
DATA_IN : IN STD_LOGIC_VECTOR (19 DOWNTO 0); --OUTPUT VECTOR
|
||||
DATA_IN_B : IN STD_LOGIC_VECTOR (19 DOWNTO 0); --OUTPUT VECTOR
|
||||
|
||||
|
||||
CHECK_DATA : OUT STD_LOGIC_VECTOR(1 downto 0) := (OTHERS => '0')
|
||||
@ -143,8 +143,8 @@ ARCHITECTURE BEHAVIORAL OF PrefetchTagRAM_TB_STIM_GEN IS
|
||||
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL D_INT_A : STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL D_INT_B : STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL D_INT_A : STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL D_INT_B : STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
|
||||
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
|
||||
SIGNAL DO_WRITE : STD_LOGIC := '0';
|
||||
@ -215,8 +215,8 @@ WR_AGEN_INST_A:ENTITY work.PrefetchTagRAM_TB_AGEN
|
||||
|
||||
WR_DGEN_INST_A:ENTITY work.PrefetchTagRAM_TB_DGEN
|
||||
GENERIC MAP (
|
||||
DATA_GEN_WIDTH => 22,
|
||||
DOUT_WIDTH => 22,
|
||||
DATA_GEN_WIDTH => 20,
|
||||
DOUT_WIDTH => 20,
|
||||
DATA_PART_CNT => DATA_PART_CNT_A,
|
||||
SEED => 2
|
||||
)
|
||||
@ -254,8 +254,8 @@ WR_AGEN_INST_B:ENTITY work.PrefetchTagRAM_TB_AGEN
|
||||
|
||||
WR_DGEN_INST_B:ENTITY work.PrefetchTagRAM_TB_DGEN
|
||||
GENERIC MAP (
|
||||
DATA_GEN_WIDTH => 22,
|
||||
DOUT_WIDTH => 22,
|
||||
DATA_GEN_WIDTH => 20,
|
||||
DOUT_WIDTH => 20,
|
||||
DATA_PART_CNT => DATA_PART_CNT_B,
|
||||
SEED => 2
|
||||
)
|
||||
|
||||
@ -102,11 +102,11 @@ COMPONENT PrefetchTagRAM_exdes
|
||||
DPRA : IN STD_LOGIC_VECTOR(7-1 downto 0) := (OTHERS => '0');
|
||||
CLK : IN STD_LOGIC := '0';
|
||||
WE : IN STD_LOGIC := '0';
|
||||
SPO : OUT STD_LOGIC_VECTOR(22-1 downto 0);
|
||||
DPO : OUT STD_LOGIC_VECTOR(22-1 downto 0);
|
||||
SPO : OUT STD_LOGIC_VECTOR(20-1 downto 0);
|
||||
DPO : OUT STD_LOGIC_VECTOR(20-1 downto 0);
|
||||
A : IN STD_LOGIC_VECTOR(7-1-(4*0*boolean'pos(7>4)) downto 0)
|
||||
:= (OTHERS => '0');
|
||||
D : IN STD_LOGIC_VECTOR(22-1 downto 0) := (OTHERS => '0')
|
||||
D : IN STD_LOGIC_VECTOR(20-1 downto 0) := (OTHERS => '0')
|
||||
);
|
||||
|
||||
END COMPONENT;
|
||||
@ -128,12 +128,12 @@ END COMPONENT;
|
||||
SIGNAL DPRA_R: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL WE : STD_LOGIC:='0';
|
||||
SIGNAL WE_R : STD_LOGIC:='0';
|
||||
SIGNAL SPO: STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL SPO_R: STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DPO: STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DPO_R: STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL D: STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL D_R: STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL SPO: STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL SPO_R: STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DPO: STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DPO_R: STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL D: STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL D_R: STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL CHECKER_EN_R: STD_LOGIC:='0';
|
||||
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
|
||||
@ -188,8 +188,8 @@ STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
|
||||
|
||||
DMG_DATA_CHECKER_INST_A: ENTITY work.PrefetchTagRAM_TB_CHECKER
|
||||
GENERIC MAP (
|
||||
WRITE_WIDTH => 22,
|
||||
READ_WIDTH => 22 )
|
||||
WRITE_WIDTH => 20,
|
||||
READ_WIDTH => 20 )
|
||||
PORT MAP (
|
||||
CLK => CLKA,
|
||||
RST => RSTA,
|
||||
@ -210,8 +210,8 @@ STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
|
||||
|
||||
DMG_DATA_CHECKER_INST_B: ENTITY work.PrefetchTagRAM_TB_CHECKER
|
||||
GENERIC MAP (
|
||||
WRITE_WIDTH => 22,
|
||||
READ_WIDTH => 22 )
|
||||
WRITE_WIDTH => 20,
|
||||
READ_WIDTH => 20 )
|
||||
PORT MAP (
|
||||
CLK => CLKA,
|
||||
RST => RSTA,
|
||||
|
||||
@ -8,22 +8,22 @@
|
||||
<msg type="info" file="sim" num="172" delta="old" >Generating IP...
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'PrefetchDataRAM' already exists in the project. Output products for this core may be overwritten.</arg>
|
||||
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'PrefetchTagRAM' already exists in the project. Output products for this core may be overwritten.</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'PrefetchDataRAM' already exists in the project. Output products for this core may be overwritten.</arg>
|
||||
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'PrefetchTagRAM' already exists in the project. Output products for this core may be overwritten.</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'PrefetchDataRAM'...</arg>
|
||||
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'PrefetchTagRAM'...</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Overwriting existing file C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchDataRAM/doc/blk_mem_gen_v7_3_vinfo.html with file from view xilinx_documentation</arg>
|
||||
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Overwriting existing file C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM/doc/dist_mem_gen_v7_2_vinfo.html with file from view xilinx_documentation</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="sim" num="949" delta="new" >Finished generation of ASY schematic symbol.
|
||||
<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="sim" num="948" delta="new" >Finished FLIST file generation.
|
||||
<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<messages>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/L2WayRAM.v" into library work</arg>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/PrefetchTagRAM.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
@ -1,67 +1,67 @@
|
||||
INFO:sim:172 - Generating IP...
|
||||
Applying current project options...
|
||||
Finished applying current project options.
|
||||
WARNING:sim - A core named 'PrefetchDataRAM' already exists in the project.
|
||||
WARNING:sim - A core named 'PrefetchTagRAM' already exists in the project.
|
||||
Output products for this core may be overwritten.
|
||||
Resolving generics for 'PrefetchDataRAM'...
|
||||
WARNING:sim - A core named 'PrefetchDataRAM' already exists in the project.
|
||||
Resolving generics for 'PrefetchTagRAM'...
|
||||
WARNING:sim - A core named 'PrefetchTagRAM' already exists in the project.
|
||||
Output products for this core may be overwritten.
|
||||
Applying external generics to 'PrefetchDataRAM'...
|
||||
Delivering associated files for 'PrefetchDataRAM'...
|
||||
Delivering EJava files for 'PrefetchDataRAM'...
|
||||
Generating implementation netlist for 'PrefetchDataRAM'...
|
||||
INFO:sim - Pre-processing HDL files for 'PrefetchDataRAM'...
|
||||
Running synthesis for 'PrefetchDataRAM'
|
||||
Applying external generics to 'PrefetchTagRAM'...
|
||||
Delivering associated files for 'PrefetchTagRAM'...
|
||||
Delivering EJava files for 'PrefetchTagRAM'...
|
||||
Generating implementation netlist for 'PrefetchTagRAM'...
|
||||
INFO:sim - Pre-processing HDL files for 'PrefetchTagRAM'...
|
||||
Running synthesis for 'PrefetchTagRAM'
|
||||
Running ngcbuild...
|
||||
Writing VEO instantiation template for 'PrefetchDataRAM'...
|
||||
Writing Verilog behavioral simulation model for 'PrefetchDataRAM'...
|
||||
Writing VEO instantiation template for 'PrefetchTagRAM'...
|
||||
Writing Verilog behavioral simulation model for 'PrefetchTagRAM'...
|
||||
WARNING:sim - Overwriting existing file
|
||||
C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchDataR
|
||||
AM/doc/blk_mem_gen_v7_3_vinfo.html with file from view xilinx_documentation
|
||||
Delivered 1 file into directory
|
||||
C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchDataRAM
|
||||
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM/
|
||||
doc/dist_mem_gen_v7_2_vinfo.html with file from view xilinx_documentation
|
||||
Delivered 2 files into directory
|
||||
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM
|
||||
Generating ASY schematic symbol...
|
||||
INFO:sim:949 - Finished generation of ASY schematic symbol.
|
||||
Generating SYM schematic symbol for 'PrefetchDataRAM'...
|
||||
Generating SYM schematic symbol for 'PrefetchTagRAM'...
|
||||
Generating metadata file...
|
||||
Regenerating ISE project file for 'PrefetchDataRAM'...
|
||||
Regenerating ISE project file for 'PrefetchTagRAM'...
|
||||
Generating ISE project...
|
||||
XCO file found: PrefetchDataRAM.xco
|
||||
XMDF file found: PrefetchDataRAM_xmdf.tcl
|
||||
XCO file found: PrefetchTagRAM.xco
|
||||
XMDF file found: PrefetchTagRAM_xmdf.tcl
|
||||
Adding
|
||||
C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchDataRAM.
|
||||
asy -view all -origin_type imported
|
||||
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.asy
|
||||
-view all -origin_type imported
|
||||
Adding
|
||||
C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchDataRAM.
|
||||
ngc -view all -origin_type created
|
||||
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.ngc
|
||||
-view all -origin_type created
|
||||
Checking file
|
||||
"C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchDataRAM
|
||||
.ngc" for project device match ...
|
||||
"C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.ng
|
||||
c" for project device match ...
|
||||
File
|
||||
"C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchDataRAM
|
||||
.ngc" device information matches project device.
|
||||
"C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.ng
|
||||
c" device information matches project device.
|
||||
Adding
|
||||
C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchDataRAM.
|
||||
sym -view all -origin_type imported
|
||||
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.sym
|
||||
-view all -origin_type imported
|
||||
Adding
|
||||
C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchDataRAM.
|
||||
v -view all -origin_type created
|
||||
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.v
|
||||
-view all -origin_type created
|
||||
INFO:HDLCompiler:1845 - Analyzing Verilog file
|
||||
"C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchData
|
||||
RAM.v" into library work
|
||||
"C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM
|
||||
.v" into library work
|
||||
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
|
||||
Adding
|
||||
C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchDataRAM.
|
||||
veo -view all -origin_type imported
|
||||
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.veo
|
||||
-view all -origin_type imported
|
||||
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
|
||||
Please set the new top explicitly by running the "project set top" command.
|
||||
To re-calculate the new top automatically, set the "Auto Implementation Top"
|
||||
property to true.
|
||||
Top level has been set to "/PrefetchDataRAM"
|
||||
Top level has been set to "/PrefetchTagRAM"
|
||||
Generating README file...
|
||||
Generating FLIST file...
|
||||
INFO:sim:948 - Finished FLIST file generation.
|
||||
Launching README viewer...
|
||||
Moving files to output directory...
|
||||
Finished moving files to output directory
|
||||
Wrote CGP file for project 'PrefetchDataRAM'.
|
||||
Wrote CGP file for project 'PrefetchTagRAM'.
|
||||
|
||||
@ -3,19 +3,19 @@ User Configuration
|
||||
-------------------------------------
|
||||
Algorithm : Minimum_Area
|
||||
Memory Type : True_Dual_Port_RAM
|
||||
Port A Read Width : 32
|
||||
Port B Read Width : 32
|
||||
Port A Write Width : 32
|
||||
Port B Write Width : 32
|
||||
Memory Depth : 2048
|
||||
Port A Read Width : 47
|
||||
Port B Read Width : 47
|
||||
Port A Write Width : 47
|
||||
Port B Write Width : 47
|
||||
Memory Depth : 1024
|
||||
--------------------------------------------------------------
|
||||
|
||||
Block RAM resource(s) (9K BRAMs) : 0
|
||||
Block RAM resource(s) (18K BRAMs) : 4
|
||||
Block RAM resource(s) (18K BRAMs) : 3
|
||||
--------------------------------------------------------------
|
||||
Clock A Frequency : 100
|
||||
Port A Enable Rate : 100
|
||||
Port A Write Rate : 50
|
||||
----------------------------------------------------------
|
||||
Estimated Power for IP : 12.385856 mW
|
||||
Estimated Power for IP : 11.043736 mW
|
||||
----------------------------------------------------------
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<messages>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/PrefetchDataRAM.v" into library work</arg>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/L2WayRAM.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
@ -5,451 +5,97 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="UtilitiesC" num="159" delta="old" >Message file "<arg fmt="%s" index="1">usenglish/ip.msg</arg>" wasn't found.
|
||||
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\dist_mem_gen_v7_2\dist_mem_gen_v7_2.vhd" Line 142: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">8</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">8</arg>
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\dist_mem_gen_v7_2\dist_mem_gen_v7_2_xst.vhd" Line 164: Assignment to <arg fmt="%s" index="1">gnd_bus</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">8</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">8</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">8</arg>
|
||||
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\dist_mem_gen_v7_2\dist_mem_gen_v7_2.vhd" Line 164: Net <<arg fmt="%s" index="1">gnd</arg>> does not have a driver.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">2</arg>: (<arg fmt="%d" index="2">16</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">8</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">8</arg>
|
||||
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\dist_mem_gen_v7_2\dist_mem_gen_v7_2.vhd" Line 165: Net <<arg fmt="%s" index="1">gnd_bus[6]</arg>> does not have a driver.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">24</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">8</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">8</arg>
|
||||
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\dist_mem_gen_v7_2\dist_mem_gen_v7_2.vhd" Line 166: Net <<arg fmt="%s" index="1">vcc</arg>> does not have a driver.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">8</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">8</arg>
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchTagRAM.vhd</arg>" line <arg fmt="%s" index="2">121</arg>: Output port <<arg fmt="%s" index="3">qspo</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">8</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">8</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">8</arg>
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchTagRAM.vhd</arg>" line <arg fmt="%s" index="2">121</arg>: Output port <<arg fmt="%s" index="3">qdpo</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">2</arg>: (<arg fmt="%d" index="2">16</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">8</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">8</arg>
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">spra</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">24</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">8</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">8</arg>
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">i_ce</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qspo_ce</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qdpo_ce</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="746" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_width.vhd" Line 978: Range is empty (null range)
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qdpo_clk</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="220" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_width.vhd" Line 978: Assignment ignored
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qspo_rst</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="746" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_width.vhd" Line 979: Range is empty (null range)
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qdpo_rst</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="220" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_width.vhd" Line 979: Assignment ignored
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qspo_srst</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_width.vhd" Line 430: Net <<arg fmt="%s" index="1">dina_pad[8]</arg>> does not have a driver.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qdpo_srst</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_width.vhd" Line 434: Net <<arg fmt="%s" index="1">dinb_pad[8]</arg>> does not have a driver.
|
||||
<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">gnd_bus<6:0></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd" Line 1546: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
|
||||
<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">gnd</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd" Line 1559: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
|
||||
<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">vcc</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_mux.vhd" Line 459: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">spra</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_mux.vhd" Line 470: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">i_ce</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_mux.vhd" Line 472: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qspo_ce</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_mux.vhd" Line 872: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qspo_rst</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd" Line 447: Net <<arg fmt="%s" index="1">sbiterr_array[7]</arg>> does not have a driver.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qspo_srst</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd" Line 448: Net <<arg fmt="%s" index="1">dbiterr_array[7]</arg>> does not have a driver.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qdpo_clk</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">rdaddrecc</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qdpo_ce</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_bid</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qdpo_rst</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_bresp</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">qdpo_srst</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_rid</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">qspo</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_rdata</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">qdpo</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_rresp</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_rdaddrecc</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">sbiterr</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">dbiterr</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_awready</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_wready</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_bvalid</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_arready</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_rlast</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_rvalid</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_sbiterr</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchDataRAM.vhd</arg>" line <arg fmt="%s" index="2">165</arg>: Output port <<arg fmt="%s" index="3">s_axi_dbiterr</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_AWID</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_AWADDR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_AWLEN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_AWSIZE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_AWBURST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_WDATA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_WSTRB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_ARID</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_ARADDR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_ARLEN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_ARSIZE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_ARBURST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AClk</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_ARESETN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_AWVALID</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_WLAST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_WVALID</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_BREADY</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_ARVALID</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_RREADY</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">S_AXI_INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2935" delta="old" >Signal '<arg fmt="%s" index="1">S_AXI_BID</arg>', unconnected in block '<arg fmt="%s" index="2">blk_mem_gen_v7_3_xst</arg>', is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">S_AXI_BRESP</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2935" delta="old" >Signal '<arg fmt="%s" index="1">S_AXI_RID</arg>', unconnected in block '<arg fmt="%s" index="2">blk_mem_gen_v7_3_xst</arg>', is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">S_AXI_RDATA</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">S_AXI_RRESP</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">S_AXI_RDADDRECC</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">S_AXI_AWREADY</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">S_AXI_WREADY</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">S_AXI_BVALID</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">S_AXI_ARREADY</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">S_AXI_RLAST</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">S_AXI_RVALID</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">S_AXI_SBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">S_AXI_DBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">RSTA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">RSTB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">INJECTDBITERR_I</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">INJECTSBITERR_I</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1342</arg>: Output port <<arg fmt="%s" index="3">SBITERR</arg>> of the instance <<arg fmt="%s" index="4">ramloop[0].ram.r</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1342</arg>: Output port <<arg fmt="%s" index="3">DBITERR</arg>> of the instance <<arg fmt="%s" index="4">ramloop[0].ram.r</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1342</arg>: Output port <<arg fmt="%s" index="3">SBITERR</arg>> of the instance <<arg fmt="%s" index="4">ramloop[1].ram.r</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1342</arg>: Output port <<arg fmt="%s" index="3">DBITERR</arg>> of the instance <<arg fmt="%s" index="4">ramloop[1].ram.r</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1342</arg>: Output port <<arg fmt="%s" index="3">SBITERR</arg>> of the instance <<arg fmt="%s" index="4">ramloop[2].ram.r</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1342</arg>: Output port <<arg fmt="%s" index="3">DBITERR</arg>> of the instance <<arg fmt="%s" index="4">ramloop[2].ram.r</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1342</arg>: Output port <<arg fmt="%s" index="3">SBITERR</arg>> of the instance <<arg fmt="%s" index="4">ramloop[3].ram.r</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1342</arg>: Output port <<arg fmt="%s" index="3">DBITERR</arg>> of the instance <<arg fmt="%s" index="4">ramloop[3].ram.r</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1606</arg>: Output port <<arg fmt="%s" index="3">RDADDRECC</arg>> of the instance <<arg fmt="%s" index="4">has_mux_a.A</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1606</arg>: Output port <<arg fmt="%s" index="3">SBITERR</arg>> of the instance <<arg fmt="%s" index="4">has_mux_a.A</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1606</arg>: Output port <<arg fmt="%s" index="3">DBITERR</arg>> of the instance <<arg fmt="%s" index="4">has_mux_a.A</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1750</arg>: Output port <<arg fmt="%s" index="3">RDADDRECC</arg>> of the instance <<arg fmt="%s" index="4">has_mux_b.B</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1750</arg>: Output port <<arg fmt="%s" index="3">SBITERR</arg>> of the instance <<arg fmt="%s" index="4">has_mux_b.B</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%s" index="2">1750</arg>: Output port <<arg fmt="%s" index="3">DBITERR</arg>> of the instance <<arg fmt="%s" index="4">has_mux_b.B</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">RDADDRECC</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2935" delta="new" >Signal '<arg fmt="%s" index="1">sbiterr_array</arg>', unconnected in block '<arg fmt="%s" index="2">blk_mem_gen_generic_cstr</arg>', is tied to its initial value (<arg fmt="%s" index="3">00000000</arg>).
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2935" delta="new" >Signal '<arg fmt="%s" index="1">dbiterr_array</arg>', unconnected in block '<arg fmt="%s" index="2">blk_mem_gen_generic_cstr</arg>', is tied to its initial value (<arg fmt="%s" index="3">00000000</arg>).
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">SBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">DBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2935" delta="new" >Signal '<arg fmt="%s" index="1">dina_pad<8></arg>', unconnected in block '<arg fmt="%s" index="2">blk_mem_gen_prim_width_1</arg>', is tied to its initial value (<arg fmt="%s" index="3">0</arg>).
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2935" delta="new" >Signal '<arg fmt="%s" index="1">dinb_pad<8></arg>', unconnected in block '<arg fmt="%s" index="2">blk_mem_gen_prim_width_1</arg>', is tied to its initial value (<arg fmt="%s" index="3">0</arg>).
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">SBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">DBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2935" delta="new" >Signal '<arg fmt="%s" index="1">dina_pad<8></arg>', unconnected in block '<arg fmt="%s" index="2">blk_mem_gen_prim_width_2</arg>', is tied to its initial value (<arg fmt="%s" index="3">0</arg>).
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2935" delta="new" >Signal '<arg fmt="%s" index="1">dinb_pad<8></arg>', unconnected in block '<arg fmt="%s" index="2">blk_mem_gen_prim_width_2</arg>', is tied to its initial value (<arg fmt="%s" index="3">0</arg>).
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">SBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">DBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2935" delta="new" >Signal '<arg fmt="%s" index="1">dina_pad<8></arg>', unconnected in block '<arg fmt="%s" index="2">blk_mem_gen_prim_width_3</arg>', is tied to its initial value (<arg fmt="%s" index="3">0</arg>).
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2935" delta="new" >Signal '<arg fmt="%s" index="1">dinb_pad<8></arg>', unconnected in block '<arg fmt="%s" index="2">blk_mem_gen_prim_width_3</arg>', is tied to its initial value (<arg fmt="%s" index="3">0</arg>).
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">SBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">DBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2935" delta="new" >Signal '<arg fmt="%s" index="1">dina_pad<8></arg>', unconnected in block '<arg fmt="%s" index="2">blk_mem_gen_prim_width_4</arg>', is tied to its initial value (<arg fmt="%s" index="3">0</arg>).
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2935" delta="new" >Signal '<arg fmt="%s" index="1">dinb_pad<8></arg>', unconnected in block '<arg fmt="%s" index="2">blk_mem_gen_prim_width_4</arg>', is tied to its initial value (<arg fmt="%s" index="3">0</arg>).
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">SBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">DBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MUX_RST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MUX_REGCE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">ADDR_IN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">SBITERRIN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">DBITERRIN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MEM_LAT_RST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MEM_REG_RST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MEM_REGCE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">WE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">RDADDRECC_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CLKB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">SBITERR_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">DBITERR_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">RDADDRECC</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">SBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">DBITERR</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">has_mux_b.B/sel_pipe_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">blk_mem_gen_generic_cstr</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">has_mux_a.A/sel_pipe_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">blk_mem_gen_generic_cstr</arg>>.
|
||||
<msg type="info" file="Xst" num="3216" delta="new" >HDL ADVISOR - LUT implementation is currently selected for the RAM <<arg fmt="%s" index="1">Mram_ram</arg>>. If you want the register to be removed and the RAM to be implemented as block RAM, please change the RAM implementation style accordingly.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
||||
|
||||
@ -10,13 +10,13 @@
|
||||
<ClosedNode>/ClkGen C:|Users|Dog|Documents|GitHub|Warp-LC|fpga|ClkGen.v</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>WarpLC (C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.v)</SelectedItem>
|
||||
<SelectedItem>WarpLC (C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.v)</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001f9000000020000000000000000000000000200000064ffffffff000000810000000300000002000001f90000000100000003000000000000000100000003</ViewHeaderState>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000016a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000016a0000000100000003000000000000000100000003</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
|
||||
<CurrentItem>WarpLC (C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.v)</CurrentItem>
|
||||
<CurrentItem>WarpLC (C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.v)</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
@ -28,13 +28,13 @@
|
||||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem/>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000</ViewHeaderState>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000153000000010000000100000000000000000000000064ffffffff000000810000000000000001000001530000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem/>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView guiview="File" >
|
||||
<ClosedNodes>
|
||||
@ -43,7 +43,7 @@
|
||||
<SelectedItems/>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000002d70000000100000000</ViewHeaderState>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000032b000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004200000001000000000000002400000001000000000000006600000001000000000000025f0000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>WarpLC.v</CurrentItem>
|
||||
</ItemView>
|
||||
@ -87,9 +87,9 @@
|
||||
<SelectedItems>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="vertical" >12</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000ea000000010000000100000000000000000000000064ffffffff000000810000000000000001000000ea0000000100000000</ViewHeaderState>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000142000000010000000100000000000000000000000064ffffffff000000810000000000000001000001420000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
@ -98,13 +98,13 @@
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem/>
|
||||
<SelectedItem>CORE Generator</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000</ViewHeaderState>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000153000000010000000100000000000000000000000064ffffffff000000810000000000000001000001530000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem/>
|
||||
<CurrentItem>CORE Generator</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2021-11-01T12:11:55</DateModified>
|
||||
<DateModified>2021-11-02T00:18:51</DateModified>
|
||||
<ModuleName>WarpLC</ModuleName>
|
||||
<SummaryTimeStamp>2021-11-01T06:10:50</SummaryTimeStamp>
|
||||
<SavedFilePath>C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/iseconfig/WarpLC.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\</ImplementationReportsDirectory>
|
||||
<SavedFilePath>C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/iseconfig/WarpLC.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\</ImplementationReportsDirectory>
|
||||
<DateInitialized>2021-10-29T06:26:45</DateInitialized>
|
||||
<EnableMessageFiltering>false</EnableMessageFiltering>
|
||||
</header>
|
||||
|
||||
@ -1,33 +1,33 @@
|
||||
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
|
||||
<xtag-section name="ParStatistics">
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>63</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>348</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>348</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>676</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>1810</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>1810</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>2.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>2.5 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>3.0 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>3.2 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>3.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>3.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>3.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>3.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>3.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>3.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 11 CPU</xtag-par-property-name>=<xtag-par-property-value>3.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>7.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>7.5</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>0.7</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>3.4 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>3.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>5.1 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>5.5 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>8.0 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>8.0 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>8.0 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>8.0 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>8.0 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>8.0 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 11 CPU</xtag-par-property-name>=<xtag-par-property-value>8.0 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>10.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>13.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>13.7</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>10.1</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>15.6</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>14.5</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>14.9</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0313</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.6608</xtag-par-property-value></TD></TR>
|
||||
</xtag-section>
|
||||
</TABLE>
|
||||
|
||||
@ -3,11 +3,11 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pn" timeStamp="Mon Nov 01 06:10:40 2021">
|
||||
<application name="pn" timeStamp="Tue Nov 02 00:32:55 2021">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="048F5CC81F664AF08A457B4C46CE1270" type="project"/>
|
||||
<property name="ProjectIteration" value="40" type="project"/>
|
||||
<property name="ProjectFile" value="C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xise" type="project"/>
|
||||
<property name="ProjectIteration" value="42" type="project"/>
|
||||
<property name="ProjectFile" value="C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xise" type="project"/>
|
||||
<property name="ProjectCreationTimestamp" value="2021-10-29T06:11:44" type="project"/>
|
||||
</section>
|
||||
<section name="Project Statistics" visible="true">
|
||||
@ -28,14 +28,13 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
|
||||
<property name="PROP_intProjectCreationTimestamp" value="2021-10-29T06:11:44" type="design"/>
|
||||
<property name="PROP_intWbtProjectID" value="048F5CC81F664AF08A457B4C46CE1270" type="design"/>
|
||||
<property name="PROP_intWbtProjectIteration" value="40" type="process"/>
|
||||
<property name="PROP_intWbtProjectIteration" value="42" type="process"/>
|
||||
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
|
||||
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
|
||||
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
|
||||
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
|
||||
<property name="PROP_xilxPostTrceUncovPath" value="10000" type="process"/>
|
||||
<property name="PROP_xilxSynthGlobOpt" value="Inpad To Outpad" type="process"/>
|
||||
<property name="PROPEXT_parGenAsyDlyRpt_spartan6" value="true" type="process"/>
|
||||
<property name="PROP_AutoTop" value="true" type="design"/>
|
||||
<property name="PROP_DevFamily" value="Spartan6" type="design"/>
|
||||
<property name="PROP_MapExtraEffort_spartan6" value="Continue on Impossible" type="process"/>
|
||||
@ -56,7 +55,7 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="PROP_netgenPostXlateSimModelName" value="L2Prefetch_translate.v" type="process"/>
|
||||
<property name="FILE_COREGEN" value="4" type="source"/>
|
||||
<property name="FILE_UCF" value="1" type="source"/>
|
||||
<property name="FILE_VERILOG" value="6" type="source"/>
|
||||
<property name="FILE_VERILOG" value="7" type="source"/>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
|
||||
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Loading…
x
Reference in New Issue
Block a user