Macintosh-HW/Warp-LC
1
0
Fork 0
mirror of https://github.com/garrettsworkshop/Warp-LC.git synced 2025-02-19 18:31:12 +00:00
Code Issues Projects Releases Wiki Activity

Cache stuff

Browse Source
This commit is contained in:
Zane Kaminski 2021-11-01 12:12:16 -04:00
parent 374d7663d3
commit 22482ee4e4
336 changed files with 9320 additions and 28526 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
fpga/CS.v Normal file
View File

@ -0,0 +1,22 @@
module CS(
input [31:8] A
output RAMCS,
output ROMCS,
output VRAMCS,
output CacheCS,
output LoMemCacheCS,
output [27:0] CA);
assign RAMCS = A[31:30]==2'b00;
assign ROMCS = A[31:28]==4'h4;
assign VRAMCS = A[31:20]==12'h50F;
assign CacheCS = RAMCS || ROMCS || VRAMCS;
assign LoMemCacheCS = RAMCS && A[25:12]==0;
assign CA[27] = A[30];
assign CA[26] = A[28];
assign CA[25:0] = A[25:0];
endmodule

65
fpga/L2Cache.v
View File

@ -1,25 +1,48 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:44:08 10/31/2021
// Design Name:
// Module Name: L2Cache
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module L2Cache(
);
input CLK,
input CPUCLKr,
input [27:2] RDA,
output [31:0] RDD,
output Match,
input [27:2] WRA,
input [31:0] WRD,
input [3:0] WRM,
input TS,
input WR,
input CLR,
input ALL);
/* Cache ways */
wire [31:0] WayRDD[7:0];
wire WayRDMatch[7:0];
L2CacheWay Way[7:0] (
.CLK(CLK),
.CPUCLKr(CPUCLKr),
.RDA(RDA),
.RDD(WayRDD),
.RDMatch(WayRDMatch),
.WRA(WRA),
.WRD(WRD),
.WRM(WRM),
.TS(TS),
.WR(WR),
.CLR(CLR),
.ALL(ALL));
assign Match == WayRDMatch[0] || WayRDMatch[1] ||
WayRDMatch[2] || WayRDMatch[3] ||
WayRDMatch[4] || WayRDMatch[5] ||
WayRDMatch[6] || WayRDMatch[7];
assign RDD[31:0] = WayRDMatch[0] ? WayRDD[0] :
WayRDMatch[1] ? WayRDD[1] :
WayRDMatch[2] ? WayRDD[2] :
WayRDMatch[3] ? WayRDD[3] :
WayRDMatch[4] ? WayRDD[4] :
WayRDMatch[5] ? WayRDD[5] :
WayRDMatch[6] ? WayRDD[6] :
WayRDMatch[7] ? WayRDD[7] : 0;
endmodule

1
fpga/L2CacheWay.cmd_log Normal file
View File

@ -0,0 +1 @@
vhdtdtfi -lang verilog -prj WarpLC -o C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/L2CacheWay.tfi -lib work C:/Users/zanek/Documents/GitHub/Warp-LC/fpga//L2CacheWay.v -module L2CacheWay -template C:/Xilinx/14.7/ISE_DS/ISE//data/tfi.tft -deleteonerror

20
fpga/L2CacheWay.tfi Normal file
View File

@ -0,0 +1,20 @@
// Instantiate the module
L2CacheWay instance_name (
.CLK(CLK),
.CPUCLKr(CPUCLKr),
.RDA(RDA),
.RDD(RDD),
.Match(Match),
.WRA(WRA),
.WRD(WRD),
.WR(WR),
.WRM(WRM),
.CLR(CLR),
.RDMatch(RDMatch),
.TSMatch(TSMatch)
);

54
fpga/L2CacheWay.v Normal file
View File

@ -0,0 +1,54 @@
/* L2 Cache Way
* 1024 x 49 bits
* (1) Valid
* (16) Tag - {A[30], A[28], A[25:0]}
* (32) Data
*/
module L2CacheWay(
input CLK,
input CPUCLKr,
input [27:2] RDA,
output [31:0] RDD,
output RDMatch,
input [27:2] WRA,
input [31:0] WRD,
input [3:0] WRM,
input TS,
input WR,
input CLR,
input ALL);
/* Read address */
wire [15:0] RDATag = RDA[27:12];
wire [11:0] RDAIndex = RDA[11:2];
/* Write address */
wire [15:0] WRATag = WRA[27:12];
wire [11:0] WRAIndex = WRA[11:2];
/* Cache way RAM */
wire [31:0] RDD;
wire [31:0] TSD;
wire [15:0] RDTag;
wire [15:0] TSTag;
wire RDValid;
wire TSValid;
assign RDMatch = RDValid && RDTag==RDATag;
wire TSMatch = TSValid && TSTag==WRATag;
L2WayRAM way (
.clka(CLK),
.ena(~CPUCLKr),
.wea(1'b0),
.addra(RDAIndex),
.dina(50'b0),
.douta({RDValid, RDTag, RDD}),
.clkb(CLK),
.enb(1'b0),
.web(1'b0),
.addrb(WRAIndex),
.dinb({~CLR, WRATag, WRD}),
.doutb({TSValid, TSTag, TSD}));
endmodule

4
fpga/PLL.ucf
View File

@ -35,10 +35,10 @@ NET "CPU_nSTERM" TNM_NET = CPU_nSTERM;
NET CLKFB_OUT FEEDBACK = 160ps NET CLKFB_IN;
TIMESPEC TS_CLKIN = PERIOD "CLKIN" 30 ns HIGH 50%;
#TIMESPEC TS_CLKIN = PERIOD "CLKIN" 30 ns HIGH 50%;
#NET "FSB_A[*]" OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
#NET "CPU_nAS" OFFSET = IN 15ns VALID 15ns BEFORE CLKIN;
TIMESPEC TS_CPU_nSTERM_A = FROM "FSB_A" TO "CPU_nSTERM" 15ns;
#TIMESPEC TS_CPU_nSTERM_A = FROM "FSB_A" TO "CPU_nSTERM" 15ns;
#Created by Constraints Editor (xc6slx9-ftg256-2) - 2021/10/31

62
fpga/Prefetch.v Normal file
View File

@ -0,0 +1,62 @@
/* L2 Prefetch Buffer
* Prefetch tag RAM - 128 x 22s bits
* (1) Valid
* (21) Tag - {A[30], A[28], A[25:0]}
* Prefetch data RAM -
*/
module L2Prefetch(
input CLK,
input CPUCLKr,
input [27:2] RDA,
output [31:0] RDD,
output Match,
input [27:2] WRA,
input [31:0] WRD,
input WR,
input [3:0] WRM,
input CLR);
/* Read Address */
wire [18:0] RDATag = RDA[27:9];
wire [6:0] RDAIndex = RDA[8:2];
/* Write Address */
wire [18:0] WRATag = WRA[27:9];
wire [6:0] WRAIndex = WRA[8:2];
/* Tag & Valid */
wire [18:0] RDTag;
wire [18:0] TSTag;
wire RDValid;
wire TSValid;
wire RDMatch = RDValid && RDTag==RDATag;
wire TSMatch = TSValid && TSTag==WRATag;
PrefetchTagRAM Tag (
.clk(CLK),
.we(WR && (WRM[3:0]==4'b1111 || TSMatch)),
.a(WRAIndex),
.d({~CLR, WRATag}),
.spo({TSValid, TSTag}),
.dpra(RDAIndex),
.dpo({RDValid, RDTag}));
assign Match = RDMatch;
/* Data */
PrefetchDataRAM your_instance_name (
.clka(CLK),
.ena(~CPUCLKr),
.wea(1'b0),
.addra(addra), // input [8 : 0] addra
.dina(dina), // input [31 : 0] dina
.douta(douta), // output [31 : 0] douta
.clkb(clkb), // input clkb
.enb(enb), // input enb
.web(web), // input [0 : 0] web
.addrb(addrb), // input [8 : 0] addrb
.dinb(dinb), // input [31 : 0] dinb
.doutb(doutb)); // output [31 : 0] doutb
endmodule

53
fpga/PrefetchBuf.v
View File

@ -1,53 +0,0 @@
module L2Prefetch(
input CLK,
input CPUCLKr,
input [28:2] RDA,
output [31:0] RDD,
output Match,
input [28:2] WRA,
input [31:0] WRD,
input WR,
input [3:0] WRM,
input CLR);
/* Read Address */
wire [20:0] RDATag = RDA[28:7];
wire [4:0] RDAIndex = RDA[6:2];
/* Write Address */
wire [20:0] WRATag = WRA[28:7];
wire [4:0] WRAIndex = WRA[6:2];
/* Way 0 Tag & Valid */
wire [20:0] RDTag;
wire [20:0] TSTag;
wire RDValid;
wire TSValid;
wire RDMatch = RDValid && RDTag==RDATag;
wire TSMatch = TSValid && TSTag==RDATag;
PrefetchTagRAM Way0Tag (
.clk(CLK),
.we(WR && (WRM[3:0]==4'b1111 || TSMatch)),
.a(WRA[8:2]),
.d({~CLR, WRATag[20:0]}),
.spo({TSValid, TSTag[20:0]}),
.dpra(RDA[8:2]),
.dpo({RDValid, RDTag[20:0]}));
/* Way 0 Data */
PrefetchDataRAM Way0Data (
.clka(CLK),
.ena(WR && (WRM[3:0]==4'b1111 || TSMatch)),
.wea(WRM[3:0]),
.addra(WRAIndex[4:0]),
.dina(WRD[31:0]),
.clkb(CLK),
.enb(~CPUCLKr),
.addrb({2'b00, RDAIndex[4:0]}),
.doutb(RDD[31:0]));
assign Match = RDMatch;
endmodule

223
fpga/WarpLC.bld
View File

@ -1,19 +1,178 @@
Release 14.7 ngdbuild P.20131013 (nt64)
Release 14.7 ngdbuild P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p
xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2
WarpLC.ngc WarpLC.ngd
Reading NGO file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.ngc" ...
Reading NGO file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.ngc" ...
Loading design module "ipcore_dir/PrefetchTagRAM.ngc"...
Loading design module "ipcore_dir/PrefetchDataRAM.ngc"...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "PLL.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<0>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<0>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<1>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<1>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<2>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<2>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<3>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<3>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<4>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<4>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<5>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<5>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<6>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<6>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<7>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<7>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<8>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<8>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<9>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<9>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<10>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<10>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<11>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<11>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<12>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<12>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<13>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<13>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<14>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<14>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<15>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<15>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<16>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<16>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<17>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<17>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<18>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<18>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<19>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<19>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<20>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<20>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<21>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<21>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<22>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<22>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<23>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<23>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<24>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<24>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<25>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<25>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<26>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<26>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<27>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<27>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<28>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<28>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<29>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<29>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<30>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<30>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<31>" SLEW = SLOW>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/FSB_D<31>' because those design objects do not
contain or drive any instances of the correct type.
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nAS" IOBDELAY = NONE>: This
constraint cannot be distributed from the design objects matching 'NET:
UniqueName: /WarpLC/EXPANDED/CPU_nAS' because those design objects do not
@ -59,21 +218,41 @@ WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<31>" IOBDELAY = NONE>:
UniqueName: /WarpLC/EXPANDED/FSB_A<31>' because those design objects do not
contain or drive any instances of the correct type.
INFO:ConstraintSystem:178 - TNM 'CLKIN', used in period specification
'TS_CLKIN', was traced into PLL_ADV instance PLL_ADV. The following new TNM
groups and period specifications were generated at the PLL_ADV output(s):
CLKFBOUT: <TIMESPEC TS_cg_pll_clkfbout = PERIOD "cg_pll_clkfbout" TS_CLKIN
HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'CLKIN', used in period specification
'TS_CLKIN', was traced into PLL_ADV instance PLL_ADV. The following new TNM
groups and period specifications were generated at the PLL_ADV output(s):
CLKOUT0: <TIMESPEC TS_cg_pll_clkout0 = PERIOD "cg_pll_clkout0" TS_CLKIN / 2
HIGH 50%>
Done...
Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'FSB_D<31>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<30>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<29>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<28>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<27>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<26>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<25>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<24>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<23>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<22>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<21>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<20>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<19>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<18>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<17>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<16>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<15>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<14>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<13>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<12>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<11>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<10>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<9>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<8>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<7>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<6>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<5>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<4>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<3>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<2>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<1>' has no driver
WARNING:NgdBuild:452 - logical net 'FSB_D<0>' has no driver
Partition Implementation Status
-------------------------------
@ -84,12 +263,12 @@ Partition Implementation Status
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 9
Number of warnings: 73
Total memory usage is 163932 kilobytes
Total memory usage is 134544 kilobytes
Writing NGD file "WarpLC.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Total REAL time to NGDBUILD completion: 2 sec
Total CPU time to NGDBUILD completion: 2 sec
Writing NGDBUILD log file "WarpLC.bld"...

69
fpga/WarpLC.cmd_log
View File

@ -643,3 +643,72 @@ ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6s
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
trce -intstyle ise -v 3 -timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf

50
fpga/WarpLC.gise
View File

@ -22,6 +22,7 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="WarpLC.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_VERILOG_INSTTEMPLATE" xil_pn:name="L2CacheWay.tfi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="WarpLC.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="WarpLC.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="WarpLC.lso"/>
@ -73,44 +74,54 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1635709065" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635709065">
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635761418">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1635709065" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3515295135630071778" xil_pn:start_ts="1635709065">
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3515295135630071778" xil_pn:start_ts="1635761418">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1635709065" xil_pn:in_ck="-6233175969720765835" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4864019295268560826" xil_pn:start_ts="1635709065">
<transform xil_pn:end_ts="1635761418" xil_pn:in_ck="792064813085319307" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4864019295268560826" xil_pn:start_ts="1635761418">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="ipcore_dir/PLL.v"/>
<outfile xil_pn:name="ipcore_dir/PrefetchDataRAM.ngc"/>
<outfile xil_pn:name="ipcore_dir/PrefetchDataRAM.v"/>
<outfile xil_pn:name="ipcore_dir/PrefetchTagRAM.ngc"/>
<outfile xil_pn:name="ipcore_dir/PrefetchTagRAM.v"/>
</transform>
<transform xil_pn:end_ts="1635709065" xil_pn:in_ck="-4446273774904393470" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635709065">
<transform xil_pn:end_ts="1635761418" xil_pn:in_ck="8930453670915267207" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635761418">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1635709065" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6691162141195559328" xil_pn:start_ts="1635709065">
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6691162141195559328" xil_pn:start_ts="1635761418">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1635709065" xil_pn:in_ck="-4446273774904393470" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745411629038" xil_pn:start_ts="1635709065">
<transform xil_pn:end_ts="1635761418" xil_pn:in_ck="8930453670915267207" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745411629038" xil_pn:start_ts="1635761418">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform>
<transform xil_pn:end_ts="1635709065" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="5917552782042024336" xil_pn:start_ts="1635709065">
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="5917552782042024336" xil_pn:start_ts="1635761418">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform>
<transform xil_pn:end_ts="1635709075" xil_pn:in_ck="2132134388199262633" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1250938673410109993" xil_pn:start_ts="1635709065">
<transform xil_pn:end_ts="1635761423" xil_pn:in_ck="-7378490581248552107" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1250938673410109993" xil_pn:start_ts="1635761418">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="WarpLC.lso"/>
<outfile xil_pn:name="WarpLC.ngc"/>
@ -124,23 +135,28 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1635709075" xil_pn:in_ck="-7789573437496007849" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704523" xil_pn:start_ts="1635709075">
<transform xil_pn:end_ts="1635761423" xil_pn:in_ck="-7789573437496007849" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704523" xil_pn:start_ts="1635761423">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform>
<transform xil_pn:end_ts="1635709080" xil_pn:in_ck="5468170433947878565" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2511870374322119143" xil_pn:start_ts="1635709075">
<transform xil_pn:end_ts="1635761428" xil_pn:in_ck="1514068505672127241" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2511870374322119143" xil_pn:start_ts="1635761423">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="WarpLC.bld"/>
<outfile xil_pn:name="WarpLC.ngd"/>
<outfile xil_pn:name="WarpLC_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1635709108" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-5057403149233638808" xil_pn:start_ts="1635709080">
<transform xil_pn:end_ts="1635761440" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-5057403149233638808" xil_pn:start_ts="1635761428">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="WarpLC.pcf"/>
<outfile xil_pn:name="WarpLC_map.map"/>
<outfile xil_pn:name="WarpLC_map.mrp"/>
@ -152,9 +168,11 @@
<outfile xil_pn:name="WarpLC_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1635709114" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-5338882351546597350" xil_pn:start_ts="1635709108">
<transform xil_pn:end_ts="1635761446" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-5338882351546597350" xil_pn:start_ts="1635761440">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="WarpLC.ncd"/>
<outfile xil_pn:name="WarpLC.pad"/>
<outfile xil_pn:name="WarpLC.par"/>
@ -170,13 +188,15 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1635709120" xil_pn:in_ck="5584679923051828224" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1254017130453672594" xil_pn:start_ts="1635709114">
<transform xil_pn:end_ts="1635761449" xil_pn:in_ck="5584679923051828224" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-4489077157552092322" xil_pn:start_ts="1635761446">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="WarpLC.twr"/>
<outfile xil_pn:name="WarpLC.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
@ -186,6 +206,7 @@
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
@ -194,7 +215,10 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
</transforms>

2
fpga/WarpLC.ncd
View File

File diff suppressed because one or more lines are too long

2
fpga/WarpLC.ngc
View File

File diff suppressed because one or more lines are too long

2
fpga/WarpLC.ngd
View File

File diff suppressed because one or more lines are too long

2
fpga/WarpLC.ngr
View File

File diff suppressed because one or more lines are too long

216
fpga/WarpLC.pad
View File

@ -1,7 +1,7 @@
Release 14.7 - par P.20131013 (nt64)
Release 14.7 - par P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sun Oct 31 15:38:33 2021
Mon Nov 01 06:10:44 2021
# NOTE: This file is designed to be imported into a spreadsheet program
@ -22,137 +22,137 @@ Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|D
A1|||GND||||||||||||
A2||IOBS|IO_L52N_M3A9_3|UNUSED||3|||||||||
A3||IOBS|IO_L83N_VREF_3|UNUSED||3|||||||||
A4|CLKFB_OUT|IOB|IO_L1N_VREF_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
A5|FSB_D<0>|IOB|IO_L2N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
A6|FSB_D<4>|IOB|IO_L4N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
A7|FSB_D<6>|IOB|IO_L6N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
A8|FSB_D<12>|IOB|IO_L33N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
A9|FSB_D<14>|IOB|IO_L34N_GCLK18_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
A10|FSB_D<16>|IOB|IO_L35N_GCLK16_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
A11|FSB_D<22>|IOB|IO_L39N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
A12|FSB_D<28>|IOB|IO_L62N_VREF_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
A13|FSB_D<30>|IOB|IO_L63N_SCP6_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
A14|RAMCLK0|IOB|IO_L65N_SCP2_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
A4||IOBS|IO_L1N_VREF_0|UNUSED||0|||||||||
A5||IOBS|IO_L2N_0|UNUSED||0|||||||||
A6||IOBS|IO_L4N_0|UNUSED||0|||||||||
A7||IOBS|IO_L6N_0|UNUSED||0|||||||||
A8||IOBS|IO_L33N_0|UNUSED||0|||||||||
A9||IOBS|IO_L34N_GCLK18_0|UNUSED||0|||||||||
A10||IOBS|IO_L35N_GCLK16_0|UNUSED||0|||||||||
A11||IOBS|IO_L39N_0|UNUSED||0|||||||||
A12||IOBS|IO_L62N_VREF_0|UNUSED||0|||||||||
A13||IOBS|IO_L63N_SCP6_0|UNUSED||0|||||||||
A14||IOBS|IO_L65N_SCP2_0|UNUSED||0|||||||||
A15|||TMS||||||||||||
A16|||GND||||||||||||
B1||IOBS|IO_L50N_M3BA2_3|UNUSED||3|||||||||
B2||IOBM|IO_L52P_M3A8_3|UNUSED||3|||||||||
B3||IOBM|IO_L83P_3|UNUSED||3|||||||||
B4|||VCCO_0|||0|||||3.30||||
B5|CPUCLK|IOB|IO_L2P_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
B6|FSB_D<3>|IOB|IO_L4P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
B4|||VCCO_0|||0|||||any******||||
B5||IOBM|IO_L2P_0|UNUSED||0|||||||||
B6||IOBM|IO_L4P_0|UNUSED||0|||||||||
B7|||GND||||||||||||
B8|FSB_D<11>|IOB|IO_L33P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
B9|||VCCO_0|||0|||||3.30||||
B10|FSB_D<15>|IOB|IO_L35P_GCLK17_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
B8||IOBM|IO_L33P_0|UNUSED||0|||||||||
B9|||VCCO_0|||0|||||any******||||
B10||IOBM|IO_L35P_GCLK17_0|UNUSED||0|||||||||
B11|||GND||||||||||||
B12|FSB_D<27>|IOB|IO_L62P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
B13|||VCCO_0|||0|||||3.30||||
B14|FSB_A<2>|IOB|IO_L65P_SCP3_0|INPUT|LVCMOS33|0||||NONE||UNLOCATED|NO|NONE|
B15|FSB_A<6>|IOB|IO_L29P_A23_M1A13_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
B16|FSB_A<7>|IOB|IO_L29N_A22_M1A14_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
B12||IOBM|IO_L62P_0|UNUSED||0|||||||||
B13|||VCCO_0|||0|||||any******||||
B14||IOBM|IO_L65P_SCP3_0|UNUSED||0|||||||||
B15||IOBM|IO_L29P_A23_M1A13_1|UNUSED||1|||||||||
B16||IOBS|IO_L29N_A22_M1A14_1|UNUSED||1|||||||||
C1||IOBM|IO_L50P_M3WE_3|UNUSED||3|||||||||
C2||IOBS|IO_L48N_M3BA1_3|UNUSED||3|||||||||
C3||IOBM|IO_L48P_M3BA0_3|UNUSED||3|||||||||
C4|RAMCLK1|IOB|IO_L1P_HSWAPEN_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
C5|FSB_D<2>|IOB|IO_L3N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
C6|FSB_D<10>|IOB|IO_L7N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
C7|FSB_D<7>|IOB|IO_L6P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
C8|FSB_D<24>|IOB|IO_L38N_VREF_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
C9|FSB_D<13>|IOB|IO_L34P_GCLK19_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
C10|FSB_D<20>|IOB|IO_L37N_GCLK12_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
C11|FSB_D<23>|IOB|IO_L39P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
C4||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0|||||||||
C5||IOBS|IO_L3N_0|UNUSED||0|||||||||
C6||IOBS|IO_L7N_0|UNUSED||0|||||||||
C7||IOBM|IO_L6P_0|UNUSED||0|||||||||
C8||IOBS|IO_L38N_VREF_0|UNUSED||0|||||||||
C9||IOBM|IO_L34P_GCLK19_0|UNUSED||0|||||||||
C10||IOBS|IO_L37N_GCLK12_0|UNUSED||0|||||||||
C11||IOBM|IO_L39P_0|UNUSED||0|||||||||
C12|||TDI||||||||||||
C13|FSB_D<29>|IOB|IO_L63P_SCP7_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
C13||IOBM|IO_L63P_SCP7_0|UNUSED||0|||||||||
C14|||TCK||||||||||||
C15|FSB_A<14>|IOB|IO_L33P_A15_M1A10_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
C16|FSB_A<20>|IOB|IO_L33N_A14_M1A4_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
C15||IOBM|IO_L33P_A15_M1A10_1|UNUSED||1|||||||||
C16||IOBS|IO_L33N_A14_M1A4_1|UNUSED||1|||||||||
D1||IOBS|IO_L49N_M3A2_3|UNUSED||3|||||||||
D2|||VCCO_3|||3|||||any******||||
D2|||VCCO_3|||3|||||3.30||||
D3||IOBM|IO_L49P_M3A7_3|UNUSED||3|||||||||
D4|||GND||||||||||||
D5|FSB_D<1>|IOB|IO_L3P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
D6|FSB_D<9>|IOB|IO_L7P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
D7|||VCCO_0|||0|||||3.30||||
D8|FSB_D<21>|IOB|IO_L38P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
D9|FSB_D<26>|IOB|IO_L40N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
D10|||VCCO_0|||0|||||3.30||||
D11|FPUCLK|IOB|IO_L66P_SCP1_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
D12|CPU_nSTERM|IOB|IO_L66N_SCP0_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|NO|NONE|
D5||IOBM|IO_L3P_0|UNUSED||0|||||||||
D6||IOBM|IO_L7P_0|UNUSED||0|||||||||
D7|||VCCO_0|||0|||||any******||||
D8||IOBM|IO_L38P_0|UNUSED||0|||||||||
D9||IOBS|IO_L40N_0|UNUSED||0|||||||||
D10|||VCCO_0|||0|||||any******||||
D11||IOBM|IO_L66P_SCP1_0|UNUSED||0|||||||||
D12||IOBS|IO_L66N_SCP0_0|UNUSED||0|||||||||
D13|||GND||||||||||||
D14|FSB_A<10>|IOB|IO_L31P_A19_M1CKE_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
D14||IOBM|IO_L31P_A19_M1CKE_1|UNUSED||1|||||||||
D15|||VCCO_1|||1|||||any******||||
D16|FSB_A<11>|IOB|IO_L31N_A18_M1A12_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
E1||IOBS|IO_L46N_M3CLKN_3|UNUSED||3|||||||||
E2||IOBM|IO_L46P_M3CLK_3|UNUSED||3|||||||||
D16||IOBS|IO_L31N_A18_M1A12_1|UNUSED||1|||||||||
E1|FPUCLK|IOB|IO_L46N_M3CLKN_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
E2|CPUCLK|IOB|IO_L46P_M3CLK_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
E3||IOBS|IO_L54N_M3A11_3|UNUSED||3|||||||||
E4||IOBM|IO_L54P_M3RESET_3|UNUSED||3|||||||||
E5|||VCCAUX||||||||2.5||||
E6|FSB_D<8>|IOB|IO_L5N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
E7|FSB_D<17>|IOB|IO_L36P_GCLK15_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
E8|FSB_D<18>|IOB|IO_L36N_GCLK14_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
E6||IOBS|IO_L5N_0|UNUSED||0|||||||||
E7||IOBM|IO_L36P_GCLK15_0|UNUSED||0|||||||||
E8||IOBS|IO_L36N_GCLK14_0|UNUSED||0|||||||||
E9|||GND||||||||||||
E10|FSB_D<19>|IOB|IO_L37P_GCLK13_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
E11|FSB_A<3>|IOB|IO_L64N_SCP4_0|INPUT|LVCMOS33|0||||NONE||UNLOCATED|NO|NONE|
E12|FSB_A<5>|IOB|IO_L1N_A24_VREF_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
E13|FSB_A<4>|IOB|IO_L1P_A25_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
E10||IOBM|IO_L37P_GCLK13_0|UNUSED||0|||||||||
E11||IOBS|IO_L64N_SCP4_0|UNUSED||0|||||||||
E12||IOBS|IO_L1N_A24_VREF_1|UNUSED||1|||||||||
E13||IOBM|IO_L1P_A25_1|UNUSED||1|||||||||
E14|||TDO||||||||||||
E15|FSB_A<21>|IOB|IO_L34P_A13_M1WE_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
E16|FSB_A<22>|IOB|IO_L34N_A12_M1BA2_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
F1||IOBS|IO_L41N_GCLK26_M3DQ5_3|UNUSED||3|||||||||
F2||IOBM|IO_L41P_GCLK27_M3DQ4_3|UNUSED||3|||||||||
E15||IOBM|IO_L34P_A13_M1WE_1|UNUSED||1|||||||||
E16||IOBS|IO_L34N_A12_M1BA2_1|UNUSED||1|||||||||
F1|FSB_A<25>|IOB|IO_L41N_GCLK26_M3DQ5_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
F2|FSB_A<24>|IOB|IO_L41P_GCLK27_M3DQ4_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
F3||IOBS|IO_L53N_M3A12_3|UNUSED||3|||||||||
F4||IOBM|IO_L53P_M3CKE_3|UNUSED||3|||||||||
F5||IOBS|IO_L55N_M3A14_3|UNUSED||3|||||||||
F6||IOBM|IO_L55P_M3A13_3|UNUSED||3|||||||||
F7|FSB_D<5>|IOB|IO_L5P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
F7||IOBM|IO_L5P_0|UNUSED||0|||||||||
F8|||VCCAUX||||||||2.5||||
F9|FSB_D<25>|IOB|IO_L40P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
F10|FSB_D<31>|IOB|IO_L64P_SCP5_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
F9||IOBM|IO_L40P_0|UNUSED||0|||||||||
F10||IOBM|IO_L64P_SCP5_0|UNUSED||0|||||||||
F11|||VCCAUX||||||||2.5||||
F12|FSB_A<8>|IOB|IO_L30P_A21_M1RESET_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
F13|FSB_A<12>|IOB|IO_L32P_A17_M1A8_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
F14|FSB_A<13>|IOB|IO_L32N_A16_M1A9_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
F15|FSB_A<23>|IOB|IO_L35P_A11_M1A7_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
F16|FSB_A<19>|IOB|IO_L35N_A10_M1A2_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
G1||IOBS|IO_L40N_M3DQ7_3|UNUSED||3|||||||||
F12||IOBM|IO_L30P_A21_M1RESET_1|UNUSED||1|||||||||
F13||IOBM|IO_L32P_A17_M1A8_1|UNUSED||1|||||||||
F14||IOBS|IO_L32N_A16_M1A9_1|UNUSED||1|||||||||
F15||IOBM|IO_L35P_A11_M1A7_1|UNUSED||1|||||||||
F16||IOBS|IO_L35N_A10_M1A2_1|UNUSED||1|||||||||
G1|FSB_A<23>|IOB|IO_L40N_M3DQ7_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
G2|||GND||||||||||||
G3||IOBM|IO_L40P_M3DQ6_3|UNUSED||3|||||||||
G4|||VCCO_3|||3|||||any******||||
G3|FSB_A<22>|IOB|IO_L40P_M3DQ6_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
G4|||VCCO_3|||3|||||3.30||||
G5||IOBS|IO_L51N_M3A4_3|UNUSED||3|||||||||
G6||IOBM|IO_L51P_M3A10_3|UNUSED||3|||||||||
G7|||VCCINT||||||||1.2||||
G8|||GND||||||||||||
G9|||VCCINT||||||||1.2||||
G10|||VCCAUX||||||||2.5||||
G11|FSB_A<9>|IOB|IO_L30N_A20_M1A11_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
G12|FSB_A<24>|IOB|IO_L38P_A5_M1CLK_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
G11||IOBS|IO_L30N_A20_M1A11_1|UNUSED||1|||||||||
G12||IOBM|IO_L38P_A5_M1CLK_1|UNUSED||1|||||||||
G13|||VCCO_1|||1|||||any******||||
G14|FSB_A<15>|IOB|IO_L36P_A9_M1BA0_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
G14||IOBM|IO_L36P_A9_M1BA0_1|UNUSED||1|||||||||
G15|||GND||||||||||||
G16|FSB_A<16>|IOB|IO_L36N_A8_M1BA1_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
H1||IOBS|IO_L39N_M3LDQSN_3|UNUSED||3|||||||||
H2||IOBM|IO_L39P_M3LDQS_3|UNUSED||3|||||||||
H3||IOBS|IO_L44N_GCLK20_M3A6_3|UNUSED||3|||||||||
G16||IOBS|IO_L36N_A8_M1BA1_1|UNUSED||1|||||||||
H1|FSB_A<21>|IOB|IO_L39N_M3LDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
H2|FSB_A<20>|IOB|IO_L39P_M3LDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
H3|RAMCLK0|IOB|IO_L44N_GCLK20_M3A6_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
H4|CLKFB_IN|IOB|IO_L44P_GCLK21_M3A5_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
H5||IOBS|IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED||3|||||||||
H5|CPU_nSTERM|IOB|IO_L43N_GCLK22_IRDY2_M3CASN_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|NO|NONE|
H6|||VCCAUX||||||||2.5||||
H7|||GND||||||||||||
H8|||VCCINT||||||||1.2||||
H9|||GND||||||||||||
H10|||VCCINT||||||||1.2||||
H11|FSB_A<25>|IOB|IO_L38N_A4_M1CLKN_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
H11||IOBS|IO_L38N_A4_M1CLKN_1|UNUSED||1|||||||||
H12|||GND||||||||||||
H13|FSB_A<26>|IOB|IO_L39P_M1A3_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
H14|FSB_A<27>|IOB|IO_L39N_M1ODT_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
H15|FSB_A<17>|IOB|IO_L37P_A7_M1A0_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
H16|FSB_A<18>|IOB|IO_L37N_A6_M1A1_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
J1||IOBS|IO_L38N_M3DQ3_3|UNUSED||3|||||||||
J2|||VCCO_3|||3|||||any******||||
J3||IOBM|IO_L38P_M3DQ2_3|UNUSED||3|||||||||
H13||IOBM|IO_L39P_M1A3_1|UNUSED||1|||||||||
H14||IOBS|IO_L39N_M1ODT_1|UNUSED||1|||||||||
H15||IOBM|IO_L37P_A7_M1A0_1|UNUSED||1|||||||||
H16||IOBS|IO_L37N_A6_M1A1_1|UNUSED||1|||||||||
J1|FSB_A<19>|IOB|IO_L38N_M3DQ3_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
J2|||VCCO_3|||3|||||3.30||||
J3|FSB_A<18>|IOB|IO_L38P_M3DQ2_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
J4|CLKIN|IOB|IO_L42N_GCLK24_M3LDM_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
J5|||GND||||||||||||
J6||IOBM|IO_L43P_GCLK23_M3RASN_3|UNUSED||3|||||||||
J6|FSB_A<27>|IOB|IO_L43P_GCLK23_M3RASN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
J7|||VCCINT||||||||1.2||||
J8|||GND||||||||||||
J9|||VCCINT||||||||1.2||||
@ -163,10 +163,10 @@ J13||IOBM|IO_L41P_GCLK9_IRDY1_M1RASN_1|UNUSED||1|||||||||
J14||IOBM|IO_L43P_GCLK5_M1DQ4_1|UNUSED||1|||||||||
J15|||VCCO_1|||1|||||any******||||
J16||IOBS|IO_L43N_GCLK4_M1DQ5_1|UNUSED||1|||||||||
K1||IOBS|IO_L37N_M3DQ1_3|UNUSED||3|||||||||
K2||IOBM|IO_L37P_M3DQ0_3|UNUSED||3|||||||||
K3||IOBM|IO_L42P_GCLK25_TRDY2_M3UDM_3|UNUSED||3|||||||||
K4|||VCCO_3|||3|||||any******||||
K1|FSB_A<17>|IOB|IO_L37N_M3DQ1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
K2|FSB_A<16>|IOB|IO_L37P_M3DQ0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
K3|FSB_A<26>|IOB|IO_L42P_GCLK25_TRDY2_M3UDM_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
K4|||VCCO_3|||3|||||3.30||||
K5||IOBM|IO_L47P_M3A0_3|UNUSED||3|||||||||
K6||IOBS|IO_L47N_M3A1_3|UNUSED||3|||||||||
K7|||GND||||||||||||
@ -179,11 +179,11 @@ K13|||VCCO_1|||1|||||any******||||
K14||IOBS|IO_L41N_GCLK8_M1CASN_1|UNUSED||1|||||||||
K15||IOBM|IO_L44P_A3_M1DQ6_1|UNUSED||1|||||||||
K16||IOBS|IO_L44N_A2_M1DQ7_1|UNUSED||1|||||||||
L1||IOBS|IO_L36N_M3DQ9_3|UNUSED||3|||||||||
L1|FSB_A<15>|IOB|IO_L36N_M3DQ9_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
L2|||GND||||||||||||
L3||IOBM|IO_L36P_M3DQ8_3|UNUSED||3|||||||||
L4||IOBM|IO_L45P_M3A3_3|UNUSED||3|||||||||
L5||IOBS|IO_L45N_M3ODT_3|UNUSED||3|||||||||
L3|FSB_A<14>|IOB|IO_L36P_M3DQ8_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
L4|CLKFB_OUT|IOB|IO_L45P_M3A3_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
L5|RAMCLK1|IOB|IO_L45N_M3ODT_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
L6|||VCCAUX||||||||2.5||||
L7||IOBS|IO_L62N_D6_2|UNUSED||2|||||||||
L8||IOBM|IO_L62P_D5_2|UNUSED||2|||||||||
@ -195,11 +195,11 @@ L13||IOBS|IO_L53N_VREF_1|UNUSED||1|||||||||
L14||IOBM|IO_L47P_FWE_B_M1DQ0_1|UNUSED||1|||||||||
L15|||GND||||||||||||
L16||IOBS|IO_L47N_LDC_M1DQ1_1|UNUSED||1|||||||||
M1||IOBS|IO_L35N_M3DQ11_3|UNUSED||3|||||||||
M2||IOBM|IO_L35P_M3DQ10_3|UNUSED||3|||||||||
M3||IOBS|IO_L1N_VREF_3|UNUSED||3|||||||||
M4||IOBM|IO_L1P_3|UNUSED||3|||||||||
M5||IOBM|IO_L2P_3|UNUSED||3|||||||||
M1|FSB_A<13>|IOB|IO_L35N_M3DQ11_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
M2|FSB_A<12>|IOB|IO_L35P_M3DQ10_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
M3|FSB_A<3>|IOB|IO_L1N_VREF_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
M4|FSB_A<2>|IOB|IO_L1P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
M5|FSB_A<4>|IOB|IO_L2P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
M6||IOBM|IO_L64P_D8_2|UNUSED||2|||||||||
M7||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2|||||||||
M8|||GND||||||||||||
@ -211,10 +211,10 @@ M13||IOBM|IO_L74P_AWAKE_1|UNUSED||1|||||||||
M14||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1|||||||||
M15||IOBM|IO_L46P_FCS_B_M1DQ2_1|UNUSED||1|||||||||
M16||IOBS|IO_L46N_FOE_B_M1DQ3_1|UNUSED||1|||||||||
N1||IOBS|IO_L34N_M3UDQSN_3|UNUSED||3|||||||||
N2|||VCCO_3|||3|||||any******||||
N3||IOBM|IO_L34P_M3UDQS_3|UNUSED||3|||||||||
N4||IOBS|IO_L2N_3|UNUSED||3|||||||||
N1|FSB_A<11>|IOB|IO_L34N_M3UDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
N2|||VCCO_3|||3|||||3.30||||
N3|FSB_A<10>|IOB|IO_L34P_M3UDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
N4|FSB_A<5>|IOB|IO_L2N_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
N5||IOBM|IO_L49P_D3_2|UNUSED||2|||||||||
N6||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
N7|||VCCO_2|||2|||||any******||||
@ -227,8 +227,8 @@ N13|||GND||||||||||||
N14||IOBM|IO_L45P_A1_M1LDQS_1|UNUSED||1|||||||||
N15|||VCCO_1|||1|||||any******||||
N16||IOBS|IO_L45N_A0_M1LDQSN_1|UNUSED||1|||||||||
P1||IOBS|IO_L33N_M3DQ13_3|UNUSED||3|||||||||
P2||IOBM|IO_L33P_M3DQ12_3|UNUSED||3|||||||||
P1|FSB_A<9>|IOB|IO_L33N_M3DQ13_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
P2|FSB_A<8>|IOB|IO_L33P_M3DQ12_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
P3|||GND||||||||||||
P4||IOBM|IO_L63P_2|UNUSED||2|||||||||
P5||IOBS|IO_L49N_D4_2|UNUSED||2|||||||||
@ -243,8 +243,8 @@ P13|||DONE_2||||||||||||
P14|||SUSPEND||||||||||||
P15||IOBM|IO_L48P_HDC_M1DQ8_1|UNUSED||1|||||||||
P16||IOBS|IO_L48N_M1DQ9_1|UNUSED||1|||||||||
R1||IOBS|IO_L32N_M3DQ15_3|UNUSED||3|||||||||
R2||IOBM|IO_L32P_M3DQ14_3|UNUSED||3|||||||||
R1|FSB_A<7>|IOB|IO_L32N_M3DQ15_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
R2|FSB_A<6>|IOB|IO_L32P_M3DQ14_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
R3||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
R4|||VCCO_2|||2|||||any******||||
R5||IOBM|IO_L48P_D7_2|UNUSED||2|||||||||

107
fpga/WarpLC.par
View File

@ -1,7 +1,7 @@
Release 14.7 par P.20131013 (nt64)
Release 14.7 par P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
DOG-PC:: Sun Oct 31 15:38:29 2021
ZANEPC:: Mon Nov 01 06:10:41 2021
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
@ -33,27 +33,27 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 33 out of 5,720 1%
Number of Slice LUTs: 89 out of 5,720 1%
Number used as logic: 9 out of 5,720 1%
Number using O6 output only: 8
Number using O6 output only: 7
Number using O5 output only: 1
Number using O5 and O6: 0
Number using O5 and O6: 1
Number used as ROM: 0
Number used as Memory: 24 out of 1,440 1%
Number used as Dual Port RAM: 24
Number using O6 output only: 4
Number used as Memory: 80 out of 1,440 5%
Number used as Dual Port RAM: 80
Number using O6 output only: 80
Number using O5 output only: 0
Number using O5 and O6: 20
Number using O5 and O6: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 0
Slice Logic Distribution:
Number of occupied Slices: 9 out of 1,430 1%
Number of occupied Slices: 23 out of 1,430 1%
Number of MUXCYs used: 8 out of 2,860 1%
Number of LUT Flip Flop pairs used: 33
Number with an unused Flip Flop: 32 out of 33 96%
Number with an unused LUT: 0 out of 33 0%
Number of fully used LUT-FF pairs: 1 out of 33 3%
Number of LUT Flip Flop pairs used: 89
Number with an unused Flip Flop: 88 out of 89 98%
Number with an unused LUT: 0 out of 89 0%
Number of fully used LUT-FF pairs: 1 out of 89 1%
Number of slice register sites lost
to control set restrictions: 0 out of 11,440 0%
@ -64,12 +64,12 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 66 out of 186 35%
Number of bonded IOBs: 34 out of 186 18%
IOB Flip Flops: 5
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 1 out of 64 1%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
@ -106,31 +106,31 @@ PAR will use up to 4 processors
Starting Multi-threaded Router
Phase 1 : 386 unrouted; REAL time: 3 secs
Phase 1 : 672 unrouted; REAL time: 2 secs
Phase 2 : 172 unrouted; REAL time: 3 secs
Phase 2 : 328 unrouted; REAL time: 2 secs
Phase 3 : 110 unrouted; REAL time: 3 secs
Phase 3 : 155 unrouted; REAL time: 2 secs
Phase 4 : 110 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs
Phase 4 : 155 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
Updating file: WarpLC.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs
Total REAL time to Router completion: 4 secs
Total CPU time to Router completion (all processors): 4 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs
Total REAL time to Router completion: 3 secs
Total CPU time to Router completion (all processors): 3 secs
Generating "PAR" statistics.
@ -141,10 +141,10 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| FSBCLK | BUFGMUX_X3Y13| No | 17 | 0.625 | 2.088 |
| FSBCLK | BUFGMUX_X3Y13| No | 29 | 0.585 | 2.022 |
+---------------------+--------------+------+------+------------+-------------+
|cg/pll/clkfb_bufg_ou | | | | | |
| t | BUFGMUX_X2Y3| No | 2 | 0.062 | 2.139 |
| t | BUFGMUX_X2Y3| No | 2 | 0.062 | 2.072 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
@ -157,55 +157,16 @@ for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 2
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP " | MAXDELAY | 7.121ns| 7.879ns| 0| 0
FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pl | SETUP | 11.311ns| 3.689ns| 0| 0
l_clkout0" TS_CLKIN / 2 HIGH 50% | HOLD | 0.458ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns H | MINLOWPULSE | 20.000ns| 10.000ns| 0| 0
IGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_p | MINPERIOD | 27.334ns| 2.666ns| 0| 0
ll_clkfbout" TS_CLKIN HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_CLKIN
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_CLKIN | 30.000ns| 10.000ns| 7.378ns| 0| 0| 0| 6|
| TS_cg_pll_clkfbout | 30.000ns| 2.666ns| N/A| 0| 0| 0| 0|
| TS_cg_pll_clkout0 | 15.000ns| 3.689ns| N/A| 0| 0| 6| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 4 secs
Total CPU time to PAR completion (all processors): 4 secs
Total REAL time to PAR completion: 3 secs
Total CPU time to PAR completion (all processors): 3 secs
Peak Memory Usage: 322 MB
Peak Memory Usage: 258 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.

344
fpga/WarpLC.pcf
View File

@ -1,18 +1,8 @@
//! **************************************************************************
// Written by: Map P.20131013 on Sun Oct 31 15:38:26 2021
// Written by: Map P.20131013 on Mon Nov 01 06:10:38 2021
//! **************************************************************************
SCHEMATIC START;
PIN
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<26>
= BEL
"l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram"
PINNAME CLKAWRCLK;
PIN
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<27>
= BEL
"l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram"
PINNAME CLKBRDCLK;
PIN cg/CPUCLK_inst_pins<1> = BEL "cg/CPUCLK_inst" PINNAME CK0;
PIN cg/CPUCLK_inst_pins<2> = BEL "cg/CPUCLK_inst" PINNAME CK1;
PIN cg/FPUCLK_inst_pins<1> = BEL "cg/FPUCLK_inst" PINNAME CK0;
@ -21,98 +11,166 @@ PIN cg/RAMCLK0_inst_pins<1> = BEL "cg/RAMCLK0_inst" PINNAME CK0;
PIN cg/RAMCLK0_inst_pins<2> = BEL "cg/RAMCLK0_inst" PINNAME CK1;
PIN cg/RAMCLK1_inst_pins<1> = BEL "cg/RAMCLK1_inst" PINNAME CK0;
PIN cg/RAMCLK1_inst_pins<2> = BEL "cg/RAMCLK1_inst" PINNAME CK1;
TIMEGRP cg_pll_clkout0 = BEL "cg/pll/clkout1_buf" PIN
"l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<26>"
PIN
"l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<27>"
BEL "cg/CPUCLKr" BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP"
TIMEGRP cg_pll_clkout0 = BEL "cg/pll/clkout1_buf" BEL "cg/CPUCLKr" BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.LOW"
PIN "cg/CPUCLK_inst_pins<1>" PIN "cg/CPUCLK_inst_pins<2>" PIN
"cg/CPUCLK_inst_pins<1>" PIN "cg/CPUCLK_inst_pins<2>" PIN
"cg/FPUCLK_inst_pins<1>" PIN "cg/FPUCLK_inst_pins<2>" PIN
@ -127,106 +185,172 @@ TIMEGRP cg_pll_clkfbout = BEL "cg/pll/clkfbout_bufg" PIN
"cg/pll/clkfbout_oddr_pins<1>" PIN "cg/pll/clkfbout_oddr_pins<2>" PIN
"cg/pll/clkfbout_oddr_pins<1>" PIN "cg/pll/clkfbout_oddr_pins<2>";
TIMEGRP CPU_nSTERM = BEL "CPU_nSTERM";
TIMEGRP FSB_A = BEL "CPU_nSTERM" PIN
"l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<27>"
TIMEGRP FSB_A = BEL "CPU_nSTERM" BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.HIGH"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/SP"
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.LOW"
BEL
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP";
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.LOW"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.HIGH"
BEL
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.LOW";
PIN SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0_pins<0> = BEL
"SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0" PINNAME DIVCLK;
PIN cg/pll/pll_base_inst/PLL_ADV_pins<2> = BEL "cg/pll/pll_base_inst/PLL_ADV"
PINNAME CLKIN1;
TIMEGRP CLKIN = PIN "SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0_pins<0>" PIN
"cg/pll/pll_base_inst/PLL_ADV_pins<2>";
TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%;
TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns;
TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" TS_CLKIN HIGH 50%;
TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%;
BEL "CLKFB_OUT" FEEDBACK = 0.16 ns BEL "CLKFB_IN";
SCHEMATIC END;

3
fpga/WarpLC.prj
View File

@ -1,7 +1,6 @@
verilog work "ipcore_dir/PLL.v"
verilog work "ipcore_dir/PrefetchTagRAM.v"
verilog work "ipcore_dir/PrefetchDataRAM.v"
verilog work "SizeDecode.v"
verilog work "PrefetchBuf.v"
verilog work "Prefetch.v"
verilog work "ClkGen.v"
verilog work "WarpLC.v"

2
fpga/WarpLC.ptwx
View File

@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstRollupTable uID="1" anchorID="1"><twConstRollup name="TS_CLKIN" fullName="TS_CLKIN = PERIOD TIMEGRP &quot;CLKIN&quot; 30 ns HIGH 50%;" type="origin" depth="0" requirement="30.000" prefType="period" actual="10.000" actualRollup="7.378" errors="0" errorRollup="0" items="0" itemsRollup="6"/><twConstRollup name="TS_cg_pll_clkfbout" fullName="TS_cg_pll_clkfbout = PERIOD TIMEGRP &quot;cg_pll_clkfbout&quot; TS_CLKIN HIGH 50%;" type="child" depth="1" requirement="30.000" prefType="period" actual="2.666" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_cg_pll_clkout0" fullName="TS_cg_pll_clkout0 = PERIOD TIMEGRP &quot;cg_pll_clkout0&quot; TS_CLKIN / 2 HIGH 50%;" type="child" depth="1" requirement="15.000" prefType="period" actual="3.689" actualRollup="N/A" errors="0" errorRollup="0" items="6" itemsRollup="0"/></twConstRollupTable><twConstSummaryTable twEmptyConstraints = "2" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP &quot;FSB_A&quot; TO TIMEGRP &quot;CPU_nSTERM&quot; 15 ns</twConstName><twConstData type="MAXDELAY" slack="7.121" best="7.879" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_cg_pll_clkout0 = PERIOD TIMEGRP &quot;cg_pll_clkout0&quot; TS_CLKIN / 2 HIGH 50%</twConstName><twConstData type="SETUP" slack="11.311" best="3.689" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.458" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_CLKIN = PERIOD TIMEGRP &quot;CLKIN&quot; 30 ns HIGH 50%</twConstName><twConstData type="MINLOWPULSE" slack="20.000" best="10.000" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_cg_pll_clkfbout = PERIOD TIMEGRP &quot;cg_pll_clkfbout&quot; TS_CLKIN HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="27.334" best="2.666" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt></twSumRpt></twBody></twReport>

284
fpga/WarpLC.syr
View File

@ -1,4 +1,4 @@
Release 14.7 - xst P.20131013 (nt64)
Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
@ -108,19 +108,17 @@ Cores Search Directories : {"ipcore_dir" }
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" into library work
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" into library work
Parsing module <PLL>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" into library work
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" into library work
Parsing module <PrefetchTagRAM>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" into library work
Parsing module <PrefetchDataRAM>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\SizeDecode.v" into library work
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\SizeDecode.v" into library work
Parsing module <SizeDecode>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" into library work
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" into library work
Parsing module <L2Prefetch>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" into library work
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ClkGen.v" into library work
Parsing module <ClkGen>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" into library work
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" into library work
Parsing module <WarpLC>.
=========================================================================
@ -128,7 +126,7 @@ Parsing module <WarpLC>.
=========================================================================
Elaborating module <WarpLC>.
WARNING:HDLCompiler:1016 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port LOCKED is not connected to this instance
WARNING:HDLCompiler:1016 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port LOCKED is not connected to this instance
Elaborating module <ClkGen>.
@ -139,11 +137,11 @@ Elaborating module <IBUFG>.
Elaborating module <BUFIO2FB(DIVIDE_BYPASS="TRUE")>.
Elaborating module <PLL_BASE(BANDWIDTH="HIGH",CLK_FEEDBACK="CLKFBOUT",COMPENSATION="EXTERNAL",DIVCLK_DIVIDE=1,CLKFBOUT_MULT=28,CLKFBOUT_PHASE=0.0,CLKOUT0_DIVIDE=14,CLKOUT0_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,CLKIN_PERIOD=30.0,REF_JITTER=0.01)>.
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to clkout1_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to clkout2_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to clkout3_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to clkout4_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to clkout5_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to clkout1_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to clkout2_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to clkout3_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to clkout4_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to clkout5_unused ignored, since the identifier is never used
Elaborating module <BUFG>.
@ -152,26 +150,23 @@ Elaborating module <ODDR2>.
Elaborating module <ODDR2(DDR_ALIGNMENT="C0",INIT=1'b0,SRTYPE="ASYNC")>.
Elaborating module <SizeDecode>.
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to FSB_B ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to FSB_B ignored, since the identifier is never used
Elaborating module <L2Prefetch>.
Elaborating module <PrefetchTagRAM>.
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module <PrefetchTagRAM> remains a black box.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 33: Size mismatch in connection of port <a>. Formal port size is 5-bit while actual signal size is 7-bit.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 36: Size mismatch in connection of port <dpra>. Formal port size is 5-bit while actual signal size is 7-bit.
Elaborating module <PrefetchDataRAM>.
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" Line 39: Empty module <PrefetchDataRAM> remains a black box.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 44: Size mismatch in connection of port <addra>. Formal port size is 7-bit while actual signal size is 5-bit.
WARNING:Xst:2972 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 91. All outputs of instance <sd> of block <SizeDecode> are unconnected in block <WarpLC>. Underlying logic will be removed.
WARNING:HDLCompiler:1499 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module <PrefetchTagRAM> remains a black box.
WARNING:HDLCompiler:189 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 40: Size mismatch in connection of port <d>. Formal port size is 22-bit while actual signal size is 20-bit.
WARNING:HDLCompiler:189 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 41: Size mismatch in connection of port <spo>. Formal port size is 22-bit while actual signal size is 20-bit.
WARNING:HDLCompiler:189 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 43: Size mismatch in connection of port <dpo>. Formal port size is 22-bit while actual signal size is 20-bit.
WARNING:Xst:2972 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 91. All outputs of instance <sd> of block <SizeDecode> are unconnected in block <WarpLC>. Underlying logic will be removed.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <WarpLC>.
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v".
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v".
Set property "IOSTANDARD = LVCMOS33" for signal <FSB_A>.
Set property "IOBDELAY = NONE" for signal <FSB_A>.
Set property "IOSTANDARD = LVCMOS33" for signal <FSB_SIZ>.
@ -203,32 +198,32 @@ Synthesizing Unit <WarpLC>.
Set property "IOSTANDARD = LVCMOS33" for signal <CLKFB_OUT>.
Set property "DRIVE = 24" for signal <CLKFB_OUT>.
Set property "SLEW = FAST" for signal <CLKFB_OUT>.
WARNING:Xst:647 - Input <FSB_A<31:29>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSB_A<31:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CPU_nAS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 91: Output port <B> of the instance <sd> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 91: Output port <B> of the instance <sd> is unconnected or connected to loadless signal.
Summary:
no macro.
Unit <WarpLC> synthesized.
Synthesizing Unit <ClkGen>.
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v".
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" line 32: Output port <LOCKED> of the instance <pll> is unconnected or connected to loadless signal.
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ClkGen.v".
INFO:Xst:3210 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ClkGen.v" line 32: Output port <LOCKED> of the instance <pll> is unconnected or connected to loadless signal.
Found 1-bit register for signal <CPUCLKr>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <ClkGen> synthesized.
Synthesizing Unit <PLL>.
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v".
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v".
Summary:
no macro.
Unit <PLL> synthesized.
Synthesizing Unit <L2Prefetch>.
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v".
WARNING:Xst:647 - Input <RDA<28:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRA<28:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 21-bit comparator equal for signal <RDTag[20]_RDATag[20]_equal_5_o> created at line 28
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v".
WARNING:Xst:647 - Input <WRD> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CPUCLKr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 19-bit comparator equal for signal <RDTag[18]_RDATag[18]_equal_5_o> created at line 34
Summary:
inferred 1 Comparator(s).
Unit <L2Prefetch> synthesized.
@ -240,7 +235,7 @@ Macro Statistics
# Registers : 1
1-bit register : 1
# Comparators : 1
21-bit comparator equal : 1
19-bit comparator equal : 1
=========================================================================
@ -249,9 +244,7 @@ Macro Statistics
=========================================================================
Reading core <ipcore_dir/PrefetchTagRAM.ngc>.
Reading core <ipcore_dir/PrefetchDataRAM.ngc>.
Loading core <PrefetchTagRAM> for timing and area information for instance <Way0Tag>.
Loading core <PrefetchDataRAM> for timing and area information for instance <Way0Data>.
Loading core <PrefetchTagRAM> for timing and area information for instance <Tag>.
=========================================================================
Advanced HDL Synthesis Report
@ -260,7 +253,7 @@ Macro Statistics
# Registers : 1
Flip-Flops : 1
# Comparators : 1
21-bit comparator equal : 1
19-bit comparator equal : 1
=========================================================================
@ -309,26 +302,26 @@ Top Level Output File Name : WarpLC.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 22
# GND : 2
# BELS : 21
# GND : 1
# INV : 3
# LUT1 : 1
# LUT6 : 7
# LUT2 : 1
# LUT6 : 6
# MUXCY : 8
# VCC : 1
# FlipFlops/Latches : 50
# FD : 44
# FDR : 1
# ODDR2 : 5
# RAMS : 23
# RAM32X1D : 22
# RAMB8BWER : 1
# RAMS : 22
# RAM128X1D : 22
# Clock Buffers : 2
# BUFG : 2
# IO Buffers : 66
# IO Buffers : 34
# IBUF : 26
# IBUFG : 2
# OBUF : 38
# OBUF : 6
# Others : 2
# BUFIO2FB : 1
# PLL_ADV : 1
@ -341,25 +334,23 @@ Selected Device : 6slx9ftg256-2
Slice Logic Utilization:
Number of Slice Registers: 50 out of 11440 0%
Number of Slice LUTs: 55 out of 5720 0%
Number of Slice LUTs: 99 out of 5720 1%
Number used as Logic: 11 out of 5720 0%
Number used as Memory: 44 out of 1440 3%
Number used as RAM: 44
Number used as Memory: 88 out of 1440 6%
Number used as RAM: 88
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 105
Number with an unused Flip Flop: 55 out of 105 52%
Number with an unused LUT: 50 out of 105 47%
Number of fully used LUT-FF pairs: 0 out of 105 0%
Number of LUT Flip Flop pairs used: 149
Number with an unused Flip Flop: 99 out of 149 66%
Number with an unused LUT: 50 out of 149 33%
Number of fully used LUT-FF pairs: 0 out of 149 0%
Number of unique control sets: 2
IO Utilization:
Number of IOs: 75
Number of bonded IOBs: 66 out of 186 35%
Number of bonded IOBs: 34 out of 186 18%
Specific Feature Utilization:
Number of Block RAM/FIFO: 1 out of 32 3%
Number using Block RAM only: 1
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
Number of PLL_ADVs: 1 out of 2 50%
@ -384,7 +375,7 @@ Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
cg/pll/pll_base_inst/CLKOUT0 | BUFG | 76 |
cg/pll/pll_base_inst/CLKOUT0 | BUFG | 75 |
cg/pll/pll_base_inst/CLKFBOUT | BUFG | 2 |
-----------------------------------+------------------------+-------+
@ -396,10 +387,10 @@ Timing Summary:
---------------
Speed Grade: -2
Minimum period: 4.696ns (Maximum Frequency: 212.947MHz)
Minimum input arrival time before clock: 3.719ns
Maximum output required time after clock: 6.384ns
Maximum combinational path delay: 8.292ns
Minimum period: 4.616ns (Maximum Frequency: 216.638MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.656ns
Timing Details:
---------------
@ -407,10 +398,10 @@ All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'cg/pll/pll_base_inst/CLKOUT0'
Clock period: 4.696ns (frequency: 212.947MHz)
Total number of paths / destination ports: 50 / 50
Clock period: 4.616ns (frequency: 216.638MHz)
Total number of paths / destination ports: 5 / 5
-------------------------------------------------------------------------
Delay: 2.348ns (Levels of Logic = 1)
Delay: 2.308ns (Levels of Logic = 1)
Source: cg/CPUCLKr (FF)
Destination: cg/CPUCLK_inst (FF)
Source Clock: cg/pll/pll_base_inst/CLKOUT0 rising
@ -421,91 +412,38 @@ Delay: 2.348ns (Levels of Logic = 1)
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 4 0.525 0.803 cg/CPUCLKr (cg/CPUCLKr)
INV:I->O 3 0.255 0.765 l2pre/CPUCLKr_INV_15_o1_INV_0 (l2pre/CPUCLKr_INV_15_o)
INV:I->O 2 0.255 0.725 cg/CPUCLKr_INV_2_o1_INV_0 (cg/CPUCLKr_INV_2_o)
ODDR2:D1 0.000 cg/CPUCLK_inst
----------------------------------------
Total 2.348ns (0.780ns logic, 1.568ns route)
(33.2% logic, 66.8% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'cg/pll/pll_base_inst/CLKOUT0'
Total number of paths / destination ports: 225 / 137
-------------------------------------------------------------------------
Offset: 3.719ns (Levels of Logic = 3)
Source: FSB_A<2> (PAD)
Destination: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_21 (FF)
Destination Clock: cg/pll/pll_base_inst/CLKOUT0 rising
Data Path: FSB_A<2> to l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_21
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 23 1.328 1.357 FSB_A_2_IBUF (FSB_A_2_IBUF)
begin scope: 'l2pre/Way0Tag:dpra<0>'
RAM32X1D:DPRA0->DPO 2 0.235 0.725 U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 (dpo<2>)
FD:D 0.074 U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_2
----------------------------------------
Total 3.719ns (1.637ns logic, 2.082ns route)
(44.0% logic, 56.0% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cg/pll/pll_base_inst/CLKOUT0'
Total number of paths / destination ports: 54 / 33
-------------------------------------------------------------------------
Offset: 6.384ns (Levels of Logic = 11)
Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 (RAM)
Destination: CPU_nSTERM (PAD)
Source Clock: cg/pll/pll_base_inst/CLKOUT0 rising
Data Path: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 to CPU_nSTERM
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
RAM32X1D:WCLK->DPO 2 1.012 0.954 U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 (dpo<2>)
end scope: 'l2pre/Way0Tag:dpo<2>'
LUT6:I3->O 1 0.235 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>)
MUXCY:S->O 1 0.215 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<0> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<0>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<1> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<1>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<2> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<2>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<4> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<4>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<5> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<5>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6> (l2pre/RDTag[20]_RDATag[20]_equal_5_o)
MUXCY:CI->O 1 0.235 0.681 CPU_nSTERM1_cy (CPU_nSTERM_OBUF)
OBUF:I->O 2.912 CPU_nSTERM_OBUF (CPU_nSTERM)
----------------------------------------
Total 6.384ns (4.749ns logic, 1.635ns route)
(74.4% logic, 25.6% route)
Total 2.308ns (0.780ns logic, 1.528ns route)
(33.8% logic, 66.2% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 132 / 2
Total number of paths / destination ports: 20 / 2
-------------------------------------------------------------------------
Delay: 8.292ns (Levels of Logic = 13)
Source: FSB_A<2> (PAD)
Delay: 6.656ns (Levels of Logic = 11)
Source: FSB_A<11> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path: FSB_A<2> to CPU_nSTERM
Data Path: FSB_A<11> to CPU_nSTERM
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 23 1.328 1.357 FSB_A_2_IBUF (FSB_A_2_IBUF)
begin scope: 'l2pre/Way0Tag:dpra<0>'
RAM32X1D:DPRA0->DPO 2 0.235 0.954 U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 (dpo<2>)
end scope: 'l2pre/Way0Tag:dpo<2>'
LUT6:I3->O 1 0.235 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>)
MUXCY:S->O 1 0.215 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<0> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<0>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<1> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<1>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<2> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<2>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<4> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<4>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<5> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<5>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6> (l2pre/RDTag[20]_RDATag[20]_equal_5_o)
IBUF:I->O 1 1.328 0.910 FSB_A_11_IBUF (FSB_A_11_IBUF)
LUT6:I3->O 1 0.235 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_lut<0> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_lut<0>)
MUXCY:S->O 1 0.215 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<0> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<0>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<1> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<1>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<2> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<2>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<3> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<3>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<4> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<4>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<5> (l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<5>)
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<6> (l2pre/RDTag[18]_RDATag[18]_equal_5_o)
MUXCY:CI->O 1 0.235 0.681 CPU_nSTERM1_cy (CPU_nSTERM_OBUF)
OBUF:I->O 2.912 CPU_nSTERM_OBUF (CPU_nSTERM)
----------------------------------------
Total 8.292ns (5.300ns logic, 2.992ns route)
(63.9% logic, 36.1% route)
Total 6.656ns (5.065ns logic, 1.591ns route)
(76.1% logic, 23.9% route)
=========================================================================
@ -517,20 +455,84 @@ Clock to Setup on destination clock cg/pll/pll_base_inst/CLKOUT0
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------------------+---------+---------+---------+---------+
cg/pll/pll_base_inst/CLKOUT0| 2.568| | 2.348| |
cg/pll/pll_base_inst/CLKOUT0| 2.308| | 2.308| |
----------------------------+---------+---------+---------+---------+
=========================================================================
WARNING:Xst:615 - Instance associated with port FSB_D<31> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<31> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<30> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<30> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<29> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<29> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<28> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<28> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<27> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<27> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<26> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<26> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<25> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<25> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<24> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<24> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<23> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<23> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<22> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<22> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<21> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<21> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<20> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<20> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<19> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<19> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<18> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<18> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<17> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<17> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<16> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<16> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<15> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<15> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<14> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<14> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<13> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<13> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<12> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<12> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<11> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<11> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<10> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<10> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<9> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<9> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<8> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<8> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<7> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<7> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<6> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<6> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<5> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<5> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<4> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<4> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<3> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<3> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<2> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<2> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<1> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<1> not found, property DRIVE not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<0> not found, property IOSTANDARD not attached.
WARNING:Xst:615 - Instance associated with port FSB_D<0> not found, property DRIVE not attached.
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.67 secs
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.42 secs
-->
Total memory usage is 258804 kilobytes
Total memory usage is 224828 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 17 ( 0 filtered)
Number of warnings : 80 ( 0 filtered)
Number of infos : 3 ( 0 filtered)

5888
fpga/WarpLC.twr
View File

File diff suppressed because it is too large Load Diff

46
fpga/WarpLC.twx
View File

File diff suppressed because one or more lines are too long

4
fpga/WarpLC.unroutes
View File

@ -1,7 +1,7 @@
Release 14.7 - par P.20131013 (nt64)
Release 14.7 - par P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sun Oct 31 15:38:33 2021
Mon Nov 01 06:10:44 2021
All signals are completely routed.

78
fpga/WarpLC.v
View File

@ -86,6 +86,16 @@ module WarpLC(
.FPUCLK(FPUCLK),
.RAMCLK0(RAMCLK0),
.RAMCLK1(RAMCLK1));
wire FSB_SEL_RAM, FSB_SEL_ROM, FSB_VRAM, FSB_SEL_Cache;
wire [27:0] FSB_CA;
CS cs(
.A(FSB_A),
.RAMCS(FSB_SEL_RAM),
.ROMCS(FSB_SEL_ROM),
.VRAMCS(FSB_VRAM),
.CacheCS(FSB_SEL_Cache),
.CA(FSB_CA));
wire [3:0] FSB_B;
SizeDecode sd (
@ -98,11 +108,11 @@ module WarpLC(
.CLK(FSBCLK),
.CPUCLKr(CPUCLKr),
.RDA(FSB_A[28:2]),
.RDA(FSB_A[27:2]),
.RDD(FSB_D[31:0]),
.Match(L2PrefetchMatch),
.WRA(27'b0),
.WRA(26'b0),
.WRD(32'b0),
.WR(1'b0),
.WRM(4'b0),
@ -111,3 +121,67 @@ module WarpLC(
assign CPU_nSTERM = ~(L2PrefetchMatch);
endmodule
/* Cacheable areas of RAM
* ...
* 0x50FFFFFF VRAM alias 0101 0000 1111 11XX XXXX XXXX XXXX XXXX
* 0x50FC0000
* 0x50FBFFFF VRAM 0101 0000 1111 10XX XXXX XXXX XXXX XXXX
* 0x50F80000
* 0x50F7FFFF VRAM 0101 0000 1111 01XX XXXX XXXX XXXX XXXX
* 0x50F40000
* 0x50F3FFFF VRAM alias 0101 0000 1111 00XX XXXX XXXX XXXX XXXX
* 0x50F00000
* ...
* 0x40FFFFFF ROM alias? 0100 0000 111X XXXX XXXX XXXX XXXX XXXX
* 0x40E00000
* 0x40DFFFFF ROM 0100 0000 110X XXXX XXXX XXXX XXXX XXXX
* 0x40C00000
* 0x40BFFFFF ROM 0100 0000 101X XXXX XXXX XXXX XXXX XXXX
* 0x40A00000
* 0x409FFFFF ROM alias? 0100 0000 100X XXXX XXXX XXXX XXXX XXXX
* 0x40800000
* 0x407FFFFF ROM alias? 0100 0000 011X XXXX XXXX XXXX XXXX XXXX
* 0x40600000
* 0x405FFFFF ROM alias? 0100 0000 010X XXXX XXXX XXXX XXXX XXXX
* 0x40400000
* 0x403FFFFF ROM alias? 0100 0000 001X XXXX XXXX XXXX XXXX XXXX
* 0x40200000
* 0x401FFFFF ROM alias? 0100 0000 000X XXXX XXXX XXXX XXXX XXXX
* 0x40000000
* 0x3FFFFFFF RAM alias? 0011 11XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x3C000000
* 0x3BFFFFFF RAM alias? 0011 10XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x38000000
* 0x37FFFFFF RAM alias? 0011 01XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x34000000
* 0x33FFFFFF RAM alias? 0011 00XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x30000000
* 0x2FFFFFFF RAM alias? 0010 11XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x2C000000
* 0x2BFFFFFF RAM alias? 0010 10XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x28000000
* 0x27FFFFFF RAM alias? 0010 01XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x24000000
* 0x23FFFFFF RAM alias? 0010 00XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x20000000
* 0x1FFFFFFF RAM alias? 0001 11XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x1C000000
* 0x1BFFFFFF RAM alias? 0001 10XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x18000000
* 0x17FFFFFF RAM alias? 0001 01XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x14000000
* 0x13FFFFFF RAM alias? 0001 00XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x10000000
* 0x0FFFFFFF RAM alias? 0000 11XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x0C000000
* 0x0BFFFFFF RAM alias? 0000 10XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x08000000
* 0x07FFFFFF RAM alias? 0000 01XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x04000000
* 0x03FFFFFF RAM (26 bits) 0000 00XX XXXX XXXX XXXX XXXX XXXX XXXX
* 0x00000000
*/

34
fpga/WarpLC.xise
View File

@ -17,30 +17,26 @@
<files>
<file xil_pn:name="WarpLC.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="PLL.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="PrefetchBuf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="ipcore_dir/PrefetchTagRAM.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="ipcore_dir/PrefetchDataRAM.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="ClkGen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="L2Cache.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
@ -48,8 +44,24 @@
</file>
<file xil_pn:name="SizeDecode.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="ipcore_dir/L2WayRAM.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="L2CacheWay.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="Prefetch.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="CS.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="ipcore_dir/PrefetchTagRAM.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
@ -59,6 +71,9 @@
<file xil_pn:name="ipcore_dir/PLL.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/L2WayRAM.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
@ -171,6 +186,7 @@
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
@ -288,7 +304,7 @@
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="1000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="10000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>

40
fpga/WarpLC_envsettings.html
View File

@ -22,10 +22,10 @@
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\PuTTY\;<br>C:\Program Files (x86)\WinMerge;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Dog\AppData\Local\GitHubDesktop\bin</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\PuTTY\;<br>C:\Program Files (x86)\WinMerge;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Dog\AppData\Local\GitHubDesktop\bin</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\PuTTY\;<br>C:\Program Files (x86)\WinMerge;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Dog\AppData\Local\GitHubDesktop\bin</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\PuTTY\;<br>C:\Program Files (x86)\WinMerge;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Dog\AppData\Local\GitHubDesktop\bin</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
</tr>
<tr>
<td>XILINX</td>
@ -556,31 +556,31 @@
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz</td>
<td>Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz</td>
<td>Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz</td>
<td>Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz</td>
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>Dog-PC</td>
<td>Dog-PC</td>
<td>Dog-PC</td>
<td>Dog-PC</td>
<td>ZanePC</td>
<td>ZanePC</td>
<td>ZanePC</td>
<td>ZanePC</td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td>Microsoft , 64-bit</td>
<td>Microsoft , 64-bit</td>
<td>Microsoft , 64-bit</td>
<td>Microsoft , 64-bit</td>
</tr>
<tr>
<td>OS Release</td>
<td>Service Pack 1 (build 7601)</td>
<td>Service Pack 1 (build 7601)</td>
<td>Service Pack 1 (build 7601)</td>
<td>Service Pack 1 (build 7601)</td>
<td>major release (build 9200)</td>
<td>major release (build 9200)</td>
<td>major release (build 9200)</td>
<td>major release (build 9200)</td>
</tr>
</TABLE>
</BODY> </HTML>

2
fpga/WarpLC_guide.ncd
View File

File diff suppressed because one or more lines are too long

88
fpga/WarpLC_map.map
View File

@ -1,4 +1,4 @@
Release 14.7 Map P.20131013 (nt64)
Release 14.7 Map P.20131013 (nt)
Xilinx Map Application Log File for Design 'WarpLC'
Design Information
@ -10,7 +10,7 @@ Target Device : xc6slx9
Target Package : ftg256
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Sun Oct 31 15:38:01 2021
Mapped Date : Mon Nov 01 06:10:29 2021
Running global optimization...
Mapping design into LUTs...
@ -20,103 +20,97 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 10 secs
Total CPU time at the beginning of Placer: 10 secs
Total REAL time at the beginning of Placer: 7 secs
Total CPU time at the beginning of Placer: 6 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:283d) REAL time: 10 secs
Phase 1.1 Initial Placement Analysis (Checksum:60b6) REAL time: 8 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:283d) REAL time: 11 secs
Phase 2.7 Design Feasibility Check (Checksum:60b6) REAL time: 8 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:283d) REAL time: 11 secs
Phase 3.31 Local Placement Optimization (Checksum:60b6) REAL time: 8 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
....
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:8c2c3f8) REAL time: 15 secs
(Checksum:11959966) REAL time: 8 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:8c2c3f8) REAL time: 15 secs
Phase 5.36 Local Placement Optimization (Checksum:11959966) REAL time: 8 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:8c2c3f8) REAL time: 15 secs
Phase 6.30 Global Clock Region Assignment (Checksum:11959966) REAL time: 8 secs
Phase 7.3 Local Placement Optimization
...
....
Phase 7.3 Local Placement Optimization (Checksum:f4c788ab) REAL time: 21 secs
Phase 7.3 Local Placement Optimization (Checksum:1284e9e0) REAL time: 8 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:f4c788ab) REAL time: 21 secs
Phase 8.5 Local Placement Optimization (Checksum:1284e9e0) REAL time: 8 secs
Phase 9.8 Global Placement
................
..
Phase 9.8 Global Placement (Checksum:67f9eb6e) REAL time: 21 secs
................................................................
..................
Phase 9.8 Global Placement (Checksum:f7b99523) REAL time: 8 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:67f9eb6e) REAL time: 21 secs
Phase 10.5 Local Placement Optimization (Checksum:f7b99523) REAL time: 8 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:32dd77c2) REAL time: 22 secs
Phase 11.18 Placement Optimization (Checksum:6614d61e) REAL time: 9 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:32dd77c2) REAL time: 22 secs
Phase 12.5 Local Placement Optimization (Checksum:6614d61e) REAL time: 9 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:32dd77c2) REAL time: 22 secs
Phase 13.34 Placement Validation (Checksum:6614d61e) REAL time: 9 secs
Total REAL time to Placer completion: 22 secs
Total CPU time to Placer completion: 22 secs
Total REAL time to Placer completion: 9 secs
Total CPU time to Placer completion: 6 secs
Running physical synthesis...
Physical synthesis completed.
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 1
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 1 out of 11,440 1%
Number used as Flip Flops: 1
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 33 out of 5,720 1%
Number of Slice LUTs: 89 out of 5,720 1%
Number used as logic: 9 out of 5,720 1%
Number using O6 output only: 8
Number using O6 output only: 7
Number using O5 output only: 1
Number using O5 and O6: 0
Number using O5 and O6: 1
Number used as ROM: 0
Number used as Memory: 24 out of 1,440 1%
Number used as Dual Port RAM: 24
Number using O6 output only: 4
Number used as Memory: 80 out of 1,440 5%
Number used as Dual Port RAM: 80
Number using O6 output only: 80
Number using O5 output only: 0
Number using O5 and O6: 20
Number using O5 and O6: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 0
Slice Logic Distribution:
Number of occupied Slices: 9 out of 1,430 1%
Number of occupied Slices: 23 out of 1,430 1%
Number of MUXCYs used: 8 out of 2,860 1%
Number of LUT Flip Flop pairs used: 33
Number with an unused Flip Flop: 32 out of 33 96%
Number with an unused LUT: 0 out of 33 0%
Number of fully used LUT-FF pairs: 1 out of 33 3%
Number of LUT Flip Flop pairs used: 89
Number with an unused Flip Flop: 88 out of 89 98%
Number with an unused LUT: 0 out of 89 0%
Number of fully used LUT-FF pairs: 1 out of 89 1%
Number of unique control sets: 2
Number of slice register sites lost
to control set restrictions: 11 out of 11,440 1%
to control set restrictions: 7 out of 11,440 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
@ -125,12 +119,12 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 66 out of 186 35%
Number of bonded IOBs: 34 out of 186 18%
IOB Flip Flops: 5
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 1 out of 64 1%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
@ -159,11 +153,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 1.67
Average Fanout of Non-Clock Nets: 5.20
Peak Memory Usage: 368 MB
Total REAL time to MAP completion: 25 secs
Total CPU time to MAP completion (all processors): 25 secs
Peak Memory Usage: 287 MB
Total REAL time to MAP completion: 10 secs
Total CPU time to MAP completion (all processors): 8 secs
Mapping completed.
See MAP report file "WarpLC_map.mrp" for details.

490
fpga/WarpLC_map.mrp
View File

@ -1,4 +1,4 @@
Release 14.7 Map P.20131013 (nt64)
Release 14.7 Map P.20131013 (nt)
Xilinx Mapping Report File for Design 'WarpLC'
Design Information
@ -10,42 +10,42 @@ Target Device : xc6slx9
Target Package : ftg256
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Sun Oct 31 15:38:01 2021
Mapped Date : Mon Nov 01 06:10:29 2021
Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 1 out of 11,440 1%
Number used as Flip Flops: 1
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 33 out of 5,720 1%
Number of Slice LUTs: 89 out of 5,720 1%
Number used as logic: 9 out of 5,720 1%
Number using O6 output only: 8
Number using O6 output only: 7
Number using O5 output only: 1
Number using O5 and O6: 0
Number using O5 and O6: 1
Number used as ROM: 0
Number used as Memory: 24 out of 1,440 1%
Number used as Dual Port RAM: 24
Number using O6 output only: 4
Number used as Memory: 80 out of 1,440 5%
Number used as Dual Port RAM: 80
Number using O6 output only: 80
Number using O5 output only: 0
Number using O5 and O6: 20
Number using O5 and O6: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 0
Slice Logic Distribution:
Number of occupied Slices: 9 out of 1,430 1%
Number of occupied Slices: 23 out of 1,430 1%
Number of MUXCYs used: 8 out of 2,860 1%
Number of LUT Flip Flop pairs used: 33
Number with an unused Flip Flop: 32 out of 33 96%
Number with an unused LUT: 0 out of 33 0%
Number of fully used LUT-FF pairs: 1 out of 33 3%
Number of LUT Flip Flop pairs used: 89
Number with an unused Flip Flop: 88 out of 89 98%
Number with an unused LUT: 0 out of 89 0%
Number of fully used LUT-FF pairs: 1 out of 89 1%
Number of unique control sets: 2
Number of slice register sites lost
to control set restrictions: 11 out of 11,440 1%
to control set restrictions: 7 out of 11,440 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
@ -54,12 +54,12 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 66 out of 186 35%
Number of bonded IOBs: 34 out of 186 18%
IOB Flip Flops: 5
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 1 out of 64 1%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
@ -88,11 +88,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 1.67
Average Fanout of Non-Clock Nets: 5.20
Peak Memory Usage: 368 MB
Total REAL time to MAP completion: 25 secs
Total CPU time to MAP completion (all processors): 25 secs
Peak Memory Usage: 287 MB
Total REAL time to MAP completion: 10 secs
Total CPU time to MAP completion (all processors): 8 secs
Table of Contents
-----------------
@ -115,10 +115,6 @@ Section 1 - Errors
Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Section 3 - Informational
-------------------------
@ -126,7 +122,7 @@ INFO:Map:284 - Map is running with the multi-threading option on. Map currently
supports the use of up to 2 processors. Based on the the user options and
machine load, Map will use 2 processors during this run.
INFO:LIT:243 - Logical network FSB_A<31> has no load.
INFO:LIT:395 - The above info message is repeated 54 more times for the
INFO:LIT:395 - The above info message is repeated 86 more times for the
following (max. 5 shown):
FSB_A<30>,
FSB_A<29>,
@ -145,9 +141,9 @@ INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
46 block(s) removed
48 block(s) removed
2 block(s) optimized away
68 signal(s) removed
70 signal(s) removed
Section 5 - Removed Logic
-------------------------
@ -163,295 +159,303 @@ above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<0>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<0>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_0"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_0" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<1>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<1>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_1"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_1" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<2>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<2>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_2"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_2" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<3>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<3>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_3"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_3" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<4>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<4>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_4"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_4" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<5>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<5>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_5"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_5" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<6>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<6>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_6"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_6" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<7>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<7>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_7"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_7" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<8>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<8>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_8"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_8" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<9>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<9>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_9"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_9" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<10>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<10>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_10"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_10" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<11>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<11>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_11"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_11" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<12>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<12>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_12"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_12" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<13>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<13>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_13"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_13" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<14>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<14>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_14"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_14" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<15>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<15>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_15"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_15" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<16>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<16>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_16"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_16" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<17>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<17>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_17"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_17" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<18>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<18>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_18"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_18" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<19>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<19>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_19"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_19" (FF)
removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<20>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<20>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_20"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_20" (FF)
removed.
The signal "l2pre/Tag/dpo<20>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<21>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<21>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_21"
(FF) removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_21" (FF)
removed.
The signal "l2pre/Tag/dpo<21>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<0>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<0>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_0"
(FF) removed.
The signal "l2pre/Way0Tag/spo<0>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_0" (FF)
removed.
The signal "l2pre/Tag/spo<0>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<1>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<1>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_1"
(FF) removed.
The signal "l2pre/Way0Tag/spo<1>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_1" (FF)
removed.
The signal "l2pre/Tag/spo<1>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<2>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<2>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_2"
(FF) removed.
The signal "l2pre/Way0Tag/spo<2>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_2" (FF)
removed.
The signal "l2pre/Tag/spo<2>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<3>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<3>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_3"
(FF) removed.
The signal "l2pre/Way0Tag/spo<3>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_3" (FF)
removed.
The signal "l2pre/Tag/spo<3>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<4>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<4>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_4"
(FF) removed.
The signal "l2pre/Way0Tag/spo<4>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_4" (FF)
removed.
The signal "l2pre/Tag/spo<4>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<5>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<5>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_5"
(FF) removed.
The signal "l2pre/Way0Tag/spo<5>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_5" (FF)
removed.
The signal "l2pre/Tag/spo<5>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<6>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<6>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_6"
(FF) removed.
The signal "l2pre/Way0Tag/spo<6>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_6" (FF)
removed.
The signal "l2pre/Tag/spo<6>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<7>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<7>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_7"
(FF) removed.
The signal "l2pre/Way0Tag/spo<7>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_7" (FF)
removed.
The signal "l2pre/Tag/spo<7>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<8>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<8>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_8"
(FF) removed.
The signal "l2pre/Way0Tag/spo<8>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_8" (FF)
removed.
The signal "l2pre/Tag/spo<8>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<9>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<9>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_9"
(FF) removed.
The signal "l2pre/Way0Tag/spo<9>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_9" (FF)
removed.
The signal "l2pre/Tag/spo<9>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<10>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<10>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_10"
(FF) removed.
The signal "l2pre/Way0Tag/spo<10>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_10" (FF)
removed.
The signal "l2pre/Tag/spo<10>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<11>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<11>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_11"
(FF) removed.
The signal "l2pre/Way0Tag/spo<11>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_11" (FF)
removed.
The signal "l2pre/Tag/spo<11>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<12>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<12>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_12"
(FF) removed.
The signal "l2pre/Way0Tag/spo<12>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_12" (FF)
removed.
The signal "l2pre/Tag/spo<12>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<13>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<13>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_13"
(FF) removed.
The signal "l2pre/Way0Tag/spo<13>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_13" (FF)
removed.
The signal "l2pre/Tag/spo<13>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<14>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<14>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_14"
(FF) removed.
The signal "l2pre/Way0Tag/spo<14>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_14" (FF)
removed.
The signal "l2pre/Tag/spo<14>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<15>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<15>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_15"
(FF) removed.
The signal "l2pre/Way0Tag/spo<15>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_15" (FF)
removed.
The signal "l2pre/Tag/spo<15>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<16>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<16>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_16"
(FF) removed.
The signal "l2pre/Way0Tag/spo<16>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_16" (FF)
removed.
The signal "l2pre/Tag/spo<16>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<17>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<17>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_17"
(FF) removed.
The signal "l2pre/Way0Tag/spo<17>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_17" (FF)
removed.
The signal "l2pre/Tag/spo<17>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<18>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<18>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_18"
(FF) removed.
The signal "l2pre/Way0Tag/spo<18>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_18" (FF)
removed.
The signal "l2pre/Tag/spo<18>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<19>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<19>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_19"
(FF) removed.
The signal "l2pre/Way0Tag/spo<19>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_19" (FF)
removed.
The signal "l2pre/Tag/spo<19>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<20>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<20>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_20"
(FF) removed.
The signal "l2pre/Way0Tag/spo<20>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_20" (FF)
removed.
The signal "l2pre/Tag/spo<20>" is loadless and has been removed.
The signal
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<21>"
is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<21>" is
loadless and has been removed.
Loadless block
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_21"
(FF) removed.
The signal "l2pre/Way0Tag/spo<21>" is loadless and has been removed.
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_21" (FF)
removed.
The signal "l2pre/Tag/spo<21>" is loadless and has been removed.
The signal "cg/pll/pll_base_inst/N2" is sourceless and has been removed.
The signal "cg/pll/pll_base_inst/N3" is sourceless and has been removed.
Unused block "cg/pll/pll_base_inst/XST_GND" (ZERO) removed.
Unused block "cg/pll/pll_base_inst/XST_VCC" (ONE) removed.
Unused block
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21"
(RAM128X1D) removed.
Unused block
"l2pre/Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22"
(RAM128X1D) removed.
Optimized Block(s):
TYPE BLOCK
@ -500,38 +504,6 @@ Section 6 - IOB Properties
| FSB_A<25> | IOB | INPUT | LVCMOS33 | | | | | | |
| FSB_A<26> | IOB | INPUT | LVCMOS33 | | | | | | |
| FSB_A<27> | IOB | INPUT | LVCMOS33 | | | | | | |
| FSB_D<0> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<1> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<2> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<3> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<4> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<5> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<6> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<7> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<8> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<9> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<10> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<11> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<12> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<13> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<14> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<15> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<16> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<17> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<18> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<19> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<20> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<21> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<22> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<23> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<24> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<25> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<26> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<27> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<28> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<29> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<30> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| FSB_D<31> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
| RAMCLK0 | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
| RAMCLK1 | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+

2
fpga/WarpLC_map.ncd
View File

File diff suppressed because one or more lines are too long

2
fpga/WarpLC_map.ngm
View File

File diff suppressed because one or more lines are too long

195
fpga/WarpLC_map.psr
View File

@ -1,4 +1,4 @@
Release 14.7 Physical Synthesis Report P.20131013 (nt64)
Release 14.7 Physical Synthesis Report P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
TABLE OF CONTENTS
@ -30,9 +30,9 @@ Target Device : 6slx9ftg256-2
=========================================================================
---- Statistics
Number of registers added by Synchronous Optimization | 1
Number of LUTs removed by SmartOpt Trimming | 95
Number of LUTs removed by SmartOpt Trimming | 94
Overall change in number of design objects | -94
Overall change in number of design objects | -93
---- Details
@ -44,101 +44,100 @@ cg/CPUCLKr | Synchronous Optimizatio
Removed components | Optimization
-------------------------------------------------------|--------------------------
][288_1 | SmartOpt Trimming
][291_2 | SmartOpt Trimming
][293_4 | SmartOpt Trimming
][294_5 | SmartOpt Trimming
][297_7 | SmartOpt Trimming
][73_8 | SmartOpt Trimming
][const_101_66 | SmartOpt Trimming
][const_102_67 | SmartOpt Trimming
][const_104_68 | SmartOpt Trimming
][const_105_69 | SmartOpt Trimming
][const_107_70 | SmartOpt Trimming
][const_108_71 | SmartOpt Trimming
][const_110_72 | SmartOpt Trimming
][const_111_73 | SmartOpt Trimming
][const_113_74 | SmartOpt Trimming
][const_114_75 | SmartOpt Trimming
][const_116_76 | SmartOpt Trimming
][const_117_77 | SmartOpt Trimming
][const_119_78 | SmartOpt Trimming
][const_120_79 | SmartOpt Trimming
][const_122_80 | SmartOpt Trimming
][const_123_81 | SmartOpt Trimming
][const_125_82 | SmartOpt Trimming
][const_126_83 | SmartOpt Trimming
][const_128_84 | SmartOpt Trimming
][const_129_85 | SmartOpt Trimming
][const_131_86 | SmartOpt Trimming
][const_132_87 | SmartOpt Trimming
][const_134_88 | SmartOpt Trimming
][const_135_89 | SmartOpt Trimming
][const_137_90 | SmartOpt Trimming
][const_138_91 | SmartOpt Trimming
][const_140_92 | SmartOpt Trimming
][const_141_93 | SmartOpt Trimming
][const_143_94 | SmartOpt Trimming
][const_144_95 | SmartOpt Trimming
][const_146_96 | SmartOpt Trimming
][const_147_97 | SmartOpt Trimming
][const_15_9 | SmartOpt Trimming
][const_17_10 | SmartOpt Trimming
][const_18_11 | SmartOpt Trimming
][const_20_12 | SmartOpt Trimming
][const_21_13 | SmartOpt Trimming
][const_23_14 | SmartOpt Trimming
][const_24_15 | SmartOpt Trimming
][const_26_16 | SmartOpt Trimming
][const_27_17 | SmartOpt Trimming
][const_29_18 | SmartOpt Trimming
][const_30_19 | SmartOpt Trimming
][const_32_20 | SmartOpt Trimming
][const_33_21 | SmartOpt Trimming
][const_35_22 | SmartOpt Trimming
][const_36_23 | SmartOpt Trimming
][const_38_24 | SmartOpt Trimming
][const_39_25 | SmartOpt Trimming
][const_41_26 | SmartOpt Trimming
][const_42_27 | SmartOpt Trimming
][const_44_28 | SmartOpt Trimming
][const_45_29 | SmartOpt Trimming
][const_47_30 | SmartOpt Trimming
][const_48_31 | SmartOpt Trimming
][const_50_32 | SmartOpt Trimming
][const_51_33 | SmartOpt Trimming
][const_53_34 | SmartOpt Trimming
][const_54_35 | SmartOpt Trimming
][const_56_36 | SmartOpt Trimming
][const_57_37 | SmartOpt Trimming
][const_59_38 | SmartOpt Trimming
][const_60_39 | SmartOpt Trimming
][const_62_40 | SmartOpt Trimming
][const_63_41 | SmartOpt Trimming
][const_65_42 | SmartOpt Trimming
][const_66_43 | SmartOpt Trimming
][const_68_44 | SmartOpt Trimming
][const_69_45 | SmartOpt Trimming
][const_71_46 | SmartOpt Trimming
][const_72_47 | SmartOpt Trimming
][const_74_48 | SmartOpt Trimming
][const_75_49 | SmartOpt Trimming
][const_77_50 | SmartOpt Trimming
][const_78_51 | SmartOpt Trimming
][const_80_52 | SmartOpt Trimming
][const_81_53 | SmartOpt Trimming
][const_83_54 | SmartOpt Trimming
][const_84_55 | SmartOpt Trimming
][const_86_56 | SmartOpt Trimming
][const_87_57 | SmartOpt Trimming
][const_89_58 | SmartOpt Trimming
][const_90_59 | SmartOpt Trimming
][const_92_60 | SmartOpt Trimming
][const_93_61 | SmartOpt Trimming
][const_95_62 | SmartOpt Trimming
][const_96_63 | SmartOpt Trimming
][const_98_64 | SmartOpt Trimming
][const_99_65 | SmartOpt Trimming
][282_1 | SmartOpt Trimming
][285_2 | SmartOpt Trimming
][287_4 | SmartOpt Trimming
][288_5 | SmartOpt Trimming
][69_7 | SmartOpt Trimming
][const_101_65 | SmartOpt Trimming
][const_102_66 | SmartOpt Trimming
][const_104_67 | SmartOpt Trimming
][const_105_68 | SmartOpt Trimming
][const_107_69 | SmartOpt Trimming
][const_108_70 | SmartOpt Trimming
][const_110_71 | SmartOpt Trimming
][const_111_72 | SmartOpt Trimming
][const_113_73 | SmartOpt Trimming
][const_114_74 | SmartOpt Trimming
][const_116_75 | SmartOpt Trimming
][const_117_76 | SmartOpt Trimming
][const_119_77 | SmartOpt Trimming
][const_120_78 | SmartOpt Trimming
][const_122_79 | SmartOpt Trimming
][const_123_80 | SmartOpt Trimming
][const_125_81 | SmartOpt Trimming
][const_126_82 | SmartOpt Trimming
][const_128_83 | SmartOpt Trimming
][const_129_84 | SmartOpt Trimming
][const_131_85 | SmartOpt Trimming
][const_132_86 | SmartOpt Trimming
][const_134_87 | SmartOpt Trimming
][const_135_88 | SmartOpt Trimming
][const_137_89 | SmartOpt Trimming
][const_138_90 | SmartOpt Trimming
][const_140_91 | SmartOpt Trimming
][const_141_92 | SmartOpt Trimming
][const_143_93 | SmartOpt Trimming
][const_144_94 | SmartOpt Trimming
][const_146_95 | SmartOpt Trimming
][const_147_96 | SmartOpt Trimming
][const_15_8 | SmartOpt Trimming
][const_17_9 | SmartOpt Trimming
][const_18_10 | SmartOpt Trimming
][const_20_11 | SmartOpt Trimming
][const_21_12 | SmartOpt Trimming
][const_23_13 | SmartOpt Trimming
][const_24_14 | SmartOpt Trimming
][const_26_15 | SmartOpt Trimming
][const_27_16 | SmartOpt Trimming
][const_29_17 | SmartOpt Trimming
][const_30_18 | SmartOpt Trimming
][const_32_19 | SmartOpt Trimming
][const_33_20 | SmartOpt Trimming
][const_35_21 | SmartOpt Trimming
][const_36_22 | SmartOpt Trimming
][const_38_23 | SmartOpt Trimming
][const_39_24 | SmartOpt Trimming
][const_41_25 | SmartOpt Trimming
][const_42_26 | SmartOpt Trimming
][const_44_27 | SmartOpt Trimming
][const_45_28 | SmartOpt Trimming
][const_47_29 | SmartOpt Trimming
][const_48_30 | SmartOpt Trimming
][const_50_31 | SmartOpt Trimming
][const_51_32 | SmartOpt Trimming
][const_53_33 | SmartOpt Trimming
][const_54_34 | SmartOpt Trimming
][const_56_35 | SmartOpt Trimming
][const_57_36 | SmartOpt Trimming
][const_59_37 | SmartOpt Trimming
][const_60_38 | SmartOpt Trimming
][const_62_39 | SmartOpt Trimming
][const_63_40 | SmartOpt Trimming
][const_65_41 | SmartOpt Trimming
][const_66_42 | SmartOpt Trimming
][const_68_43 | SmartOpt Trimming
][const_69_44 | SmartOpt Trimming
][const_71_45 | SmartOpt Trimming
][const_72_46 | SmartOpt Trimming
][const_74_47 | SmartOpt Trimming
][const_75_48 | SmartOpt Trimming
][const_77_49 | SmartOpt Trimming
][const_78_50 | SmartOpt Trimming
][const_80_51 | SmartOpt Trimming
][const_81_52 | SmartOpt Trimming
][const_83_53 | SmartOpt Trimming
][const_84_54 | SmartOpt Trimming
][const_86_55 | SmartOpt Trimming
][const_87_56 | SmartOpt Trimming
][const_89_57 | SmartOpt Trimming
][const_90_58 | SmartOpt Trimming
][const_92_59 | SmartOpt Trimming
][const_93_60 | SmartOpt Trimming
][const_95_61 | SmartOpt Trimming
][const_96_62 | SmartOpt Trimming
][const_98_63 | SmartOpt Trimming
][const_99_64 | SmartOpt Trimming
Flops added for Enable Generation

318
fpga/WarpLC_map.xrpt
View File

@ -1,18 +1,18 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt64" product="ISE" version="14.7">
<document OS="nt" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Sun Oct 31 15:38:26 2021">
<application stringID="Map" timeStamp="Mon Nov 01 06:10:39 2021">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\PuTTY\;C:\Program Files (x86)\WinMerge;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\Microchip\xc8\v2.31\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\Dog\AppData\Local\GitHubDesktop\bin"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files\Microchip\xc8\v2.31\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\PuTTY\;C:\Program Files\WinMerge;C:\Program Files\dotnet\;C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;C:\Users\zanek\AppData\Local\GitHubDesktop\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\zanek\.dotnet\tools;C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
@ -36,16 +36,16 @@
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
<item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
<item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
</item>
<item stringID="User_EnvHost" value="Dog-PC"/>
<item stringID="User_EnvHost" value="ZanePC"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Xeon(R) CPU W3680 @ 3.33GHz"/>
<item stringID="speed" value="3316 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz"/>
<item stringID="speed" value="3500 MHz"/>
</row>
</table>
</section>
@ -76,16 +76,16 @@
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="33">
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="89">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="1"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="8"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="0"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="7"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="1"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="4"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="20"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="80"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
@ -99,7 +99,7 @@
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="66"/>
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="34"/>
<item AVAILABLE="14" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="5"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
@ -121,10 +121,10 @@
<section stringID="MAP_DESIGN_SUMMARY">
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="1"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="377184"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="25 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="25 secs "/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="293380"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="10 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="8 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="1">
@ -133,16 +133,16 @@
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="33">
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="89">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="1"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="8"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="0"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="7"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="1"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="4"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="20"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="80"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
@ -156,19 +156,19 @@
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="9">
<item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="23">
<item AVAILABLE="355" dataType="int" stringID="MAP_NUM_SLICEL" value="2"/>
<item AVAILABLE="360" dataType="int" stringID="MAP_NUM_SLICEM" value="6"/>
<item AVAILABLE="360" dataType="int" stringID="MAP_NUM_SLICEM" value="20"/>
<item AVAILABLE="715" dataType="int" stringID="MAP_NUM_SLICEX" value="1"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="33">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="32"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="89">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="88"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="0"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="1"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="66"/>
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="34"/>
<item AVAILABLE="14" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="5"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
@ -184,7 +184,7 @@
<section stringID="MAP_HARD_IP_REPORTING"/>
<section stringID="MAP_RAM_FIFO_DATA">
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="1"/>
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
</section>
<section stringID="MAP_IP_DATA">
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
@ -427,262 +427,6 @@
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="33">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="34">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="35">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="36">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="37">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="38">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;5>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="39">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;6>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="40">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;7>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="41">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;8>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="42">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;9>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="43">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;10>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="44">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;11>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="45">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;12>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="46">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;13>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="47">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;14>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="48">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;15>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="49">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;16>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="50">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;17>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="51">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;18>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="52">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;19>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="53">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;20>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="54">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;21>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="55">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;22>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="56">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;23>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="57">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;24>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="58">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;25>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="59">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;26>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="60">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;27>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="61">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;28>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="62">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;29>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="63">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;30>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="64">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="FSB_D&lt;31>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="65">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RAMCLK0"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
@ -691,7 +435,7 @@
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/>
<item label="Reg&#xA;(s)" stringID="REGS" value="ODDR"/>
</row>
<row stringID="row" value="66">
<row stringID="row" value="34">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RAMCLK1"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
@ -751,7 +495,7 @@
</task>
<section stringID="MAP_RAM_FIFO_DATA">
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="1"/>
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
</section>
<section stringID="MAP_IP_DATA">
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>

45
fpga/WarpLC_ngdbuild.xrpt
View File

@ -1,18 +1,18 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt64" product="ISE" version="14.7">
<document OS="nt" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Sun Oct 31 15:37:59 2021">
<application stringID="NgdBuild" timeStamp="Mon Nov 01 06:10:26 2021">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\PuTTY\;C:\Program Files (x86)\WinMerge;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\Microchip\xc8\v2.31\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\Dog\AppData\Local\GitHubDesktop\bin"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files\Microchip\xc8\v2.31\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\PuTTY\;C:\Program Files\WinMerge;C:\Program Files\dotnet\;C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;C:\Users\zanek\AppData\Local\GitHubDesktop\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\zanek\.dotnet\tools;C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
@ -36,16 +36,16 @@
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
<item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
<item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
</item>
<item stringID="User_EnvHost" value="Dog-PC"/>
<item stringID="User_EnvHost" value="ZanePC"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Xeon(R) CPU W3680 @ 3.33GHz"/>
<item stringID="speed" value="3316 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz"/>
<item stringID="speed" value="3500 MHz"/>
</row>
</table>
</section>
@ -62,26 +62,26 @@
<section stringID="NGDBUILD_DESIGN_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="9"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="73"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFIO2FB" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="44"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="38"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_ODDR2" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32X1D" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAMB8BWER" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM128X1D" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
@ -89,18 +89,17 @@
<item dataType="int" stringID="NGDBUILD_NUM_BUFIO2FB" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="44"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="38"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_ODDR2" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_PLL_ADV" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAMB8BWER" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
</section>
<section stringID="NGDBUILD_CORE_SUMMARY">
@ -111,13 +110,9 @@
<item stringID="NGDBUILD_CORE_INFO" type="clk_wiz_v3_6" value="PLL"/>
<item clkin1_period="30.000" clkin2_period="30.000" clock_mgr_type="MANUAL" component_name="PLL" feedback_source="FDBK_AUTO_OFFCHIP" feedback_type="SINGLE" manual_override="false" num_out_clk="1" primtype_sel="PLL_BASE" stringID="NGDBUILD_CORE_PARAMETERS" use_clk_valid="false" use_dyn_phase_shift="false" use_dyn_reconfig="false" use_freeze="false" use_inclk_stopped="false" use_inclk_switchover="false" use_locked="true" use_max_i_jitter="false" use_min_o_jitter="true" use_phase_alignment="true" use_power_down="false" use_reset="false" use_status="false" value="PLL"/>
</scope>
<scope stringID="NGDBUILD_CORE_INSTANCE" value="PrefetchDataRAM">
<item stringID="NGDBUILD_CORE_INFO" type="blk_mem_gen_v7_3" value="PrefetchDataRAM"/>
<item c_addra_width="7" c_addrb_width="7" c_algorithm="1" c_axi_id_width="4" c_axi_slave_type="0" c_axi_type="1" c_byte_size="8" c_common_clk="1" c_default_data="0" c_disable_warn_bhv_coll="0" c_disable_warn_bhv_range="0" c_elaboration_dir="masked_value" c_enable_32bit_address="0" c_family="spartan6" c_has_axi_id="0" c_has_ena="1" c_has_enb="1" c_has_injecterr="0" c_has_mem_output_regs_a="0" c_has_mem_output_regs_b="0" c_has_mux_output_regs_a="0" c_has_mux_output_regs_b="0" c_has_regcea="0" c_has_regceb="0" c_has_rsta="0" c_has_rstb="0" c_has_softecc_input_regs_a="0" c_has_softecc_output_regs_b="0" c_init_file="BlankString" c_init_file_name="no_coe_file_loaded" c_inita_val="0" c_initb_val="0" c_interface_type="0" c_load_init_file="0" c_mem_type="1" c_mux_pipeline_stages="0" c_prim_type="1" c_read_depth_a="128" c_read_depth_b="128" c_read_width_a="32" c_read_width_b="32" c_rst_priority_a="CE" c_rst_priority_b="CE" c_rst_type="SYNC" c_rstram_a="0" c_rstram_b="0" c_sim_collision_check="ALL" c_use_bram_block="0" c_use_byte_wea="1" c_use_byte_web="1" c_use_default_data="0" c_use_ecc="0" c_use_softecc="0" c_wea_width="4" c_web_width="4" c_write_depth_a="128" c_write_depth_b="128" c_write_mode_a="READ_FIRST" c_write_mode_b="READ_FIRST" c_write_width_a="32" c_write_width_b="32" c_xdevicefamily="spartan6" stringID="NGDBUILD_CORE_PARAMETERS" value="PrefetchDataRAM"/>
</scope>
<scope stringID="NGDBUILD_CORE_INSTANCE" value="PrefetchTagRAM">
<item stringID="NGDBUILD_CORE_INFO" type="dist_mem_gen_v7_2" value="PrefetchTagRAM"/>
<item c_addr_width="5" c_default_data="0" c_depth="32" c_elaboration_dir="masked_value" c_family="spartan6" c_has_clk="1" c_has_d="1" c_has_dpo="1" c_has_dpra="1" c_has_i_ce="0" c_has_qdpo="0" c_has_qdpo_ce="0" c_has_qdpo_clk="0" c_has_qdpo_rst="0" c_has_qdpo_srst="0" c_has_qspo="0" c_has_qspo_ce="0" c_has_qspo_rst="0" c_has_qspo_srst="0" c_has_spo="1" c_has_spra="0" c_has_we="1" c_mem_init_file="no_coe_file_loaded" c_mem_type="2" c_parser_type="1" c_pipeline_stages="0" c_qce_joined="0" c_qualify_we="0" c_read_mif="0" c_reg_a_d_inputs="0" c_reg_dpra_input="0" c_sync_enable="1" c_width="22" stringID="NGDBUILD_CORE_PARAMETERS" value="PrefetchTagRAM"/>
<item c_addr_width="7" c_default_data="0" c_depth="128" c_elaboration_dir="masked_value" c_family="spartan6" c_has_clk="1" c_has_d="1" c_has_dpo="1" c_has_dpra="1" c_has_i_ce="0" c_has_qdpo="0" c_has_qdpo_ce="0" c_has_qdpo_clk="0" c_has_qdpo_rst="0" c_has_qdpo_srst="0" c_has_qspo="0" c_has_qspo_ce="0" c_has_qspo_rst="0" c_has_qspo_srst="0" c_has_spo="1" c_has_spra="0" c_has_we="1" c_mem_init_file="no_coe_file_loaded" c_mem_type="2" c_parser_type="1" c_pipeline_stages="0" c_qce_joined="0" c_qualify_we="0" c_read_mif="0" c_reg_a_d_inputs="0" c_reg_dpra_input="0" c_sync_enable="1" c_width="22" stringID="NGDBUILD_CORE_PARAMETERS" value="PrefetchTagRAM"/>
</scope>
</section>
</section>

216
fpga/WarpLC_pad.csv
View File

@ -1,7 +1,7 @@
#Release 14.7 - par P.20131013 (nt64)
#Release 14.7 - par P.20131013 (nt)
#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
#Sun Oct 31 15:38:33 2021
#Mon Nov 01 06:10:44 2021
#
## NOTE: This file is designed to be imported into a spreadsheet program
@ -22,137 +22,137 @@ Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,D
A1,,,GND,,,,,,,,,,,,
A2,,IOBS,IO_L52N_M3A9_3,UNUSED,,3,,,,,,,,,
A3,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,,
A4,CLKFB_OUT,IOB,IO_L1N_VREF_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
A5,FSB_D<0>,IOB,IO_L2N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
A6,FSB_D<4>,IOB,IO_L4N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
A7,FSB_D<6>,IOB,IO_L6N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
A8,FSB_D<12>,IOB,IO_L33N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
A9,FSB_D<14>,IOB,IO_L34N_GCLK18_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
A10,FSB_D<16>,IOB,IO_L35N_GCLK16_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
A11,FSB_D<22>,IOB,IO_L39N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
A12,FSB_D<28>,IOB,IO_L62N_VREF_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
A13,FSB_D<30>,IOB,IO_L63N_SCP6_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
A14,RAMCLK0,IOB,IO_L65N_SCP2_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
A4,,IOBS,IO_L1N_VREF_0,UNUSED,,0,,,,,,,,,
A5,,IOBS,IO_L2N_0,UNUSED,,0,,,,,,,,,
A6,,IOBS,IO_L4N_0,UNUSED,,0,,,,,,,,,
A7,,IOBS,IO_L6N_0,UNUSED,,0,,,,,,,,,
A8,,IOBS,IO_L33N_0,UNUSED,,0,,,,,,,,,
A9,,IOBS,IO_L34N_GCLK18_0,UNUSED,,0,,,,,,,,,
A10,,IOBS,IO_L35N_GCLK16_0,UNUSED,,0,,,,,,,,,
A11,,IOBS,IO_L39N_0,UNUSED,,0,,,,,,,,,
A12,,IOBS,IO_L62N_VREF_0,UNUSED,,0,,,,,,,,,
A13,,IOBS,IO_L63N_SCP6_0,UNUSED,,0,,,,,,,,,
A14,,IOBS,IO_L65N_SCP2_0,UNUSED,,0,,,,,,,,,
A15,,,TMS,,,,,,,,,,,,
A16,,,GND,,,,,,,,,,,,
B1,,IOBS,IO_L50N_M3BA2_3,UNUSED,,3,,,,,,,,,
B2,,IOBM,IO_L52P_M3A8_3,UNUSED,,3,,,,,,,,,
B3,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,,
B4,,,VCCO_0,,,0,,,,,3.30,,,,
B5,CPUCLK,IOB,IO_L2P_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
B6,FSB_D<3>,IOB,IO_L4P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
B4,,,VCCO_0,,,0,,,,,any******,,,,
B5,,IOBM,IO_L2P_0,UNUSED,,0,,,,,,,,,
B6,,IOBM,IO_L4P_0,UNUSED,,0,,,,,,,,,
B7,,,GND,,,,,,,,,,,,
B8,FSB_D<11>,IOB,IO_L33P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
B9,,,VCCO_0,,,0,,,,,3.30,,,,
B10,FSB_D<15>,IOB,IO_L35P_GCLK17_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
B8,,IOBM,IO_L33P_0,UNUSED,,0,,,,,,,,,
B9,,,VCCO_0,,,0,,,,,any******,,,,
B10,,IOBM,IO_L35P_GCLK17_0,UNUSED,,0,,,,,,,,,
B11,,,GND,,,,,,,,,,,,
B12,FSB_D<27>,IOB,IO_L62P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
B13,,,VCCO_0,,,0,,,,,3.30,,,,
B14,FSB_A<2>,IOB,IO_L65P_SCP3_0,INPUT,LVCMOS33,0,,,,NONE,,UNLOCATED,NO,NONE,
B15,FSB_A<6>,IOB,IO_L29P_A23_M1A13_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
B16,FSB_A<7>,IOB,IO_L29N_A22_M1A14_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
B12,,IOBM,IO_L62P_0,UNUSED,,0,,,,,,,,,
B13,,,VCCO_0,,,0,,,,,any******,,,,
B14,,IOBM,IO_L65P_SCP3_0,UNUSED,,0,,,,,,,,,
B15,,IOBM,IO_L29P_A23_M1A13_1,UNUSED,,1,,,,,,,,,
B16,,IOBS,IO_L29N_A22_M1A14_1,UNUSED,,1,,,,,,,,,
C1,,IOBM,IO_L50P_M3WE_3,UNUSED,,3,,,,,,,,,
C2,,IOBS,IO_L48N_M3BA1_3,UNUSED,,3,,,,,,,,,
C3,,IOBM,IO_L48P_M3BA0_3,UNUSED,,3,,,,,,,,,
C4,RAMCLK1,IOB,IO_L1P_HSWAPEN_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
C5,FSB_D<2>,IOB,IO_L3N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
C6,FSB_D<10>,IOB,IO_L7N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
C7,FSB_D<7>,IOB,IO_L6P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
C8,FSB_D<24>,IOB,IO_L38N_VREF_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
C9,FSB_D<13>,IOB,IO_L34P_GCLK19_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
C10,FSB_D<20>,IOB,IO_L37N_GCLK12_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
C11,FSB_D<23>,IOB,IO_L39P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
C4,,IOBM,IO_L1P_HSWAPEN_0,UNUSED,,0,,,,,,,,,
C5,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,,
C6,,IOBS,IO_L7N_0,UNUSED,,0,,,,,,,,,
C7,,IOBM,IO_L6P_0,UNUSED,,0,,,,,,,,,
C8,,IOBS,IO_L38N_VREF_0,UNUSED,,0,,,,,,,,,
C9,,IOBM,IO_L34P_GCLK19_0,UNUSED,,0,,,,,,,,,
C10,,IOBS,IO_L37N_GCLK12_0,UNUSED,,0,,,,,,,,,
C11,,IOBM,IO_L39P_0,UNUSED,,0,,,,,,,,,
C12,,,TDI,,,,,,,,,,,,
C13,FSB_D<29>,IOB,IO_L63P_SCP7_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
C13,,IOBM,IO_L63P_SCP7_0,UNUSED,,0,,,,,,,,,
C14,,,TCK,,,,,,,,,,,,
C15,FSB_A<14>,IOB,IO_L33P_A15_M1A10_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
C16,FSB_A<20>,IOB,IO_L33N_A14_M1A4_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
C15,,IOBM,IO_L33P_A15_M1A10_1,UNUSED,,1,,,,,,,,,
C16,,IOBS,IO_L33N_A14_M1A4_1,UNUSED,,1,,,,,,,,,
D1,,IOBS,IO_L49N_M3A2_3,UNUSED,,3,,,,,,,,,
D2,,,VCCO_3,,,3,,,,,any******,,,,
D2,,,VCCO_3,,,3,,,,,3.30,,,,
D3,,IOBM,IO_L49P_M3A7_3,UNUSED,,3,,,,,,,,,
D4,,,GND,,,,,,,,,,,,
D5,FSB_D<1>,IOB,IO_L3P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
D6,FSB_D<9>,IOB,IO_L7P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
D7,,,VCCO_0,,,0,,,,,3.30,,,,
D8,FSB_D<21>,IOB,IO_L38P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
D9,FSB_D<26>,IOB,IO_L40N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
D10,,,VCCO_0,,,0,,,,,3.30,,,,
D11,FPUCLK,IOB,IO_L66P_SCP1_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
D12,CPU_nSTERM,IOB,IO_L66N_SCP0_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,NO,NONE,
D5,,IOBM,IO_L3P_0,UNUSED,,0,,,,,,,,,
D6,,IOBM,IO_L7P_0,UNUSED,,0,,,,,,,,,
D7,,,VCCO_0,,,0,,,,,any******,,,,
D8,,IOBM,IO_L38P_0,UNUSED,,0,,,,,,,,,
D9,,IOBS,IO_L40N_0,UNUSED,,0,,,,,,,,,
D10,,,VCCO_0,,,0,,,,,any******,,,,
D11,,IOBM,IO_L66P_SCP1_0,UNUSED,,0,,,,,,,,,
D12,,IOBS,IO_L66N_SCP0_0,UNUSED,,0,,,,,,,,,
D13,,,GND,,,,,,,,,,,,
D14,FSB_A<10>,IOB,IO_L31P_A19_M1CKE_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
D14,,IOBM,IO_L31P_A19_M1CKE_1,UNUSED,,1,,,,,,,,,
D15,,,VCCO_1,,,1,,,,,any******,,,,
D16,FSB_A<11>,IOB,IO_L31N_A18_M1A12_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
E1,,IOBS,IO_L46N_M3CLKN_3,UNUSED,,3,,,,,,,,,
E2,,IOBM,IO_L46P_M3CLK_3,UNUSED,,3,,,,,,,,,
D16,,IOBS,IO_L31N_A18_M1A12_1,UNUSED,,1,,,,,,,,,
E1,FPUCLK,IOB,IO_L46N_M3CLKN_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
E2,CPUCLK,IOB,IO_L46P_M3CLK_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
E3,,IOBS,IO_L54N_M3A11_3,UNUSED,,3,,,,,,,,,
E4,,IOBM,IO_L54P_M3RESET_3,UNUSED,,3,,,,,,,,,
E5,,,VCCAUX,,,,,,,,2.5,,,,
E6,FSB_D<8>,IOB,IO_L5N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
E7,FSB_D<17>,IOB,IO_L36P_GCLK15_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
E8,FSB_D<18>,IOB,IO_L36N_GCLK14_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
E6,,IOBS,IO_L5N_0,UNUSED,,0,,,,,,,,,
E7,,IOBM,IO_L36P_GCLK15_0,UNUSED,,0,,,,,,,,,
E8,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,,
E9,,,GND,,,,,,,,,,,,
E10,FSB_D<19>,IOB,IO_L37P_GCLK13_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
E11,FSB_A<3>,IOB,IO_L64N_SCP4_0,INPUT,LVCMOS33,0,,,,NONE,,UNLOCATED,NO,NONE,
E12,FSB_A<5>,IOB,IO_L1N_A24_VREF_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
E13,FSB_A<4>,IOB,IO_L1P_A25_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
E10,,IOBM,IO_L37P_GCLK13_0,UNUSED,,0,,,,,,,,,
E11,,IOBS,IO_L64N_SCP4_0,UNUSED,,0,,,,,,,,,
E12,,IOBS,IO_L1N_A24_VREF_1,UNUSED,,1,,,,,,,,,
E13,,IOBM,IO_L1P_A25_1,UNUSED,,1,,,,,,,,,
E14,,,TDO,,,,,,,,,,,,
E15,FSB_A<21>,IOB,IO_L34P_A13_M1WE_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
E16,FSB_A<22>,IOB,IO_L34N_A12_M1BA2_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
F1,,IOBS,IO_L41N_GCLK26_M3DQ5_3,UNUSED,,3,,,,,,,,,
F2,,IOBM,IO_L41P_GCLK27_M3DQ4_3,UNUSED,,3,,,,,,,,,
E15,,IOBM,IO_L34P_A13_M1WE_1,UNUSED,,1,,,,,,,,,
E16,,IOBS,IO_L34N_A12_M1BA2_1,UNUSED,,1,,,,,,,,,
F1,FSB_A<25>,IOB,IO_L41N_GCLK26_M3DQ5_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
F2,FSB_A<24>,IOB,IO_L41P_GCLK27_M3DQ4_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
F3,,IOBS,IO_L53N_M3A12_3,UNUSED,,3,,,,,,,,,
F4,,IOBM,IO_L53P_M3CKE_3,UNUSED,,3,,,,,,,,,
F5,,IOBS,IO_L55N_M3A14_3,UNUSED,,3,,,,,,,,,
F6,,IOBM,IO_L55P_M3A13_3,UNUSED,,3,,,,,,,,,
F7,FSB_D<5>,IOB,IO_L5P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
F7,,IOBM,IO_L5P_0,UNUSED,,0,,,,,,,,,
F8,,,VCCAUX,,,,,,,,2.5,,,,
F9,FSB_D<25>,IOB,IO_L40P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
F10,FSB_D<31>,IOB,IO_L64P_SCP5_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
F9,,IOBM,IO_L40P_0,UNUSED,,0,,,,,,,,,
F10,,IOBM,IO_L64P_SCP5_0,UNUSED,,0,,,,,,,,,
F11,,,VCCAUX,,,,,,,,2.5,,,,
F12,FSB_A<8>,IOB,IO_L30P_A21_M1RESET_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
F13,FSB_A<12>,IOB,IO_L32P_A17_M1A8_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
F14,FSB_A<13>,IOB,IO_L32N_A16_M1A9_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
F15,FSB_A<23>,IOB,IO_L35P_A11_M1A7_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
F16,FSB_A<19>,IOB,IO_L35N_A10_M1A2_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
G1,,IOBS,IO_L40N_M3DQ7_3,UNUSED,,3,,,,,,,,,
F12,,IOBM,IO_L30P_A21_M1RESET_1,UNUSED,,1,,,,,,,,,
F13,,IOBM,IO_L32P_A17_M1A8_1,UNUSED,,1,,,,,,,,,
F14,,IOBS,IO_L32N_A16_M1A9_1,UNUSED,,1,,,,,,,,,
F15,,IOBM,IO_L35P_A11_M1A7_1,UNUSED,,1,,,,,,,,,
F16,,IOBS,IO_L35N_A10_M1A2_1,UNUSED,,1,,,,,,,,,
G1,FSB_A<23>,IOB,IO_L40N_M3DQ7_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
G2,,,GND,,,,,,,,,,,,
G3,,IOBM,IO_L40P_M3DQ6_3,UNUSED,,3,,,,,,,,,
G4,,,VCCO_3,,,3,,,,,any******,,,,
G3,FSB_A<22>,IOB,IO_L40P_M3DQ6_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
G4,,,VCCO_3,,,3,,,,,3.30,,,,
G5,,IOBS,IO_L51N_M3A4_3,UNUSED,,3,,,,,,,,,
G6,,IOBM,IO_L51P_M3A10_3,UNUSED,,3,,,,,,,,,
G7,,,VCCINT,,,,,,,,1.2,,,,
G8,,,GND,,,,,,,,,,,,
G9,,,VCCINT,,,,,,,,1.2,,,,
G10,,,VCCAUX,,,,,,,,2.5,,,,
G11,FSB_A<9>,IOB,IO_L30N_A20_M1A11_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
G12,FSB_A<24>,IOB,IO_L38P_A5_M1CLK_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
G11,,IOBS,IO_L30N_A20_M1A11_1,UNUSED,,1,,,,,,,,,
G12,,IOBM,IO_L38P_A5_M1CLK_1,UNUSED,,1,,,,,,,,,
G13,,,VCCO_1,,,1,,,,,any******,,,,
G14,FSB_A<15>,IOB,IO_L36P_A9_M1BA0_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
G14,,IOBM,IO_L36P_A9_M1BA0_1,UNUSED,,1,,,,,,,,,
G15,,,GND,,,,,,,,,,,,
G16,FSB_A<16>,IOB,IO_L36N_A8_M1BA1_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
H1,,IOBS,IO_L39N_M3LDQSN_3,UNUSED,,3,,,,,,,,,
H2,,IOBM,IO_L39P_M3LDQS_3,UNUSED,,3,,,,,,,,,
H3,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,,
G16,,IOBS,IO_L36N_A8_M1BA1_1,UNUSED,,1,,,,,,,,,
H1,FSB_A<21>,IOB,IO_L39N_M3LDQSN_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
H2,FSB_A<20>,IOB,IO_L39P_M3LDQS_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
H3,RAMCLK0,IOB,IO_L44N_GCLK20_M3A6_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
H4,CLKFB_IN,IOB,IO_L44P_GCLK21_M3A5_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
H5,,IOBS,IO_L43N_GCLK22_IRDY2_M3CASN_3,UNUSED,,3,,,,,,,,,
H5,CPU_nSTERM,IOB,IO_L43N_GCLK22_IRDY2_M3CASN_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,NO,NONE,
H6,,,VCCAUX,,,,,,,,2.5,,,,
H7,,,GND,,,,,,,,,,,,
H8,,,VCCINT,,,,,,,,1.2,,,,
H9,,,GND,,,,,,,,,,,,
H10,,,VCCINT,,,,,,,,1.2,,,,
H11,FSB_A<25>,IOB,IO_L38N_A4_M1CLKN_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
H11,,IOBS,IO_L38N_A4_M1CLKN_1,UNUSED,,1,,,,,,,,,
H12,,,GND,,,,,,,,,,,,
H13,FSB_A<26>,IOB,IO_L39P_M1A3_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
H14,FSB_A<27>,IOB,IO_L39N_M1ODT_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
H15,FSB_A<17>,IOB,IO_L37P_A7_M1A0_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
H16,FSB_A<18>,IOB,IO_L37N_A6_M1A1_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
J1,,IOBS,IO_L38N_M3DQ3_3,UNUSED,,3,,,,,,,,,
J2,,,VCCO_3,,,3,,,,,any******,,,,
J3,,IOBM,IO_L38P_M3DQ2_3,UNUSED,,3,,,,,,,,,
H13,,IOBM,IO_L39P_M1A3_1,UNUSED,,1,,,,,,,,,
H14,,IOBS,IO_L39N_M1ODT_1,UNUSED,,1,,,,,,,,,
H15,,IOBM,IO_L37P_A7_M1A0_1,UNUSED,,1,,,,,,,,,
H16,,IOBS,IO_L37N_A6_M1A1_1,UNUSED,,1,,,,,,,,,
J1,FSB_A<19>,IOB,IO_L38N_M3DQ3_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
J2,,,VCCO_3,,,3,,,,,3.30,,,,
J3,FSB_A<18>,IOB,IO_L38P_M3DQ2_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
J4,CLKIN,IOB,IO_L42N_GCLK24_M3LDM_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
J5,,,GND,,,,,,,,,,,,
J6,,IOBM,IO_L43P_GCLK23_M3RASN_3,UNUSED,,3,,,,,,,,,
J6,FSB_A<27>,IOB,IO_L43P_GCLK23_M3RASN_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
J7,,,VCCINT,,,,,,,,1.2,,,,
J8,,,GND,,,,,,,,,,,,
J9,,,VCCINT,,,,,,,,1.2,,,,
@ -163,10 +163,10 @@ J13,,IOBM,IO_L41P_GCLK9_IRDY1_M1RASN_1,UNUSED,,1,,,,,,,,,
J14,,IOBM,IO_L43P_GCLK5_M1DQ4_1,UNUSED,,1,,,,,,,,,
J15,,,VCCO_1,,,1,,,,,any******,,,,
J16,,IOBS,IO_L43N_GCLK4_M1DQ5_1,UNUSED,,1,,,,,,,,,
K1,,IOBS,IO_L37N_M3DQ1_3,UNUSED,,3,,,,,,,,,
K2,,IOBM,IO_L37P_M3DQ0_3,UNUSED,,3,,,,,,,,,
K3,,IOBM,IO_L42P_GCLK25_TRDY2_M3UDM_3,UNUSED,,3,,,,,,,,,
K4,,,VCCO_3,,,3,,,,,any******,,,,
K1,FSB_A<17>,IOB,IO_L37N_M3DQ1_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
K2,FSB_A<16>,IOB,IO_L37P_M3DQ0_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
K3,FSB_A<26>,IOB,IO_L42P_GCLK25_TRDY2_M3UDM_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
K4,,,VCCO_3,,,3,,,,,3.30,,,,
K5,,IOBM,IO_L47P_M3A0_3,UNUSED,,3,,,,,,,,,
K6,,IOBS,IO_L47N_M3A1_3,UNUSED,,3,,,,,,,,,
K7,,,GND,,,,,,,,,,,,
@ -179,11 +179,11 @@ K13,,,VCCO_1,,,1,,,,,any******,,,,
K14,,IOBS,IO_L41N_GCLK8_M1CASN_1,UNUSED,,1,,,,,,,,,
K15,,IOBM,IO_L44P_A3_M1DQ6_1,UNUSED,,1,,,,,,,,,
K16,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,,
L1,,IOBS,IO_L36N_M3DQ9_3,UNUSED,,3,,,,,,,,,
L1,FSB_A<15>,IOB,IO_L36N_M3DQ9_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
L2,,,GND,,,,,,,,,,,,
L3,,IOBM,IO_L36P_M3DQ8_3,UNUSED,,3,,,,,,,,,
L4,,IOBM,IO_L45P_M3A3_3,UNUSED,,3,,,,,,,,,
L5,,IOBS,IO_L45N_M3ODT_3,UNUSED,,3,,,,,,,,,
L3,FSB_A<14>,IOB,IO_L36P_M3DQ8_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
L4,CLKFB_OUT,IOB,IO_L45P_M3A3_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
L5,RAMCLK1,IOB,IO_L45N_M3ODT_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
L6,,,VCCAUX,,,,,,,,2.5,,,,
L7,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,,
L8,,IOBM,IO_L62P_D5_2,UNUSED,,2,,,,,,,,,
@ -195,11 +195,11 @@ L13,,IOBS,IO_L53N_VREF_1,UNUSED,,1,,,,,,,,,
L14,,IOBM,IO_L47P_FWE_B_M1DQ0_1,UNUSED,,1,,,,,,,,,
L15,,,GND,,,,,,,,,,,,
L16,,IOBS,IO_L47N_LDC_M1DQ1_1,UNUSED,,1,,,,,,,,,
M1,,IOBS,IO_L35N_M3DQ11_3,UNUSED,,3,,,,,,,,,
M2,,IOBM,IO_L35P_M3DQ10_3,UNUSED,,3,,,,,,,,,
M3,,IOBS,IO_L1N_VREF_3,UNUSED,,3,,,,,,,,,
M4,,IOBM,IO_L1P_3,UNUSED,,3,,,,,,,,,
M5,,IOBM,IO_L2P_3,UNUSED,,3,,,,,,,,,
M1,FSB_A<13>,IOB,IO_L35N_M3DQ11_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
M2,FSB_A<12>,IOB,IO_L35P_M3DQ10_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
M3,FSB_A<3>,IOB,IO_L1N_VREF_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
M4,FSB_A<2>,IOB,IO_L1P_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
M5,FSB_A<4>,IOB,IO_L2P_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
M6,,IOBM,IO_L64P_D8_2,UNUSED,,2,,,,,,,,,
M7,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,,
M8,,,GND,,,,,,,,,,,,
@ -211,10 +211,10 @@ M13,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,,
M14,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,,
M15,,IOBM,IO_L46P_FCS_B_M1DQ2_1,UNUSED,,1,,,,,,,,,
M16,,IOBS,IO_L46N_FOE_B_M1DQ3_1,UNUSED,,1,,,,,,,,,
N1,,IOBS,IO_L34N_M3UDQSN_3,UNUSED,,3,,,,,,,,,
N2,,,VCCO_3,,,3,,,,,any******,,,,
N3,,IOBM,IO_L34P_M3UDQS_3,UNUSED,,3,,,,,,,,,
N4,,IOBS,IO_L2N_3,UNUSED,,3,,,,,,,,,
N1,FSB_A<11>,IOB,IO_L34N_M3UDQSN_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
N2,,,VCCO_3,,,3,,,,,3.30,,,,
N3,FSB_A<10>,IOB,IO_L34P_M3UDQS_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
N4,FSB_A<5>,IOB,IO_L2N_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
N5,,IOBM,IO_L49P_D3_2,UNUSED,,2,,,,,,,,,
N6,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,,
N7,,,VCCO_2,,,2,,,,,any******,,,,
@ -227,8 +227,8 @@ N13,,,GND,,,,,,,,,,,,
N14,,IOBM,IO_L45P_A1_M1LDQS_1,UNUSED,,1,,,,,,,,,
N15,,,VCCO_1,,,1,,,,,any******,,,,
N16,,IOBS,IO_L45N_A0_M1LDQSN_1,UNUSED,,1,,,,,,,,,
P1,,IOBS,IO_L33N_M3DQ13_3,UNUSED,,3,,,,,,,,,
P2,,IOBM,IO_L33P_M3DQ12_3,UNUSED,,3,,,,,,,,,
P1,FSB_A<9>,IOB,IO_L33N_M3DQ13_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
P2,FSB_A<8>,IOB,IO_L33P_M3DQ12_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
P3,,,GND,,,,,,,,,,,,
P4,,IOBM,IO_L63P_2,UNUSED,,2,,,,,,,,,
P5,,IOBS,IO_L49N_D4_2,UNUSED,,2,,,,,,,,,
@ -243,8 +243,8 @@ P13,,,DONE_2,,,,,,,,,,,,
P14,,,SUSPEND,,,,,,,,,,,,
P15,,IOBM,IO_L48P_HDC_M1DQ8_1,UNUSED,,1,,,,,,,,,
P16,,IOBS,IO_L48N_M1DQ9_1,UNUSED,,1,,,,,,,,,
R1,,IOBS,IO_L32N_M3DQ15_3,UNUSED,,3,,,,,,,,,
R2,,IOBM,IO_L32P_M3DQ14_3,UNUSED,,3,,,,,,,,,
R1,FSB_A<7>,IOB,IO_L32N_M3DQ15_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
R2,FSB_A<6>,IOB,IO_L32P_M3DQ14_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
R3,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,,
R4,,,VCCO_2,,,2,,,,,any******,,,,
R5,,IOBM,IO_L48P_D7_2,UNUSED,,2,,,,,,,,,

1 #Release 14.7 - par P.20131013 (nt64) #Release 14.7 - par P.20131013 (nt)
2 #Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3 #Sun Oct 31 15:38:33 2021 #Mon Nov 01 06:10:44 2021
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
22 A3,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,,
23 A4,CLKFB_OUT,IOB,IO_L1N_VREF_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE, A4,,IOBS,IO_L1N_VREF_0,UNUSED,,0,,,,,,,,,
24 A5,FSB_D<0>,IOB,IO_L2N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, A5,,IOBS,IO_L2N_0,UNUSED,,0,,,,,,,,,
25 A6,FSB_D<4>,IOB,IO_L4N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, A6,,IOBS,IO_L4N_0,UNUSED,,0,,,,,,,,,
26 A7,FSB_D<6>,IOB,IO_L6N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, A7,,IOBS,IO_L6N_0,UNUSED,,0,,,,,,,,,
27 A8,FSB_D<12>,IOB,IO_L33N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, A8,,IOBS,IO_L33N_0,UNUSED,,0,,,,,,,,,
28 A9,FSB_D<14>,IOB,IO_L34N_GCLK18_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, A9,,IOBS,IO_L34N_GCLK18_0,UNUSED,,0,,,,,,,,,
29 A10,FSB_D<16>,IOB,IO_L35N_GCLK16_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, A10,,IOBS,IO_L35N_GCLK16_0,UNUSED,,0,,,,,,,,,
30 A11,FSB_D<22>,IOB,IO_L39N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, A11,,IOBS,IO_L39N_0,UNUSED,,0,,,,,,,,,
31 A12,FSB_D<28>,IOB,IO_L62N_VREF_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, A12,,IOBS,IO_L62N_VREF_0,UNUSED,,0,,,,,,,,,
32 A13,FSB_D<30>,IOB,IO_L63N_SCP6_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, A13,,IOBS,IO_L63N_SCP6_0,UNUSED,,0,,,,,,,,,
33 A14,RAMCLK0,IOB,IO_L65N_SCP2_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE, A14,,IOBS,IO_L65N_SCP2_0,UNUSED,,0,,,,,,,,,
34 A15,,,TMS,,,,,,,,,,,,
35 A16,,,GND,,,,,,,,,,,,
36 B1,,IOBS,IO_L50N_M3BA2_3,UNUSED,,3,,,,,,,,,
37 B2,,IOBM,IO_L52P_M3A8_3,UNUSED,,3,,,,,,,,,
38 B3,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,,
39 B4,,,VCCO_0,,,0,,,,,3.30,,,, B4,,,VCCO_0,,,0,,,,,any******,,,,
40 B5,CPUCLK,IOB,IO_L2P_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE, B5,,IOBM,IO_L2P_0,UNUSED,,0,,,,,,,,,
41 B6,FSB_D<3>,IOB,IO_L4P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, B6,,IOBM,IO_L4P_0,UNUSED,,0,,,,,,,,,
42 B7,,,GND,,,,,,,,,,,,
43 B8,FSB_D<11>,IOB,IO_L33P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, B8,,IOBM,IO_L33P_0,UNUSED,,0,,,,,,,,,
44 B9,,,VCCO_0,,,0,,,,,3.30,,,, B9,,,VCCO_0,,,0,,,,,any******,,,,
45 B10,FSB_D<15>,IOB,IO_L35P_GCLK17_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, B10,,IOBM,IO_L35P_GCLK17_0,UNUSED,,0,,,,,,,,,
46 B11,,,GND,,,,,,,,,,,,
47 B12,FSB_D<27>,IOB,IO_L62P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, B12,,IOBM,IO_L62P_0,UNUSED,,0,,,,,,,,,
48 B13,,,VCCO_0,,,0,,,,,3.30,,,, B13,,,VCCO_0,,,0,,,,,any******,,,,
49 B14,FSB_A<2>,IOB,IO_L65P_SCP3_0,INPUT,LVCMOS33,0,,,,NONE,,UNLOCATED,NO,NONE, B14,,IOBM,IO_L65P_SCP3_0,UNUSED,,0,,,,,,,,,
50 B15,FSB_A<6>,IOB,IO_L29P_A23_M1A13_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, B15,,IOBM,IO_L29P_A23_M1A13_1,UNUSED,,1,,,,,,,,,
51 B16,FSB_A<7>,IOB,IO_L29N_A22_M1A14_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, B16,,IOBS,IO_L29N_A22_M1A14_1,UNUSED,,1,,,,,,,,,
52 C1,,IOBM,IO_L50P_M3WE_3,UNUSED,,3,,,,,,,,,
53 C2,,IOBS,IO_L48N_M3BA1_3,UNUSED,,3,,,,,,,,,
54 C3,,IOBM,IO_L48P_M3BA0_3,UNUSED,,3,,,,,,,,,
55 C4,RAMCLK1,IOB,IO_L1P_HSWAPEN_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE, C4,,IOBM,IO_L1P_HSWAPEN_0,UNUSED,,0,,,,,,,,,
56 C5,FSB_D<2>,IOB,IO_L3N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, C5,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,,
57 C6,FSB_D<10>,IOB,IO_L7N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, C6,,IOBS,IO_L7N_0,UNUSED,,0,,,,,,,,,
58 C7,FSB_D<7>,IOB,IO_L6P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, C7,,IOBM,IO_L6P_0,UNUSED,,0,,,,,,,,,
59 C8,FSB_D<24>,IOB,IO_L38N_VREF_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, C8,,IOBS,IO_L38N_VREF_0,UNUSED,,0,,,,,,,,,
60 C9,FSB_D<13>,IOB,IO_L34P_GCLK19_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, C9,,IOBM,IO_L34P_GCLK19_0,UNUSED,,0,,,,,,,,,
61 C10,FSB_D<20>,IOB,IO_L37N_GCLK12_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, C10,,IOBS,IO_L37N_GCLK12_0,UNUSED,,0,,,,,,,,,
62 C11,FSB_D<23>,IOB,IO_L39P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, C11,,IOBM,IO_L39P_0,UNUSED,,0,,,,,,,,,
63 C12,,,TDI,,,,,,,,,,,,
64 C13,FSB_D<29>,IOB,IO_L63P_SCP7_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, C13,,IOBM,IO_L63P_SCP7_0,UNUSED,,0,,,,,,,,,
65 C14,,,TCK,,,,,,,,,,,,
66 C15,FSB_A<14>,IOB,IO_L33P_A15_M1A10_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, C15,,IOBM,IO_L33P_A15_M1A10_1,UNUSED,,1,,,,,,,,,
67 C16,FSB_A<20>,IOB,IO_L33N_A14_M1A4_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, C16,,IOBS,IO_L33N_A14_M1A4_1,UNUSED,,1,,,,,,,,,
68 D1,,IOBS,IO_L49N_M3A2_3,UNUSED,,3,,,,,,,,,
69 D2,,,VCCO_3,,,3,,,,,any******,,,, D2,,,VCCO_3,,,3,,,,,3.30,,,,
70 D3,,IOBM,IO_L49P_M3A7_3,UNUSED,,3,,,,,,,,,
71 D4,,,GND,,,,,,,,,,,,
72 D5,FSB_D<1>,IOB,IO_L3P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, D5,,IOBM,IO_L3P_0,UNUSED,,0,,,,,,,,,
73 D6,FSB_D<9>,IOB,IO_L7P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, D6,,IOBM,IO_L7P_0,UNUSED,,0,,,,,,,,,
74 D7,,,VCCO_0,,,0,,,,,3.30,,,, D7,,,VCCO_0,,,0,,,,,any******,,,,
75 D8,FSB_D<21>,IOB,IO_L38P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, D8,,IOBM,IO_L38P_0,UNUSED,,0,,,,,,,,,
76 D9,FSB_D<26>,IOB,IO_L40N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, D9,,IOBS,IO_L40N_0,UNUSED,,0,,,,,,,,,
77 D10,,,VCCO_0,,,0,,,,,3.30,,,, D10,,,VCCO_0,,,0,,,,,any******,,,,
78 D11,FPUCLK,IOB,IO_L66P_SCP1_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE, D11,,IOBM,IO_L66P_SCP1_0,UNUSED,,0,,,,,,,,,
79 D12,CPU_nSTERM,IOB,IO_L66N_SCP0_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,NO,NONE, D12,,IOBS,IO_L66N_SCP0_0,UNUSED,,0,,,,,,,,,
80 D13,,,GND,,,,,,,,,,,,
81 D14,FSB_A<10>,IOB,IO_L31P_A19_M1CKE_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, D14,,IOBM,IO_L31P_A19_M1CKE_1,UNUSED,,1,,,,,,,,,
82 D15,,,VCCO_1,,,1,,,,,any******,,,,
83 D16,FSB_A<11>,IOB,IO_L31N_A18_M1A12_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, D16,,IOBS,IO_L31N_A18_M1A12_1,UNUSED,,1,,,,,,,,,
84 E1,,IOBS,IO_L46N_M3CLKN_3,UNUSED,,3,,,,,,,,, E1,FPUCLK,IOB,IO_L46N_M3CLKN_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
85 E2,,IOBM,IO_L46P_M3CLK_3,UNUSED,,3,,,,,,,,, E2,CPUCLK,IOB,IO_L46P_M3CLK_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
86 E3,,IOBS,IO_L54N_M3A11_3,UNUSED,,3,,,,,,,,,
87 E4,,IOBM,IO_L54P_M3RESET_3,UNUSED,,3,,,,,,,,,
88 E5,,,VCCAUX,,,,,,,,2.5,,,,
89 E6,FSB_D<8>,IOB,IO_L5N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, E6,,IOBS,IO_L5N_0,UNUSED,,0,,,,,,,,,
90 E7,FSB_D<17>,IOB,IO_L36P_GCLK15_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, E7,,IOBM,IO_L36P_GCLK15_0,UNUSED,,0,,,,,,,,,
91 E8,FSB_D<18>,IOB,IO_L36N_GCLK14_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, E8,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,,
92 E9,,,GND,,,,,,,,,,,,
93 E10,FSB_D<19>,IOB,IO_L37P_GCLK13_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, E10,,IOBM,IO_L37P_GCLK13_0,UNUSED,,0,,,,,,,,,
94 E11,FSB_A<3>,IOB,IO_L64N_SCP4_0,INPUT,LVCMOS33,0,,,,NONE,,UNLOCATED,NO,NONE, E11,,IOBS,IO_L64N_SCP4_0,UNUSED,,0,,,,,,,,,
95 E12,FSB_A<5>,IOB,IO_L1N_A24_VREF_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, E12,,IOBS,IO_L1N_A24_VREF_1,UNUSED,,1,,,,,,,,,
96 E13,FSB_A<4>,IOB,IO_L1P_A25_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, E13,,IOBM,IO_L1P_A25_1,UNUSED,,1,,,,,,,,,
97 E14,,,TDO,,,,,,,,,,,,
98 E15,FSB_A<21>,IOB,IO_L34P_A13_M1WE_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, E15,,IOBM,IO_L34P_A13_M1WE_1,UNUSED,,1,,,,,,,,,
99 E16,FSB_A<22>,IOB,IO_L34N_A12_M1BA2_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, E16,,IOBS,IO_L34N_A12_M1BA2_1,UNUSED,,1,,,,,,,,,
100 F1,,IOBS,IO_L41N_GCLK26_M3DQ5_3,UNUSED,,3,,,,,,,,, F1,FSB_A<25>,IOB,IO_L41N_GCLK26_M3DQ5_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
101 F2,,IOBM,IO_L41P_GCLK27_M3DQ4_3,UNUSED,,3,,,,,,,,, F2,FSB_A<24>,IOB,IO_L41P_GCLK27_M3DQ4_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
102 F3,,IOBS,IO_L53N_M3A12_3,UNUSED,,3,,,,,,,,,
103 F4,,IOBM,IO_L53P_M3CKE_3,UNUSED,,3,,,,,,,,,
104 F5,,IOBS,IO_L55N_M3A14_3,UNUSED,,3,,,,,,,,,
105 F6,,IOBM,IO_L55P_M3A13_3,UNUSED,,3,,,,,,,,,
106 F7,FSB_D<5>,IOB,IO_L5P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, F7,,IOBM,IO_L5P_0,UNUSED,,0,,,,,,,,,
107 F8,,,VCCAUX,,,,,,,,2.5,,,,
108 F9,FSB_D<25>,IOB,IO_L40P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, F9,,IOBM,IO_L40P_0,UNUSED,,0,,,,,,,,,
109 F10,FSB_D<31>,IOB,IO_L64P_SCP5_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, F10,,IOBM,IO_L64P_SCP5_0,UNUSED,,0,,,,,,,,,
110 F11,,,VCCAUX,,,,,,,,2.5,,,,
111 F12,FSB_A<8>,IOB,IO_L30P_A21_M1RESET_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, F12,,IOBM,IO_L30P_A21_M1RESET_1,UNUSED,,1,,,,,,,,,
112 F13,FSB_A<12>,IOB,IO_L32P_A17_M1A8_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, F13,,IOBM,IO_L32P_A17_M1A8_1,UNUSED,,1,,,,,,,,,
113 F14,FSB_A<13>,IOB,IO_L32N_A16_M1A9_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, F14,,IOBS,IO_L32N_A16_M1A9_1,UNUSED,,1,,,,,,,,,
114 F15,FSB_A<23>,IOB,IO_L35P_A11_M1A7_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, F15,,IOBM,IO_L35P_A11_M1A7_1,UNUSED,,1,,,,,,,,,
115 F16,FSB_A<19>,IOB,IO_L35N_A10_M1A2_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, F16,,IOBS,IO_L35N_A10_M1A2_1,UNUSED,,1,,,,,,,,,
116 G1,,IOBS,IO_L40N_M3DQ7_3,UNUSED,,3,,,,,,,,, G1,FSB_A<23>,IOB,IO_L40N_M3DQ7_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
117 G2,,,GND,,,,,,,,,,,,
118 G3,,IOBM,IO_L40P_M3DQ6_3,UNUSED,,3,,,,,,,,, G3,FSB_A<22>,IOB,IO_L40P_M3DQ6_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
119 G4,,,VCCO_3,,,3,,,,,any******,,,, G4,,,VCCO_3,,,3,,,,,3.30,,,,
120 G5,,IOBS,IO_L51N_M3A4_3,UNUSED,,3,,,,,,,,,
121 G6,,IOBM,IO_L51P_M3A10_3,UNUSED,,3,,,,,,,,,
122 G7,,,VCCINT,,,,,,,,1.2,,,,
123 G8,,,GND,,,,,,,,,,,,
124 G9,,,VCCINT,,,,,,,,1.2,,,,
125 G10,,,VCCAUX,,,,,,,,2.5,,,,
126 G11,FSB_A<9>,IOB,IO_L30N_A20_M1A11_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, G11,,IOBS,IO_L30N_A20_M1A11_1,UNUSED,,1,,,,,,,,,
127 G12,FSB_A<24>,IOB,IO_L38P_A5_M1CLK_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, G12,,IOBM,IO_L38P_A5_M1CLK_1,UNUSED,,1,,,,,,,,,
128 G13,,,VCCO_1,,,1,,,,,any******,,,,
129 G14,FSB_A<15>,IOB,IO_L36P_A9_M1BA0_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, G14,,IOBM,IO_L36P_A9_M1BA0_1,UNUSED,,1,,,,,,,,,
130 G15,,,GND,,,,,,,,,,,,
131 G16,FSB_A<16>,IOB,IO_L36N_A8_M1BA1_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, G16,,IOBS,IO_L36N_A8_M1BA1_1,UNUSED,,1,,,,,,,,,
132 H1,,IOBS,IO_L39N_M3LDQSN_3,UNUSED,,3,,,,,,,,, H1,FSB_A<21>,IOB,IO_L39N_M3LDQSN_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
133 H2,,IOBM,IO_L39P_M3LDQS_3,UNUSED,,3,,,,,,,,, H2,FSB_A<20>,IOB,IO_L39P_M3LDQS_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
134 H3,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,, H3,RAMCLK0,IOB,IO_L44N_GCLK20_M3A6_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
135 H4,CLKFB_IN,IOB,IO_L44P_GCLK21_M3A5_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
136 H5,,IOBS,IO_L43N_GCLK22_IRDY2_M3CASN_3,UNUSED,,3,,,,,,,,, H5,CPU_nSTERM,IOB,IO_L43N_GCLK22_IRDY2_M3CASN_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,NO,NONE,
137 H6,,,VCCAUX,,,,,,,,2.5,,,,
138 H7,,,GND,,,,,,,,,,,,
139 H8,,,VCCINT,,,,,,,,1.2,,,,
140 H9,,,GND,,,,,,,,,,,,
141 H10,,,VCCINT,,,,,,,,1.2,,,,
142 H11,FSB_A<25>,IOB,IO_L38N_A4_M1CLKN_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, H11,,IOBS,IO_L38N_A4_M1CLKN_1,UNUSED,,1,,,,,,,,,
143 H12,,,GND,,,,,,,,,,,,
144 H13,FSB_A<26>,IOB,IO_L39P_M1A3_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, H13,,IOBM,IO_L39P_M1A3_1,UNUSED,,1,,,,,,,,,
145 H14,FSB_A<27>,IOB,IO_L39N_M1ODT_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, H14,,IOBS,IO_L39N_M1ODT_1,UNUSED,,1,,,,,,,,,
146 H15,FSB_A<17>,IOB,IO_L37P_A7_M1A0_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, H15,,IOBM,IO_L37P_A7_M1A0_1,UNUSED,,1,,,,,,,,,
147 H16,FSB_A<18>,IOB,IO_L37N_A6_M1A1_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, H16,,IOBS,IO_L37N_A6_M1A1_1,UNUSED,,1,,,,,,,,,
148 J1,,IOBS,IO_L38N_M3DQ3_3,UNUSED,,3,,,,,,,,, J1,FSB_A<19>,IOB,IO_L38N_M3DQ3_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
149 J2,,,VCCO_3,,,3,,,,,any******,,,, J2,,,VCCO_3,,,3,,,,,3.30,,,,
150 J3,,IOBM,IO_L38P_M3DQ2_3,UNUSED,,3,,,,,,,,, J3,FSB_A<18>,IOB,IO_L38P_M3DQ2_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
151 J4,CLKIN,IOB,IO_L42N_GCLK24_M3LDM_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
152 J5,,,GND,,,,,,,,,,,,
153 J6,,IOBM,IO_L43P_GCLK23_M3RASN_3,UNUSED,,3,,,,,,,,, J6,FSB_A<27>,IOB,IO_L43P_GCLK23_M3RASN_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
154 J7,,,VCCINT,,,,,,,,1.2,,,,
155 J8,,,GND,,,,,,,,,,,,
156 J9,,,VCCINT,,,,,,,,1.2,,,,
157 J10,,,VCCAUX,,,,,,,,2.5,,,,
158 J11,,IOBM,IO_L40P_GCLK11_M1A5_1,UNUSED,,1,,,,,,,,,
163 J16,,IOBS,IO_L43N_GCLK4_M1DQ5_1,UNUSED,,1,,,,,,,,,
164 K1,,IOBS,IO_L37N_M3DQ1_3,UNUSED,,3,,,,,,,,, K1,FSB_A<17>,IOB,IO_L37N_M3DQ1_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
165 K2,,IOBM,IO_L37P_M3DQ0_3,UNUSED,,3,,,,,,,,, K2,FSB_A<16>,IOB,IO_L37P_M3DQ0_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
166 K3,,IOBM,IO_L42P_GCLK25_TRDY2_M3UDM_3,UNUSED,,3,,,,,,,,, K3,FSB_A<26>,IOB,IO_L42P_GCLK25_TRDY2_M3UDM_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
167 K4,,,VCCO_3,,,3,,,,,any******,,,, K4,,,VCCO_3,,,3,,,,,3.30,,,,
168 K5,,IOBM,IO_L47P_M3A0_3,UNUSED,,3,,,,,,,,,
169 K6,,IOBS,IO_L47N_M3A1_3,UNUSED,,3,,,,,,,,,
170 K7,,,GND,,,,,,,,,,,,
171 K8,,,VCCINT,,,,,,,,1.2,,,,
172 K9,,,GND,,,,,,,,,,,,
179 K16,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,,
180 L1,,IOBS,IO_L36N_M3DQ9_3,UNUSED,,3,,,,,,,,, L1,FSB_A<15>,IOB,IO_L36N_M3DQ9_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
181 L2,,,GND,,,,,,,,,,,,
182 L3,,IOBM,IO_L36P_M3DQ8_3,UNUSED,,3,,,,,,,,, L3,FSB_A<14>,IOB,IO_L36P_M3DQ8_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
183 L4,,IOBM,IO_L45P_M3A3_3,UNUSED,,3,,,,,,,,, L4,CLKFB_OUT,IOB,IO_L45P_M3A3_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
184 L5,,IOBS,IO_L45N_M3ODT_3,UNUSED,,3,,,,,,,,, L5,RAMCLK1,IOB,IO_L45N_M3ODT_3,OUTPUT,LVCMOS33,3,24,FAST,,,,UNLOCATED,YES,NONE,
185 L6,,,VCCAUX,,,,,,,,2.5,,,,
186 L7,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,,
187 L8,,IOBM,IO_L62P_D5_2,UNUSED,,2,,,,,,,,,
188 L9,,,VCCAUX,,,,,,,,2.5,,,,
189 L10,,IOBM,IO_L16P_2,UNUSED,,2,,,,,,,,,
195 L16,,IOBS,IO_L47N_LDC_M1DQ1_1,UNUSED,,1,,,,,,,,,
196 M1,,IOBS,IO_L35N_M3DQ11_3,UNUSED,,3,,,,,,,,, M1,FSB_A<13>,IOB,IO_L35N_M3DQ11_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
197 M2,,IOBM,IO_L35P_M3DQ10_3,UNUSED,,3,,,,,,,,, M2,FSB_A<12>,IOB,IO_L35P_M3DQ10_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
198 M3,,IOBS,IO_L1N_VREF_3,UNUSED,,3,,,,,,,,, M3,FSB_A<3>,IOB,IO_L1N_VREF_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
199 M4,,IOBM,IO_L1P_3,UNUSED,,3,,,,,,,,, M4,FSB_A<2>,IOB,IO_L1P_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
200 M5,,IOBM,IO_L2P_3,UNUSED,,3,,,,,,,,, M5,FSB_A<4>,IOB,IO_L2P_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
201 M6,,IOBM,IO_L64P_D8_2,UNUSED,,2,,,,,,,,,
202 M7,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,,
203 M8,,,GND,,,,,,,,,,,,
204 M9,,IOBM,IO_L29P_GCLK3_2,UNUSED,,2,,,,,,,,,
205 M10,,IOBS,IO_L16N_VREF_2,UNUSED,,2,,,,,,,,,
211 M16,,IOBS,IO_L46N_FOE_B_M1DQ3_1,UNUSED,,1,,,,,,,,,
212 N1,,IOBS,IO_L34N_M3UDQSN_3,UNUSED,,3,,,,,,,,, N1,FSB_A<11>,IOB,IO_L34N_M3UDQSN_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
213 N2,,,VCCO_3,,,3,,,,,any******,,,, N2,,,VCCO_3,,,3,,,,,3.30,,,,
214 N3,,IOBM,IO_L34P_M3UDQS_3,UNUSED,,3,,,,,,,,, N3,FSB_A<10>,IOB,IO_L34P_M3UDQS_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
215 N4,,IOBS,IO_L2N_3,UNUSED,,3,,,,,,,,, N4,FSB_A<5>,IOB,IO_L2N_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
216 N5,,IOBM,IO_L49P_D3_2,UNUSED,,2,,,,,,,,,
217 N6,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,,
218 N7,,,VCCO_2,,,2,,,,,any******,,,,
219 N8,,IOBS,IO_L29N_GCLK2_2,UNUSED,,2,,,,,,,,,
220 N9,,IOBM,IO_L14P_D11_2,UNUSED,,2,,,,,,,,,
227 N16,,IOBS,IO_L45N_A0_M1LDQSN_1,UNUSED,,1,,,,,,,,,
228 P1,,IOBS,IO_L33N_M3DQ13_3,UNUSED,,3,,,,,,,,, P1,FSB_A<9>,IOB,IO_L33N_M3DQ13_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
229 P2,,IOBM,IO_L33P_M3DQ12_3,UNUSED,,3,,,,,,,,, P2,FSB_A<8>,IOB,IO_L33P_M3DQ12_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
230 P3,,,GND,,,,,,,,,,,,
231 P4,,IOBM,IO_L63P_2,UNUSED,,2,,,,,,,,,
232 P5,,IOBS,IO_L49N_D4_2,UNUSED,,2,,,,,,,,,
233 P6,,IOBM,IO_L47P_2,UNUSED,,2,,,,,,,,,
234 P7,,IOBM,IO_L31P_GCLK31_D14_2,UNUSED,,2,,,,,,,,,
243 P16,,IOBS,IO_L48N_M1DQ9_1,UNUSED,,1,,,,,,,,,
244 R1,,IOBS,IO_L32N_M3DQ15_3,UNUSED,,3,,,,,,,,, R1,FSB_A<7>,IOB,IO_L32N_M3DQ15_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
245 R2,,IOBM,IO_L32P_M3DQ14_3,UNUSED,,3,,,,,,,,, R2,FSB_A<6>,IOB,IO_L32P_M3DQ14_3,INPUT,LVCMOS33,3,,,,NONE,,UNLOCATED,NO,NONE,
246 R3,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,,
247 R4,,,VCCO_2,,,2,,,,,any******,,,,
248 R5,,IOBM,IO_L48P_D7_2,UNUSED,,2,,,,,,,,,
249 R6,,,GND,,,,,,,,,,,,
250 R7,,IOBM,IO_L32P_GCLK29_2,UNUSED,,2,,,,,,,,,

216
fpga/WarpLC_pad.txt
View File

@ -1,7 +1,7 @@
Release 14.7 - par P.20131013 (nt64)
Release 14.7 - par P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sun Oct 31 15:38:33 2021
Mon Nov 01 06:10:44 2021
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
@ -23,137 +23,137 @@ Pinout by Pin Number:
|A1 | | |GND | | | | | | | | | | | |
|A2 | |IOBS |IO_L52N_M3A9_3 |UNUSED | |3 | | | | | | | | |
|A3 | |IOBS |IO_L83N_VREF_3 |UNUSED | |3 | | | | | | | | |
|A4 |CLKFB_OUT |IOB |IO_L1N_VREF_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|A5 |FSB_D<0> |IOB |IO_L2N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|A6 |FSB_D<4> |IOB |IO_L4N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|A7 |FSB_D<6> |IOB |IO_L6N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|A8 |FSB_D<12> |IOB |IO_L33N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|A9 |FSB_D<14> |IOB |IO_L34N_GCLK18_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|A10 |FSB_D<16> |IOB |IO_L35N_GCLK16_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|A11 |FSB_D<22> |IOB |IO_L39N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|A12 |FSB_D<28> |IOB |IO_L62N_VREF_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|A13 |FSB_D<30> |IOB |IO_L63N_SCP6_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|A14 |RAMCLK0 |IOB |IO_L65N_SCP2_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|A4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | |
|A5 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | |
|A6 | |IOBS |IO_L4N_0 |UNUSED | |0 | | | | | | | | |
|A7 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | |
|A8 | |IOBS |IO_L33N_0 |UNUSED | |0 | | | | | | | | |
|A9 | |IOBS |IO_L34N_GCLK18_0 |UNUSED | |0 | | | | | | | | |
|A10 | |IOBS |IO_L35N_GCLK16_0 |UNUSED | |0 | | | | | | | | |
|A11 | |IOBS |IO_L39N_0 |UNUSED | |0 | | | | | | | | |
|A12 | |IOBS |IO_L62N_VREF_0 |UNUSED | |0 | | | | | | | | |
|A13 | |IOBS |IO_L63N_SCP6_0 |UNUSED | |0 | | | | | | | | |
|A14 | |IOBS |IO_L65N_SCP2_0 |UNUSED | |0 | | | | | | | | |
|A15 | | |TMS | | | | | | | | | | | |
|A16 | | |GND | | | | | | | | | | | |
|B1 | |IOBS |IO_L50N_M3BA2_3 |UNUSED | |3 | | | | | | | | |
|B2 | |IOBM |IO_L52P_M3A8_3 |UNUSED | |3 | | | | | | | | |
|B3 | |IOBM |IO_L83P_3 |UNUSED | |3 | | | | | | | | |
|B4 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|B5 |CPUCLK |IOB |IO_L2P_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|B6 |FSB_D<3> |IOB |IO_L4P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|B4 | | |VCCO_0 | | |0 | | | | |any******| | | |
|B5 | |IOBM |IO_L2P_0 |UNUSED | |0 | | | | | | | | |
|B6 | |IOBM |IO_L4P_0 |UNUSED | |0 | | | | | | | | |
|B7 | | |GND | | | | | | | | | | | |
|B8 |FSB_D<11> |IOB |IO_L33P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|B9 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|B10 |FSB_D<15> |IOB |IO_L35P_GCLK17_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|B8 | |IOBM |IO_L33P_0 |UNUSED | |0 | | | | | | | | |
|B9 | | |VCCO_0 | | |0 | | | | |any******| | | |
|B10 | |IOBM |IO_L35P_GCLK17_0 |UNUSED | |0 | | | | | | | | |
|B11 | | |GND | | | | | | | | | | | |
|B12 |FSB_D<27> |IOB |IO_L62P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|B13 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|B14 |FSB_A<2> |IOB |IO_L65P_SCP3_0 |INPUT |LVCMOS33 |0 | | | |NONE | |UNLOCATED |NO |NONE |
|B15 |FSB_A<6> |IOB |IO_L29P_A23_M1A13_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|B16 |FSB_A<7> |IOB |IO_L29N_A22_M1A14_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|B12 | |IOBM |IO_L62P_0 |UNUSED | |0 | | | | | | | | |
|B13 | | |VCCO_0 | | |0 | | | | |any******| | | |
|B14 | |IOBM |IO_L65P_SCP3_0 |UNUSED | |0 | | | | | | | | |
|B15 | |IOBM |IO_L29P_A23_M1A13_1 |UNUSED | |1 | | | | | | | | |
|B16 | |IOBS |IO_L29N_A22_M1A14_1 |UNUSED | |1 | | | | | | | | |
|C1 | |IOBM |IO_L50P_M3WE_3 |UNUSED | |3 | | | | | | | | |
|C2 | |IOBS |IO_L48N_M3BA1_3 |UNUSED | |3 | | | | | | | | |
|C3 | |IOBM |IO_L48P_M3BA0_3 |UNUSED | |3 | | | | | | | | |
|C4 |RAMCLK1 |IOB |IO_L1P_HSWAPEN_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|C5 |FSB_D<2> |IOB |IO_L3N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|C6 |FSB_D<10> |IOB |IO_L7N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|C7 |FSB_D<7> |IOB |IO_L6P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|C8 |FSB_D<24> |IOB |IO_L38N_VREF_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|C9 |FSB_D<13> |IOB |IO_L34P_GCLK19_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|C10 |FSB_D<20> |IOB |IO_L37N_GCLK12_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|C11 |FSB_D<23> |IOB |IO_L39P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|C4 | |IOBM |IO_L1P_HSWAPEN_0 |UNUSED | |0 | | | | | | | | |
|C5 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | |
|C6 | |IOBS |IO_L7N_0 |UNUSED | |0 | | | | | | | | |
|C7 | |IOBM |IO_L6P_0 |UNUSED | |0 | | | | | | | | |
|C8 | |IOBS |IO_L38N_VREF_0 |UNUSED | |0 | | | | | | | | |
|C9 | |IOBM |IO_L34P_GCLK19_0 |UNUSED | |0 | | | | | | | | |
|C10 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | |
|C11 | |IOBM |IO_L39P_0 |UNUSED | |0 | | | | | | | | |
|C12 | | |TDI | | | | | | | | | | | |
|C13 |FSB_D<29> |IOB |IO_L63P_SCP7_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|C13 | |IOBM |IO_L63P_SCP7_0 |UNUSED | |0 | | | | | | | | |
|C14 | | |TCK | | | | | | | | | | | |
|C15 |FSB_A<14> |IOB |IO_L33P_A15_M1A10_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|C16 |FSB_A<20> |IOB |IO_L33N_A14_M1A4_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|C15 | |IOBM |IO_L33P_A15_M1A10_1 |UNUSED | |1 | | | | | | | | |
|C16 | |IOBS |IO_L33N_A14_M1A4_1 |UNUSED | |1 | | | | | | | | |
|D1 | |IOBS |IO_L49N_M3A2_3 |UNUSED | |3 | | | | | | | | |
|D2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|D2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|D3 | |IOBM |IO_L49P_M3A7_3 |UNUSED | |3 | | | | | | | | |
|D4 | | |GND | | | | | | | | | | | |
|D5 |FSB_D<1> |IOB |IO_L3P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|D6 |FSB_D<9> |IOB |IO_L7P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|D7 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|D8 |FSB_D<21> |IOB |IO_L38P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|D9 |FSB_D<26> |IOB |IO_L40N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|D10 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|D11 |FPUCLK |IOB |IO_L66P_SCP1_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|D12 |CPU_nSTERM |IOB |IO_L66N_SCP0_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |NO |NONE |
|D5 | |IOBM |IO_L3P_0 |UNUSED | |0 | | | | | | | | |
|D6 | |IOBM |IO_L7P_0 |UNUSED | |0 | | | | | | | | |
|D7 | | |VCCO_0 | | |0 | | | | |any******| | | |
|D8 | |IOBM |IO_L38P_0 |UNUSED | |0 | | | | | | | | |
|D9 | |IOBS |IO_L40N_0 |UNUSED | |0 | | | | | | | | |
|D10 | | |VCCO_0 | | |0 | | | | |any******| | | |
|D11 | |IOBM |IO_L66P_SCP1_0 |UNUSED | |0 | | | | | | | | |
|D12 | |IOBS |IO_L66N_SCP0_0 |UNUSED | |0 | | | | | | | | |
|D13 | | |GND | | | | | | | | | | | |
|D14 |FSB_A<10> |IOB |IO_L31P_A19_M1CKE_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|D14 | |IOBM |IO_L31P_A19_M1CKE_1 |UNUSED | |1 | | | | | | | | |
|D15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|D16 |FSB_A<11> |IOB |IO_L31N_A18_M1A12_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|E1 | |IOBS |IO_L46N_M3CLKN_3 |UNUSED | |3 | | | | | | | | |
|E2 | |IOBM |IO_L46P_M3CLK_3 |UNUSED | |3 | | | | | | | | |
|D16 | |IOBS |IO_L31N_A18_M1A12_1 |UNUSED | |1 | | | | | | | | |
|E1 |FPUCLK |IOB |IO_L46N_M3CLKN_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|E2 |CPUCLK |IOB |IO_L46P_M3CLK_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|E3 | |IOBS |IO_L54N_M3A11_3 |UNUSED | |3 | | | | | | | | |
|E4 | |IOBM |IO_L54P_M3RESET_3 |UNUSED | |3 | | | | | | | | |
|E5 | | |VCCAUX | | | | | | | |2.5 | | | |
|E6 |FSB_D<8> |IOB |IO_L5N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|E7 |FSB_D<17> |IOB |IO_L36P_GCLK15_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|E8 |FSB_D<18> |IOB |IO_L36N_GCLK14_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|E6 | |IOBS |IO_L5N_0 |UNUSED | |0 | | | | | | | | |
|E7 | |IOBM |IO_L36P_GCLK15_0 |UNUSED | |0 | | | | | | | | |
|E8 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | |
|E9 | | |GND | | | | | | | | | | | |
|E10 |FSB_D<19> |IOB |IO_L37P_GCLK13_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|E11 |FSB_A<3> |IOB |IO_L64N_SCP4_0 |INPUT |LVCMOS33 |0 | | | |NONE | |UNLOCATED |NO |NONE |
|E12 |FSB_A<5> |IOB |IO_L1N_A24_VREF_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|E13 |FSB_A<4> |IOB |IO_L1P_A25_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|E10 | |IOBM |IO_L37P_GCLK13_0 |UNUSED | |0 | | | | | | | | |
|E11 | |IOBS |IO_L64N_SCP4_0 |UNUSED | |0 | | | | | | | | |
|E12 | |IOBS |IO_L1N_A24_VREF_1 |UNUSED | |1 | | | | | | | | |
|E13 | |IOBM |IO_L1P_A25_1 |UNUSED | |1 | | | | | | | | |
|E14 | | |TDO | | | | | | | | | | | |
|E15 |FSB_A<21> |IOB |IO_L34P_A13_M1WE_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|E16 |FSB_A<22> |IOB |IO_L34N_A12_M1BA2_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|F1 | |IOBS |IO_L41N_GCLK26_M3DQ5_3 |UNUSED | |3 | | | | | | | | |
|F2 | |IOBM |IO_L41P_GCLK27_M3DQ4_3 |UNUSED | |3 | | | | | | | | |
|E15 | |IOBM |IO_L34P_A13_M1WE_1 |UNUSED | |1 | | | | | | | | |
|E16 | |IOBS |IO_L34N_A12_M1BA2_1 |UNUSED | |1 | | | | | | | | |
|F1 |FSB_A<25> |IOB |IO_L41N_GCLK26_M3DQ5_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|F2 |FSB_A<24> |IOB |IO_L41P_GCLK27_M3DQ4_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|F3 | |IOBS |IO_L53N_M3A12_3 |UNUSED | |3 | | | | | | | | |
|F4 | |IOBM |IO_L53P_M3CKE_3 |UNUSED | |3 | | | | | | | | |
|F5 | |IOBS |IO_L55N_M3A14_3 |UNUSED | |3 | | | | | | | | |
|F6 | |IOBM |IO_L55P_M3A13_3 |UNUSED | |3 | | | | | | | | |
|F7 |FSB_D<5> |IOB |IO_L5P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|F7 | |IOBM |IO_L5P_0 |UNUSED | |0 | | | | | | | | |
|F8 | | |VCCAUX | | | | | | | |2.5 | | | |
|F9 |FSB_D<25> |IOB |IO_L40P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|F10 |FSB_D<31> |IOB |IO_L64P_SCP5_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|F9 | |IOBM |IO_L40P_0 |UNUSED | |0 | | | | | | | | |
|F10 | |IOBM |IO_L64P_SCP5_0 |UNUSED | |0 | | | | | | | | |
|F11 | | |VCCAUX | | | | | | | |2.5 | | | |
|F12 |FSB_A<8> |IOB |IO_L30P_A21_M1RESET_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|F13 |FSB_A<12> |IOB |IO_L32P_A17_M1A8_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|F14 |FSB_A<13> |IOB |IO_L32N_A16_M1A9_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|F15 |FSB_A<23> |IOB |IO_L35P_A11_M1A7_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|F16 |FSB_A<19> |IOB |IO_L35N_A10_M1A2_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|G1 | |IOBS |IO_L40N_M3DQ7_3 |UNUSED | |3 | | | | | | | | |
|F12 | |IOBM |IO_L30P_A21_M1RESET_1 |UNUSED | |1 | | | | | | | | |
|F13 | |IOBM |IO_L32P_A17_M1A8_1 |UNUSED | |1 | | | | | | | | |
|F14 | |IOBS |IO_L32N_A16_M1A9_1 |UNUSED | |1 | | | | | | | | |
|F15 | |IOBM |IO_L35P_A11_M1A7_1 |UNUSED | |1 | | | | | | | | |
|F16 | |IOBS |IO_L35N_A10_M1A2_1 |UNUSED | |1 | | | | | | | | |
|G1 |FSB_A<23> |IOB |IO_L40N_M3DQ7_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|G2 | | |GND | | | | | | | | | | | |
|G3 | |IOBM |IO_L40P_M3DQ6_3 |UNUSED | |3 | | | | | | | | |
|G4 | | |VCCO_3 | | |3 | | | | |any******| | | |
|G3 |FSB_A<22> |IOB |IO_L40P_M3DQ6_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|G4 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|G5 | |IOBS |IO_L51N_M3A4_3 |UNUSED | |3 | | | | | | | | |
|G6 | |IOBM |IO_L51P_M3A10_3 |UNUSED | |3 | | | | | | | | |
|G7 | | |VCCINT | | | | | | | |1.2 | | | |
|G8 | | |GND | | | | | | | | | | | |
|G9 | | |VCCINT | | | | | | | |1.2 | | | |
|G10 | | |VCCAUX | | | | | | | |2.5 | | | |
|G11 |FSB_A<9> |IOB |IO_L30N_A20_M1A11_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|G12 |FSB_A<24> |IOB |IO_L38P_A5_M1CLK_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|G11 | |IOBS |IO_L30N_A20_M1A11_1 |UNUSED | |1 | | | | | | | | |
|G12 | |IOBM |IO_L38P_A5_M1CLK_1 |UNUSED | |1 | | | | | | | | |
|G13 | | |VCCO_1 | | |1 | | | | |any******| | | |
|G14 |FSB_A<15> |IOB |IO_L36P_A9_M1BA0_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|G14 | |IOBM |IO_L36P_A9_M1BA0_1 |UNUSED | |1 | | | | | | | | |
|G15 | | |GND | | | | | | | | | | | |
|G16 |FSB_A<16> |IOB |IO_L36N_A8_M1BA1_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|H1 | |IOBS |IO_L39N_M3LDQSN_3 |UNUSED | |3 | | | | | | | | |
|H2 | |IOBM |IO_L39P_M3LDQS_3 |UNUSED | |3 | | | | | | | | |
|H3 | |IOBS |IO_L44N_GCLK20_M3A6_3 |UNUSED | |3 | | | | | | | | |
|G16 | |IOBS |IO_L36N_A8_M1BA1_1 |UNUSED | |1 | | | | | | | | |
|H1 |FSB_A<21> |IOB |IO_L39N_M3LDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|H2 |FSB_A<20> |IOB |IO_L39P_M3LDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|H3 |RAMCLK0 |IOB |IO_L44N_GCLK20_M3A6_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|H4 |CLKFB_IN |IOB |IO_L44P_GCLK21_M3A5_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|H5 | |IOBS |IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED | |3 | | | | | | | | |
|H5 |CPU_nSTERM |IOB |IO_L43N_GCLK22_IRDY2_M3CASN_3|OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |NO |NONE |
|H6 | | |VCCAUX | | | | | | | |2.5 | | | |
|H7 | | |GND | | | | | | | | | | | |
|H8 | | |VCCINT | | | | | | | |1.2 | | | |
|H9 | | |GND | | | | | | | | | | | |
|H10 | | |VCCINT | | | | | | | |1.2 | | | |
|H11 |FSB_A<25> |IOB |IO_L38N_A4_M1CLKN_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|H11 | |IOBS |IO_L38N_A4_M1CLKN_1 |UNUSED | |1 | | | | | | | | |
|H12 | | |GND | | | | | | | | | | | |
|H13 |FSB_A<26> |IOB |IO_L39P_M1A3_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|H14 |FSB_A<27> |IOB |IO_L39N_M1ODT_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|H15 |FSB_A<17> |IOB |IO_L37P_A7_M1A0_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|H16 |FSB_A<18> |IOB |IO_L37N_A6_M1A1_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|J1 | |IOBS |IO_L38N_M3DQ3_3 |UNUSED | |3 | | | | | | | | |
|J2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|J3 | |IOBM |IO_L38P_M3DQ2_3 |UNUSED | |3 | | | | | | | | |
|H13 | |IOBM |IO_L39P_M1A3_1 |UNUSED | |1 | | | | | | | | |
|H14 | |IOBS |IO_L39N_M1ODT_1 |UNUSED | |1 | | | | | | | | |
|H15 | |IOBM |IO_L37P_A7_M1A0_1 |UNUSED | |1 | | | | | | | | |
|H16 | |IOBS |IO_L37N_A6_M1A1_1 |UNUSED | |1 | | | | | | | | |
|J1 |FSB_A<19> |IOB |IO_L38N_M3DQ3_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|J2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|J3 |FSB_A<18> |IOB |IO_L38P_M3DQ2_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|J4 |CLKIN |IOB |IO_L42N_GCLK24_M3LDM_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|J5 | | |GND | | | | | | | | | | | |
|J6 | |IOBM |IO_L43P_GCLK23_M3RASN_3 |UNUSED | |3 | | | | | | | | |
|J6 |FSB_A<27> |IOB |IO_L43P_GCLK23_M3RASN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|J7 | | |VCCINT | | | | | | | |1.2 | | | |
|J8 | | |GND | | | | | | | | | | | |
|J9 | | |VCCINT | | | | | | | |1.2 | | | |
@ -164,10 +164,10 @@ Pinout by Pin Number:
|J14 | |IOBM |IO_L43P_GCLK5_M1DQ4_1 |UNUSED | |1 | | | | | | | | |
|J15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|J16 | |IOBS |IO_L43N_GCLK4_M1DQ5_1 |UNUSED | |1 | | | | | | | | |
|K1 | |IOBS |IO_L37N_M3DQ1_3 |UNUSED | |3 | | | | | | | | |
|K2 | |IOBM |IO_L37P_M3DQ0_3 |UNUSED | |3 | | | | | | | | |
|K3 | |IOBM |IO_L42P_GCLK25_TRDY2_M3UDM_3 |UNUSED | |3 | | | | | | | | |
|K4 | | |VCCO_3 | | |3 | | | | |any******| | | |
|K1 |FSB_A<17> |IOB |IO_L37N_M3DQ1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|K2 |FSB_A<16> |IOB |IO_L37P_M3DQ0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|K3 |FSB_A<26> |IOB |IO_L42P_GCLK25_TRDY2_M3UDM_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|K4 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|K5 | |IOBM |IO_L47P_M3A0_3 |UNUSED | |3 | | | | | | | | |
|K6 | |IOBS |IO_L47N_M3A1_3 |UNUSED | |3 | | | | | | | | |
|K7 | | |GND | | | | | | | | | | | |
@ -180,11 +180,11 @@ Pinout by Pin Number:
|K14 | |IOBS |IO_L41N_GCLK8_M1CASN_1 |UNUSED | |1 | | | | | | | | |
|K15 | |IOBM |IO_L44P_A3_M1DQ6_1 |UNUSED | |1 | | | | | | | | |
|K16 | |IOBS |IO_L44N_A2_M1DQ7_1 |UNUSED | |1 | | | | | | | | |
|L1 | |IOBS |IO_L36N_M3DQ9_3 |UNUSED | |3 | | | | | | | | |
|L1 |FSB_A<15> |IOB |IO_L36N_M3DQ9_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|L2 | | |GND | | | | | | | | | | | |
|L3 | |IOBM |IO_L36P_M3DQ8_3 |UNUSED | |3 | | | | | | | | |
|L4 | |IOBM |IO_L45P_M3A3_3 |UNUSED | |3 | | | | | | | | |
|L5 | |IOBS |IO_L45N_M3ODT_3 |UNUSED | |3 | | | | | | | | |
|L3 |FSB_A<14> |IOB |IO_L36P_M3DQ8_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|L4 |CLKFB_OUT |IOB |IO_L45P_M3A3_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|L5 |RAMCLK1 |IOB |IO_L45N_M3ODT_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|L6 | | |VCCAUX | | | | | | | |2.5 | | | |
|L7 | |IOBS |IO_L62N_D6_2 |UNUSED | |2 | | | | | | | | |
|L8 | |IOBM |IO_L62P_D5_2 |UNUSED | |2 | | | | | | | | |
@ -196,11 +196,11 @@ Pinout by Pin Number:
|L14 | |IOBM |IO_L47P_FWE_B_M1DQ0_1 |UNUSED | |1 | | | | | | | | |
|L15 | | |GND | | | | | | | | | | | |
|L16 | |IOBS |IO_L47N_LDC_M1DQ1_1 |UNUSED | |1 | | | | | | | | |
|M1 | |IOBS |IO_L35N_M3DQ11_3 |UNUSED | |3 | | | | | | | | |
|M2 | |IOBM |IO_L35P_M3DQ10_3 |UNUSED | |3 | | | | | | | | |
|M3 | |IOBS |IO_L1N_VREF_3 |UNUSED | |3 | | | | | | | | |
|M4 | |IOBM |IO_L1P_3 |UNUSED | |3 | | | | | | | | |
|M5 | |IOBM |IO_L2P_3 |UNUSED | |3 | | | | | | | | |
|M1 |FSB_A<13> |IOB |IO_L35N_M3DQ11_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|M2 |FSB_A<12> |IOB |IO_L35P_M3DQ10_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|M3 |FSB_A<3> |IOB |IO_L1N_VREF_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|M4 |FSB_A<2> |IOB |IO_L1P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|M5 |FSB_A<4> |IOB |IO_L2P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|M6 | |IOBM |IO_L64P_D8_2 |UNUSED | |2 | | | | | | | | |
|M7 | |IOBS |IO_L31N_GCLK30_D15_2 |UNUSED | |2 | | | | | | | | |
|M8 | | |GND | | | | | | | | | | | |
@ -212,10 +212,10 @@ Pinout by Pin Number:
|M14 | |IOBS |IO_L74N_DOUT_BUSY_1 |UNUSED | |1 | | | | | | | | |
|M15 | |IOBM |IO_L46P_FCS_B_M1DQ2_1 |UNUSED | |1 | | | | | | | | |
|M16 | |IOBS |IO_L46N_FOE_B_M1DQ3_1 |UNUSED | |1 | | | | | | | | |
|N1 | |IOBS |IO_L34N_M3UDQSN_3 |UNUSED | |3 | | | | | | | | |
|N2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|N3 | |IOBM |IO_L34P_M3UDQS_3 |UNUSED | |3 | | | | | | | | |
|N4 | |IOBS |IO_L2N_3 |UNUSED | |3 | | | | | | | | |
|N1 |FSB_A<11> |IOB |IO_L34N_M3UDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|N2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|N3 |FSB_A<10> |IOB |IO_L34P_M3UDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|N4 |FSB_A<5> |IOB |IO_L2N_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|N5 | |IOBM |IO_L49P_D3_2 |UNUSED | |2 | | | | | | | | |
|N6 | |IOBS |IO_L64N_D9_2 |UNUSED | |2 | | | | | | | | |
|N7 | | |VCCO_2 | | |2 | | | | |any******| | | |
@ -228,8 +228,8 @@ Pinout by Pin Number:
|N14 | |IOBM |IO_L45P_A1_M1LDQS_1 |UNUSED | |1 | | | | | | | | |
|N15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|N16 | |IOBS |IO_L45N_A0_M1LDQSN_1 |UNUSED | |1 | | | | | | | | |
|P1 | |IOBS |IO_L33N_M3DQ13_3 |UNUSED | |3 | | | | | | | | |
|P2 | |IOBM |IO_L33P_M3DQ12_3 |UNUSED | |3 | | | | | | | | |
|P1 |FSB_A<9> |IOB |IO_L33N_M3DQ13_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|P2 |FSB_A<8> |IOB |IO_L33P_M3DQ12_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|P3 | | |GND | | | | | | | | | | | |
|P4 | |IOBM |IO_L63P_2 |UNUSED | |2 | | | | | | | | |
|P5 | |IOBS |IO_L49N_D4_2 |UNUSED | |2 | | | | | | | | |
@ -244,8 +244,8 @@ Pinout by Pin Number:
|P14 | | |SUSPEND | | | | | | | | | | | |
|P15 | |IOBM |IO_L48P_HDC_M1DQ8_1 |UNUSED | |1 | | | | | | | | |
|P16 | |IOBS |IO_L48N_M1DQ9_1 |UNUSED | |1 | | | | | | | | |
|R1 | |IOBS |IO_L32N_M3DQ15_3 |UNUSED | |3 | | | | | | | | |
|R2 | |IOBM |IO_L32P_M3DQ14_3 |UNUSED | |3 | | | | | | | | |
|R1 |FSB_A<7> |IOB |IO_L32N_M3DQ15_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|R2 |FSB_A<6> |IOB |IO_L32P_M3DQ14_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|R3 | |IOBM |IO_L65P_INIT_B_2 |UNUSED | |2 | | | | | | | | |
|R4 | | |VCCO_2 | | |2 | | | | |any******| | | |
|R5 | |IOBM |IO_L48P_D7_2 |UNUSED | |2 | | | | | | | | |

1092
fpga/WarpLC_par.xrpt
View File

File diff suppressed because it is too large Load Diff

89
fpga/WarpLC_summary.html
View File

@ -2,12 +2,12 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>ClkGen Project Status (10/31/2021 - 15:38:40)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>WarpLC Project Status (11/01/2021 - 06:10:50)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>WarpLC.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/pn_parser.xmsgs?&DataKey=Error'>2 Errors</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
@ -19,35 +19,35 @@
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx9-2ftg256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
<TD>
No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/*.xmsgs?&DataKey=Warning'>153 Warnings (53 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.unroutes'>All Signals Completely Routed</A></TD>
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.unroutes'>All Signals Completely Routed</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_envsettings.html'>
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>0 &nbsp;<A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
<TD>0 &nbsp;<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
@ -89,7 +89,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>33</TD>
<TD ALIGN=RIGHT>89</TD>
<TD ALIGN=RIGHT>5,720</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@ -101,7 +101,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>7</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@ -113,7 +113,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@ -125,19 +125,19 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
<TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>80</TD>
<TD ALIGN=RIGHT>1,440</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD ALIGN=RIGHT>5%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Dual Port RAM</TD>
<TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>80</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>80</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@ -149,7 +149,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>20</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@ -167,7 +167,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>9</TD>
<TD ALIGN=RIGHT>23</TD>
<TD ALIGN=RIGHT>1,430</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@ -179,27 +179,27 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>33</TD>
<TD ALIGN=RIGHT>89</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>33</TD>
<TD ALIGN=RIGHT>96%</TD>
<TD ALIGN=RIGHT>88</TD>
<TD ALIGN=RIGHT>89</TD>
<TD ALIGN=RIGHT>98%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>33</TD>
<TD ALIGN=RIGHT>89</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>33</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD ALIGN=RIGHT>89</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
@ -209,15 +209,15 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>11</TD>
<TD ALIGN=RIGHT>7</TD>
<TD ALIGN=RIGHT>11,440</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>66</TD>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>34</TD>
<TD ALIGN=RIGHT>186</TD>
<TD ALIGN=RIGHT>35%</TD>
<TD ALIGN=RIGHT>18%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;IOB Flip Flops</TD>
@ -233,9 +233,9 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>64</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
@ -401,7 +401,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>1.67</TD>
<TD ALIGN=RIGHT>5.20</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@ -416,18 +416,17 @@ System Settings</A>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
<A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.unroutes'>All Signals Completely Routed</A></TD>
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
<A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TABLE>
@ -438,21 +437,21 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sun Oct 31 15:37:53 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>17 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sun Oct 31 15:37:59 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>9 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sun Oct 31 15:38:27 2021</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sun Oct 31 15:38:33 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/par.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon Nov 1 06:10:22 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>80 Warnings (53 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon Nov 1 06:10:26 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>73 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon Nov 1 06:10:39 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon Nov 1 06:10:44 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/par.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sun Oct 31 15:38:38 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon Nov 1 06:10:48 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Oct 31 14:40:54 2021</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Oct 31 15:38:26 2021</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Nov 1 01:01:50 2021</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.psr'>Physical Synthesis Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon Nov 1 06:10:39 2021</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 10/31/2021 - 15:38:40</center>
<br><center><b>Date Generated:</b> 11/01/2021 - 12:11:55</center>
</BODY></HTML>

2
fpga/WarpLC_summary.xml
View File

@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="33">
<DesignSummary rev="46">
<CmdHistory>
</CmdHistory>
</DesignSummary>

100
fpga/WarpLC_usage.xml
View File

@ -4,67 +4,65 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="33">
<DesignStatistics TimeStamp="Sun Oct 31 15:38:26 2021"><group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="33">
<attrib name="value" value="66"/></item>
<item name="AGG_IO" rev="33">
<attrib name="value" value="66"/></item>
<item name="AGG_SLICE" rev="33">
<attrib name="value" value="9"/></item>
<item name="NUM_BONDED_IOB" rev="33">
<attrib name="value" value="66"/></item>
<item name="NUM_BSFULL" rev="33">
<DeviceUsageSummary rev="46">
<DesignStatistics TimeStamp="Mon Nov 01 06:10:39 2021"><group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="46">
<attrib name="value" value="34"/></item>
<item name="AGG_IO" rev="46">
<attrib name="value" value="34"/></item>
<item name="AGG_SLICE" rev="46">
<attrib name="value" value="23"/></item>
<item name="NUM_BONDED_IOB" rev="46">
<attrib name="value" value="34"/></item>
<item name="NUM_BSFULL" rev="46">
<attrib name="value" value="1"/></item>
<item name="NUM_BSLUTONLY" rev="33">
<attrib name="value" value="32"/></item>
<item name="NUM_BSUSED" rev="33">
<attrib name="value" value="33"/></item>
<item name="NUM_BUFG" rev="33">
<item name="NUM_BSLUTONLY" rev="46">
<attrib name="value" value="88"/></item>
<item name="NUM_BSUSED" rev="46">
<attrib name="value" value="89"/></item>
<item name="NUM_BUFG" rev="46">
<attrib name="value" value="2"/></item>
<item name="NUM_BUFIO2" rev="33">
<item name="NUM_BUFIO2" rev="46">
<attrib name="value" value="1"/></item>
<item name="NUM_BUFIO2FB" rev="33">
<item name="NUM_BUFIO2FB" rev="46">
<attrib name="value" value="1"/></item>
<item name="NUM_DPRAM_O5ANDO6" rev="33">
<item name="NUM_DPRAM_O6ONLY" rev="46">
<attrib name="value" value="80"/></item>
<item name="NUM_IOB_FF" rev="46">
<attrib name="value" value="5"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="46">
<attrib name="value" value="1"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="46">
<attrib name="value" value="1"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="46">
<attrib name="value" value="7"/></item>
<item name="NUM_LUT_RT_O6" rev="46">
<attrib name="value" value="1"/></item>
<item name="NUM_OLOGIC2" rev="46">
<attrib name="value" value="5"/></item>
<item name="NUM_PLL_ADV" rev="46">
<attrib name="value" value="1"/></item>
<item name="NUM_SLICEL" rev="46">
<attrib name="value" value="2"/></item>
<item name="NUM_SLICEM" rev="46">
<attrib name="value" value="20"/></item>
<item name="NUM_DPRAM_O6ONLY" rev="33">
<attrib name="value" value="4"/></item>
<item name="NUM_IOB_FF" rev="33">
<attrib name="value" value="5"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="33">
<item name="NUM_SLICEX" rev="46">
<attrib name="value" value="1"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="33">
<attrib name="value" value="8"/></item>
<item name="NUM_LUT_RT_O6" rev="33">
<attrib name="value" value="1"/></item>
<item name="NUM_OLOGIC2" rev="33">
<attrib name="value" value="5"/></item>
<item name="NUM_PLL_ADV" rev="33">
<attrib name="value" value="1"/></item>
<item name="NUM_RAMB8BWER" rev="33">
<attrib name="value" value="1"/></item>
<item name="NUM_SLICEL" rev="33">
<item name="NUM_SLICE_CARRY4" rev="46">
<attrib name="value" value="2"/></item>
<item name="NUM_SLICEM" rev="33">
<attrib name="value" value="6"/></item>
<item name="NUM_SLICEX" rev="33">
<attrib name="value" value="1"/></item>
<item name="NUM_SLICE_CARRY4" rev="33">
<item name="NUM_SLICE_CONTROLSET" rev="46">
<attrib name="value" value="2"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="33">
<attrib name="value" value="2"/></item>
<item name="NUM_SLICE_CYINIT" rev="33">
<attrib name="value" value="55"/></item>
<item name="NUM_SLICE_FF" rev="33">
<item name="NUM_SLICE_CYINIT" rev="46">
<attrib name="value" value="92"/></item>
<item name="NUM_SLICE_F7MUX" rev="46">
<attrib name="value" value="20"/></item>
<item name="NUM_SLICE_FF" rev="46">
<attrib name="value" value="1"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="33">
<item name="NUM_SLICE_UNUSEDCTRL" rev="46">
<attrib name="value" value="2"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="33">
<attrib name="value" value="11"/></item>
<item name="Xilinx Core blk_mem_gen_v7_3, Xilinx CORE Generator 14.7" rev="33">
<attrib name="value" value="1"/></item>
<item name="Xilinx Core dist_mem_gen_v7_2, Xilinx CORE Generator 14.7" rev="33">
<item name="NUM_UNUSABLE_FF_BELS" rev="46">
<attrib name="value" value="7"/></item>
<item name="Xilinx Core dist_mem_gen_v7_2, Xilinx CORE Generator 14.7" rev="46">
<attrib name="value" value="1"/></item>
</group>
</DesignStatistics>

47
fpga/WarpLC_xst.xrpt
View File

@ -1,18 +1,18 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt64" product="ISE" version="14.7">
<document OS="nt" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sun Oct 31 15:37:47 2021">
<application stringID="Xst" timeStamp="Mon Nov 01 06:10:19 2021">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\PuTTY\;C:\Program Files (x86)\WinMerge;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\Microchip\xc8\v2.31\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\Dog\AppData\Local\GitHubDesktop\bin"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files\Microchip\xc8\v2.31\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\PuTTY\;C:\Program Files\WinMerge;C:\Program Files\dotnet\;C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;C:\Users\zanek\AppData\Local\GitHubDesktop\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\zanek\.dotnet\tools;C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
@ -36,16 +36,16 @@
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
<item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
<item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
</item>
<item stringID="User_EnvHost" value="Dog-PC"/>
<item stringID="User_EnvHost" value="ZanePC"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Xeon(R) CPU W3680 @ 3.33GHz"/>
<item stringID="speed" value="3316 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz"/>
<item stringID="speed" value="3500 MHz"/>
</row>
</table>
</section>
@ -135,11 +135,12 @@
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="WarpLC.ngc"/>
</section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="22">
<item dataType="int" stringID="XST_GND" value="2"/>
<item dataType="int" stringID="XST_BELS" value="21">
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="3"/>
<item dataType="int" stringID="XST_LUT1" value="1"/>
<item dataType="int" stringID="XST_LUT6" value="7"/>
<item dataType="int" stringID="XST_LUT2" value="1"/>
<item dataType="int" stringID="XST_LUT6" value="6"/>
<item dataType="int" stringID="XST_MUXCY" value="8"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
</item>
@ -148,14 +149,14 @@
<item dataType="int" stringID="XST_FDR" value="1"/>
<item dataType="int" stringID="XST_ODDR2" value="5"/>
</item>
<item dataType="int" stringID="XST_RAMS" value="23"></item>
<item dataType="int" stringID="XST_RAMS" value="22"></item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="2">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="2"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="66">
<item dataType="int" stringID="XST_IO_BUFFERS" value="34">
<item dataType="int" stringID="XST_IBUF" value="26"/>
<item dataType="int" stringID="XST_IBUFG" value="2"/>
<item dataType="int" stringID="XST_OBUF" value="38"/>
<item dataType="int" stringID="XST_OBUF" value="6"/>
</item>
<item dataType="int" stringID="XST_OTHERS" value="2"></item>
</section>
@ -163,18 +164,16 @@
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="6slx9ftg256-2"/>
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="50"/>
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="55"/>
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="99"/>
<item AVAILABLE="5720" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="11"/>
<item AVAILABLE="1440" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="44"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="105"/>
<item AVAILABLE="105" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="55"/>
<item AVAILABLE="105" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="50"/>
<item AVAILABLE="105" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="0"/>
<item AVAILABLE="1440" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="88"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="149"/>
<item AVAILABLE="149" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="99"/>
<item AVAILABLE="149" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="50"/>
<item AVAILABLE="149" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="0"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="2"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="75"/>
<item AVAILABLE="186" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="66"/>
<item AVAILABLE="32" dataType="int" label="Number of Block RAM/FIFO" stringID="XST_NUMBER_OF_BLOCK_RAMFIFO" value="1"/>
<item dataType="int" label="Number using Block RAM only" stringID="XST_NUMBER_USING_BLOCK_RAM_ONLY" value="1"/>
<item AVAILABLE="186" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="34"/>
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="2"/>
</section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
@ -182,7 +181,7 @@
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="17"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="80"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="3"/>
</section>
</application>

5
fpga/_ngo/netlist.lst
View File

@ -1,4 +1,3 @@
C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.ngc 1635709073
ipcore_dir/PrefetchTagRAM.ngc 1635704546
ipcore_dir/PrefetchDataRAM.ngc 1635685742
C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.ngc 1635761422
ipcore_dir/PrefetchTagRAM.ngc 1635761393
OK

5
fpga/_xmsgs/map.xmsgs
View File

@ -11,7 +11,7 @@
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">FSB_A&lt;31&gt;</arg> has no load.
</msg>
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">54</arg> more times for the following (max. 5 shown):
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">86</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">FSB_A&lt;30&gt;,
FSB_A&lt;29&gt;,
FSB_A&lt;28&gt;,
@ -35,8 +35,5 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>
<msg type="warning" file="PhysDesignRules" num="2410" delta="old" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.
</msg>
</messages>

192
fpga/_xmsgs/ngdbuild.xmsgs
View File

@ -5,6 +5,102 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;0&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;0&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;1&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;1&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;2&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;2&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;3&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;3&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;4&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;4&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;5&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;5&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;6&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;6&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;7&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;7&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;8&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;8&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;9&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;9&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;10&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;10&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;11&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;11&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;12&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;12&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;13&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;13&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;14&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;14&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;15&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;15&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;16&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;16&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;17&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;17&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;18&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;18&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;19&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;19&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;20&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;20&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;21&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;21&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;22&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;22&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;23&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;23&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;24&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;24&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;25&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;25&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;26&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;26&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;27&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;27&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;28&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;28&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;29&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;29&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;30&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;30&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_D&lt;31&gt;&quot; SLEW = SLOW&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D&lt;31&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;CPU_nAS&quot; IOBDELAY = NONE&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nAS</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
@ -32,12 +128,100 @@
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;FSB_A&lt;31&gt;&quot; IOBDELAY = NONE&gt;</arg>: This constraint cannot be distributed from the design objects matching &apos;<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A&lt;31&gt;</arg>&apos; because those design objects do not contain or drive any instances of the correct type.
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">CLKIN</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_CLKIN</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">PLL_ADV</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKFBOUT</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_cg_pll_clkfbout = PERIOD &quot;cg_pll_clkfbout&quot; TS_CLKIN HIGH 50%&gt;</arg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;31&gt;</arg>&apos; has no driver
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">CLKIN</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_CLKIN</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">PLL_ADV</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT0</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_cg_pll_clkout0 = PERIOD &quot;cg_pll_clkout0&quot; TS_CLKIN / 2 HIGH 50%&gt;</arg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;30&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;29&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;28&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;27&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;26&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;25&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;24&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;23&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;22&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;21&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;20&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;19&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;18&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;17&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;16&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;15&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;14&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;13&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;12&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;11&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;10&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;9&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;8&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;7&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;6&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;5&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;4&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;3&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;2&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;1&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">FSB_D&lt;0&gt;</arg>&apos; has no driver
</msg>
</messages>

26
fpga/_xmsgs/pn_parser.xmsgs
View File

@ -8,7 +8,31 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/PrefetchBuf.v&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/CS.v&quot; into library work</arg>
</msg>
<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/CS.v</arg>&quot; Line <arg fmt="%d" index="2">3</arg>. <arg fmt="%s" index="3">Syntax error near &quot;output&quot;.</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ClkGen.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/L2Cache.v&quot; into library work</arg>
</msg>
<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/L2Cache.v</arg>&quot; Line <arg fmt="%d" index="2">34</arg>. <arg fmt="%s" index="3">Syntax error near &quot;==&quot;.</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/L2CacheWay.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/Prefetch.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/SizeDecode.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.v&quot; into library work</arg>
</msg>
</messages>

2
fpga/_xmsgs/trce.xmsgs
View File

@ -5,7 +5,7 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>

229
fpga/_xmsgs/xst.xmsgs
View File

@ -5,65 +5,254 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="1016" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port <arg fmt="%s" index="1">LOCKED</arg> is not connected to this instance
<msg type="warning" file="HDLCompiler" num="1016" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port <arg fmt="%s" index="1">LOCKED</arg> is not connected to this instance
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to <arg fmt="%s" index="1">clkout1_unused</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to <arg fmt="%s" index="1">clkout1_unused</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to <arg fmt="%s" index="1">clkout2_unused</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to <arg fmt="%s" index="1">clkout2_unused</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to <arg fmt="%s" index="1">clkout3_unused</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to <arg fmt="%s" index="1">clkout3_unused</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to <arg fmt="%s" index="1">clkout4_unused</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to <arg fmt="%s" index="1">clkout4_unused</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to <arg fmt="%s" index="1">clkout5_unused</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to <arg fmt="%s" index="1">clkout5_unused</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to <arg fmt="%s" index="1">FSB_B</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to <arg fmt="%s" index="1">FSB_B</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1499" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module &lt;<arg fmt="%s" index="1">PrefetchTagRAM</arg>&gt; remains a black box.
<msg type="warning" file="HDLCompiler" num="1499" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module &lt;<arg fmt="%s" index="1">PrefetchTagRAM</arg>&gt; remains a black box.
</msg>
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 33: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">a</arg>&gt;. Formal port size is <arg fmt="%d" index="2">5</arg>-bit while actual signal size is <arg fmt="%d" index="1">7</arg>-bit.
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 40: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">d</arg>&gt;. Formal port size is <arg fmt="%d" index="2">22</arg>-bit while actual signal size is <arg fmt="%d" index="1">20</arg>-bit.
</msg>
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 36: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">dpra</arg>&gt;. Formal port size is <arg fmt="%d" index="2">5</arg>-bit while actual signal size is <arg fmt="%d" index="1">7</arg>-bit.
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 41: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">spo</arg>&gt;. Formal port size is <arg fmt="%d" index="2">22</arg>-bit while actual signal size is <arg fmt="%d" index="1">20</arg>-bit.
</msg>
<msg type="warning" file="HDLCompiler" num="1499" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" Line 39: Empty module &lt;<arg fmt="%s" index="1">PrefetchDataRAM</arg>&gt; remains a black box.
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 43: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">dpo</arg>&gt;. Formal port size is <arg fmt="%d" index="2">22</arg>-bit while actual signal size is <arg fmt="%d" index="1">20</arg>-bit.
</msg>
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 44: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">addra</arg>&gt;. Formal port size is <arg fmt="%d" index="2">7</arg>-bit while actual signal size is <arg fmt="%d" index="1">5</arg>-bit.
<msg type="warning" file="Xst" num="2972" delta="old" >&quot;<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>&quot; line <arg fmt="%d" index="2">91</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">sd</arg>&gt; of block &lt;<arg fmt="%s" index="4">SizeDecode</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">WarpLC</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="2972" delta="old" >&quot;<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>&quot; line <arg fmt="%d" index="2">91</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">sd</arg>&gt; of block &lt;<arg fmt="%s" index="4">SizeDecode</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">WarpLC</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">FSB_A&lt;31:29&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">FSB_A&lt;31:28&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">CPU_nAS</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>&quot; line <arg fmt="%s" index="2">91</arg>: Output port &lt;<arg fmt="%s" index="3">B</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">sd</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>&quot; line <arg fmt="%s" index="2">91</arg>: Output port &lt;<arg fmt="%s" index="3">B</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">sd</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v</arg>&quot; line <arg fmt="%s" index="2">32</arg>: Output port &lt;<arg fmt="%s" index="3">LOCKED</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">pll</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ClkGen.v</arg>&quot; line <arg fmt="%s" index="2">32</arg>: Output port &lt;<arg fmt="%s" index="3">LOCKED</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">pll</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RDA&lt;28:28&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WRD</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WRA&lt;28:28&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">CPUCLKr</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="1901" delta="old" >Instance <arg fmt="%s" index="1">pll_base_inst</arg> in unit <arg fmt="%s" index="2">pll_base_inst</arg> of type <arg fmt="%s" index="3">PLL_BASE</arg> has been replaced by <arg fmt="%s" index="4">PLL_ADV</arg>
</msg>
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;31&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;31&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;30&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;30&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;29&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;29&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;28&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;28&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;27&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;27&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;26&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;26&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;25&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;25&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;24&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;24&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;23&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;23&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;22&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;22&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;21&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;21&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;20&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;20&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;19&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;19&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;18&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;18&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;17&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;17&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;16&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;16&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;15&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;15&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;14&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;14&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;13&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;13&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;12&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;12&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;11&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;11&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;10&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;10&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;9&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;9&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;8&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;8&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;7&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;7&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;6&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;6&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;5&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;5&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;4&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;4&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;3&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;3&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;2&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;2&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;1&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;1&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;0&gt;</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
</msg>
<msg type="warning" file="Xst" num="615" delta="new" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D&lt;0&gt;</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
</msg>
</messages>

53
fpga/ipcore_dir/L2WayRAM.asy Normal file
View File

@ -0,0 +1,53 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 L2WayRAM
RECTANGLE Normal 32 32 544 1376
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName addra[9:0]
PINATTR Polarity IN
LINE Wide 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName dina[49:0]
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName ena
PINATTR Polarity IN
LINE Wide 0 208 32 208
PIN 0 208 LEFT 36
PINATTR PinName wea[0:0]
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Wide 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName addrb[9:0]
PINATTR Polarity IN
LINE Wide 0 464 32 464
PIN 0 464 LEFT 36
PINATTR PinName dinb[49:0]
PINATTR Polarity IN
LINE Normal 0 496 32 496
PIN 0 496 LEFT 36
PINATTR PinName enb
PINATTR Polarity IN
LINE Wide 0 560 32 560
PIN 0 560 LEFT 36
PINATTR PinName web[0:0]
PINATTR Polarity IN
LINE Normal 0 624 32 624
PIN 0 624 LEFT 36
PINATTR PinName clkb
PINATTR Polarity IN
LINE Wide 576 80 544 80
PIN 576 80 RIGHT 36
PINATTR PinName douta[49:0]
PINATTR Polarity OUT
LINE Wide 576 368 544 368
PIN 576 368 RIGHT 36
PINATTR PinName doutb[49:0]
PINATTR Polarity OUT

53
fpga/ipcore_dir/L2WayRAM.gise Normal file
View File

@ -0,0 +1,53 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="L2WayRAM.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="L2WayRAM.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="L2WayRAM.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="L2WayRAM.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1635761278" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635761278">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4291244256852075332" xil_pn:start_ts="1635761418">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="740071792634416364" xil_pn:start_ts="1635761418">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635761418">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1635761418" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4263457726895274682" xil_pn:start_ts="1635761418">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>

0
sterminator/XC9572XL/STERMINATOR.stx → fpga/ipcore_dir/L2WayRAM.ncf
View File

3
fpga/ipcore_dir/L2WayRAM.ngc Normal file
View File

File diff suppressed because one or more lines are too long

45
fpga/ipcore_dir/L2WayRAM.sym Normal file
View File

@ -0,0 +1,45 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="L2WayRAM">
<symboltype>BLOCK</symboltype>
<timestamp>2021-11-1T9:40:30</timestamp>
<pin polarity="Input" x="0" y="80" name="addra[9:0]" />
<pin polarity="Input" x="0" y="112" name="dina[49:0]" />
<pin polarity="Input" x="0" y="144" name="ena" />
<pin polarity="Input" x="0" y="208" name="wea[0:0]" />
<pin polarity="Input" x="0" y="272" name="clka" />
<pin polarity="Input" x="0" y="432" name="addrb[9:0]" />
<pin polarity="Input" x="0" y="464" name="dinb[49:0]" />
<pin polarity="Input" x="0" y="496" name="enb" />
<pin polarity="Input" x="0" y="560" name="web[0:0]" />
<pin polarity="Input" x="0" y="624" name="clkb" />
<pin polarity="Output" x="576" y="80" name="douta[49:0]" />
<pin polarity="Output" x="576" y="368" name="doutb[49:0]" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">L2WayRAM</text>
<rect width="512" x="32" y="32" height="1344" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[9:0]" />
<line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin dina[49:0]" />
<line x2="32" y1="144" y2="144" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin ena" />
<line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin wea[0:0]" />
<line x2="32" y1="272" y2="272" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
<line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[9:0]" />
<line x2="32" y1="464" y2="464" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="464" type="pin dinb[49:0]" />
<line x2="32" y1="496" y2="496" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="496" type="pin enb" />
<line x2="32" y1="560" y2="560" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="560" type="pin web[0:0]" />
<line x2="32" y1="624" y2="624" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[49:0]" />
<line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[49:0]" />
</graph>
</symbol>

194
fpga/ipcore_dir/L2WayRAM.v Normal file
View File

@ -0,0 +1,194 @@
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2021 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file L2WayRAM.v when simulating
// the core, L2WayRAM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module L2WayRAM(
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [0 : 0] wea;
input [9 : 0] addra;
input [49 : 0] dina;
output [49 : 0] douta;
input clkb;
input enb;
input [0 : 0] web;
input [9 : 0] addrb;
input [49 : 0] dinb;
output [49 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(50),
.C_READ_WIDTH_B(50),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(50),
.C_WRITE_WIDTH_B(50),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule

70
fpga/ipcore_dir/L2WayRAM.veo Normal file
View File

@ -0,0 +1,70 @@
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2021 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.3 *
* *
* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
* direct drop-in replacement. It should be used in all new Xilinx *
* designs. The core supports RAM and ROM functions over a wide range of *
* widths and depths. Use this core to generate block memories with *
* symmetric or asymmetric read and write port widths, as well as cores *
* which can perform simultaneous write operations to separate *
* locations, and simultaneous read operations from the same location. *
* For more information on differences in interface and feature support *
* between this core and the Dual Port Block Memory and Single Port *
* Block Memory LogiCOREs, please consult the data sheet. *
*******************************************************************************/
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
L2WayRAM your_instance_name (
.clka(clka), // input clka
.ena(ena), // input ena
.wea(wea), // input [0 : 0] wea
.addra(addra), // input [9 : 0] addra
.dina(dina), // input [49 : 0] dina
.douta(douta), // output [49 : 0] douta
.clkb(clkb), // input clkb
.enb(enb), // input enb
.web(web), // input [0 : 0] web
.addrb(addrb), // input [9 : 0] addrb
.dinb(dinb), // input [49 : 0] dinb
.doutb(doutb) // output [49 : 0] doutb
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file L2WayRAM.v when simulating
// the core, L2WayRAM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

108
fpga/ipcore_dir/L2WayRAM.xco Normal file
View File

@ -0,0 +1,108 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Mon Nov 01 09:39:48 2021
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ftg256
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=L2WayRAM
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_32bit_address=false
CSET enable_a=Use_ENA_Pin
CSET enable_b=Use_ENB_Pin
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET mem_file=no_Mem_file_loaded
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=READ_FIRST
CSET operating_mode_b=READ_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=50
CSET read_width_b=50
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_bram_block=Stand_Alone
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=1024
CSET write_width_a=50
CSET write_width_b=50
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T16:22:25Z
# END Extra information
GENERATE
# CRC: 16400b8

73
fpga/ipcore_dir/L2WayRAM.xise Normal file
View File

@ -0,0 +1,73 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="L2WayRAM.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="L2WayRAM.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|L2WayRAM" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="L2WayRAM.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/L2WayRAM" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ftg256" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="L2WayRAM" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-11-01T05:40:35" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BCE6173C9B444AF498E2AE133C1C2EEF" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

213
fpga/ipcore_dir/L2WayRAM/blk_mem_gen_v7_3_readme.txt Normal file
View File

@ -0,0 +1,213 @@
Core name: Xilinx LogiCORE Block Memory Generator
Version: 7.3 Rev 1
Release: ISE 14.4 / Vivado 2012.4
Release Date: October 16, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
All Virtex-5 devices
All Spartan-3 devices
All Virtex-4 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- ISE 14.4 software support
3.2 Vivado
- 2012.4 software support
................................................................................
4. RESOLVED ISSUES
The following issues are resolved in Block Memory Generator v7.3:
4.1 ISE
4.2 Vivado
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
The following are known issues for v7.3 of this core at time of release:
1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
3. Core does not generate for large memories. Depending on the
machine the ISE CORE Generator software runs on, the maximum size of the memory that
can be generated will vary. For example, a Dual Pentium-4 server
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
- CR 415768
- AR 24034
5.2 Vivado
The following are known issues for v7.3 of this core at time of release:
The most recent information, including known issues, workarounds, and resolutions for
this version is provided in the IP Release Notes User Guide located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
12/16/2012 Xilinx, Inc. 7.3 Rev 1 ISE 14.4 and Vivado 2012.4 support;
10/16/2012 Xilinx, Inc. 7.3 ISE 14.3 and Vivado 2012.3 support;
07/25/2012 Xilinx, Inc. 7.2 ISE 14.2 and Vivado 2012.2 support;
04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
Device support; Automotive Spartan 3A
DSP device support
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
01/2006 Xilinx, Inc. 1.1 Initial release
================================================================================
8. Legal Disclaimer
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

224
fpga/ipcore_dir/L2WayRAM/doc/blk_mem_gen_v7_3_vinfo.html Normal file
View File

@ -0,0 +1,224 @@
<HTML>
<HEAD>
<TITLE>blk_mem_gen_v7_3_vinfo</TITLE>
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
</HEAD>
<BODY>
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
Core name: Xilinx LogiCORE Block Memory Generator
Version: 7.3 Rev 1
Release: ISE 14.4 / Vivado 2012.4
Release Date: October 16, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
For system requirements:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3
solution. For the latest core updates, see the product page at:
<A HREF="http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm">www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm</A>
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
All Virtex-5 devices
All Spartan-3 devices
All Virtex-4 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- ISE 14.4 software support
3.2 Vivado
- 2012.4 software support
................................................................................
4. RESOLVED ISSUES
The following issues are resolved in Block Memory Generator v7.3:
4.1 ISE
4.2 Vivado
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
The following are known issues for v7.3 of this core at time of release:
1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
3. Core does not generate for large memories. Depending on the
machine the ISE CORE Generator software runs on, the maximum size of the memory that
can be generated will vary. For example, a Dual Pentium-4 server
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
- CR 415768
- AR 24034
5.2 Vivado
The following are known issues for v7.3 of this core at time of release:
The most recent information, including known issues, workarounds, and resolutions for
this version is provided in the IP Release Notes User Guide located at
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
12/16/2012 Xilinx, Inc. 7.3 Rev 1 ISE 14.4 and Vivado 2012.4 support;
10/16/2012 Xilinx, Inc. 7.3 ISE 14.3 and Vivado 2012.3 support;
07/25/2012 Xilinx, Inc. 7.2 ISE 14.2 and Vivado 2012.2 support;
04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
Device support; Automotive Spartan 3A
DSP device support
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
01/2006 Xilinx, Inc. 1.1 Initial release
================================================================================
8. Legal Disclaimer
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
</FONT>
</PRE>
</BODY>
</HTML>

BIN
fpga/ipcore_dir/L2WayRAM/doc/pg058-blk-mem-gen.pdf Normal file
View File

Binary file not shown.

61
fpga/ipcore_dir/L2WayRAM/example_design/L2WayRAM_exdes.ucf Normal file
View File

@ -0,0 +1,61 @@
################################################################################
#
# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Tx Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "CLKA" TNM_NET = "CLKA";
NET "CLKB" TNM_NET = "CLKB";
TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ;
TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ;
################################################################################

203
fpga/ipcore_dir/L2WayRAM/example_design/L2WayRAM_exdes.vhd Normal file
View File

@ -0,0 +1,203 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: L2WayRAM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY L2WayRAM_exdes IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END L2WayRAM_exdes;
ARCHITECTURE xilinx OF L2WayRAM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT L2WayRAM IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : L2WayRAM
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;

56
fpga/ipcore_dir/L2WayRAM/example_design/L2WayRAM_exdes.xdc Normal file
View File

@ -0,0 +1,56 @@
################################################################################
#
# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ]
################################################################################

291
fpga/ipcore_dir/L2WayRAM/example_design/L2WayRAM_prod.vhd Normal file
View File

@ -0,0 +1,291 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: L2WayRAM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : READ_FIRST
-- C_WRITE_WIDTH_A : 50
-- C_READ_WIDTH_A : 50
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : READ_FIRST
-- C_WRITE_WIDTH_B : 50
-- C_READ_WIDTH_B : 50
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY L2WayRAM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END L2WayRAM_prod;
ARCHITECTURE xilinx OF L2WayRAM_prod IS
COMPONENT L2WayRAM_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : L2WayRAM_exdes
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;

48
fpga/ipcore_dir/L2WayRAM/implement/implement.bat Normal file
View File

@ -0,0 +1,48 @@
rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
copy L2WayRAM_exdes.ngc .\results\
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\L2WayRAM.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\L2WayRAM_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6slx9-ftg256-2 L2WayRAM_exdes
echo 'Running map'
map L2WayRAM_exdes -o mapped.ncd -pr i
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm L2WayRAM_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v

48
fpga/ipcore_dir/L2WayRAM/implement/implement.sh Normal file
View File

@ -0,0 +1,48 @@
#!/bin/sh
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp L2WayRAM_exdes.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../L2WayRAM.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/L2WayRAM_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6slx9-ftg256-2 L2WayRAM_exdes
echo 'Running map'
map L2WayRAM_exdes -o mapped.ncd -pr i
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm L2WayRAM_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v

55
fpga/ipcore_dir/L2WayRAM/implement/planAhead_ise.bat Normal file
View File

@ -0,0 +1,55 @@
#!/bin/sh
rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem -----------------------------------------------------------------------------
rem Script to synthesize and implement the Coregen FIFO Generator
rem -----------------------------------------------------------------------------
rmdir /S /Q results
mkdir results
cd results
copy ..\..\..\L2WayRAM.ngc .
planAhead -mode batch -source ..\planAhead_ise.tcl

55
fpga/ipcore_dir/L2WayRAM/implement/planAhead_ise.sh Normal file
View File

@ -0,0 +1,55 @@
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#-----------------------------------------------------------------------------
# Script to synthesize and implement the Coregen FIFO Generator
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
cp ../../../L2WayRAM.ngc .
planAhead -mode batch -source ../planAhead_ise.tcl

67
fpga/ipcore_dir/L2WayRAM/implement/planAhead_ise.tcl Normal file
View File

@ -0,0 +1,67 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set device xc6slx9ftg256-2
set projName L2WayRAM
set design L2WayRAM
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module L2WayRAM_exdes
add_files -norecurse {../../example_design/L2WayRAM_exdes.vhd}
add_files -norecurse {./L2WayRAM.ngc}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/L2WayRAM_exdes.xdc}
set_property top L2WayRAM_exdes [get_property srcset [current_run]]
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module L2WayRAM_exdes -file routed.sdf
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module L2WayRAM_exdes routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file report.drc
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}

1
fpga/ipcore_dir/L2WayRAM/implement/xst.prj Normal file
View File

@ -0,0 +1 @@
work ../example_design/L2WayRAM_exdes.vhd

13
fpga/ipcore_dir/L2WayRAM/implement/xst.scr Normal file
View File

@ -0,0 +1,13 @@
run
-ifmt VHDL
-ent L2WayRAM_exdes
-p xc6slx9-ftg256-2
-ifn xst.prj
-write_timing_constraints No
-iobuf YES
-max_fanout 100
-ofn L2WayRAM_exdes
-ofmt NGC
-bus_delimiter ()
-hierarchy_separator /
-case Maintain

380
fpga/ipcore_dir/L2WayRAM/simulation/L2WayRAM_synth.vhd Normal file
View File

@ -0,0 +1,380 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: L2WayRAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY L2WayRAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE L2WayRAM_synth_ARCH OF L2WayRAM_synth IS
COMPONENT L2WayRAM_exdes
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(49 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ENB: STD_LOGIC := '0';
SIGNAL ENB_R: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 49 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 49 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(49 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 50,
READ_WIDTH => 50 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 50,
READ_WIDTH => 50 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
ENA => ENA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
ENB => ENB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ENB_R <= '0' AFTER 50 ns;
WEB_R <= (OTHERS=>'0') AFTER 50 ns;
DINB_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
ENB_R <= ENB AFTER 50 ns;
WEB_R <= WEB AFTER 50 ns;
DINB_R <= DINB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: L2WayRAM_exdes PORT MAP (
--Port A
ENA => ENA_R,
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB_R,
WEB => WEB_R,
ADDRB => ADDRB_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;

142
fpga/ipcore_dir/L2WayRAM/simulation/L2WayRAM_tb.vhd Normal file
View File

@ -0,0 +1,142 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: L2WayRAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY L2WayRAM_tb IS
END ENTITY;
ARCHITECTURE L2WayRAM_tb_ARCH OF L2WayRAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
L2WayRAM_synth_inst:ENTITY work.L2WayRAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;

117
fpga/ipcore_dir/L2WayRAM/simulation/addr_gen.vhd Normal file
View File

@ -0,0 +1,117 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;

535
fpga/ipcore_dir/L2WayRAM/simulation/bmg_stim_gen.vhd Normal file
View File

@ -0,0 +1,535 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
ENB : OUT STD_LOGIC :='0';
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(50,50);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(50,50);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(1024,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(9 DOWNTO 0) <= WRITE_ADDR_A(9 DOWNTO 0);
READ_ADDR_INT_A(9 DOWNTO 0) <= READ_ADDR_A(9 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(9 DOWNTO 0) <= WRITE_ADDR_B(9 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(9 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(9 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>50,
DOUT_WIDTH => 50,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>50,
DOUT_WIDTH =>50 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
ENA <= DO_READ_A OR DO_WRITE_A ;
ENB <= DO_READ_B OR DO_WRITE_B ;
WEA(0) <= IF_THEN_ELSE(DO_WRITE_A='1','1','0') ;
WEB(0) <= IF_THEN_ELSE(DO_WRITE_B='1','1','0') ;
END ARCHITECTURE;

200
fpga/ipcore_dir/L2WayRAM/simulation/bmg_tb_pkg.vhd Normal file
View File

@ -0,0 +1,200 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;

161
fpga/ipcore_dir/L2WayRAM/simulation/checker.vhd Normal file
View File

@ -0,0 +1,161 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;

140
fpga/ipcore_dir/L2WayRAM/simulation/data_gen.vhd Normal file
View File

@ -0,0 +1,140 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;

69
fpga/ipcore_dir/L2WayRAM/simulation/functional/simcmds.tcl Normal file
View File

@ -0,0 +1,69 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
wcfg new
isim set radix hex
wave add /L2WayRAM_tb/status
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/CLKA
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/ADDRA
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/DINA
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/WEA
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/ENA
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/DOUTA
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/CLKB
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/ADDRB
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/ENB
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/DINB
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/WEB
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/DOUTB
run all
quit

69
fpga/ipcore_dir/L2WayRAM/simulation/functional/simulate_isim.bat Normal file
View File

@ -0,0 +1,69 @@
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
::
:: This file contains confidential and proprietary information
:: of Xilinx, Inc. and is protected under U.S. and
:: international copyright and other intellectual property
:: laws.
::
:: DISCLAIMER
:: This disclaimer is not a license and does not grant any
:: rights to the materials distributed herewith. Except as
:: otherwise provided in a valid license issued to you by
:: Xilinx, and to the maximum extent permitted by applicable
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
:: (2) Xilinx shall not be liable (whether in contract or tort,
:: including negligence, or under any other theory of
:: liability) for any loss or damage of any kind or nature
:: related to, arising under or in connection with these
:: materials, including for any direct, or any indirect,
:: special, incidental, or consequential loss or damage
:: (including loss of data, profits, goodwill, or any type of
:: loss or damage suffered as a result of any action brought
:: by a third party) even if such damage or loss was
:: reasonably foreseeable or Xilinx had been advised of the
:: possibility of the same.
::
:: CRITICAL APPLICATIONS
:: Xilinx products are not designed or intended to be fail-
:: safe, or for use in any application requiring fail-safe
:: performance, such as life-support or safety devices or
:: systems, Class III medical devices, nuclear facilities,
:: applications related to the deployment of airbags, or any
:: other applications that could lead to death, personal
:: injury, or severe property or environmental damage
:: (individually and collectively, "Critical
:: Applications"). Customer assumes the sole risk and
:: liability of any use of Xilinx products in Critical
:: Applications, subject only to applicable laws and
:: regulations governing limitations on product liability.
::
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
:: PART OF THIS FILE AT ALL TIMES.
::--------------------------------------------------------------------------------
echo "Compiling Core Verilog UNISIM/Behavioral model"
vlogcomp -work work ..\..\..\L2WayRAM.v
vhpcomp -work work ..\..\example_design\L2WayRAM_exdes.vhd
echo "Compiling Test Bench Files"
vhpcomp -work work ..\bmg_tb_pkg.vhd
vhpcomp -work work ..\random.vhd
vhpcomp -work work ..\data_gen.vhd
vhpcomp -work work ..\addr_gen.vhd
vhpcomp -work work ..\checker.vhd
vhpcomp -work work ..\bmg_stim_gen.vhd
vhpcomp -work work ..\L2WayRAM_synth.vhd
vhpcomp -work work ..\L2WayRAM_tb.vhd
vlogcomp -work work $XILINX\verilog\src\glbl.v
fuse work.L2WayRAM_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o L2WayRAM_tb.exe
.\L2WayRAM_tb.exe -gui -tclbatch simcmds.tcl

3
fpga/ipcore_dir/L2WayRAM/simulation/functional/simulate_mti.bat Normal file
View File

@ -0,0 +1,3 @@
#--------------------------------------------------------------------------------
vsim -c -do simulate_mti.do

76
fpga/ipcore_dir/L2WayRAM/simulation/functional/simulate_mti.do Normal file
View File

@ -0,0 +1,76 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#--------------------------------------------------------------------------------
vlib work
vmap work work
echo "Compiling Core Verilog UNISIM/Behavioral model"
vlog -work work ../../../L2WayRAM.v
vcom -work work ../../example_design/L2WayRAM_exdes.vhd
echo "Compiling Test Bench Files"
vcom -work work ../bmg_tb_pkg.vhd
vcom -work work ../random.vhd
vcom -work work ../data_gen.vhd
vcom -work work ../addr_gen.vhd
vcom -work work ../checker.vhd
vcom -work work ../bmg_stim_gen.vhd
vcom -work work ../L2WayRAM_synth.vhd
vcom -work work ../L2WayRAM_tb.vhd
vlog -work work $env(XILINX)/verilog/src/glbl.v
vsim -novopt -t ps -L XilinxCoreLib_ver -L unisims_ver glbl work.L2WayRAM_tb
#Disabled waveform to save the disk space
add log -r /*
#Ignore integer warnings at time 0
set StdArithNoWarnings 1
run 0
set StdArithNoWarnings 0
run -all

3
fpga/ipcore_dir/L2WayRAM/simulation/functional/simulate_mti.sh Normal file
View File

@ -0,0 +1,3 @@
#--------------------------------------------------------------------------------
vsim -c -do simulate_mti.do

71
fpga/ipcore_dir/L2WayRAM/simulation/functional/simulate_ncsim.sh Normal file
View File

@ -0,0 +1,71 @@
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#--------------------------------------------------------------------------------
mkdir work
echo "Compiling Core Verilog UNISIM/Behavioral model"
ncvlog -work work ../../../L2WayRAM.v
ncvhdl -v93 -work work ../../example_design/L2WayRAM_exdes.vhd
echo "Compiling Test Bench Files"
ncvhdl -v93 -work work ../bmg_tb_pkg.vhd
ncvhdl -v93 -work work ../random.vhd
ncvhdl -v93 -work work ../data_gen.vhd
ncvhdl -v93 -work work ../addr_gen.vhd
ncvhdl -v93 -work work ../checker.vhd
ncvhdl -v93 -work work ../bmg_stim_gen.vhd
ncvhdl -v93 -work work ../L2WayRAM_synth.vhd
ncvhdl -v93 -work work ../L2WayRAM_tb.vhd
echo "Elaborating Design"
ncvlog -work work $XILINX/verilog/src/glbl.v
ncelab -access +rwc glbl work.L2WayRAM_tb
echo "Simulating Design"
ncsim -gui -input @"simvision -input wave_ncsim.sv" work.L2WayRAM_tb

70
fpga/ipcore_dir/L2WayRAM/simulation/functional/simulate_vcs.sh Normal file
View File

@ -0,0 +1,70 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#--------------------------------------------------------------------------------
#!/bin/sh
rm -rf simv* csrc DVEfiles AN.DB
echo "Compiling Core Verilog UNISIM/Behavioral model"
vlogan +v2k ../../../L2WayRAM.v
vhdlan ../../example_design/L2WayRAM_exdes.vhd
echo "Compiling Test Bench Files"
vhdlan ../bmg_tb_pkg.vhd
vhdlan ../random.vhd
vhdlan ../data_gen.vhd
vhdlan ../addr_gen.vhd
vhdlan ../checker.vhd
vhdlan ../bmg_stim_gen.vhd
vhdlan ../L2WayRAM_synth.vhd
vhdlan ../L2WayRAM_tb.vhd
echo "Elaborating Design"
vlogan +v2k $XILINX/verilog/src/glbl.v
vcs +vcs+lic+wait -debug L2WayRAM_tb glbl
echo "Simulating Design"
./simv -ucli -i ucli_commands.key
dve -session vcs_session.tcl

4
fpga/ipcore_dir/L2WayRAM/simulation/functional/ucli_commands.key Normal file
View File

@ -0,0 +1,4 @@
dump -file bmg_vcs.vpd -type VPD
dump -add L2WayRAM_tb
run
quit

89
fpga/ipcore_dir/L2WayRAM/simulation/functional/vcs_session.tcl Normal file
View File

@ -0,0 +1,89 @@
#--------------------------------------------------------------------------------
#--
#-- BMG core Demo Testbench
#--
#--------------------------------------------------------------------------------
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Filename: vcs_session.tcl
#
# Description:
# This is the VCS wave form file.
#
#--------------------------------------------------------------------------------
if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
gui_open_db -design V1 -file bmg_vcs.vpd -nosource
}
gui_set_precision 1ps
gui_set_time_units 1ps
gui_open_window Wave
gui_sg_create L2WayRAM_Group
gui_list_add_group -id Wave.1 {L2WayRAM_Group}
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/status
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/CLKA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ADDRA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DINA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/WEA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ENA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DOUTA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/CLKB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ADDRB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ENB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DINB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/WEB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DOUTB
gui_zoom -window Wave.1 -full

42
fpga/ipcore_dir/L2WayRAM/simulation/functional/wave_mti.do Normal file
View File

@ -0,0 +1,42 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /L2WayRAM_tb/status
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/CLKA
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ADDRA
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DINA
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/WEA
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ENA
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DOUTA
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/CLKB
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ADDRB
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ENB
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DINB
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/WEB
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DOUTB
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
configure wave -namecolwidth 197
configure wave -valuecolwidth 106
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {9464063 ps}

27
fpga/ipcore_dir/L2WayRAM/simulation/functional/wave_ncsim.sv Normal file
View File

@ -0,0 +1,27 @@
window new WaveWindow -name "Waves for BMG Example Design"
waveform using "Waves for BMG Example Design"
waveform add -signals /L2WayRAM_tb/status
waveform add -signals /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/CLKA
waveform add -signals /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ADDRA
waveform add -signals /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DINA
waveform add -signals /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/WEA
waveform add -signals /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ENA
waveform add -signals /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DOUTA
waveform add -signals /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/CLKB
waveform add -signals /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ADDRB
waveform add -signals /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ENB
waveform add -signals /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DINB
waveform add -signals /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/WEB
waveform add -signals /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DOUTB
console submit -using simulator -wait no "run"

112
fpga/ipcore_dir/L2WayRAM/simulation/random.vhd Normal file
View File

@ -0,0 +1,112 @@
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;

69
fpga/ipcore_dir/L2WayRAM/simulation/timing/simcmds.tcl Normal file
View File

@ -0,0 +1,69 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
wcfg new
isim set radix hex
wave add /L2WayRAM_tb/status
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/CLKA
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/ADDRA
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/DINA
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/WEA
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/ENA
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/DOUTA
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/CLKB
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/ADDRB
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/ENB
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/DINB
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/WEB
wave add /L2WayRAM_tb/L2WayRAM_synth_inst/BMG_PORT/DOUTB
run all
quit

65
fpga/ipcore_dir/L2WayRAM/simulation/timing/simulate_isim.bat Normal file
View File

@ -0,0 +1,65 @@
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
::
:: This file contains confidential and proprietary information
:: of Xilinx, Inc. and is protected under U.S. and
:: international copyright and other intellectual property
:: laws.
::
:: DISCLAIMER
:: This disclaimer is not a license and does not grant any
:: rights to the materials distributed herewith. Except as
:: otherwise provided in a valid license issued to you by
:: Xilinx, and to the maximum extent permitted by applicable
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
:: (2) Xilinx shall not be liable (whether in contract or tort,
:: including negligence, or under any other theory of
:: liability) for any loss or damage of any kind or nature
:: related to, arising under or in connection with these
:: materials, including for any direct, or any indirect,
:: special, incidental, or consequential loss or damage
:: (including loss of data, profits, goodwill, or any type of
:: loss or damage suffered as a result of any action brought
:: by a third party) even if such damage or loss was
:: reasonably foreseeable or Xilinx had been advised of the
:: possibility of the same.
::
:: CRITICAL APPLICATIONS
:: Xilinx products are not designed or intended to be fail-
:: safe, or for use in any application requiring fail-safe
:: performance, such as life-support or safety devices or
:: systems, Class III medical devices, nuclear facilities,
:: applications related to the deployment of airbags, or any
:: other applications that could lead to death, personal
:: injury, or severe property or environmental damage
:: (individually and collectively, "Critical
:: Applications"). Customer assumes the sole risk and
:: liability of any use of Xilinx products in Critical
:: Applications, subject only to applicable laws and
:: regulations governing limitations on product liability.
::
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
:: PART OF THIS FILE AT ALL TIMES.
::--------------------------------------------------------------------------------
vlogcomp -work work ..\..\implement\results\routed.v
echo "Compiling Test Bench Files"
vhpcomp -work work ..\bmg_tb_pkg.vhd
vhpcomp -work work ..\random.vhd
vhpcomp -work work ..\data_gen.vhd
vhpcomp -work work ..\addr_gen.vhd
vhpcomp -work work ..\checker.vhd
vhpcomp -work work ..\bmg_stim_gen.vhd
vhpcomp -work work ..\L2WayRAM_synth.vhd
vhpcomp -work work ..\L2WayRAM_tb.vhd
fuse -L simprims_ver work.L2WayRAM_tb work.glbl -o L2WayRAM_tb.exe
.\L2WayRAM_tb.exe -sdftyp /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port=..\..\implement\results\routed.sdf -gui -tclbatch simcmds.tcl

3
fpga/ipcore_dir/L2WayRAM/simulation/timing/simulate_mti.bat Normal file
View File

@ -0,0 +1,3 @@
#--------------------------------------------------------------------------------
vsim -c -do simulate_mti.do

75
fpga/ipcore_dir/L2WayRAM/simulation/timing/simulate_mti.do Normal file
View File

@ -0,0 +1,75 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set work work
#--------------------------------------------------------------------------------
vlib work
vmap work work
echo "Compiling Core Verilog UNISIM/Behavioral model"
vlog -work work ../../implement/results/routed.v
echo "Compiling Test Bench Files"
vcom -work work ../bmg_tb_pkg.vhd
vcom -work work ../random.vhd
vcom -work work ../data_gen.vhd
vcom -work work ../addr_gen.vhd
vcom -work work ../checker.vhd
vcom -work work ../bmg_stim_gen.vhd
vcom -work work ../L2WayRAM_synth.vhd
vcom -work work ../L2WayRAM_tb.vhd
vsim -novopt -t ps -L simprims_ver +transport_int_delays -sdftyp /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port=../../implement/results/routed.sdf $work.L2WayRAM_tb $work.glbl -novopt
#Disabled waveform to save the disk space
add log -r /*
#Ignore integer warnings at time 0
set StdArithNoWarnings 1
run 0
set StdArithNoWarnings 0
run -all

3
fpga/ipcore_dir/L2WayRAM/simulation/timing/simulate_mti.sh Normal file
View File

@ -0,0 +1,3 @@
#--------------------------------------------------------------------------------
vsim -c -do simulate_mti.do

78
fpga/ipcore_dir/L2WayRAM/simulation/timing/simulate_ncsim.sh Normal file
View File

@ -0,0 +1,78 @@
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set work work
#--------------------------------------------------------------------------------
mkdir work
ncvlog -work work ../../implement/results/routed.v
echo "Compiling Test Bench Files"
ncvhdl -v93 -work work ../bmg_tb_pkg.vhd
ncvhdl -v93 -work work ../random.vhd
ncvhdl -v93 -work work ../data_gen.vhd
ncvhdl -v93 -work work ../addr_gen.vhd
ncvhdl -v93 -work work ../checker.vhd
ncvhdl -v93 -work work ../bmg_stim_gen.vhd
ncvhdl -v93 -work work ../L2WayRAM_synth.vhd
ncvhdl -v93 -work work ../L2WayRAM_tb.vhd
echo "Compiling SDF file"
ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X
echo "Generating SDF command file"
echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd
echo 'SCOPE = :L2WayRAM_synth_inst:BMG_PORT,' >> sdf.cmd
echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd
echo "Elaborating Design"
ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd $work.L2WayRAM_tb
echo "Simulating Design"
ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.L2WayRAM_tb

70
fpga/ipcore_dir/L2WayRAM/simulation/timing/simulate_vcs.sh Normal file
View File

@ -0,0 +1,70 @@
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#--------------------------------------------------------------------------------
#!/bin/sh
rm -rf simv* csrc DVEfiles AN.DB
echo "Compiling Core Verilog UNISIM/Behavioral model"
vlogan +v2k ../../implement/results/routed.v
echo "Compiling Test Bench Files"
vhdlan ../bmg_tb_pkg.vhd
vhdlan ../random.vhd
vhdlan ../data_gen.vhd
vhdlan ../addr_gen.vhd
vhdlan ../checker.vhd
vhdlan ../bmg_stim_gen.vhd
vhdlan ../L2WayRAM_synth.vhd
vhdlan ../L2WayRAM_tb.vhd
echo "Elaborating Design"
vcs +neg_tchk +vcs+lic+wait -debug L2WayRAM_tb glbl
echo "Simulating Design"
./simv -ucli -i ucli_commands.key
dve -session vcs_session.tcl

4
fpga/ipcore_dir/L2WayRAM/simulation/timing/ucli_commands.key Normal file
View File

@ -0,0 +1,4 @@
dump -file bmg_vcs.vpd -type VPD
dump -add L2WayRAM_tb
run
quit

89
fpga/ipcore_dir/L2WayRAM/simulation/timing/vcs_session.tcl Normal file
View File

@ -0,0 +1,89 @@
#--------------------------------------------------------------------------------
#--
#-- BMG Generator v8.4 Core Demo Testbench
#--
#--------------------------------------------------------------------------------
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Filename: vcs_session.tcl
#
# Description:
# This is the VCS wave form file.
#
#--------------------------------------------------------------------------------
if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
gui_open_db -design V1 -file bmg_vcs.vpd -nosource
}
gui_set_precision 1ps
gui_set_time_units 1ps
gui_open_window Wave
gui_sg_create L2WayRAM_Group
gui_list_add_group -id Wave.1 {L2WayRAM_Group}
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/status
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/CLKA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ADDRA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DINA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/WEA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ENA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DOUTA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/CLKB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ADDRB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ENB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DINB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/WEB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DOUTB
gui_zoom -window Wave.1 -full

42
fpga/ipcore_dir/L2WayRAM/simulation/timing/wave_mti.do Normal file
View File

@ -0,0 +1,42 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /L2WayRAM_tb/status
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/CLKA
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ADDRA
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DINA
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/WEA
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ENA
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DOUTA
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/CLKB
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ADDRB
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ENB
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DINB
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/WEB
add wave -noupdate /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DOUTB
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {9464063 ps}

Some files were not shown because too many files have changed in this diff Show More