mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2025-04-07 21:37:12 +00:00
idk
This commit is contained in:
Zane Kaminski
parent
609e06be1c
commit
374d7663d3
10
.gitignore
vendored
10
.gitignore
vendored
@ -15,15 +15,5 @@ _autosave-*
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*-save.kicad_pcb
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fp-info-cache
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# Netlist files (exported from Eeschema)
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*.net
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# Autorouter files (exported from Pcbnew)
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*.dsn
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*.ses
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# Exported BOM files
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*.xml
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*.csv
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*.DS_Store
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@ -18,7 +18,7 @@
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module CLKGEN(
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module ClkGen(
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input CLKIN,
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input CLKFB_IN,
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output CLKFB_OUT,
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@ -29,7 +29,7 @@ module CLKGEN(
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output RAMCLK0,
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output RAMCLK1);
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CLK instance_name (
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PLL pll (
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.CLKIN(CLKIN),
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.CLKFB_IN(CLKFB_IN),
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.CLKFB_OUT(CLKFB_OUT),
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82
fpga/ClkGen_summary.html
Normal file
82
fpga/ClkGen_summary.html
Normal file
@ -0,0 +1,82 @@
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
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<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='4'><B>ClkGen Project Status (10/31/2021 - 15:38:40)</B></TD></TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
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<TD>WarpLC.xise</TD>
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<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
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<TD> No Errors </TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
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<TD>ClkGen</TD>
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<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
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<TD>Placed and Routed</TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
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<TD>xc6slx9-2ftg256</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
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<TD>Balanced</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
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<TD>
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</TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
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<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
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<TD> </TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
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<TD> </TD>
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</TR>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
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<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
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<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
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<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
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<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Oct 31 14:40:54 2021</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Oct 31 15:38:26 2021</TD></TR>
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</TABLE>
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<br><center><b>Date Generated:</b> 10/31/2021 - 15:38:40</center>
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</BODY></HTML>
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25
fpga/L2Cache.v
Normal file
25
fpga/L2Cache.v
Normal file
@ -0,0 +1,25 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 09:44:08 10/31/2021
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// Design Name:
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// Module Name: L2Cache
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module L2Cache(
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);
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endmodule
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77
fpga/PLL.ucf
77
fpga/PLL.ucf
@ -1,39 +1,44 @@
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NET "CLKIN" TNM_NET = CLKIN;
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#NET "FSB_A[31]" TNM_NET = FSB_A;
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#NET "FSB_A[30]" TNM_NET = FSB_A;
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#NET "FSB_A[29]" TNM_NET = FSB_A;
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#NET "FSB_A[28]" TNM_NET = FSB_A;
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NET "FSB_A[27]" TNM_NET = FSB_A;
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NET "FSB_A[26]" TNM_NET = FSB_A;
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NET "FSB_A[25]" TNM_NET = FSB_A;
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NET "FSB_A[24]" TNM_NET = FSB_A;
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NET "FSB_A[23]" TNM_NET = FSB_A;
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NET "FSB_A[22]" TNM_NET = FSB_A;
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NET "FSB_A[21]" TNM_NET = FSB_A;
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NET "FSB_A[20]" TNM_NET = FSB_A;
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NET "FSB_A[19]" TNM_NET = FSB_A;
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NET "FSB_A[18]" TNM_NET = FSB_A;
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NET "FSB_A[17]" TNM_NET = FSB_A;
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NET "FSB_A[16]" TNM_NET = FSB_A;
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NET "FSB_A[15]" TNM_NET = FSB_A;
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NET "FSB_A[14]" TNM_NET = FSB_A;
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NET "FSB_A[13]" TNM_NET = FSB_A;
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NET "FSB_A[12]" TNM_NET = FSB_A;
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NET "FSB_A[11]" TNM_NET = FSB_A;
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NET "FSB_A[10]" TNM_NET = FSB_A;
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NET "FSB_A[9]" TNM_NET = FSB_A;
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NET "FSB_A[8]" TNM_NET = FSB_A;
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NET "FSB_A[7]" TNM_NET = FSB_A;
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NET "FSB_A[6]" TNM_NET = FSB_A;
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NET "FSB_A[5]" TNM_NET = FSB_A;
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NET "FSB_A[4]" TNM_NET = FSB_A;
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NET "FSB_A[3]" TNM_NET = FSB_A;
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NET "FSB_A[2]" TNM_NET = FSB_A;
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#NET "FSB_A[1]" TNM_NET = FSB_A;
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#NET "FSB_A[0]" TNM_NET = FSB_A;
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NET "CPU_nSTERM" TNM_NET = CPU_nSTERM;
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NET CLKFB_OUT FEEDBACK = 160ps NET CLKFB_IN;
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NET CLKIN PERIOD = 30ns HIGH;
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TIMESPEC TS_CLKIN = PERIOD "CLKIN" 30 ns HIGH 50%;
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NET INt OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[31] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[30] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[29] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[28] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[27] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[26] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[25] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[24] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[23] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[22] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[21] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[20] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[19] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[18] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[17] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[16] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[15] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[14] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[13] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[12] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[11] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[10] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[9] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[8] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[7] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
|
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NET FSB_A[6] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
|
||||
NET FSB_A[5] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
|
||||
NET FSB_A[4] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
|
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NET FSB_A[3] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
|
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NET FSB_A[2] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
|
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NET FSB_A[1] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
|
||||
NET FSB_A[0] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
|
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NET CPU_nAS OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
|
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NET OUTt OFFSET = OUT 5ns AFTER CLKIN;
|
||||
#NET "FSB_A[*]" OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
|
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#NET "CPU_nAS" OFFSET = IN 15ns VALID 15ns BEFORE CLKIN;
|
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|
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TIMESPEC TS_CPU_nSTERM_A = FROM "FSB_A" TO "CPU_nSTERM" 15ns;
|
||||
#Created by Constraints Editor (xc6slx9-ftg256-2) - 2021/10/31
|
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|
||||
@ -1,41 +1,53 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 19:13:46 10/30/2021
|
||||
// Design Name:
|
||||
// Module Name: PrefetchBuf
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module PrefetchBuf(
|
||||
input [31:0] RDA,
|
||||
output [31:0] RDD,
|
||||
output Match,
|
||||
input CLK,
|
||||
input [31:0] WRA,
|
||||
input [31:0] WRDin,
|
||||
output [31:0] WRDout,
|
||||
input [3:0] WE,
|
||||
input TS);
|
||||
|
||||
RAM128X1D Way0[55:0] (
|
||||
.DPO(WRDout),
|
||||
.SPO(RDD),
|
||||
.A(WRA[10:2]),
|
||||
.D({A[WRDin[7:0]),
|
||||
.DPRA(RDA),
|
||||
.WCLK(CLK),
|
||||
.WE(WE));
|
||||
module L2Prefetch(
|
||||
input CLK,
|
||||
input CPUCLKr,
|
||||
|
||||
input [28:2] RDA,
|
||||
output [31:0] RDD,
|
||||
output Match,
|
||||
|
||||
input [28:2] WRA,
|
||||
input [31:0] WRD,
|
||||
input WR,
|
||||
input [3:0] WRM,
|
||||
input CLR);
|
||||
|
||||
/* Read Address */
|
||||
wire [20:0] RDATag = RDA[28:7];
|
||||
wire [4:0] RDAIndex = RDA[6:2];
|
||||
|
||||
/* Write Address */
|
||||
wire [20:0] WRATag = WRA[28:7];
|
||||
wire [4:0] WRAIndex = WRA[6:2];
|
||||
|
||||
/* Way 0 Tag & Valid */
|
||||
wire [20:0] RDTag;
|
||||
wire [20:0] TSTag;
|
||||
wire RDValid;
|
||||
wire TSValid;
|
||||
wire RDMatch = RDValid && RDTag==RDATag;
|
||||
wire TSMatch = TSValid && TSTag==RDATag;
|
||||
PrefetchTagRAM Way0Tag (
|
||||
.clk(CLK),
|
||||
.we(WR && (WRM[3:0]==4'b1111 || TSMatch)),
|
||||
.a(WRA[8:2]),
|
||||
.d({~CLR, WRATag[20:0]}),
|
||||
.spo({TSValid, TSTag[20:0]}),
|
||||
.dpra(RDA[8:2]),
|
||||
.dpo({RDValid, RDTag[20:0]}));
|
||||
|
||||
/* Way 0 Data */
|
||||
PrefetchDataRAM Way0Data (
|
||||
.clka(CLK),
|
||||
.ena(WR && (WRM[3:0]==4'b1111 || TSMatch)),
|
||||
.wea(WRM[3:0]),
|
||||
.addra(WRAIndex[4:0]),
|
||||
.dina(WRD[31:0]),
|
||||
.clkb(CLK),
|
||||
.enb(~CPUCLKr),
|
||||
.addrb({2'b00, RDAIndex[4:0]}),
|
||||
.doutb(RDD[31:0]));
|
||||
|
||||
assign Match = RDMatch;
|
||||
|
||||
endmodule
|
||||
|
||||
16
fpga/SizeDecode.v
Normal file
16
fpga/SizeDecode.v
Normal file
@ -0,0 +1,16 @@
|
||||
module SizeDecode(
|
||||
input [1:0] A,
|
||||
input [1:0] SIZ,
|
||||
output [3:0] B);
|
||||
|
||||
assign B[3] = (A[1:0]==2'b00);
|
||||
assign B[2] = (A[1:0]==2'b01) ||
|
||||
(A[1:0]==2'b00 && SIZ[1:0]!=2'b01); // Not 8-bit
|
||||
assign B[1] = (A[1:0]==2'b10) ||
|
||||
(A[1:0]==2'b01 && SIZ[1:0]!=2'b01) || // Not 8-bit
|
||||
(A[1:0]==2'b00 && SIZ[1:0]!=2'b01 && SIZ[1:0]!=2'b10); // Not 8-bit or 16-bit
|
||||
assign B[0] = (A[1:0]==2'b11) ||
|
||||
(A[1:0]==2'b01 && SIZ[1:0]!=2'b01) || // Not 8-bit
|
||||
(A[1:0]==2'b00 && SIZ[1:0]!=2'b01 && SIZ[1:0]!=2'b10) ||
|
||||
(A[1:0]==2'b00 && SIZ[1:0]==2'b00); // 32-bit
|
||||
endmodule
|
||||
@ -1,20 +1,75 @@
|
||||
Release 14.7 ngdbuild P.20131013 (nt)
|
||||
Release 14.7 ngdbuild P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
|
||||
ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2
|
||||
WarpLC.ngc WarpLC.ngd
|
||||
Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
|
||||
-intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p
|
||||
xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
|
||||
Reading NGO file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.ngc" ...
|
||||
Reading NGO file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.ngc" ...
|
||||
Loading design module "ipcore_dir/PrefetchTagRAM.ngc"...
|
||||
Loading design module "ipcore_dir/PrefetchDataRAM.ngc"...
|
||||
Gathering constraint information from source properties...
|
||||
Done.
|
||||
|
||||
Annotating constraints to design from ucf file "PLL.ucf" ...
|
||||
Resolving constraint associations...
|
||||
Checking Constraint Associations...
|
||||
INFO:ConstraintSystem - The Period constraint <NET CLKIN PERIOD = 30ns HIGH;>
|
||||
[PLL.ucf(3)], is specified using the Net Period method which is not
|
||||
recommended. Please use the Timespec PERIOD method.
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nAS" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nAS' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_SIZ<0>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_SIZ<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_SIZ<1>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_SIZ<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<0>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_A<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<1>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_A<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<28>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_A<28>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<29>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_A<29>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<30>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_A<30>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<31>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_A<31>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
INFO:ConstraintSystem:178 - TNM 'CLKIN', used in period specification
|
||||
'TS_CLKIN', was traced into PLL_ADV instance PLL_ADV. The following new TNM
|
||||
groups and period specifications were generated at the PLL_ADV output(s):
|
||||
CLKFBOUT: <TIMESPEC TS_cg_pll_clkfbout = PERIOD "cg_pll_clkfbout" TS_CLKIN
|
||||
HIGH 50%>
|
||||
|
||||
INFO:ConstraintSystem:178 - TNM 'CLKIN', used in period specification
|
||||
'TS_CLKIN', was traced into PLL_ADV instance PLL_ADV. The following new TNM
|
||||
groups and period specifications were generated at the PLL_ADV output(s):
|
||||
CLKOUT0: <TIMESPEC TS_cg_pll_clkout0 = PERIOD "cg_pll_clkout0" TS_CLKIN / 2
|
||||
HIGH 50%>
|
||||
|
||||
Done...
|
||||
|
||||
@ -29,12 +84,12 @@ Partition Implementation Status
|
||||
|
||||
NGDBUILD Design Results Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
Number of warnings: 9
|
||||
|
||||
Total memory usage is 133904 kilobytes
|
||||
Total memory usage is 163932 kilobytes
|
||||
|
||||
Writing NGD file "WarpLC.ngd" ...
|
||||
Total REAL time to NGDBUILD completion: 1 sec
|
||||
Total CPU time to NGDBUILD completion: 1 sec
|
||||
Total REAL time to NGDBUILD completion: 3 sec
|
||||
Total CPU time to NGDBUILD completion: 3 sec
|
||||
|
||||
Writing NGDBUILD log file "WarpLC.bld"...
|
||||
|
||||
@ -501,3 +501,145 @@ ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6s
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-3 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -xe c -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -xe c -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -xe c -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -xe c -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -xe c -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
|
||||
@ -48,6 +48,7 @@
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="WarpLC_map.mrp" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="WarpLC_map.ncd" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="WarpLC_map.ngm" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:fileType="FILE_PSR" xil_pn:name="WarpLC_map.psr"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="WarpLC_map.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="WarpLC_ngdbuild.xrpt"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="WarpLC_pad.csv" xil_pn:subbranch="Par"/>
|
||||
@ -72,45 +73,45 @@
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635544541">
|
||||
<transform xil_pn:end_ts="1635709065" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635709065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3515295135630071778" xil_pn:start_ts="1635544541">
|
||||
<transform xil_pn:end_ts="1635709065" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3515295135630071778" xil_pn:start_ts="1635709065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:in_ck="-7186897629097209311" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4864019295268560826" xil_pn:start_ts="1635544541">
|
||||
<transform xil_pn:end_ts="1635709065" xil_pn:in_ck="-6233175969720765835" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4864019295268560826" xil_pn:start_ts="1635709065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="ipcore_dir/CLK.v"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PLL.v"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PrefetchDataRAM.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PrefetchDataRAM.v"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PrefetchTagRAM.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PrefetchTagRAM.v"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:in_ck="2640051198016270512" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635544541">
|
||||
<transform xil_pn:end_ts="1635709065" xil_pn:in_ck="-4446273774904393470" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635709065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6691162141195559328" xil_pn:start_ts="1635544541">
|
||||
<transform xil_pn:end_ts="1635709065" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6691162141195559328" xil_pn:start_ts="1635709065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:in_ck="2640051198016270512" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745411629038" xil_pn:start_ts="1635544541">
|
||||
<transform xil_pn:end_ts="1635709065" xil_pn:in_ck="-4446273774904393470" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745411629038" xil_pn:start_ts="1635709065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="5917552782042024336" xil_pn:start_ts="1635544541">
|
||||
<transform xil_pn:end_ts="1635709065" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="5917552782042024336" xil_pn:start_ts="1635709065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544781" xil_pn:in_ck="-4595070235146848110" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7414298865524902037" xil_pn:start_ts="1635544776">
|
||||
<transform xil_pn:end_ts="1635709075" xil_pn:in_ck="2132134388199262633" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1250938673410109993" xil_pn:start_ts="1635709065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
<outfile xil_pn:name="WarpLC.lso"/>
|
||||
<outfile xil_pn:name="WarpLC.ngc"/>
|
||||
<outfile xil_pn:name="WarpLC.ngr"/>
|
||||
@ -120,48 +121,47 @@
|
||||
<outfile xil_pn:name="WarpLC.xst"/>
|
||||
<outfile xil_pn:name="WarpLC_xst.xrpt"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544781" xil_pn:in_ck="-7789573454286277367" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704523" xil_pn:start_ts="1635544781">
|
||||
<transform xil_pn:end_ts="1635709075" xil_pn:in_ck="-7789573437496007849" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704523" xil_pn:start_ts="1635709075">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544784" xil_pn:in_ck="5584679923051828355" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2511870374322119143" xil_pn:start_ts="1635544781">
|
||||
<transform xil_pn:end_ts="1635709080" xil_pn:in_ck="5468170433947878565" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2511870374322119143" xil_pn:start_ts="1635709075">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="WarpLC.bld"/>
|
||||
<outfile xil_pn:name="WarpLC.ngd"/>
|
||||
<outfile xil_pn:name="WarpLC_ngdbuild.xrpt"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544789" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="111412226054857016" xil_pn:start_ts="1635544784">
|
||||
<transform xil_pn:end_ts="1635709108" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-5057403149233638808" xil_pn:start_ts="1635709080">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
<outfile xil_pn:name="WarpLC.pcf"/>
|
||||
<outfile xil_pn:name="WarpLC_map.map"/>
|
||||
<outfile xil_pn:name="WarpLC_map.mrp"/>
|
||||
<outfile xil_pn:name="WarpLC_map.ncd"/>
|
||||
<outfile xil_pn:name="WarpLC_map.ngm"/>
|
||||
<outfile xil_pn:name="WarpLC_map.psr"/>
|
||||
<outfile xil_pn:name="WarpLC_map.xrpt"/>
|
||||
<outfile xil_pn:name="WarpLC_summary.xml"/>
|
||||
<outfile xil_pn:name="WarpLC_usage.xml"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544794" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1635544789">
|
||||
<transform xil_pn:end_ts="1635709114" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-5338882351546597350" xil_pn:start_ts="1635709108">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
<outfile xil_pn:name="WarpLC.ncd"/>
|
||||
<outfile xil_pn:name="WarpLC.pad"/>
|
||||
<outfile xil_pn:name="WarpLC.par"/>
|
||||
<outfile xil_pn:name="WarpLC.ptwx"/>
|
||||
<outfile xil_pn:name="WarpLC.unroutes"/>
|
||||
<outfile xil_pn:name="WarpLC.xpi"/>
|
||||
<outfile xil_pn:name="WarpLC_pad.csv"/>
|
||||
<outfile xil_pn:name="WarpLC_pad.txt"/>
|
||||
<outfile xil_pn:name="WarpLC_par.xrpt"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
@ -170,30 +170,31 @@
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544798" xil_pn:in_ck="5584679923051828224" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1635544794">
|
||||
<transform xil_pn:end_ts="1635709120" xil_pn:in_ck="5584679923051828224" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1254017130453672594" xil_pn:start_ts="1635709114">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="WarpLC.twr"/>
|
||||
<outfile xil_pn:name="WarpLC.twx"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635517529" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791352" xil_pn:start_ts="1635517526">
|
||||
<transform xil_pn:end_ts="1635705655" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791352" xil_pn:start_ts="1635705650">
|
||||
<status xil_pn:value="AbortedRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635705810" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1635705810">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
234
fpga/WarpLC.pad
234
fpga/WarpLC.pad
@ -1,7 +1,7 @@
|
||||
Release 14.7 - par P.20131013 (nt)
|
||||
Release 14.7 - par P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Fri Oct 29 17:59:53 2021
|
||||
Sun Oct 31 15:38:33 2021
|
||||
|
||||
|
||||
# NOTE: This file is designed to be imported into a spreadsheet program
|
||||
@ -22,137 +22,137 @@ Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|D
|
||||
A1|||GND||||||||||||
|
||||
A2||IOBS|IO_L52N_M3A9_3|UNUSED||3|||||||||
|
||||
A3||IOBS|IO_L83N_VREF_3|UNUSED||3|||||||||
|
||||
A4||IOBS|IO_L1N_VREF_0|UNUSED||0|||||||||
|
||||
A5||IOBS|IO_L2N_0|UNUSED||0|||||||||
|
||||
A6||IOBS|IO_L4N_0|UNUSED||0|||||||||
|
||||
A7||IOBS|IO_L6N_0|UNUSED||0|||||||||
|
||||
A8||IOBS|IO_L33N_0|UNUSED||0|||||||||
|
||||
A9||IOBS|IO_L34N_GCLK18_0|UNUSED||0|||||||||
|
||||
A10||IOBS|IO_L35N_GCLK16_0|UNUSED||0|||||||||
|
||||
A11||IOBS|IO_L39N_0|UNUSED||0|||||||||
|
||||
A12||IOBS|IO_L62N_VREF_0|UNUSED||0|||||||||
|
||||
A13||IOBS|IO_L63N_SCP6_0|UNUSED||0|||||||||
|
||||
A14||IOBS|IO_L65N_SCP2_0|UNUSED||0|||||||||
|
||||
A4|CLKFB_OUT|IOB|IO_L1N_VREF_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
|
||||
A5|FSB_D<0>|IOB|IO_L2N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A6|FSB_D<4>|IOB|IO_L4N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A7|FSB_D<6>|IOB|IO_L6N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A8|FSB_D<12>|IOB|IO_L33N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A9|FSB_D<14>|IOB|IO_L34N_GCLK18_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A10|FSB_D<16>|IOB|IO_L35N_GCLK16_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A11|FSB_D<22>|IOB|IO_L39N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A12|FSB_D<28>|IOB|IO_L62N_VREF_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A13|FSB_D<30>|IOB|IO_L63N_SCP6_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
A14|RAMCLK0|IOB|IO_L65N_SCP2_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
|
||||
A15|||TMS||||||||||||
|
||||
A16|||GND||||||||||||
|
||||
B1|CPUCLK|IOB|IO_L50N_M3BA2_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
B1||IOBS|IO_L50N_M3BA2_3|UNUSED||3|||||||||
|
||||
B2||IOBM|IO_L52P_M3A8_3|UNUSED||3|||||||||
|
||||
B3||IOBM|IO_L83P_3|UNUSED||3|||||||||
|
||||
B4|||VCCO_0|||0|||||any******||||
|
||||
B5||IOBM|IO_L2P_0|UNUSED||0|||||||||
|
||||
B6||IOBM|IO_L4P_0|UNUSED||0|||||||||
|
||||
B4|||VCCO_0|||0|||||3.30||||
|
||||
B5|CPUCLK|IOB|IO_L2P_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
|
||||
B6|FSB_D<3>|IOB|IO_L4P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
B7|||GND||||||||||||
|
||||
B8||IOBM|IO_L33P_0|UNUSED||0|||||||||
|
||||
B9|||VCCO_0|||0|||||any******||||
|
||||
B10||IOBM|IO_L35P_GCLK17_0|UNUSED||0|||||||||
|
||||
B8|FSB_D<11>|IOB|IO_L33P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
B9|||VCCO_0|||0|||||3.30||||
|
||||
B10|FSB_D<15>|IOB|IO_L35P_GCLK17_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
B11|||GND||||||||||||
|
||||
B12||IOBM|IO_L62P_0|UNUSED||0|||||||||
|
||||
B13|||VCCO_0|||0|||||any******||||
|
||||
B14||IOBM|IO_L65P_SCP3_0|UNUSED||0|||||||||
|
||||
B15||IOBM|IO_L29P_A23_M1A13_1|UNUSED||1|||||||||
|
||||
B16||IOBS|IO_L29N_A22_M1A14_1|UNUSED||1|||||||||
|
||||
C1|FPUCLK|IOB|IO_L50P_M3WE_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
C2|INt|IOB|IO_L48N_M3BA1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
C3|OUTt|IOB|IO_L48P_M3BA0_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|NO|NONE|
|
||||
C4||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0|||||||||
|
||||
C5||IOBS|IO_L3N_0|UNUSED||0|||||||||
|
||||
C6||IOBS|IO_L7N_0|UNUSED||0|||||||||
|
||||
C7||IOBM|IO_L6P_0|UNUSED||0|||||||||
|
||||
C8||IOBS|IO_L38N_VREF_0|UNUSED||0|||||||||
|
||||
C9||IOBM|IO_L34P_GCLK19_0|UNUSED||0|||||||||
|
||||
C10||IOBS|IO_L37N_GCLK12_0|UNUSED||0|||||||||
|
||||
C11||IOBM|IO_L39P_0|UNUSED||0|||||||||
|
||||
B12|FSB_D<27>|IOB|IO_L62P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
B13|||VCCO_0|||0|||||3.30||||
|
||||
B14|FSB_A<2>|IOB|IO_L65P_SCP3_0|INPUT|LVCMOS33|0||||NONE||UNLOCATED|NO|NONE|
|
||||
B15|FSB_A<6>|IOB|IO_L29P_A23_M1A13_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
B16|FSB_A<7>|IOB|IO_L29N_A22_M1A14_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
C1||IOBM|IO_L50P_M3WE_3|UNUSED||3|||||||||
|
||||
C2||IOBS|IO_L48N_M3BA1_3|UNUSED||3|||||||||
|
||||
C3||IOBM|IO_L48P_M3BA0_3|UNUSED||3|||||||||
|
||||
C4|RAMCLK1|IOB|IO_L1P_HSWAPEN_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
|
||||
C5|FSB_D<2>|IOB|IO_L3N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C6|FSB_D<10>|IOB|IO_L7N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C7|FSB_D<7>|IOB|IO_L6P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C8|FSB_D<24>|IOB|IO_L38N_VREF_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C9|FSB_D<13>|IOB|IO_L34P_GCLK19_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C10|FSB_D<20>|IOB|IO_L37N_GCLK12_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C11|FSB_D<23>|IOB|IO_L39P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C12|||TDI||||||||||||
|
||||
C13||IOBM|IO_L63P_SCP7_0|UNUSED||0|||||||||
|
||||
C13|FSB_D<29>|IOB|IO_L63P_SCP7_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
C14|||TCK||||||||||||
|
||||
C15||IOBM|IO_L33P_A15_M1A10_1|UNUSED||1|||||||||
|
||||
C16||IOBS|IO_L33N_A14_M1A4_1|UNUSED||1|||||||||
|
||||
D1|RAMCLK0|IOB|IO_L49N_M3A2_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
D2|||VCCO_3|||3|||||3.30||||
|
||||
D3|RAMCLK1|IOB|IO_L49P_M3A7_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
C15|FSB_A<14>|IOB|IO_L33P_A15_M1A10_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
C16|FSB_A<20>|IOB|IO_L33N_A14_M1A4_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
D1||IOBS|IO_L49N_M3A2_3|UNUSED||3|||||||||
|
||||
D2|||VCCO_3|||3|||||any******||||
|
||||
D3||IOBM|IO_L49P_M3A7_3|UNUSED||3|||||||||
|
||||
D4|||GND||||||||||||
|
||||
D5||IOBM|IO_L3P_0|UNUSED||0|||||||||
|
||||
D6||IOBM|IO_L7P_0|UNUSED||0|||||||||
|
||||
D7|||VCCO_0|||0|||||any******||||
|
||||
D8||IOBM|IO_L38P_0|UNUSED||0|||||||||
|
||||
D9||IOBS|IO_L40N_0|UNUSED||0|||||||||
|
||||
D10|||VCCO_0|||0|||||any******||||
|
||||
D11||IOBM|IO_L66P_SCP1_0|UNUSED||0|||||||||
|
||||
D12||IOBS|IO_L66N_SCP0_0|UNUSED||0|||||||||
|
||||
D5|FSB_D<1>|IOB|IO_L3P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
D6|FSB_D<9>|IOB|IO_L7P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
D7|||VCCO_0|||0|||||3.30||||
|
||||
D8|FSB_D<21>|IOB|IO_L38P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
D9|FSB_D<26>|IOB|IO_L40N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
D10|||VCCO_0|||0|||||3.30||||
|
||||
D11|FPUCLK|IOB|IO_L66P_SCP1_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE|
|
||||
D12|CPU_nSTERM|IOB|IO_L66N_SCP0_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|NO|NONE|
|
||||
D13|||GND||||||||||||
|
||||
D14||IOBM|IO_L31P_A19_M1CKE_1|UNUSED||1|||||||||
|
||||
D14|FSB_A<10>|IOB|IO_L31P_A19_M1CKE_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
D15|||VCCO_1|||1|||||any******||||
|
||||
D16||IOBS|IO_L31N_A18_M1A12_1|UNUSED||1|||||||||
|
||||
E1|FSB_A<27>|IOB|IO_L46N_M3CLKN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
E2|FSB_A<24>|IOB|IO_L46P_M3CLK_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
D16|FSB_A<11>|IOB|IO_L31N_A18_M1A12_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
E1||IOBS|IO_L46N_M3CLKN_3|UNUSED||3|||||||||
|
||||
E2||IOBM|IO_L46P_M3CLK_3|UNUSED||3|||||||||
|
||||
E3||IOBS|IO_L54N_M3A11_3|UNUSED||3|||||||||
|
||||
E4||IOBM|IO_L54P_M3RESET_3|UNUSED||3|||||||||
|
||||
E5|||VCCAUX||||||||2.5||||
|
||||
E6||IOBS|IO_L5N_0|UNUSED||0|||||||||
|
||||
E7||IOBM|IO_L36P_GCLK15_0|UNUSED||0|||||||||
|
||||
E8||IOBS|IO_L36N_GCLK14_0|UNUSED||0|||||||||
|
||||
E6|FSB_D<8>|IOB|IO_L5N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
E7|FSB_D<17>|IOB|IO_L36P_GCLK15_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
E8|FSB_D<18>|IOB|IO_L36N_GCLK14_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
E9|||GND||||||||||||
|
||||
E10||IOBM|IO_L37P_GCLK13_0|UNUSED||0|||||||||
|
||||
E11||IOBS|IO_L64N_SCP4_0|UNUSED||0|||||||||
|
||||
E12||IOBS|IO_L1N_A24_VREF_1|UNUSED||1|||||||||
|
||||
E13||IOBM|IO_L1P_A25_1|UNUSED||1|||||||||
|
||||
E10|FSB_D<19>|IOB|IO_L37P_GCLK13_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
E11|FSB_A<3>|IOB|IO_L64N_SCP4_0|INPUT|LVCMOS33|0||||NONE||UNLOCATED|NO|NONE|
|
||||
E12|FSB_A<5>|IOB|IO_L1N_A24_VREF_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
E13|FSB_A<4>|IOB|IO_L1P_A25_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
E14|||TDO||||||||||||
|
||||
E15||IOBM|IO_L34P_A13_M1WE_1|UNUSED||1|||||||||
|
||||
E16||IOBS|IO_L34N_A12_M1BA2_1|UNUSED||1|||||||||
|
||||
F1|FSB_A<23>|IOB|IO_L41N_GCLK26_M3DQ5_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
F2|FSB_A<22>|IOB|IO_L41P_GCLK27_M3DQ4_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
E15|FSB_A<21>|IOB|IO_L34P_A13_M1WE_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
E16|FSB_A<22>|IOB|IO_L34N_A12_M1BA2_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
F1||IOBS|IO_L41N_GCLK26_M3DQ5_3|UNUSED||3|||||||||
|
||||
F2||IOBM|IO_L41P_GCLK27_M3DQ4_3|UNUSED||3|||||||||
|
||||
F3||IOBS|IO_L53N_M3A12_3|UNUSED||3|||||||||
|
||||
F4||IOBM|IO_L53P_M3CKE_3|UNUSED||3|||||||||
|
||||
F5||IOBS|IO_L55N_M3A14_3|UNUSED||3|||||||||
|
||||
F6||IOBM|IO_L55P_M3A13_3|UNUSED||3|||||||||
|
||||
F7||IOBM|IO_L5P_0|UNUSED||0|||||||||
|
||||
F7|FSB_D<5>|IOB|IO_L5P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
F8|||VCCAUX||||||||2.5||||
|
||||
F9||IOBM|IO_L40P_0|UNUSED||0|||||||||
|
||||
F10||IOBM|IO_L64P_SCP5_0|UNUSED||0|||||||||
|
||||
F9|FSB_D<25>|IOB|IO_L40P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
F10|FSB_D<31>|IOB|IO_L64P_SCP5_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE|
|
||||
F11|||VCCAUX||||||||2.5||||
|
||||
F12||IOBM|IO_L30P_A21_M1RESET_1|UNUSED||1|||||||||
|
||||
F13||IOBM|IO_L32P_A17_M1A8_1|UNUSED||1|||||||||
|
||||
F14||IOBS|IO_L32N_A16_M1A9_1|UNUSED||1|||||||||
|
||||
F15||IOBM|IO_L35P_A11_M1A7_1|UNUSED||1|||||||||
|
||||
F16||IOBS|IO_L35N_A10_M1A2_1|UNUSED||1|||||||||
|
||||
G1|FSB_A<29>|IOB|IO_L40N_M3DQ7_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
F12|FSB_A<8>|IOB|IO_L30P_A21_M1RESET_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
F13|FSB_A<12>|IOB|IO_L32P_A17_M1A8_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
F14|FSB_A<13>|IOB|IO_L32N_A16_M1A9_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
F15|FSB_A<23>|IOB|IO_L35P_A11_M1A7_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
F16|FSB_A<19>|IOB|IO_L35N_A10_M1A2_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
G1||IOBS|IO_L40N_M3DQ7_3|UNUSED||3|||||||||
|
||||
G2|||GND||||||||||||
|
||||
G3|FSB_A<19>|IOB|IO_L40P_M3DQ6_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
G4|||VCCO_3|||3|||||3.30||||
|
||||
G3||IOBM|IO_L40P_M3DQ6_3|UNUSED||3|||||||||
|
||||
G4|||VCCO_3|||3|||||any******||||
|
||||
G5||IOBS|IO_L51N_M3A4_3|UNUSED||3|||||||||
|
||||
G6|CLKFB_OUT|IOB|IO_L51P_M3A10_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
G6||IOBM|IO_L51P_M3A10_3|UNUSED||3|||||||||
|
||||
G7|||VCCINT||||||||1.2||||
|
||||
G8|||GND||||||||||||
|
||||
G9|||VCCINT||||||||1.2||||
|
||||
G10|||VCCAUX||||||||2.5||||
|
||||
G11||IOBS|IO_L30N_A20_M1A11_1|UNUSED||1|||||||||
|
||||
G12||IOBM|IO_L38P_A5_M1CLK_1|UNUSED||1|||||||||
|
||||
G11|FSB_A<9>|IOB|IO_L30N_A20_M1A11_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
G12|FSB_A<24>|IOB|IO_L38P_A5_M1CLK_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
G13|||VCCO_1|||1|||||any******||||
|
||||
G14||IOBM|IO_L36P_A9_M1BA0_1|UNUSED||1|||||||||
|
||||
G14|FSB_A<15>|IOB|IO_L36P_A9_M1BA0_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
G15|||GND||||||||||||
|
||||
G16||IOBS|IO_L36N_A8_M1BA1_1|UNUSED||1|||||||||
|
||||
H1|FSB_A<26>|IOB|IO_L39N_M3LDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H2|FSB_A<25>|IOB|IO_L39P_M3LDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H3|CPU_nAS|IOB|IO_L44N_GCLK20_M3A6_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
G16|FSB_A<16>|IOB|IO_L36N_A8_M1BA1_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
H1||IOBS|IO_L39N_M3LDQSN_3|UNUSED||3|||||||||
|
||||
H2||IOBM|IO_L39P_M3LDQS_3|UNUSED||3|||||||||
|
||||
H3||IOBS|IO_L44N_GCLK20_M3A6_3|UNUSED||3|||||||||
|
||||
H4|CLKFB_IN|IOB|IO_L44P_GCLK21_M3A5_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H5|FSB_A<30>|IOB|IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H5||IOBS|IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED||3|||||||||
|
||||
H6|||VCCAUX||||||||2.5||||
|
||||
H7|||GND||||||||||||
|
||||
H8|||VCCINT||||||||1.2||||
|
||||
H9|||GND||||||||||||
|
||||
H10|||VCCINT||||||||1.2||||
|
||||
H11||IOBS|IO_L38N_A4_M1CLKN_1|UNUSED||1|||||||||
|
||||
H11|FSB_A<25>|IOB|IO_L38N_A4_M1CLKN_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
H12|||GND||||||||||||
|
||||
H13||IOBM|IO_L39P_M1A3_1|UNUSED||1|||||||||
|
||||
H14||IOBS|IO_L39N_M1ODT_1|UNUSED||1|||||||||
|
||||
H15||IOBM|IO_L37P_A7_M1A0_1|UNUSED||1|||||||||
|
||||
H16||IOBS|IO_L37N_A6_M1A1_1|UNUSED||1|||||||||
|
||||
J1|FSB_A<17>|IOB|IO_L38N_M3DQ3_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J2|||VCCO_3|||3|||||3.30||||
|
||||
J3|FSB_A<16>|IOB|IO_L38P_M3DQ2_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H13|FSB_A<26>|IOB|IO_L39P_M1A3_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
H14|FSB_A<27>|IOB|IO_L39N_M1ODT_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
H15|FSB_A<17>|IOB|IO_L37P_A7_M1A0_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
H16|FSB_A<18>|IOB|IO_L37N_A6_M1A1_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE|
|
||||
J1||IOBS|IO_L38N_M3DQ3_3|UNUSED||3|||||||||
|
||||
J2|||VCCO_3|||3|||||any******||||
|
||||
J3||IOBM|IO_L38P_M3DQ2_3|UNUSED||3|||||||||
|
||||
J4|CLKIN|IOB|IO_L42N_GCLK24_M3LDM_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J5|||GND||||||||||||
|
||||
J6|FSB_A<21>|IOB|IO_L43P_GCLK23_M3RASN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J6||IOBM|IO_L43P_GCLK23_M3RASN_3|UNUSED||3|||||||||
|
||||
J7|||VCCINT||||||||1.2||||
|
||||
J8|||GND||||||||||||
|
||||
J9|||VCCINT||||||||1.2||||
|
||||
@ -163,12 +163,12 @@ J13||IOBM|IO_L41P_GCLK9_IRDY1_M1RASN_1|UNUSED||1|||||||||
|
||||
J14||IOBM|IO_L43P_GCLK5_M1DQ4_1|UNUSED||1|||||||||
|
||||
J15|||VCCO_1|||1|||||any******||||
|
||||
J16||IOBS|IO_L43N_GCLK4_M1DQ5_1|UNUSED||1|||||||||
|
||||
K1|FSB_A<5>|IOB|IO_L37N_M3DQ1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K2|FSB_A<14>|IOB|IO_L37P_M3DQ0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K3|FSB_A<28>|IOB|IO_L42P_GCLK25_TRDY2_M3UDM_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K4|||VCCO_3|||3|||||3.30||||
|
||||
K5|CPUCLKi|IOB|IO_L47P_M3A0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K6|FSB_A<18>|IOB|IO_L47N_M3A1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K1||IOBS|IO_L37N_M3DQ1_3|UNUSED||3|||||||||
|
||||
K2||IOBM|IO_L37P_M3DQ0_3|UNUSED||3|||||||||
|
||||
K3||IOBM|IO_L42P_GCLK25_TRDY2_M3UDM_3|UNUSED||3|||||||||
|
||||
K4|||VCCO_3|||3|||||any******||||
|
||||
K5||IOBM|IO_L47P_M3A0_3|UNUSED||3|||||||||
|
||||
K6||IOBS|IO_L47N_M3A1_3|UNUSED||3|||||||||
|
||||
K7|||GND||||||||||||
|
||||
K8|||VCCINT||||||||1.2||||
|
||||
K9|||GND||||||||||||
|
||||
@ -179,11 +179,11 @@ K13|||VCCO_1|||1|||||any******||||
|
||||
K14||IOBS|IO_L41N_GCLK8_M1CASN_1|UNUSED||1|||||||||
|
||||
K15||IOBM|IO_L44P_A3_M1DQ6_1|UNUSED||1|||||||||
|
||||
K16||IOBS|IO_L44N_A2_M1DQ7_1|UNUSED||1|||||||||
|
||||
L1|FSB_A<11>|IOB|IO_L36N_M3DQ9_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L1||IOBS|IO_L36N_M3DQ9_3|UNUSED||3|||||||||
|
||||
L2|||GND||||||||||||
|
||||
L3|FSB_A<4>|IOB|IO_L36P_M3DQ8_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L4|FSB_A<31>|IOB|IO_L45P_M3A3_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L5|FSB_A<20>|IOB|IO_L45N_M3ODT_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L3||IOBM|IO_L36P_M3DQ8_3|UNUSED||3|||||||||
|
||||
L4||IOBM|IO_L45P_M3A3_3|UNUSED||3|||||||||
|
||||
L5||IOBS|IO_L45N_M3ODT_3|UNUSED||3|||||||||
|
||||
L6|||VCCAUX||||||||2.5||||
|
||||
L7||IOBS|IO_L62N_D6_2|UNUSED||2|||||||||
|
||||
L8||IOBM|IO_L62P_D5_2|UNUSED||2|||||||||
|
||||
@ -195,11 +195,11 @@ L13||IOBS|IO_L53N_VREF_1|UNUSED||1|||||||||
|
||||
L14||IOBM|IO_L47P_FWE_B_M1DQ0_1|UNUSED||1|||||||||
|
||||
L15|||GND||||||||||||
|
||||
L16||IOBS|IO_L47N_LDC_M1DQ1_1|UNUSED||1|||||||||
|
||||
M1|FSB_A<1>|IOB|IO_L35N_M3DQ11_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M2|FSB_A<2>|IOB|IO_L35P_M3DQ10_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M3|FSB_A<6>|IOB|IO_L1N_VREF_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M4|FSB_A<8>|IOB|IO_L1P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M5|FSB_A<15>|IOB|IO_L2P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M1||IOBS|IO_L35N_M3DQ11_3|UNUSED||3|||||||||
|
||||
M2||IOBM|IO_L35P_M3DQ10_3|UNUSED||3|||||||||
|
||||
M3||IOBS|IO_L1N_VREF_3|UNUSED||3|||||||||
|
||||
M4||IOBM|IO_L1P_3|UNUSED||3|||||||||
|
||||
M5||IOBM|IO_L2P_3|UNUSED||3|||||||||
|
||||
M6||IOBM|IO_L64P_D8_2|UNUSED||2|||||||||
|
||||
M7||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2|||||||||
|
||||
M8|||GND||||||||||||
|
||||
@ -211,10 +211,10 @@ M13||IOBM|IO_L74P_AWAKE_1|UNUSED||1|||||||||
|
||||
M14||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1|||||||||
|
||||
M15||IOBM|IO_L46P_FCS_B_M1DQ2_1|UNUSED||1|||||||||
|
||||
M16||IOBS|IO_L46N_FOE_B_M1DQ3_1|UNUSED||1|||||||||
|
||||
N1|FSB_A<10>|IOB|IO_L34N_M3UDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N2|||VCCO_3|||3|||||3.30||||
|
||||
N3|FSB_A<13>|IOB|IO_L34P_M3UDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N4|FSB_A<0>|IOB|IO_L2N_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N1||IOBS|IO_L34N_M3UDQSN_3|UNUSED||3|||||||||
|
||||
N2|||VCCO_3|||3|||||any******||||
|
||||
N3||IOBM|IO_L34P_M3UDQS_3|UNUSED||3|||||||||
|
||||
N4||IOBS|IO_L2N_3|UNUSED||3|||||||||
|
||||
N5||IOBM|IO_L49P_D3_2|UNUSED||2|||||||||
|
||||
N6||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
|
||||
N7|||VCCO_2|||2|||||any******||||
|
||||
@ -227,8 +227,8 @@ N13|||GND||||||||||||
|
||||
N14||IOBM|IO_L45P_A1_M1LDQS_1|UNUSED||1|||||||||
|
||||
N15|||VCCO_1|||1|||||any******||||
|
||||
N16||IOBS|IO_L45N_A0_M1LDQSN_1|UNUSED||1|||||||||
|
||||
P1|FSB_A<7>|IOB|IO_L33N_M3DQ13_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
P2|FSB_A<12>|IOB|IO_L33P_M3DQ12_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
P1||IOBS|IO_L33N_M3DQ13_3|UNUSED||3|||||||||
|
||||
P2||IOBM|IO_L33P_M3DQ12_3|UNUSED||3|||||||||
|
||||
P3|||GND||||||||||||
|
||||
P4||IOBM|IO_L63P_2|UNUSED||2|||||||||
|
||||
P5||IOBS|IO_L49N_D4_2|UNUSED||2|||||||||
|
||||
@ -243,8 +243,8 @@ P13|||DONE_2||||||||||||
|
||||
P14|||SUSPEND||||||||||||
|
||||
P15||IOBM|IO_L48P_HDC_M1DQ8_1|UNUSED||1|||||||||
|
||||
P16||IOBS|IO_L48N_M1DQ9_1|UNUSED||1|||||||||
|
||||
R1|FSB_A<9>|IOB|IO_L32N_M3DQ15_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
R2|FSB_A<3>|IOB|IO_L32P_M3DQ14_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
R1||IOBS|IO_L32N_M3DQ15_3|UNUSED||3|||||||||
|
||||
R2||IOBM|IO_L32P_M3DQ14_3|UNUSED||3|||||||||
|
||||
R3||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
|
||||
R4|||VCCO_2|||2|||||any******||||
|
||||
R5||IOBM|IO_L48P_D7_2|UNUSED||2|||||||||
|
||||
|
||||
254
fpga/WarpLC.par
254
fpga/WarpLC.par
@ -1,28 +1,21 @@
|
||||
Release 14.7 par P.20131013 (nt)
|
||||
Release 14.7 par P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
ZANEPC:: Fri Oct 29 17:59:50 2021
|
||||
DOG-PC:: Sun Oct 31 15:38:29 2021
|
||||
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
|
||||
|
||||
Constraints file: WarpLC.pcf.
|
||||
Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
|
||||
"WarpLC" is an NCD, version 3.2, device xc6slx9, package ftg256, speed -2
|
||||
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
|
||||
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
|
||||
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
|
||||
'C:\ispLEVER_Classic2_0\license\license.dat;C:\lscc\diamond\3.12\license\license.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'.
|
||||
INFO:Security:54 - 'xc6slx9' is a WebPack part.
|
||||
INFO:Security:66 - Your license for 'ISE' is for evaluation use only.
|
||||
WARNING:Security:43 - No license file was found in the standard Xilinx license directory.
|
||||
WARNING:Security:44 - Since no license file was found,
|
||||
please run the Xilinx License Configuration Manager
|
||||
(xlcm or "Manage Xilinx Licenses")
|
||||
to assist in obtaining a license.
|
||||
WARNING:Security:40 - Your license for 'ISE' expires in 4 days.
|
||||
|
||||
----------------------------------------------------------------------
|
||||
INFO:Par:338 -
|
||||
Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are
|
||||
not meeting timing but where the designer wants the tools to continue iterating on the design until no further design
|
||||
speed improvements are possible. This can result in very long runtimes since the tools will continue improving the
|
||||
design even if the time specs can not be met. If you are looking for the best possible design speed available from a
|
||||
long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design
|
||||
speed improvements have shrunk to the point that the time specs are not expected to be met.
|
||||
|
||||
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
|
||||
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
||||
@ -35,30 +28,32 @@ Device speed data version: "PRODUCTION 1.23 2013-10-13".
|
||||
Device Utilization Summary:
|
||||
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 34 out of 11,440 1%
|
||||
Number used as Flip Flops: 34
|
||||
Number of Slice Registers: 1 out of 11,440 1%
|
||||
Number used as Flip Flops: 1
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 17 out of 5,720 1%
|
||||
Number used as logic: 13 out of 5,720 1%
|
||||
Number using O6 output only: 11
|
||||
Number using O5 output only: 0
|
||||
Number using O5 and O6: 2
|
||||
Number of Slice LUTs: 33 out of 5,720 1%
|
||||
Number used as logic: 9 out of 5,720 1%
|
||||
Number using O6 output only: 8
|
||||
Number using O5 output only: 1
|
||||
Number using O5 and O6: 0
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 0 out of 1,440 0%
|
||||
Number used exclusively as route-thrus: 4
|
||||
Number with same-slice register load: 4
|
||||
Number with same-slice carry load: 0
|
||||
Number with other load: 0
|
||||
Number used as Memory: 24 out of 1,440 1%
|
||||
Number used as Dual Port RAM: 24
|
||||
Number using O6 output only: 4
|
||||
Number using O5 output only: 0
|
||||
Number using O5 and O6: 20
|
||||
Number used as Single Port RAM: 0
|
||||
Number used as Shift Register: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 11 out of 1,430 1%
|
||||
Number of MUXCYs used: 12 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 41
|
||||
Number with an unused Flip Flop: 11 out of 41 26%
|
||||
Number with an unused LUT: 24 out of 41 58%
|
||||
Number of fully used LUT-FF pairs: 6 out of 41 14%
|
||||
Number of occupied Slices: 9 out of 1,430 1%
|
||||
Number of MUXCYs used: 8 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 33
|
||||
Number with an unused Flip Flop: 32 out of 33 96%
|
||||
Number with an unused LUT: 0 out of 33 0%
|
||||
Number of fully used LUT-FF pairs: 1 out of 33 3%
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 0 out of 11,440 0%
|
||||
|
||||
@ -69,12 +64,12 @@ Slice Logic Distribution:
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 43 out of 186 23%
|
||||
Number of bonded IOBs: 66 out of 186 35%
|
||||
IOB Flip Flops: 5
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 0 out of 32 0%
|
||||
Number of RAMB8BWERs: 0 out of 64 0%
|
||||
Number of RAMB8BWERs: 1 out of 64 1%
|
||||
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2s: 1
|
||||
Number used as BUFIO2_2CLKs: 0
|
||||
@ -107,42 +102,35 @@ Specific Feature Utilization:
|
||||
Overall effort level (-ol): High
|
||||
Router effort level (-rl): High
|
||||
|
||||
Starting initial Timing Analysis. REAL time: 2 secs
|
||||
Finished initial Timing Analysis. REAL time: 2 secs
|
||||
|
||||
Starting Router
|
||||
PAR will use up to 4 processors
|
||||
Starting Multi-threaded Router
|
||||
|
||||
|
||||
Phase 1 : 164 unrouted; REAL time: 2 secs
|
||||
Phase 1 : 386 unrouted; REAL time: 3 secs
|
||||
|
||||
Phase 2 : 120 unrouted; REAL time: 2 secs
|
||||
Phase 2 : 172 unrouted; REAL time: 3 secs
|
||||
|
||||
Phase 3 : 68 unrouted; REAL time: 2 secs
|
||||
Phase 3 : 110 unrouted; REAL time: 3 secs
|
||||
|
||||
Phase 4 : 68 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs
|
||||
Phase 4 : 110 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs
|
||||
|
||||
Updating file: WarpLC.ncd with current fully routed design.
|
||||
|
||||
Phase 5 : 0 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs
|
||||
Phase 5 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs
|
||||
|
||||
Phase 6 : 0 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs
|
||||
Phase 6 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs
|
||||
|
||||
Phase 7 : 0 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs
|
||||
Phase 7 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs
|
||||
|
||||
Phase 8 : 0 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs
|
||||
Phase 8 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs
|
||||
|
||||
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
Phase 9 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs
|
||||
|
||||
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
Total REAL time to Router completion: 2 secs
|
||||
Total CPU time to Router completion: 2 secs
|
||||
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs
|
||||
Total REAL time to Router completion: 4 secs
|
||||
Total CPU time to Router completion (all processors): 4 secs
|
||||
|
||||
Generating "PAR" statistics.
|
||||
|
||||
@ -153,11 +141,10 @@ Generating Clock Report
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
|CLKGEN_inst/instance | | | | | |
|
||||
|_name/clkfb_bufg_out | | | | | |
|
||||
| | BUFGMUX_X3Y13| No | 2 | 0.000 | 2.077 |
|
||||
| FSBCLK | BUFGMUX_X3Y13| No | 17 | 0.625 | 2.088 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| FSBCLK | BUFGMUX_X2Y3| No | 17 | 0.700 | 2.135 |
|
||||
|cg/pll/clkfb_bufg_ou | | | | | |
|
||||
| t | BUFGMUX_X2Y3| No | 2 | 0.062 | 2.139 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
|
||||
* Net Skew is the difference between the minimum and maximum routing
|
||||
@ -179,123 +166,17 @@ Asterisk (*) preceding a constraint indicates it was not met.
|
||||
Constraint | Check | Worst Case | Best Case | Timing | Timing
|
||||
| | Slack | Achievable | Errors | Score
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 1 | SETUP | 1.520ns| 10.480ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.772ns| | 0| 0
|
||||
TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP " | MAXDELAY | 7.121ns| 7.879ns| 0| 0
|
||||
FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<27>" OFFSET = IN 12 ns VALID | SETUP | 1.666ns| 10.334ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.698ns| | 0| 0
|
||||
TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pl | SETUP | 11.311ns| 3.689ns| 0| 0
|
||||
l_clkout0" TS_CLKIN / 2 HIGH 50% | HOLD | 0.458ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "INt" OFFSET = IN 12 ns VALID 12 ns | SETUP | 1.668ns| 10.332ns| 0| 0
|
||||
BEFORE COMP "CLKIN" | HOLD | 4.292ns| | 0| 0
|
||||
TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns H | MINLOWPULSE | 20.000ns| 10.000ns| 0| 0
|
||||
IGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 1 | SETUP | 1.713ns| 10.287ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.756ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<21>" OFFSET = IN 12 ns VALID | SETUP | 1.725ns| 10.275ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.718ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<28>" OFFSET = IN 12 ns VALID | SETUP | 1.739ns| 10.261ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.510ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<31>" OFFSET = IN 12 ns VALID | SETUP | 1.753ns| 10.247ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.707ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<15>" OFFSET = IN 12 ns VALID | SETUP | 1.904ns| 10.096ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.834ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<20>" OFFSET = IN 12 ns VALID | SETUP | 1.936ns| 10.064ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.578ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 1 | SETUP | 1.972ns| 10.028ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.706ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<24>" OFFSET = IN 12 ns VALID | SETUP | 1.974ns| 10.026ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.679ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<13>" OFFSET = IN 12 ns VALID | SETUP | 1.989ns| 10.011ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.709ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 1 | SETUP | 1.991ns| 10.009ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.618ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<19>" OFFSET = IN 12 ns VALID | SETUP | 2.005ns| 9.995ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.722ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.081ns| 9.919ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.621ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<22>" OFFSET = IN 12 ns VALID | SETUP | 2.093ns| 9.907ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.637ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<25>" OFFSET = IN 12 ns VALID | SETUP | 2.117ns| 9.883ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.244ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.124ns| 9.876ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.242ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<18>" OFFSET = IN 12 ns VALID | SETUP | 2.132ns| 9.868ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.829ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<29>" OFFSET = IN 12 ns VALID | SETUP | 2.136ns| 9.864ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.448ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<30>" OFFSET = IN 12 ns VALID | SETUP | 2.153ns| 9.847ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.725ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.158ns| 9.842ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.237ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<12>" OFFSET = IN 12 ns VALID | SETUP | 2.179ns| 9.821ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.605ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.234ns| 9.766ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.288ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.243ns| 9.757ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.464ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<23>" OFFSET = IN 12 ns VALID | SETUP | 2.263ns| 9.737ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.472ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<26>" OFFSET = IN 12 ns VALID | SETUP | 2.343ns| 9.657ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.292ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 | SETUP | 2.359ns| 9.641ns| 0| 0
|
||||
ns BEFORE COMP "CLKIN" | HOLD | 3.896ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<16>" OFFSET = IN 12 ns VALID | SETUP | 2.435ns| 9.565ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.493ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<10>" OFFSET = IN 12 ns VALID | SETUP | 2.438ns| 9.562ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.463ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<11>" OFFSET = IN 12 ns VALID | SETUP | 2.478ns| 9.522ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.200ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.735ns| 9.265ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.204ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<17>" OFFSET = IN 12 ns VALID | SETUP | 2.739ns| 9.261ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.474ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<14>" OFFSET = IN 12 ns VALID | SETUP | 2.916ns| 9.084ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.242ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP | MAXDELAY | 2.960ns| 2.040ns| 0| 0
|
||||
"CLKIN" | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
PERIOD analysis for net "CLKGEN_inst/inst | SETUP | 12.300ns| 2.700ns| 0| 0
|
||||
ance_name/clkout0" derived from NET "CLK | HOLD | 0.457ns| | 0| 0
|
||||
GEN_inst/instance_name/clkin1" PERIOD = 3 | | | | |
|
||||
0 ns HIGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
NET "CLKGEN_inst/instance_name/clkin1" PE | MINLOWPULSE | 20.000ns| 10.000ns| 0| 0
|
||||
RIOD = 30 ns HIGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
PERIOD analysis for net "CLKGEN_inst/inst | MINPERIOD | 27.334ns| 2.666ns| 0| 0
|
||||
ance_name/clkfbout" derived from NET "CL | | | | |
|
||||
KGEN_inst/instance_name/clkin1" PERIOD = | | | | |
|
||||
30 ns HIGH 50% | | | | |
|
||||
TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_p | MINPERIOD | 27.334ns| 2.666ns| 0| 0
|
||||
ll_clkfbout" TS_CLKIN HIGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@ -303,18 +184,15 @@ Derived Constraint Report
|
||||
Review Timing Report for more details on the following derived constraints.
|
||||
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
|
||||
or "Run Timing Analysis" from Timing Analyzer (timingan).
|
||||
Derived Constraints for CLKGEN_inst/instance_name/clkin1
|
||||
Derived Constraints for TS_CLKIN
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
| | Period | Actual Period | Timing Errors | Paths Analyzed |
|
||||
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|
||||
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|CLKGEN_inst/instance_name/clkin| 30.000ns| 10.000ns| 5.400ns| 0| 0| 0| 35|
|
||||
|1 | | | | | | | |
|
||||
| CLKGEN_inst/instance_name/clko| 15.000ns| 2.700ns| N/A| 0| 0| 35| 0|
|
||||
| ut0 | | | | | | | |
|
||||
| CLKGEN_inst/instance_name/clkf| 30.000ns| 2.666ns| N/A| 0| 0| 0| 0|
|
||||
| bout | | | | | | | |
|
||||
|TS_CLKIN | 30.000ns| 10.000ns| 7.378ns| 0| 0| 0| 6|
|
||||
| TS_cg_pll_clkfbout | 30.000ns| 2.666ns| N/A| 0| 0| 0| 0|
|
||||
| TS_cg_pll_clkout0 | 15.000ns| 3.689ns| N/A| 0| 0| 6| 0|
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|
||||
All constraints were met.
|
||||
@ -324,10 +202,10 @@ Generating Pad Report.
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
Total REAL time to PAR completion: 3 secs
|
||||
Total CPU time to PAR completion: 3 secs
|
||||
Total REAL time to PAR completion: 4 secs
|
||||
Total CPU time to PAR completion (all processors): 4 secs
|
||||
|
||||
Peak Memory Usage: 257 MB
|
||||
Peak Memory Usage: 322 MB
|
||||
|
||||
Placer: Placement generated during map.
|
||||
Routing: Completed - No errors found.
|
||||
@ -335,7 +213,7 @@ Timing: Completed - No errors found.
|
||||
|
||||
Number of error messages: 0
|
||||
Number of warning messages: 0
|
||||
Number of info messages: 0
|
||||
Number of info messages: 1
|
||||
|
||||
Writing design to file WarpLC.ncd
|
||||
|
||||
|
||||
262
fpga/WarpLC.pcf
262
fpga/WarpLC.pcf
@ -1,44 +1,232 @@
|
||||
//! **************************************************************************
|
||||
// Written by: Map P.20131013 on Fri Oct 29 17:59:48 2021
|
||||
// Written by: Map P.20131013 on Sun Oct 31 15:38:26 2021
|
||||
//! **************************************************************************
|
||||
|
||||
SCHEMATIC START;
|
||||
NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%;
|
||||
COMP "FSB_A<31>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<30>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<29>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<28>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "INt" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP "CLKIN";
|
||||
PIN
|
||||
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<26>
|
||||
= BEL
|
||||
"l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram"
|
||||
PINNAME CLKAWRCLK;
|
||||
PIN
|
||||
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<27>
|
||||
= BEL
|
||||
"l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram"
|
||||
PINNAME CLKBRDCLK;
|
||||
PIN cg/CPUCLK_inst_pins<1> = BEL "cg/CPUCLK_inst" PINNAME CK0;
|
||||
PIN cg/CPUCLK_inst_pins<2> = BEL "cg/CPUCLK_inst" PINNAME CK1;
|
||||
PIN cg/FPUCLK_inst_pins<1> = BEL "cg/FPUCLK_inst" PINNAME CK0;
|
||||
PIN cg/FPUCLK_inst_pins<2> = BEL "cg/FPUCLK_inst" PINNAME CK1;
|
||||
PIN cg/RAMCLK0_inst_pins<1> = BEL "cg/RAMCLK0_inst" PINNAME CK0;
|
||||
PIN cg/RAMCLK0_inst_pins<2> = BEL "cg/RAMCLK0_inst" PINNAME CK1;
|
||||
PIN cg/RAMCLK1_inst_pins<1> = BEL "cg/RAMCLK1_inst" PINNAME CK0;
|
||||
PIN cg/RAMCLK1_inst_pins<2> = BEL "cg/RAMCLK1_inst" PINNAME CK1;
|
||||
TIMEGRP cg_pll_clkout0 = BEL "cg/pll/clkout1_buf" PIN
|
||||
"l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<26>"
|
||||
PIN
|
||||
"l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<27>"
|
||||
BEL "cg/CPUCLKr" BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP"
|
||||
PIN "cg/CPUCLK_inst_pins<1>" PIN "cg/CPUCLK_inst_pins<2>" PIN
|
||||
"cg/CPUCLK_inst_pins<1>" PIN "cg/CPUCLK_inst_pins<2>" PIN
|
||||
"cg/FPUCLK_inst_pins<1>" PIN "cg/FPUCLK_inst_pins<2>" PIN
|
||||
"cg/FPUCLK_inst_pins<1>" PIN "cg/FPUCLK_inst_pins<2>" PIN
|
||||
"cg/RAMCLK0_inst_pins<1>" PIN "cg/RAMCLK0_inst_pins<2>" PIN
|
||||
"cg/RAMCLK0_inst_pins<1>" PIN "cg/RAMCLK0_inst_pins<2>" PIN
|
||||
"cg/RAMCLK1_inst_pins<1>" PIN "cg/RAMCLK1_inst_pins<2>" PIN
|
||||
"cg/RAMCLK1_inst_pins<1>" PIN "cg/RAMCLK1_inst_pins<2>";
|
||||
PIN cg/pll/clkfbout_oddr_pins<1> = BEL "cg/pll/clkfbout_oddr" PINNAME CK0;
|
||||
PIN cg/pll/clkfbout_oddr_pins<2> = BEL "cg/pll/clkfbout_oddr" PINNAME CK1;
|
||||
TIMEGRP cg_pll_clkfbout = BEL "cg/pll/clkfbout_bufg" PIN
|
||||
"cg/pll/clkfbout_oddr_pins<1>" PIN "cg/pll/clkfbout_oddr_pins<2>" PIN
|
||||
"cg/pll/clkfbout_oddr_pins<1>" PIN "cg/pll/clkfbout_oddr_pins<2>";
|
||||
TIMEGRP CPU_nSTERM = BEL "CPU_nSTERM";
|
||||
TIMEGRP FSB_A = BEL "CPU_nSTERM" PIN
|
||||
"l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<27>"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/SP"
|
||||
BEL
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP";
|
||||
PIN SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0_pins<0> = BEL
|
||||
"SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0" PINNAME DIVCLK;
|
||||
PIN cg/pll/pll_base_inst/PLL_ADV_pins<2> = BEL "cg/pll/pll_base_inst/PLL_ADV"
|
||||
PINNAME CLKIN1;
|
||||
TIMEGRP CLKIN = PIN "SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0_pins<0>" PIN
|
||||
"cg/pll/pll_base_inst/PLL_ADV_pins<2>";
|
||||
TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%;
|
||||
TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns;
|
||||
TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" TS_CLKIN HIGH 50%;
|
||||
TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%;
|
||||
BEL "CLKFB_OUT" FEEDBACK = 0.16 ns BEL "CLKFB_IN";
|
||||
SCHEMATIC END;
|
||||
|
||||
|
||||
@ -1,3 +1,7 @@
|
||||
verilog work "ipcore_dir/CLK.v"
|
||||
verilog work "CLKGEN.v"
|
||||
verilog work "ipcore_dir/PLL.v"
|
||||
verilog work "ipcore_dir/PrefetchTagRAM.v"
|
||||
verilog work "ipcore_dir/PrefetchDataRAM.v"
|
||||
verilog work "SizeDecode.v"
|
||||
verilog work "PrefetchBuf.v"
|
||||
verilog work "ClkGen.v"
|
||||
verilog work "WarpLC.v"
|
||||
|
||||
File diff suppressed because one or more lines are too long
356
fpga/WarpLC.syr
356
fpga/WarpLC.syr
@ -1,16 +1,16 @@
|
||||
Release 14.7 - xst P.20131013 (nt)
|
||||
Release 14.7 - xst P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
--> Parameter TMPDIR set to xst/projnav.tmp
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.08 secs
|
||||
Total CPU time to Xst completion: 0.09 secs
|
||||
|
||||
--> Parameter xsthdpdir set to xst
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.08 secs
|
||||
Total CPU time to Xst completion: 0.09 secs
|
||||
|
||||
--> Reading design: WarpLC.prj
|
||||
|
||||
@ -81,12 +81,12 @@ Equivalent register Removal : YES
|
||||
|
||||
---- General Options
|
||||
Optimization Goal : Speed
|
||||
Optimization Effort : 1
|
||||
Optimization Effort : 2
|
||||
Power Reduction : NO
|
||||
Keep Hierarchy : No
|
||||
Netlist Hierarchy : As_Optimized
|
||||
RTL Output : Yes
|
||||
Global Optimization : AllClockNets
|
||||
Global Optimization : Inpad_To_Outpad
|
||||
Read Cores : YES
|
||||
Write Timing Constraints : NO
|
||||
Cross Clock Analysis : NO
|
||||
@ -108,11 +108,19 @@ Cores Search Directories : {"ipcore_dir" }
|
||||
=========================================================================
|
||||
* HDL Parsing *
|
||||
=========================================================================
|
||||
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" into library work
|
||||
Parsing module <CLK>.
|
||||
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\CLKGEN.v" into library work
|
||||
Parsing module <CLKGEN>.
|
||||
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" into library work
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" into library work
|
||||
Parsing module <PLL>.
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" into library work
|
||||
Parsing module <PrefetchTagRAM>.
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" into library work
|
||||
Parsing module <PrefetchDataRAM>.
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\SizeDecode.v" into library work
|
||||
Parsing module <SizeDecode>.
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" into library work
|
||||
Parsing module <L2Prefetch>.
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" into library work
|
||||
Parsing module <ClkGen>.
|
||||
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" into library work
|
||||
Parsing module <WarpLC>.
|
||||
|
||||
=========================================================================
|
||||
@ -120,46 +128,62 @@ Parsing module <WarpLC>.
|
||||
=========================================================================
|
||||
|
||||
Elaborating module <WarpLC>.
|
||||
WARNING:HDLCompiler:1016 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port LOCKED is not connected to this instance
|
||||
|
||||
Elaborating module <CLKGEN>.
|
||||
Elaborating module <ClkGen>.
|
||||
|
||||
Elaborating module <CLK>.
|
||||
Elaborating module <PLL>.
|
||||
|
||||
Elaborating module <IBUFG>.
|
||||
|
||||
Elaborating module <BUFIO2FB(DIVIDE_BYPASS="TRUE")>.
|
||||
|
||||
Elaborating module <PLL_BASE(BANDWIDTH="OPTIMIZED",CLK_FEEDBACK="CLKFBOUT",COMPENSATION="EXTERNAL",DIVCLK_DIVIDE=1,CLKFBOUT_MULT=12,CLKFBOUT_PHASE=0.0,CLKOUT0_DIVIDE=6,CLKOUT0_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,CLKIN_PERIOD=30.0,REF_JITTER=0.008)>.
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 128: Assignment to clkout1_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 129: Assignment to clkout2_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 130: Assignment to clkout3_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 131: Assignment to clkout4_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 132: Assignment to clkout5_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 133: Assignment to locked_unused ignored, since the identifier is never used
|
||||
Elaborating module <PLL_BASE(BANDWIDTH="HIGH",CLK_FEEDBACK="CLKFBOUT",COMPENSATION="EXTERNAL",DIVCLK_DIVIDE=1,CLKFBOUT_MULT=28,CLKFBOUT_PHASE=0.0,CLKOUT0_DIVIDE=14,CLKOUT0_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,CLKIN_PERIOD=30.0,REF_JITTER=0.01)>.
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to clkout1_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to clkout2_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to clkout3_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to clkout4_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to clkout5_unused ignored, since the identifier is never used
|
||||
|
||||
Elaborating module <BUFG>.
|
||||
|
||||
Elaborating module <ODDR2>.
|
||||
|
||||
Elaborating module <ODDR2(DDR_ALIGNMENT="C0",INIT=1'b0,SRTYPE="ASYNC")>.
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 84: Assignment to CPUCLKr ignored, since the identifier is never used
|
||||
|
||||
Elaborating module <SizeDecode>.
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to FSB_B ignored, since the identifier is never used
|
||||
|
||||
Elaborating module <L2Prefetch>.
|
||||
|
||||
Elaborating module <PrefetchTagRAM>.
|
||||
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module <PrefetchTagRAM> remains a black box.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 33: Size mismatch in connection of port <a>. Formal port size is 5-bit while actual signal size is 7-bit.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 36: Size mismatch in connection of port <dpra>. Formal port size is 5-bit while actual signal size is 7-bit.
|
||||
|
||||
Elaborating module <PrefetchDataRAM>.
|
||||
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" Line 39: Empty module <PrefetchDataRAM> remains a black box.
|
||||
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 44: Size mismatch in connection of port <addra>. Formal port size is 7-bit while actual signal size is 5-bit.
|
||||
WARNING:Xst:2972 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 91. All outputs of instance <sd> of block <SizeDecode> are unconnected in block <WarpLC>. Underlying logic will be removed.
|
||||
|
||||
=========================================================================
|
||||
* HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Synthesizing Unit <WarpLC>.
|
||||
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v".
|
||||
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v".
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <FSB_A>.
|
||||
Set property "IOBDELAY = NONE" for signal <FSB_A>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <FSB_SIZ>.
|
||||
Set property "IOBDELAY = NONE" for signal <FSB_SIZ>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <FSB_D>.
|
||||
Set property "DRIVE = 8" for signal <FSB_D>.
|
||||
Set property "SLEW = SLOW" for signal <FSB_D>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nAS>.
|
||||
Set property "IOBDELAY = NONE" for signal <CPU_nAS>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <INt>.
|
||||
Set property "IOBDELAY = NONE" for signal <INt>.
|
||||
Set property "IOB = FALSE" for signal <OUTt>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <OUTt>.
|
||||
Set property "DRIVE = 24" for signal <OUTt>.
|
||||
Set property "SLEW = FAST" for signal <OUTt>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nSTERM>.
|
||||
Set property "DRIVE = 24" for signal <CPU_nSTERM>.
|
||||
Set property "SLEW = FAST" for signal <CPU_nSTERM>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPUCLK>.
|
||||
Set property "DRIVE = 24" for signal <CPUCLK>.
|
||||
Set property "SLEW = FAST" for signal <CPUCLK>.
|
||||
@ -172,8 +196,6 @@ Synthesizing Unit <WarpLC>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAMCLK1>.
|
||||
Set property "DRIVE = 24" for signal <RAMCLK1>.
|
||||
Set property "SLEW = FAST" for signal <RAMCLK1>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPUCLKi>.
|
||||
Set property "IOBDELAY = NONE" for signal <CPUCLKi>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CLKIN>.
|
||||
Set property "IOBDELAY = NONE" for signal <CLKIN>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CLKFB_IN>.
|
||||
@ -181,37 +203,44 @@ Synthesizing Unit <WarpLC>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CLKFB_OUT>.
|
||||
Set property "DRIVE = 24" for signal <CLKFB_OUT>.
|
||||
Set property "SLEW = FAST" for signal <CLKFB_OUT>.
|
||||
INFO:Xst:3210 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 79: Output port <CPUCLKr> of the instance <CLKGEN_inst> is unconnected or connected to loadless signal.
|
||||
Found 32-bit register for signal <AR>.
|
||||
Found 1-bit register for signal <OUTt>.
|
||||
Found 32-bit comparator equal for signal <FSB_A[31]_AR[31]_equal_2_o> created at line 92
|
||||
WARNING:Xst:647 - Input <FSB_A<31:29>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <CPU_nAS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 91: Output port <B> of the instance <sd> is unconnected or connected to loadless signal.
|
||||
Summary:
|
||||
inferred 33 D-type flip-flop(s).
|
||||
inferred 1 Comparator(s).
|
||||
no macro.
|
||||
Unit <WarpLC> synthesized.
|
||||
|
||||
Synthesizing Unit <CLKGEN>.
|
||||
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\CLKGEN.v".
|
||||
Synthesizing Unit <ClkGen>.
|
||||
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v".
|
||||
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" line 32: Output port <LOCKED> of the instance <pll> is unconnected or connected to loadless signal.
|
||||
Found 1-bit register for signal <CPUCLKr>.
|
||||
Summary:
|
||||
inferred 1 D-type flip-flop(s).
|
||||
Unit <CLKGEN> synthesized.
|
||||
Unit <ClkGen> synthesized.
|
||||
|
||||
Synthesizing Unit <CLK>.
|
||||
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v".
|
||||
Synthesizing Unit <PLL>.
|
||||
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v".
|
||||
Summary:
|
||||
no macro.
|
||||
Unit <CLK> synthesized.
|
||||
Unit <PLL> synthesized.
|
||||
|
||||
Synthesizing Unit <L2Prefetch>.
|
||||
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v".
|
||||
WARNING:Xst:647 - Input <RDA<28:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <WRA<28:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
Found 21-bit comparator equal for signal <RDTag[20]_RDATag[20]_equal_5_o> created at line 28
|
||||
Summary:
|
||||
inferred 1 Comparator(s).
|
||||
Unit <L2Prefetch> synthesized.
|
||||
|
||||
=========================================================================
|
||||
HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Registers : 3
|
||||
1-bit register : 2
|
||||
32-bit register : 1
|
||||
# Registers : 1
|
||||
1-bit register : 1
|
||||
# Comparators : 1
|
||||
32-bit comparator equal : 1
|
||||
21-bit comparator equal : 1
|
||||
|
||||
=========================================================================
|
||||
|
||||
@ -219,15 +248,19 @@ Macro Statistics
|
||||
* Advanced HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Reading core <ipcore_dir/PrefetchTagRAM.ngc>.
|
||||
Reading core <ipcore_dir/PrefetchDataRAM.ngc>.
|
||||
Loading core <PrefetchTagRAM> for timing and area information for instance <Way0Tag>.
|
||||
Loading core <PrefetchDataRAM> for timing and area information for instance <Way0Data>.
|
||||
|
||||
=========================================================================
|
||||
Advanced HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Registers : 34
|
||||
Flip-Flops : 34
|
||||
# Registers : 1
|
||||
Flip-Flops : 1
|
||||
# Comparators : 1
|
||||
32-bit comparator equal : 1
|
||||
21-bit comparator equal : 1
|
||||
|
||||
=========================================================================
|
||||
|
||||
@ -238,11 +271,13 @@ INFO:Xst:1901 - Instance pll_base_inst in unit pll_base_inst of type PLL_BASE ha
|
||||
|
||||
Optimizing unit <WarpLC> ...
|
||||
|
||||
Optimizing unit <CLK> ...
|
||||
Optimizing unit <ClkGen> ...
|
||||
|
||||
Optimizing unit <PLL> ...
|
||||
|
||||
Mapping all equations...
|
||||
Building and optimizing final netlist ...
|
||||
Found area constraint ratio of 100 (+ 5) on block WarpLC, actual ratio is 1.
|
||||
Found area constraint ratio of 100 (+ 5) on block WarpLC, actual ratio is 0.
|
||||
|
||||
Final Macro Processing ...
|
||||
|
||||
@ -250,8 +285,8 @@ Final Macro Processing ...
|
||||
Final Register Report
|
||||
|
||||
Macro Statistics
|
||||
# Registers : 34
|
||||
Flip-Flops : 34
|
||||
# Registers : 1
|
||||
Flip-Flops : 1
|
||||
|
||||
=========================================================================
|
||||
|
||||
@ -274,23 +309,26 @@ Top Level Output File Name : WarpLC.ngc
|
||||
|
||||
Primitive and Black Box Usage:
|
||||
------------------------------
|
||||
# BELS : 29
|
||||
# GND : 1
|
||||
# BELS : 22
|
||||
# GND : 2
|
||||
# INV : 3
|
||||
# LUT3 : 1
|
||||
# LUT4 : 1
|
||||
# LUT6 : 10
|
||||
# MUXCY : 12
|
||||
# LUT1 : 1
|
||||
# LUT6 : 7
|
||||
# MUXCY : 8
|
||||
# VCC : 1
|
||||
# FlipFlops/Latches : 39
|
||||
# FD : 34
|
||||
# FlipFlops/Latches : 50
|
||||
# FD : 44
|
||||
# FDR : 1
|
||||
# ODDR2 : 5
|
||||
# RAMS : 23
|
||||
# RAM32X1D : 22
|
||||
# RAMB8BWER : 1
|
||||
# Clock Buffers : 2
|
||||
# BUFG : 2
|
||||
# IO Buffers : 43
|
||||
# IBUF : 35
|
||||
# IO Buffers : 66
|
||||
# IBUF : 26
|
||||
# IBUFG : 2
|
||||
# OBUF : 6
|
||||
# OBUF : 38
|
||||
# Others : 2
|
||||
# BUFIO2FB : 1
|
||||
# PLL_ADV : 1
|
||||
@ -302,22 +340,26 @@ Selected Device : 6slx9ftg256-2
|
||||
|
||||
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 39 out of 11440 0%
|
||||
Number of Slice LUTs: 15 out of 5720 0%
|
||||
Number used as Logic: 15 out of 5720 0%
|
||||
Number of Slice Registers: 50 out of 11440 0%
|
||||
Number of Slice LUTs: 55 out of 5720 0%
|
||||
Number used as Logic: 11 out of 5720 0%
|
||||
Number used as Memory: 44 out of 1440 3%
|
||||
Number used as RAM: 44
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of LUT Flip Flop pairs used: 52
|
||||
Number with an unused Flip Flop: 13 out of 52 25%
|
||||
Number with an unused LUT: 37 out of 52 71%
|
||||
Number of fully used LUT-FF pairs: 2 out of 52 3%
|
||||
Number of unique control sets: 1
|
||||
Number of LUT Flip Flop pairs used: 105
|
||||
Number with an unused Flip Flop: 55 out of 105 52%
|
||||
Number with an unused LUT: 50 out of 105 47%
|
||||
Number of fully used LUT-FF pairs: 0 out of 105 0%
|
||||
Number of unique control sets: 2
|
||||
|
||||
IO Utilization:
|
||||
Number of IOs: 43
|
||||
Number of bonded IOBs: 43 out of 186 23%
|
||||
Number of IOs: 75
|
||||
Number of bonded IOBs: 66 out of 186 35%
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of Block RAM/FIFO: 1 out of 32 3%
|
||||
Number using Block RAM only: 1
|
||||
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
|
||||
Number of PLL_ADVs: 1 out of 2 50%
|
||||
|
||||
@ -339,12 +381,12 @@ NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
||||
|
||||
Clock Information:
|
||||
------------------
|
||||
------------------------------------------------+------------------------+-------+
|
||||
Clock Signal | Clock buffer(FF name) | Load |
|
||||
------------------------------------------------+------------------------+-------+
|
||||
CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 | BUFG | 42 |
|
||||
CLKGEN_inst/instance_name/pll_base_inst/CLKFBOUT| BUFG | 2 |
|
||||
------------------------------------------------+------------------------+-------+
|
||||
-----------------------------------+------------------------+-------+
|
||||
Clock Signal | Clock buffer(FF name) | Load |
|
||||
-----------------------------------+------------------------+-------+
|
||||
cg/pll/pll_base_inst/CLKOUT0 | BUFG | 76 |
|
||||
cg/pll/pll_base_inst/CLKFBOUT | BUFG | 2 |
|
||||
-----------------------------------+------------------------+-------+
|
||||
|
||||
Asynchronous Control Signals Information:
|
||||
----------------------------------------
|
||||
@ -354,129 +396,141 @@ Timing Summary:
|
||||
---------------
|
||||
Speed Grade: -2
|
||||
|
||||
Minimum period: 2.580ns (Maximum Frequency: 387.597MHz)
|
||||
Minimum input arrival time before clock: 3.547ns
|
||||
Maximum output required time after clock: 4.118ns
|
||||
Maximum combinational path delay: 1.328ns
|
||||
Minimum period: 4.696ns (Maximum Frequency: 212.947MHz)
|
||||
Minimum input arrival time before clock: 3.719ns
|
||||
Maximum output required time after clock: 6.384ns
|
||||
Maximum combinational path delay: 8.292ns
|
||||
|
||||
Timing Details:
|
||||
---------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default period analysis for Clock 'CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0'
|
||||
Clock period: 2.580ns (frequency: 387.597MHz)
|
||||
Total number of paths / destination ports: 35 / 4
|
||||
Timing constraint: Default period analysis for Clock 'cg/pll/pll_base_inst/CLKOUT0'
|
||||
Clock period: 4.696ns (frequency: 212.947MHz)
|
||||
Total number of paths / destination ports: 50 / 50
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 1.290ns (Levels of Logic = 0)
|
||||
Source: CLKGEN_inst/CPUCLKr (FF)
|
||||
Destination: CLKGEN_inst/FPUCLK_inst (FF)
|
||||
Source Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 rising
|
||||
Destination Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 falling
|
||||
Delay: 2.348ns (Levels of Logic = 1)
|
||||
Source: cg/CPUCLKr (FF)
|
||||
Destination: cg/CPUCLK_inst (FF)
|
||||
Source Clock: cg/pll/pll_base_inst/CLKOUT0 rising
|
||||
Destination Clock: cg/pll/pll_base_inst/CLKOUT0 falling
|
||||
|
||||
Data Path: CLKGEN_inst/CPUCLKr to CLKGEN_inst/FPUCLK_inst
|
||||
Data Path: cg/CPUCLKr to cg/CPUCLK_inst
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FD:C->Q 3 0.525 0.765 CLKGEN_inst/CPUCLKr (CLKGEN_inst/CPUCLKr)
|
||||
ODDR2:D1 0.000 CLKGEN_inst/FPUCLK_inst
|
||||
FDR:C->Q 4 0.525 0.803 cg/CPUCLKr (cg/CPUCLKr)
|
||||
INV:I->O 3 0.255 0.765 l2pre/CPUCLKr_INV_15_o1_INV_0 (l2pre/CPUCLKr_INV_15_o)
|
||||
ODDR2:D1 0.000 cg/CPUCLK_inst
|
||||
----------------------------------------
|
||||
Total 1.290ns (0.525ns logic, 0.765ns route)
|
||||
(40.7% logic, 59.3% route)
|
||||
Total 2.348ns (0.780ns logic, 1.568ns route)
|
||||
(33.2% logic, 66.8% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0'
|
||||
Total number of paths / destination ports: 67 / 33
|
||||
Timing constraint: Default OFFSET IN BEFORE for Clock 'cg/pll/pll_base_inst/CLKOUT0'
|
||||
Total number of paths / destination ports: 225 / 137
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 3.547ns (Levels of Logic = 14)
|
||||
Offset: 3.719ns (Levels of Logic = 3)
|
||||
Source: FSB_A<2> (PAD)
|
||||
Destination: OUTt (FF)
|
||||
Destination Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 rising
|
||||
Destination: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_21 (FF)
|
||||
Destination Clock: cg/pll/pll_base_inst/CLKOUT0 rising
|
||||
|
||||
Data Path: FSB_A<2> to OUTt
|
||||
Data Path: FSB_A<2> to l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_21
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 2 1.328 1.181 FSB_A_2_IBUF (FSB_A_2_IBUF)
|
||||
LUT6:I0->O 1 0.254 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0>)
|
||||
MUXCY:S->O 1 0.215 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<0> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<0>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<1> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<1>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<2> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<2>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<4> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<4>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<5> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<5>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<6> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<6>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<8> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<8>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<9> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<9>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<10> (FSB_A[31]_AR[31]_equal_2_o)
|
||||
MUXCY:CI->O 1 0.262 0.000 CPU_nAS_FSB_A[31]_AND_3_o1_cy (CPU_nAS_FSB_A[31]_AND_3_o)
|
||||
FD:D 0.074 OUTt
|
||||
IBUF:I->O 23 1.328 1.357 FSB_A_2_IBUF (FSB_A_2_IBUF)
|
||||
begin scope: 'l2pre/Way0Tag:dpra<0>'
|
||||
RAM32X1D:DPRA0->DPO 2 0.235 0.725 U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 (dpo<2>)
|
||||
FD:D 0.074 U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_2
|
||||
----------------------------------------
|
||||
Total 3.547ns (2.366ns logic, 1.181ns route)
|
||||
(66.7% logic, 33.3% route)
|
||||
Total 3.719ns (1.637ns logic, 2.082ns route)
|
||||
(44.0% logic, 56.0% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0'
|
||||
Total number of paths / destination ports: 1 / 1
|
||||
Timing constraint: Default OFFSET OUT AFTER for Clock 'cg/pll/pll_base_inst/CLKOUT0'
|
||||
Total number of paths / destination ports: 54 / 33
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 4.118ns (Levels of Logic = 1)
|
||||
Source: OUTt (FF)
|
||||
Destination: OUTt (PAD)
|
||||
Source Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 rising
|
||||
Offset: 6.384ns (Levels of Logic = 11)
|
||||
Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 (RAM)
|
||||
Destination: CPU_nSTERM (PAD)
|
||||
Source Clock: cg/pll/pll_base_inst/CLKOUT0 rising
|
||||
|
||||
Data Path: OUTt to OUTt
|
||||
Data Path: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 to CPU_nSTERM
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FD:C->Q 1 0.525 0.681 OUTt (OUTt_OBUF)
|
||||
OBUF:I->O 2.912 OUTt_OBUF (OUTt)
|
||||
RAM32X1D:WCLK->DPO 2 1.012 0.954 U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 (dpo<2>)
|
||||
end scope: 'l2pre/Way0Tag:dpo<2>'
|
||||
LUT6:I3->O 1 0.235 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>)
|
||||
MUXCY:S->O 1 0.215 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<0> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<0>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<1> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<1>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<2> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<2>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<4> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<4>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<5> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<5>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6> (l2pre/RDTag[20]_RDATag[20]_equal_5_o)
|
||||
MUXCY:CI->O 1 0.235 0.681 CPU_nSTERM1_cy (CPU_nSTERM_OBUF)
|
||||
OBUF:I->O 2.912 CPU_nSTERM_OBUF (CPU_nSTERM)
|
||||
----------------------------------------
|
||||
Total 4.118ns (3.437ns logic, 0.681ns route)
|
||||
(83.5% logic, 16.5% route)
|
||||
Total 6.384ns (4.749ns logic, 1.635ns route)
|
||||
(74.4% logic, 25.6% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default path analysis
|
||||
Total number of paths / destination ports: 1 / 1
|
||||
Total number of paths / destination ports: 132 / 2
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 1.328ns (Levels of Logic = 1)
|
||||
Source: CLKFB_IN (PAD)
|
||||
Destination: CLKGEN_inst/instance_name/clkfb_bufio2fb:I (PAD)
|
||||
Delay: 8.292ns (Levels of Logic = 13)
|
||||
Source: FSB_A<2> (PAD)
|
||||
Destination: CPU_nSTERM (PAD)
|
||||
|
||||
Data Path: CLKFB_IN to CLKGEN_inst/instance_name/clkfb_bufio2fb:I
|
||||
Data Path: FSB_A<2> to CPU_nSTERM
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUFG:I->O 0 1.328 0.000 CLKGEN_inst/instance_name/clkfb_ibufg (CLKGEN_inst/instance_name/clkfb_ibuf2bufio2fb)
|
||||
BUFIO2FB:I 0.000 CLKGEN_inst/instance_name/clkfb_bufio2fb
|
||||
IBUF:I->O 23 1.328 1.357 FSB_A_2_IBUF (FSB_A_2_IBUF)
|
||||
begin scope: 'l2pre/Way0Tag:dpra<0>'
|
||||
RAM32X1D:DPRA0->DPO 2 0.235 0.954 U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 (dpo<2>)
|
||||
end scope: 'l2pre/Way0Tag:dpo<2>'
|
||||
LUT6:I3->O 1 0.235 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>)
|
||||
MUXCY:S->O 1 0.215 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<0> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<0>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<1> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<1>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<2> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<2>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<4> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<4>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<5> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<5>)
|
||||
MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6> (l2pre/RDTag[20]_RDATag[20]_equal_5_o)
|
||||
MUXCY:CI->O 1 0.235 0.681 CPU_nSTERM1_cy (CPU_nSTERM_OBUF)
|
||||
OBUF:I->O 2.912 CPU_nSTERM_OBUF (CPU_nSTERM)
|
||||
----------------------------------------
|
||||
Total 1.328ns (1.328ns logic, 0.000ns route)
|
||||
(100.0% logic, 0.0% route)
|
||||
Total 8.292ns (5.300ns logic, 2.992ns route)
|
||||
(63.9% logic, 36.1% route)
|
||||
|
||||
=========================================================================
|
||||
|
||||
Cross Clock Domains Report:
|
||||
--------------------------
|
||||
|
||||
Clock to Setup on destination clock CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0
|
||||
-----------------------------------------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
-----------------------------------------------+---------+---------+---------+---------+
|
||||
CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0| 2.454| | 1.290| |
|
||||
-----------------------------------------------+---------+---------+---------+---------+
|
||||
Clock to Setup on destination clock cg/pll/pll_base_inst/CLKOUT0
|
||||
----------------------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
----------------------------+---------+---------+---------+---------+
|
||||
cg/pll/pll_base_inst/CLKOUT0| 2.568| | 2.348| |
|
||||
----------------------------+---------+---------+---------+---------+
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 2.00 secs
|
||||
Total CPU time to Xst completion: 2.72 secs
|
||||
Total REAL time to Xst completion: 6.00 secs
|
||||
Total CPU time to Xst completion: 6.67 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 225148 kilobytes
|
||||
Total memory usage is 258804 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 7 ( 0 filtered)
|
||||
Number of infos : 2 ( 0 filtered)
|
||||
Number of warnings : 17 ( 0 filtered)
|
||||
Number of infos : 3 ( 0 filtered)
|
||||
|
||||
|
||||
14381
fpga/WarpLC.twr
14381
fpga/WarpLC.twr
File diff suppressed because it is too large
Load Diff
230
fpga/WarpLC.twx
230
fpga/WarpLC.twx
File diff suppressed because one or more lines are too long
@ -1,7 +1,7 @@
|
||||
Release 14.7 - par P.20131013 (nt)
|
||||
Release 14.7 - par P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Fri Oct 29 17:59:53 2021
|
||||
Sun Oct 31 15:38:33 2021
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
@ -29,13 +29,17 @@ module WarpLC(
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY = "NONE" *)
|
||||
input INt,
|
||||
input [1:0] FSB_SIZ,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "8" *)
|
||||
(* SLEW = "SLOW" *)
|
||||
output [31:0] FSB_D,
|
||||
|
||||
(* IOB = "FALSE" *)
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLEW = "FAST" *)
|
||||
output reg OUTt,
|
||||
output CPU_nSTERM,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
@ -56,11 +60,7 @@ module WarpLC(
|
||||
(* DRIVE = "24" *)
|
||||
(* SLEW = "FAST" *)
|
||||
output RAMCLK1,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY = "NONE" *)
|
||||
input CPUCLKi,
|
||||
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY = "NONE" *)
|
||||
input CLKIN,
|
||||
@ -76,7 +76,7 @@ module WarpLC(
|
||||
|
||||
wire FSBCLK;
|
||||
wire CPUCLKr;
|
||||
CLKGEN CLKGEN_inst(
|
||||
ClkGen cg (
|
||||
.CLKIN(CLKIN),
|
||||
.CLKFB_IN(CLKFB_IN),
|
||||
.CLKFB_OUT(CLKFB_OUT),
|
||||
@ -86,11 +86,28 @@ module WarpLC(
|
||||
.FPUCLK(FPUCLK),
|
||||
.RAMCLK0(RAMCLK0),
|
||||
.RAMCLK1(RAMCLK1));
|
||||
|
||||
wire [3:0] FSB_B;
|
||||
SizeDecode sd (
|
||||
.A(FSB_A[1:0]),
|
||||
.SIZ(FSB_SIZ[1:0]),
|
||||
.B(FSB_B[3:0]));
|
||||
|
||||
reg [31:0] AR;
|
||||
always @(posedge FSBCLK) begin
|
||||
OUTt <= ~CPU_nAS && INt && CPUCLKi && FSB_A[31:0]==AR[31:0];
|
||||
AR[31:0] <= FSB_A[31:0];
|
||||
end
|
||||
wire L2PrefetchMatch;
|
||||
L2Prefetch l2pre (
|
||||
.CLK(FSBCLK),
|
||||
.CPUCLKr(CPUCLKr),
|
||||
|
||||
.RDA(FSB_A[28:2]),
|
||||
.RDD(FSB_D[31:0]),
|
||||
.Match(L2PrefetchMatch),
|
||||
|
||||
.WRA(27'b0),
|
||||
.WRD(32'b0),
|
||||
.WR(1'b0),
|
||||
.WRM(4'b0),
|
||||
.CLR(1'b0));
|
||||
|
||||
assign CPU_nSTERM = ~(L2PrefetchMatch);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -17,28 +17,46 @@
|
||||
<files>
|
||||
<file xil_pn:name="WarpLC.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/CLK.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="PLL.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="CLKGEN.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="sterminator.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
|
||||
</file>
|
||||
<file xil_pn:name="PrefetchBuf.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/CLK.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<file xil_pn:name="ipcore_dir/PrefetchTagRAM.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PrefetchDataRAM.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="ClkGen.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
</file>
|
||||
<file xil_pn:name="L2Cache.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="SizeDecode.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PrefetchTagRAM.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PrefetchDataRAM.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PLL.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
@ -67,7 +85,7 @@
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
@ -108,8 +126,8 @@
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@ -121,7 +139,7 @@
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
@ -147,10 +165,10 @@
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="Inpad To Outpad" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
@ -201,7 +219,7 @@
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="High" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
@ -222,7 +240,7 @@
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="WarpLC" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="L2Prefetch" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
@ -234,12 +252,12 @@
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="WarpLC_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="WarpLC_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="WarpLC_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="WarpLC_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="L2Prefetch_map.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="L2Prefetch_timesim.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="L2Prefetch_synthesis.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="L2Prefetch_translate.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@ -255,7 +273,7 @@
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
@ -270,7 +288,7 @@
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="1000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
@ -7,13 +7,13 @@ run
|
||||
-p xc6slx9-2-ftg256
|
||||
-top WarpLC
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-opt_level 2
|
||||
-power NO
|
||||
-iuc NO
|
||||
-keep_hierarchy No
|
||||
-netlist_hierarchy As_Optimized
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-glob_opt Inpad_To_Outpad
|
||||
-read_cores YES
|
||||
-sd {"ipcore_dir" }
|
||||
-write_timing_constraints NO
|
||||
|
||||
342
fpga/WarpLC_2021-10-31-15-23-24.twx
Normal file
342
fpga/WarpLC_2021-10-31-15-23-24.twx
Normal file
File diff suppressed because one or more lines are too long
@ -22,10 +22,10 @@
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Path</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\PuTTY\;<br>C:\Program Files (x86)\WinMerge;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Dog\AppData\Local\GitHubDesktop\bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\PuTTY\;<br>C:\Program Files (x86)\WinMerge;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Dog\AppData\Local\GitHubDesktop\bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\PuTTY\;<br>C:\Program Files (x86)\WinMerge;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Dog\AppData\Local\GitHubDesktop\bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\PuTTY\;<br>C:\Program Files (x86)\WinMerge;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\Dog\AppData\Local\GitHubDesktop\bin</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX</td>
|
||||
@ -106,7 +106,7 @@
|
||||
<tr>
|
||||
<td>-opt_level</td>
|
||||
<td>Optimization Effort</td>
|
||||
<td>1</td>
|
||||
<td>2</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -142,7 +142,7 @@
|
||||
<tr>
|
||||
<td>-glob_opt</td>
|
||||
<td>Global Optimization Goal</td>
|
||||
<td>AllClockNets</td>
|
||||
<td>Inpad_To_Outpad</td>
|
||||
<td>AllClockNets</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -410,18 +410,42 @@
|
||||
<td>high</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-xe</td>
|
||||
<td>Placer Extra Effort Map</td>
|
||||
<td>CONTINUE</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-xt</td>
|
||||
<td>Extra Cost Tables</td>
|
||||
<td>0</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-global_opt</td>
|
||||
<td>Global Optimization map</td>
|
||||
<td>TRUE</td>
|
||||
<td>FALSE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ir</td>
|
||||
<td>Use RLOC Constraints</td>
|
||||
<td>OFF</td>
|
||||
<td>OFF</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-logic_opt</td>
|
||||
<td>Combinatorial Logic Optimization</td>
|
||||
<td>TRUE</td>
|
||||
<td>FALSE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-mt</td>
|
||||
<td>Enable Multi-Threading</td>
|
||||
<td>2</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-t</td>
|
||||
<td>Starting Placer Cost Table (1-100) Map</td>
|
||||
<td>1</td>
|
||||
@ -434,6 +458,12 @@
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-equivalent_register_removal</td>
|
||||
<td>Equivalent Register Removal</td>
|
||||
<td>TRUE</td>
|
||||
<td>TRUE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
@ -482,6 +512,12 @@
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-xe</td>
|
||||
<td> </td>
|
||||
<td>c</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
@ -490,7 +526,7 @@
|
||||
<tr>
|
||||
<td>-mt</td>
|
||||
<td>Enable Multi-Threading</td>
|
||||
<td>off</td>
|
||||
<td>4</td>
|
||||
<td>off</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -520,31 +556,31 @@
|
||||
</tr>
|
||||
<tr>
|
||||
<td>CPU Architecture/Speed</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
<td>Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz</td>
|
||||
<td>Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz</td>
|
||||
<td>Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz</td>
|
||||
<td>Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Host</td>
|
||||
<td>ZanePC</td>
|
||||
<td>ZanePC</td>
|
||||
<td>ZanePC</td>
|
||||
<td>ZanePC</td>
|
||||
<td>Dog-PC</td>
|
||||
<td>Dog-PC</td>
|
||||
<td>Dog-PC</td>
|
||||
<td>Dog-PC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Name</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Release</td>
|
||||
<td>major release (build 9200)</td>
|
||||
<td>major release (build 9200)</td>
|
||||
<td>major release (build 9200)</td>
|
||||
<td>major release (build 9200)</td>
|
||||
<td>Service Pack 1 (build 7601)</td>
|
||||
<td>Service Pack 1 (build 7601)</td>
|
||||
<td>Service Pack 1 (build 7601)</td>
|
||||
<td>Service Pack 1 (build 7601)</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
</BODY> </HTML>
|
||||
File diff suppressed because one or more lines are too long
@ -1,32 +1,18 @@
|
||||
Release 14.7 Map P.20131013 (nt)
|
||||
Release 14.7 Map P.20131013 (nt64)
|
||||
Xilinx Map Application Log File for Design 'WarpLC'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol
|
||||
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
|
||||
-pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high
|
||||
-xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2
|
||||
-ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
Target Device : xc6slx9
|
||||
Target Package : ftg256
|
||||
Target Speed : -2
|
||||
Mapper Version : spartan6 -- $Revision: 1.55 $
|
||||
Mapped Date : Fri Oct 29 17:59:44 2021
|
||||
Mapped Date : Sun Oct 31 15:38:01 2021
|
||||
|
||||
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
|
||||
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
|
||||
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
|
||||
'C:\ispLEVER_Classic2_0\license\license.dat;C:\lscc\diamond\3.12\license\license
|
||||
.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'.
|
||||
INFO:Security:54 - 'xc6slx9' is a WebPack part.
|
||||
INFO:Security:66 - Your license for 'ISE' is for evaluation use only.
|
||||
WARNING:Security:43 - No license file was found in the standard Xilinx license
|
||||
directory.
|
||||
WARNING:Security:44 - Since no license file was found,
|
||||
please run the Xilinx License Configuration Manager
|
||||
(xlcm or "Manage Xilinx Licenses")
|
||||
to assist in obtaining a license.
|
||||
WARNING:Security:40 - Your license for 'ISE' expires in 4 days.
|
||||
----------------------------------------------------------------------
|
||||
Running global optimization...
|
||||
Mapping design into LUTs...
|
||||
Running directed packing...
|
||||
Running delay-based LUT packing...
|
||||
@ -34,94 +20,103 @@ Updating timing models...
|
||||
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
|
||||
(.mrp).
|
||||
Running timing-driven placement...
|
||||
Total REAL time at the beginning of Placer: 2 secs
|
||||
Total CPU time at the beginning of Placer: 2 secs
|
||||
Total REAL time at the beginning of Placer: 10 secs
|
||||
Total CPU time at the beginning of Placer: 10 secs
|
||||
|
||||
Phase 1.1 Initial Placement Analysis
|
||||
Phase 1.1 Initial Placement Analysis (Checksum:18bd) REAL time: 2 secs
|
||||
Phase 1.1 Initial Placement Analysis (Checksum:283d) REAL time: 10 secs
|
||||
|
||||
Phase 2.7 Design Feasibility Check
|
||||
Phase 2.7 Design Feasibility Check (Checksum:18bd) REAL time: 2 secs
|
||||
Phase 2.7 Design Feasibility Check (Checksum:283d) REAL time: 11 secs
|
||||
|
||||
Phase 3.31 Local Placement Optimization
|
||||
Phase 3.31 Local Placement Optimization (Checksum:18bd) REAL time: 2 secs
|
||||
Phase 3.31 Local Placement Optimization (Checksum:283d) REAL time: 11 secs
|
||||
|
||||
Phase 4.2 Initial Placement for Architecture Specific Features
|
||||
...
|
||||
....
|
||||
Phase 4.2 Initial Placement for Architecture Specific Features
|
||||
(Checksum:4099679c) REAL time: 3 secs
|
||||
(Checksum:8c2c3f8) REAL time: 15 secs
|
||||
|
||||
Phase 5.36 Local Placement Optimization
|
||||
Phase 5.36 Local Placement Optimization (Checksum:4099679c) REAL time: 3 secs
|
||||
Phase 5.36 Local Placement Optimization (Checksum:8c2c3f8) REAL time: 15 secs
|
||||
|
||||
Phase 6.30 Global Clock Region Assignment
|
||||
Phase 6.30 Global Clock Region Assignment (Checksum:4099679c) REAL time: 3 secs
|
||||
Phase 6.30 Global Clock Region Assignment (Checksum:8c2c3f8) REAL time: 15 secs
|
||||
|
||||
Phase 7.3 Local Placement Optimization
|
||||
...
|
||||
Phase 7.3 Local Placement Optimization (Checksum:432b55c8) REAL time: 3 secs
|
||||
....
|
||||
Phase 7.3 Local Placement Optimization (Checksum:f4c788ab) REAL time: 21 secs
|
||||
|
||||
Phase 8.5 Local Placement Optimization
|
||||
Phase 8.5 Local Placement Optimization (Checksum:432b55c8) REAL time: 3 secs
|
||||
Phase 8.5 Local Placement Optimization (Checksum:f4c788ab) REAL time: 21 secs
|
||||
|
||||
Phase 9.8 Global Placement
|
||||
..
|
||||
................
|
||||
................
|
||||
..
|
||||
Phase 9.8 Global Placement (Checksum:8bf5099b) REAL time: 3 secs
|
||||
Phase 9.8 Global Placement (Checksum:67f9eb6e) REAL time: 21 secs
|
||||
|
||||
Phase 10.5 Local Placement Optimization
|
||||
Phase 10.5 Local Placement Optimization (Checksum:8bf5099b) REAL time: 3 secs
|
||||
Phase 10.5 Local Placement Optimization (Checksum:67f9eb6e) REAL time: 21 secs
|
||||
|
||||
Phase 11.18 Placement Optimization
|
||||
Phase 11.18 Placement Optimization (Checksum:8bd6219d) REAL time: 3 secs
|
||||
Phase 11.18 Placement Optimization (Checksum:32dd77c2) REAL time: 22 secs
|
||||
|
||||
Phase 12.5 Local Placement Optimization
|
||||
Phase 12.5 Local Placement Optimization (Checksum:8bd6219d) REAL time: 3 secs
|
||||
Phase 12.5 Local Placement Optimization (Checksum:32dd77c2) REAL time: 22 secs
|
||||
|
||||
Phase 13.34 Placement Validation
|
||||
Phase 13.34 Placement Validation (Checksum:8bd2a88c) REAL time: 3 secs
|
||||
Phase 13.34 Placement Validation (Checksum:32dd77c2) REAL time: 22 secs
|
||||
|
||||
Total REAL time to Placer completion: 3 secs
|
||||
Total CPU time to Placer completion: 3 secs
|
||||
Total REAL time to Placer completion: 22 secs
|
||||
Total CPU time to Placer completion: 22 secs
|
||||
Running physical synthesis...
|
||||
|
||||
Physical synthesis completed.
|
||||
Running post-placement packing...
|
||||
Writing output files...
|
||||
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
|
||||
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
|
||||
default, may be incorrect and should not be used. For more information,
|
||||
please reference Xilinx Answer Record 39999.
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Design Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
Number of warnings: 1
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 34 out of 11,440 1%
|
||||
Number used as Flip Flops: 34
|
||||
Number of Slice Registers: 1 out of 11,440 1%
|
||||
Number used as Flip Flops: 1
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 17 out of 5,720 1%
|
||||
Number used as logic: 13 out of 5,720 1%
|
||||
Number using O6 output only: 11
|
||||
Number using O5 output only: 0
|
||||
Number using O5 and O6: 2
|
||||
Number of Slice LUTs: 33 out of 5,720 1%
|
||||
Number used as logic: 9 out of 5,720 1%
|
||||
Number using O6 output only: 8
|
||||
Number using O5 output only: 1
|
||||
Number using O5 and O6: 0
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 0 out of 1,440 0%
|
||||
Number used exclusively as route-thrus: 4
|
||||
Number with same-slice register load: 4
|
||||
Number with same-slice carry load: 0
|
||||
Number with other load: 0
|
||||
Number used as Memory: 24 out of 1,440 1%
|
||||
Number used as Dual Port RAM: 24
|
||||
Number using O6 output only: 4
|
||||
Number using O5 output only: 0
|
||||
Number using O5 and O6: 20
|
||||
Number used as Single Port RAM: 0
|
||||
Number used as Shift Register: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 11 out of 1,430 1%
|
||||
Number of MUXCYs used: 12 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 41
|
||||
Number with an unused Flip Flop: 11 out of 41 26%
|
||||
Number with an unused LUT: 24 out of 41 58%
|
||||
Number of fully used LUT-FF pairs: 6 out of 41 14%
|
||||
Number of unique control sets: 1
|
||||
Number of occupied Slices: 9 out of 1,430 1%
|
||||
Number of MUXCYs used: 8 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 33
|
||||
Number with an unused Flip Flop: 32 out of 33 96%
|
||||
Number with an unused LUT: 0 out of 33 0%
|
||||
Number of fully used LUT-FF pairs: 1 out of 33 3%
|
||||
Number of unique control sets: 2
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 6 out of 11,440 1%
|
||||
to control set restrictions: 11 out of 11,440 1%
|
||||
|
||||
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
||||
one Flip Flop within a slice. A control set is a unique combination of
|
||||
@ -130,12 +125,12 @@ Slice Logic Distribution:
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 43 out of 186 23%
|
||||
Number of bonded IOBs: 66 out of 186 35%
|
||||
IOB Flip Flops: 5
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 0 out of 32 0%
|
||||
Number of RAMB8BWERs: 0 out of 64 0%
|
||||
Number of RAMB8BWERs: 1 out of 64 1%
|
||||
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2s: 1
|
||||
Number used as BUFIO2_2CLKs: 0
|
||||
@ -164,11 +159,11 @@ Specific Feature Utilization:
|
||||
Number of STARTUPs: 0 out of 1 0%
|
||||
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 1.41
|
||||
Average Fanout of Non-Clock Nets: 1.67
|
||||
|
||||
Peak Memory Usage: 276 MB
|
||||
Total REAL time to MAP completion: 3 secs
|
||||
Total CPU time to MAP completion: 3 secs
|
||||
Peak Memory Usage: 368 MB
|
||||
Total REAL time to MAP completion: 25 secs
|
||||
Total CPU time to MAP completion (all processors): 25 secs
|
||||
|
||||
Mapping completed.
|
||||
See MAP report file "WarpLC_map.mrp" for details.
|
||||
|
||||
@ -1,49 +1,51 @@
|
||||
Release 14.7 Map P.20131013 (nt)
|
||||
Release 14.7 Map P.20131013 (nt64)
|
||||
Xilinx Mapping Report File for Design 'WarpLC'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol
|
||||
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
|
||||
-pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high
|
||||
-xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2
|
||||
-ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
Target Device : xc6slx9
|
||||
Target Package : ftg256
|
||||
Target Speed : -2
|
||||
Mapper Version : spartan6 -- $Revision: 1.55 $
|
||||
Mapped Date : Fri Oct 29 17:59:44 2021
|
||||
Mapped Date : Sun Oct 31 15:38:01 2021
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
Number of warnings: 1
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 34 out of 11,440 1%
|
||||
Number used as Flip Flops: 34
|
||||
Number of Slice Registers: 1 out of 11,440 1%
|
||||
Number used as Flip Flops: 1
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 17 out of 5,720 1%
|
||||
Number used as logic: 13 out of 5,720 1%
|
||||
Number using O6 output only: 11
|
||||
Number using O5 output only: 0
|
||||
Number using O5 and O6: 2
|
||||
Number of Slice LUTs: 33 out of 5,720 1%
|
||||
Number used as logic: 9 out of 5,720 1%
|
||||
Number using O6 output only: 8
|
||||
Number using O5 output only: 1
|
||||
Number using O5 and O6: 0
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 0 out of 1,440 0%
|
||||
Number used exclusively as route-thrus: 4
|
||||
Number with same-slice register load: 4
|
||||
Number with same-slice carry load: 0
|
||||
Number with other load: 0
|
||||
Number used as Memory: 24 out of 1,440 1%
|
||||
Number used as Dual Port RAM: 24
|
||||
Number using O6 output only: 4
|
||||
Number using O5 output only: 0
|
||||
Number using O5 and O6: 20
|
||||
Number used as Single Port RAM: 0
|
||||
Number used as Shift Register: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 11 out of 1,430 1%
|
||||
Number of MUXCYs used: 12 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 41
|
||||
Number with an unused Flip Flop: 11 out of 41 26%
|
||||
Number with an unused LUT: 24 out of 41 58%
|
||||
Number of fully used LUT-FF pairs: 6 out of 41 14%
|
||||
Number of unique control sets: 1
|
||||
Number of occupied Slices: 9 out of 1,430 1%
|
||||
Number of MUXCYs used: 8 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 33
|
||||
Number with an unused Flip Flop: 32 out of 33 96%
|
||||
Number with an unused LUT: 0 out of 33 0%
|
||||
Number of fully used LUT-FF pairs: 1 out of 33 3%
|
||||
Number of unique control sets: 2
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 6 out of 11,440 1%
|
||||
to control set restrictions: 11 out of 11,440 1%
|
||||
|
||||
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
||||
one Flip Flop within a slice. A control set is a unique combination of
|
||||
@ -52,12 +54,12 @@ Slice Logic Distribution:
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 43 out of 186 23%
|
||||
Number of bonded IOBs: 66 out of 186 35%
|
||||
IOB Flip Flops: 5
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 0 out of 32 0%
|
||||
Number of RAMB8BWERs: 0 out of 64 0%
|
||||
Number of RAMB8BWERs: 1 out of 64 1%
|
||||
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2s: 1
|
||||
Number used as BUFIO2_2CLKs: 0
|
||||
@ -86,11 +88,11 @@ Specific Feature Utilization:
|
||||
Number of STARTUPs: 0 out of 1 0%
|
||||
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 1.41
|
||||
Average Fanout of Non-Clock Nets: 1.67
|
||||
|
||||
Peak Memory Usage: 276 MB
|
||||
Total REAL time to MAP completion: 3 secs
|
||||
Total CPU time to MAP completion: 3 secs
|
||||
Peak Memory Usage: 368 MB
|
||||
Total REAL time to MAP completion: 25 secs
|
||||
Total CPU time to MAP completion (all processors): 25 secs
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
@ -113,22 +115,26 @@ Section 1 - Errors
|
||||
|
||||
Section 2 - Warnings
|
||||
--------------------
|
||||
WARNING:Security:43 - No license file was found in the standard Xilinx license
|
||||
directory.
|
||||
WARNING:Security:44 - Since no license file was found,
|
||||
WARNING:Security:40 - Your license for 'ISE' expires in 4 days.
|
||||
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
|
||||
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
|
||||
default, may be incorrect and should not be used. For more information,
|
||||
please reference Xilinx Answer Record 39999.
|
||||
|
||||
Section 3 - Informational
|
||||
-------------------------
|
||||
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
|
||||
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
|
||||
'C:\ispLEVER_Classic2_0\license\license.dat;C:\lscc\diamond\3.12\license\license
|
||||
.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'.
|
||||
INFO:Security:54 - 'xc6slx9' is a WebPack part.
|
||||
INFO:Security:66 - Your license for 'ISE' is for evaluation use only.
|
||||
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
|
||||
supports the use of up to 2 processors. Based on the the user options and
|
||||
machine load, Map will use 2 processors during this run.
|
||||
INFO:LIT:243 - Logical network FSB_A<31> has no load.
|
||||
INFO:LIT:395 - The above info message is repeated 54 more times for the
|
||||
following (max. 5 shown):
|
||||
FSB_A<30>,
|
||||
FSB_A<29>,
|
||||
FSB_A<28>,
|
||||
FSB_A<1>,
|
||||
FSB_A<0>
|
||||
To see the details of these info messages, please use the -detail switch.
|
||||
INFO:MapLib:562 - No environment variables are currently set.
|
||||
INFO:MapLib:159 - Net Timing constraints on signal CLKIN are pushed forward
|
||||
through input buffer.
|
||||
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
|
||||
0.000 to 85.000 Celsius)
|
||||
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
|
||||
@ -139,11 +145,314 @@ INFO:Pack:1650 - Map created a placed design.
|
||||
|
||||
Section 4 - Removed Logic Summary
|
||||
---------------------------------
|
||||
46 block(s) removed
|
||||
2 block(s) optimized away
|
||||
68 signal(s) removed
|
||||
|
||||
Section 5 - Removed Logic
|
||||
-------------------------
|
||||
|
||||
The trimmed logic report below shows the logic removed from your design due to
|
||||
sourceless or loadless signals, and VCC or ground connections. If the removal
|
||||
of a signal or symbol results in the subsequent removal of an additional signal
|
||||
or symbol, the message explaining that second removal will be indented. This
|
||||
indentation will be repeated as a chain of related logic is removed.
|
||||
|
||||
To quickly locate the original cause for the removal of a chain of logic, look
|
||||
above the place where that logic is listed in the trimming report, then locate
|
||||
the lines that are least indented (begin at the leftmost edge).
|
||||
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<0>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_0"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<1>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_1"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<2>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_2"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<3>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_3"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<4>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_4"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<5>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_5"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<6>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_6"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<7>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_7"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<8>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_8"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<9>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_9"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<10>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_10"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<11>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_11"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<12>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_12"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<13>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_13"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<14>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_14"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<15>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_15"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<16>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_16"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<17>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_17"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<18>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_18"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<19>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_19"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<20>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_20"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<21>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_21"
|
||||
(FF) removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<0>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_0"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<0>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<1>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_1"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<1>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<2>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_2"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<2>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<3>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_3"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<3>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<4>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_4"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<4>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<5>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_5"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<5>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<6>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_6"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<6>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<7>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_7"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<7>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<8>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_8"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<8>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<9>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_9"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<9>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<10>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_10"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<10>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<11>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_11"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<11>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<12>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_12"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<12>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<13>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_13"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<13>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<14>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_14"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<14>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<15>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_15"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<15>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<16>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_16"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<16>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<17>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_17"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<17>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<18>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_18"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<18>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<19>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_19"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<19>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<20>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_20"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<20>" is loadless and has been removed.
|
||||
The signal
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<21>"
|
||||
is loadless and has been removed.
|
||||
Loadless block
|
||||
"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_21"
|
||||
(FF) removed.
|
||||
The signal "l2pre/Way0Tag/spo<21>" is loadless and has been removed.
|
||||
The signal "cg/pll/pll_base_inst/N2" is sourceless and has been removed.
|
||||
The signal "cg/pll/pll_base_inst/N3" is sourceless and has been removed.
|
||||
Unused block "cg/pll/pll_base_inst/XST_GND" (ZERO) removed.
|
||||
Unused block "cg/pll/pll_base_inst/XST_VCC" (ONE) removed.
|
||||
|
||||
Optimized Block(s):
|
||||
TYPE BLOCK
|
||||
GND XST_GND
|
||||
@ -163,11 +472,8 @@ Section 6 - IOB Properties
|
||||
| CLKFB_OUT | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
| CLKIN | IOB | INPUT | LVCMOS25 | | | | | | |
|
||||
| CPUCLK | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
| CPUCLKi | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| CPU_nAS | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| CPU_nSTERM | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | | | |
|
||||
| FPUCLK | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
| FSB_A<0> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<1> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<2> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<3> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<4> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
@ -194,12 +500,38 @@ Section 6 - IOB Properties
|
||||
| FSB_A<25> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<26> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<27> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<28> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<29> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<30> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<31> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| INt | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| OUTt | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | | | |
|
||||
| FSB_D<0> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<1> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<2> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<3> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<4> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<5> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<6> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<7> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<8> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<9> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<10> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<11> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<12> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<13> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<14> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<15> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<16> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<17> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<18> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<19> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<20> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<21> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<22> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<23> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<24> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<25> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<26> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<27> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<28> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<29> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<30> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| FSB_D<31> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | |
|
||||
| RAMCLK0 | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
| RAMCLK1 | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
145
fpga/WarpLC_map.psr
Normal file
145
fpga/WarpLC_map.psr
Normal file
@ -0,0 +1,145 @@
|
||||
Release 14.7 Physical Synthesis Report P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
TABLE OF CONTENTS
|
||||
1) Physical Synthesis Options Summary
|
||||
2) Optimizations statistics and details
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Physical Synthesis Options Summary *
|
||||
=========================================================================
|
||||
---- Options
|
||||
Global Optimization : ON
|
||||
Retiming : OFF
|
||||
Equivalent Register Removal : ON
|
||||
Timing-Driven Packing and Placement : ON
|
||||
Logic Optimization : ON
|
||||
Register Duplication : OFF
|
||||
|
||||
---- Intelligent clock gating : OFF
|
||||
|
||||
---- Target Parameters
|
||||
Target Device : 6slx9ftg256-2
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Optimizations *
|
||||
=========================================================================
|
||||
---- Statistics
|
||||
Number of registers added by Synchronous Optimization | 1
|
||||
Number of LUTs removed by SmartOpt Trimming | 95
|
||||
|
||||
Overall change in number of design objects | -94
|
||||
|
||||
|
||||
---- Details
|
||||
|
||||
New or modified components | Optimization | Objective
|
||||
-------------------------------------------------------|--------------------------|----------------------
|
||||
cg/CPUCLKr | Synchronous Optimization | Performance
|
||||
|
||||
|
||||
Removed components | Optimization
|
||||
-------------------------------------------------------|--------------------------
|
||||
][288_1 | SmartOpt Trimming
|
||||
][291_2 | SmartOpt Trimming
|
||||
][293_4 | SmartOpt Trimming
|
||||
][294_5 | SmartOpt Trimming
|
||||
][297_7 | SmartOpt Trimming
|
||||
][73_8 | SmartOpt Trimming
|
||||
][const_101_66 | SmartOpt Trimming
|
||||
][const_102_67 | SmartOpt Trimming
|
||||
][const_104_68 | SmartOpt Trimming
|
||||
][const_105_69 | SmartOpt Trimming
|
||||
][const_107_70 | SmartOpt Trimming
|
||||
][const_108_71 | SmartOpt Trimming
|
||||
][const_110_72 | SmartOpt Trimming
|
||||
][const_111_73 | SmartOpt Trimming
|
||||
][const_113_74 | SmartOpt Trimming
|
||||
][const_114_75 | SmartOpt Trimming
|
||||
][const_116_76 | SmartOpt Trimming
|
||||
][const_117_77 | SmartOpt Trimming
|
||||
][const_119_78 | SmartOpt Trimming
|
||||
][const_120_79 | SmartOpt Trimming
|
||||
][const_122_80 | SmartOpt Trimming
|
||||
][const_123_81 | SmartOpt Trimming
|
||||
][const_125_82 | SmartOpt Trimming
|
||||
][const_126_83 | SmartOpt Trimming
|
||||
][const_128_84 | SmartOpt Trimming
|
||||
][const_129_85 | SmartOpt Trimming
|
||||
][const_131_86 | SmartOpt Trimming
|
||||
][const_132_87 | SmartOpt Trimming
|
||||
][const_134_88 | SmartOpt Trimming
|
||||
][const_135_89 | SmartOpt Trimming
|
||||
][const_137_90 | SmartOpt Trimming
|
||||
][const_138_91 | SmartOpt Trimming
|
||||
][const_140_92 | SmartOpt Trimming
|
||||
][const_141_93 | SmartOpt Trimming
|
||||
][const_143_94 | SmartOpt Trimming
|
||||
][const_144_95 | SmartOpt Trimming
|
||||
][const_146_96 | SmartOpt Trimming
|
||||
][const_147_97 | SmartOpt Trimming
|
||||
][const_15_9 | SmartOpt Trimming
|
||||
][const_17_10 | SmartOpt Trimming
|
||||
][const_18_11 | SmartOpt Trimming
|
||||
][const_20_12 | SmartOpt Trimming
|
||||
][const_21_13 | SmartOpt Trimming
|
||||
][const_23_14 | SmartOpt Trimming
|
||||
][const_24_15 | SmartOpt Trimming
|
||||
][const_26_16 | SmartOpt Trimming
|
||||
][const_27_17 | SmartOpt Trimming
|
||||
][const_29_18 | SmartOpt Trimming
|
||||
][const_30_19 | SmartOpt Trimming
|
||||
][const_32_20 | SmartOpt Trimming
|
||||
][const_33_21 | SmartOpt Trimming
|
||||
][const_35_22 | SmartOpt Trimming
|
||||
][const_36_23 | SmartOpt Trimming
|
||||
][const_38_24 | SmartOpt Trimming
|
||||
][const_39_25 | SmartOpt Trimming
|
||||
][const_41_26 | SmartOpt Trimming
|
||||
][const_42_27 | SmartOpt Trimming
|
||||
][const_44_28 | SmartOpt Trimming
|
||||
][const_45_29 | SmartOpt Trimming
|
||||
][const_47_30 | SmartOpt Trimming
|
||||
][const_48_31 | SmartOpt Trimming
|
||||
][const_50_32 | SmartOpt Trimming
|
||||
][const_51_33 | SmartOpt Trimming
|
||||
][const_53_34 | SmartOpt Trimming
|
||||
][const_54_35 | SmartOpt Trimming
|
||||
][const_56_36 | SmartOpt Trimming
|
||||
][const_57_37 | SmartOpt Trimming
|
||||
][const_59_38 | SmartOpt Trimming
|
||||
][const_60_39 | SmartOpt Trimming
|
||||
][const_62_40 | SmartOpt Trimming
|
||||
][const_63_41 | SmartOpt Trimming
|
||||
][const_65_42 | SmartOpt Trimming
|
||||
][const_66_43 | SmartOpt Trimming
|
||||
][const_68_44 | SmartOpt Trimming
|
||||
][const_69_45 | SmartOpt Trimming
|
||||
][const_71_46 | SmartOpt Trimming
|
||||
][const_72_47 | SmartOpt Trimming
|
||||
][const_74_48 | SmartOpt Trimming
|
||||
][const_75_49 | SmartOpt Trimming
|
||||
][const_77_50 | SmartOpt Trimming
|
||||
][const_78_51 | SmartOpt Trimming
|
||||
][const_80_52 | SmartOpt Trimming
|
||||
][const_81_53 | SmartOpt Trimming
|
||||
][const_83_54 | SmartOpt Trimming
|
||||
][const_84_55 | SmartOpt Trimming
|
||||
][const_86_56 | SmartOpt Trimming
|
||||
][const_87_57 | SmartOpt Trimming
|
||||
][const_89_58 | SmartOpt Trimming
|
||||
][const_90_59 | SmartOpt Trimming
|
||||
][const_92_60 | SmartOpt Trimming
|
||||
][const_93_61 | SmartOpt Trimming
|
||||
][const_95_62 | SmartOpt Trimming
|
||||
][const_96_63 | SmartOpt Trimming
|
||||
][const_98_64 | SmartOpt Trimming
|
||||
][const_99_65 | SmartOpt Trimming
|
||||
|
||||
|
||||
Flops added for Enable Generation
|
||||
-------------------------
|
||||
@ -1,18 +1,18 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="nt" product="ISE" version="14.7">
|
||||
<document OS="nt64" product="ISE" version="14.7">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Map" timeStamp="Fri Oct 29 17:59:48 2021">
|
||||
<application stringID="Map" timeStamp="Sun Oct 31 15:38:26 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files\Microchip\xc8\v2.31\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\PuTTY\;C:\Program Files\WinMerge;C:\Program Files\dotnet\;C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;C:\Users\zanek\AppData\Local\GitHubDesktop\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\zanek\.dotnet\tools;C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\PuTTY\;C:\Program Files (x86)\WinMerge;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\Microchip\xc8\v2.31\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\Dog\AppData\Local\GitHubDesktop\bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
@ -36,26 +36,31 @@
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
|
||||
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="ZanePC"/>
|
||||
<item stringID="User_EnvHost" value="Dog-PC"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz"/>
|
||||
<item stringID="speed" value="3500 MHz"/>
|
||||
<item stringID="arch" value="Intel(R) Xeon(R) CPU W3680 @ 3.33GHz"/>
|
||||
<item stringID="speed" value="3316 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="MAP_OPTION_SUMMARY">
|
||||
<item DEFAULT="high" label="-ol" stringID="MAP_EFFORTLEVEL" value="high"/>
|
||||
<item DEFAULT="" label="-xe" stringID="MAP_EXTRAEFFORTLEVEL" value="CONTINUE"/>
|
||||
<item DEFAULT="0" label="-xt" stringID="MAP_EXTRA_COST_TABLE" value="0"/>
|
||||
<item DEFAULT="FALSE" label="-global_opt" stringID="MAP_GLOBALOPT" value="TRUE"/>
|
||||
<item DEFAULT="OFF" label="-ir" stringID="MAP_IGNORERLOCS" value="OFF"/>
|
||||
<item DEFAULT="FALSE" label="-logic_opt" stringID="MAP_LOGICOPT" value="TRUE"/>
|
||||
<item DEFAULT="OFF" stringID="MAP_LUTCOMPRESSIONMODE" value="OFF"/>
|
||||
<item DEFAULT="0" label="-mt" stringID="MAP_MULTI_THREADING" value="2"/>
|
||||
<item DEFAULT="0" label="-t" stringID="MAP_PLACERCOSTTABLE" value="1"/>
|
||||
<item DEFAULT="4" label="-r" stringID="MAP_REGORDERING" value="4"/>
|
||||
<item DEFAULT="TRUE" label="-equivalent_register_removal" stringID="MAP_REMOVEEQUIVREGISTERS" value="TRUE"/>
|
||||
<item DEFAULT="FALSE" stringID="MAP_REPLICATELUTS" value="TRUE"/>
|
||||
<item DEFAULT="None" label="-intstyle" stringID="MAP_INTSTYLE" value="ise"/>
|
||||
<item DEFAULT="off" label="-lc" stringID="MAP_LUT_COMBINING" value="off"/>
|
||||
@ -65,22 +70,22 @@
|
||||
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx9-ftg256-2"/>
|
||||
</section>
|
||||
<task stringID="MAP_PACK_REPORT">
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="34">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="34"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="1">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="1"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="13">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="0"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="11"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="2"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="33">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="1"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="8"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="4"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="20"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
|
||||
@ -94,7 +99,7 @@
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="43"/>
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="66"/>
|
||||
<item AVAILABLE="14" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="5"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
|
||||
@ -116,28 +121,28 @@
|
||||
<section stringID="MAP_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
|
||||
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="282568"/>
|
||||
<item stringID="MAP_TOTAL_REAL_TIME" value="3 secs "/>
|
||||
<item stringID="MAP_TOTAL_CPU_TIME" value="3 secs "/>
|
||||
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="1"/>
|
||||
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="377184"/>
|
||||
<item stringID="MAP_TOTAL_REAL_TIME" value="25 secs "/>
|
||||
<item stringID="MAP_TOTAL_CPU_TIME" value="25 secs "/>
|
||||
</section>
|
||||
<section stringID="MAP_SLICE_REPORTING">
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="34">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="34"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="1">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="1"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="17">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="0"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="11"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="2"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="33">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="1"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="8"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="4"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="20"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
|
||||
@ -145,25 +150,25 @@
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="4"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="4"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="11">
|
||||
<item AVAILABLE="355" dataType="int" stringID="MAP_NUM_SLICEL" value="3"/>
|
||||
<item AVAILABLE="360" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
|
||||
<item AVAILABLE="715" dataType="int" stringID="MAP_NUM_SLICEX" value="8"/>
|
||||
<item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="9">
|
||||
<item AVAILABLE="355" dataType="int" stringID="MAP_NUM_SLICEL" value="2"/>
|
||||
<item AVAILABLE="360" dataType="int" stringID="MAP_NUM_SLICEM" value="6"/>
|
||||
<item AVAILABLE="715" dataType="int" stringID="MAP_NUM_SLICEX" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="41">
|
||||
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="11"/>
|
||||
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="24"/>
|
||||
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="6"/>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="33">
|
||||
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="32"/>
|
||||
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="0"/>
|
||||
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="1"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="MAP_IOB_REPORTING">
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="43"/>
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="66"/>
|
||||
<item AVAILABLE="14" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="5"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
|
||||
@ -179,7 +184,7 @@
|
||||
<section stringID="MAP_HARD_IP_REPORTING"/>
|
||||
<section stringID="MAP_RAM_FIFO_DATA">
|
||||
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
|
||||
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
|
||||
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="1"/>
|
||||
</section>
|
||||
<section stringID="MAP_IP_DATA">
|
||||
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
|
||||
@ -249,18 +254,14 @@
|
||||
<item label="Reg
(s)" stringID="REGS" value="ODDR"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPUCLKi"/>
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPU_nSTERM"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
</row>
|
||||
<row stringID="row" value="6">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPU_nAS"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="7">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FPUCLK"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
@ -269,213 +270,419 @@
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="ODDR"/>
|
||||
</row>
|
||||
<row stringID="row" value="8">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<0>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="9">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<1>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="10">
|
||||
<row stringID="row" value="7">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<2>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="11">
|
||||
<row stringID="row" value="8">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<3>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="12">
|
||||
<row stringID="row" value="9">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<4>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="13">
|
||||
<row stringID="row" value="10">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<5>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="14">
|
||||
<row stringID="row" value="11">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<6>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="15">
|
||||
<row stringID="row" value="12">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<7>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="16">
|
||||
<row stringID="row" value="13">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<8>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="17">
|
||||
<row stringID="row" value="14">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<9>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="18">
|
||||
<row stringID="row" value="15">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<10>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="19">
|
||||
<row stringID="row" value="16">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<11>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="20">
|
||||
<row stringID="row" value="17">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<12>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="21">
|
||||
<row stringID="row" value="18">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<13>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="22">
|
||||
<row stringID="row" value="19">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<14>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="23">
|
||||
<row stringID="row" value="20">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<15>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="24">
|
||||
<row stringID="row" value="21">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<16>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="25">
|
||||
<row stringID="row" value="22">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<17>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="26">
|
||||
<row stringID="row" value="23">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<18>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="27">
|
||||
<row stringID="row" value="24">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<19>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="28">
|
||||
<row stringID="row" value="25">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<20>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="29">
|
||||
<row stringID="row" value="26">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<21>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="30">
|
||||
<row stringID="row" value="27">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<22>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="31">
|
||||
<row stringID="row" value="28">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<23>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="32">
|
||||
<row stringID="row" value="29">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<24>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="33">
|
||||
<row stringID="row" value="30">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<25>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="34">
|
||||
<row stringID="row" value="31">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<26>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="35">
|
||||
<row stringID="row" value="32">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<27>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="36">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<28>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="37">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<29>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="38">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<30>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="39">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<31>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="40">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="INt"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="41">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="OUTt"/>
|
||||
<row stringID="row" value="33">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<0>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="34">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<1>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="35">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<2>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="36">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<3>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="37">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<4>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="38">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<5>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="39">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<6>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="40">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<7>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="41">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<8>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="42">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<9>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="43">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<10>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="44">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<11>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="45">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<12>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="46">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<13>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="47">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<14>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="48">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<15>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="49">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<16>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="50">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<17>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="51">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<18>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="52">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<19>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="53">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<20>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="54">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<21>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="55">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<22>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="56">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<23>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="57">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<24>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="58">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<25>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="59">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<26>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="60">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<27>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="61">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<28>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="62">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<29>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="63">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<30>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="64">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_D<31>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
</row>
|
||||
<row stringID="row" value="65">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RAMCLK0"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
@ -484,7 +691,7 @@
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="ODDR"/>
|
||||
</row>
|
||||
<row stringID="row" value="43">
|
||||
<row stringID="row" value="66">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RAMCLK1"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
@ -505,7 +712,7 @@
|
||||
<section stringID="MAP_TIMING_REPORT"/>
|
||||
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
|
||||
<section stringID="MAP_GENERAL_CONFIG_DATA">
|
||||
<item stringID="MAP_BANDWIDTH" value="OPTIMIZED"/>
|
||||
<item stringID="MAP_BANDWIDTH" value="HIGH"/>
|
||||
<item stringID="MAP_CLK_FEEDBACK" value="CLKFBOUT"/>
|
||||
<item stringID="MAP_COMPENSATION" value="EXTERNAL"/>
|
||||
<item stringID="MAP_CLKFBOUT_PHASE" value="0.0"/>
|
||||
@ -531,7 +738,7 @@
|
||||
<item stringID="MAP_DIVCLK_DIVIDE" value="1"/>
|
||||
</section>
|
||||
<section stringID="MAP_CONTROL_SET_INFORMATION">
|
||||
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="1"/>
|
||||
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="2"/>
|
||||
<tree stringID="MAP_CONTROL_SET_HIERARCHY">
|
||||
<property stringID="MAP_CLOCK_SIGNAL"/>
|
||||
<property stringID="MAP_RESET_SIGNAL"/>
|
||||
@ -544,7 +751,7 @@
|
||||
</task>
|
||||
<section stringID="MAP_RAM_FIFO_DATA">
|
||||
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
|
||||
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
|
||||
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="1"/>
|
||||
</section>
|
||||
<section stringID="MAP_IP_DATA">
|
||||
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
|
||||
@ -568,7 +775,7 @@
|
||||
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
|
||||
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_RPMS" value="0"/>
|
||||
<item stringID="MAP_BANDWIDTH" value="OPTIMIZED"/>
|
||||
<item stringID="MAP_BANDWIDTH" value="HIGH"/>
|
||||
<item stringID="MAP_CLK_FEEDBACK" value="CLKFBOUT"/>
|
||||
<item stringID="MAP_COMPENSATION" value="EXTERNAL"/>
|
||||
<item stringID="MAP_CLKFBOUT_PHASE" value="0.0"/>
|
||||
|
||||
@ -1,18 +1,18 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="nt" product="ISE" version="14.7">
|
||||
<document OS="nt64" product="ISE" version="14.7">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Fri Oct 29 17:59:43 2021">
|
||||
<application stringID="NgdBuild" timeStamp="Sun Oct 31 15:37:59 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files\Microchip\xc8\v2.31\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\PuTTY\;C:\Program Files\WinMerge;C:\Program Files\dotnet\;C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;C:\Users\zanek\AppData\Local\GitHubDesktop\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\zanek\.dotnet\tools;C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\PuTTY\;C:\Program Files (x86)\WinMerge;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\Microchip\xc8\v2.31\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\Dog\AppData\Local\GitHubDesktop\bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
@ -36,16 +36,16 @@
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
|
||||
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="ZanePC"/>
|
||||
<item stringID="User_EnvHost" value="Dog-PC"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz"/>
|
||||
<item stringID="speed" value="3500 MHz"/>
|
||||
<item stringID="arch" value="Intel(R) Xeon(R) CPU W3680 @ 3.33GHz"/>
|
||||
<item stringID="speed" value="3316 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
@ -62,49 +62,64 @@
|
||||
<section stringID="NGDBUILD_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="9"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="2"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFIO2FB" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="34"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="44"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="26"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="12"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="8"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="38"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ODDR2" value="5"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAM32X1D" value="22"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAMB8BWER" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFIO2FB" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="34"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="44"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="26"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="12"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="8"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="38"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ODDR2" value="5"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_PLL_ADV" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAMB8BWER" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
|
||||
<section stringID="NGDBUILD_CORE_INSTANCES">
|
||||
<scope stringID="NGDBUILD_CORE_INSTANCE" value="CLK">
|
||||
<item stringID="NGDBUILD_CORE_INFO" type="clk_wiz_v3_6" value="CLK"/>
|
||||
<item clkin1_period="30.0" clkin2_period="30.0" clock_mgr_type="MANUAL" component_name="CLK" feedback_source="FDBK_AUTO_OFFCHIP" feedback_type="SINGLE" manual_override="false" num_out_clk="1" primtype_sel="PLL_BASE" stringID="NGDBUILD_CORE_PARAMETERS" use_clk_valid="false" use_dyn_phase_shift="false" use_dyn_reconfig="false" use_freeze="false" use_inclk_stopped="false" use_inclk_switchover="false" use_locked="false" use_max_i_jitter="false" use_min_o_jitter="false" use_phase_alignment="true" use_power_down="false" use_reset="false" use_status="false" value="CLK"/>
|
||||
</scope>
|
||||
<section stringID="NGDBUILD_CORE_SUMMARY">
|
||||
<item COUNT="1" stringID="NGDBUILD_CORE" value="dist_mem_gen_v7_2, Xilinx CORE Generator 14.7"/>
|
||||
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
|
||||
<section stringID="NGDBUILD_CORE_INSTANCES">
|
||||
<scope stringID="NGDBUILD_CORE_INSTANCE" value="PLL">
|
||||
<item stringID="NGDBUILD_CORE_INFO" type="clk_wiz_v3_6" value="PLL"/>
|
||||
<item clkin1_period="30.000" clkin2_period="30.000" clock_mgr_type="MANUAL" component_name="PLL" feedback_source="FDBK_AUTO_OFFCHIP" feedback_type="SINGLE" manual_override="false" num_out_clk="1" primtype_sel="PLL_BASE" stringID="NGDBUILD_CORE_PARAMETERS" use_clk_valid="false" use_dyn_phase_shift="false" use_dyn_reconfig="false" use_freeze="false" use_inclk_stopped="false" use_inclk_switchover="false" use_locked="true" use_max_i_jitter="false" use_min_o_jitter="true" use_phase_alignment="true" use_power_down="false" use_reset="false" use_status="false" value="PLL"/>
|
||||
</scope>
|
||||
<scope stringID="NGDBUILD_CORE_INSTANCE" value="PrefetchDataRAM">
|
||||
<item stringID="NGDBUILD_CORE_INFO" type="blk_mem_gen_v7_3" value="PrefetchDataRAM"/>
|
||||
<item c_addra_width="7" c_addrb_width="7" c_algorithm="1" c_axi_id_width="4" c_axi_slave_type="0" c_axi_type="1" c_byte_size="8" c_common_clk="1" c_default_data="0" c_disable_warn_bhv_coll="0" c_disable_warn_bhv_range="0" c_elaboration_dir="masked_value" c_enable_32bit_address="0" c_family="spartan6" c_has_axi_id="0" c_has_ena="1" c_has_enb="1" c_has_injecterr="0" c_has_mem_output_regs_a="0" c_has_mem_output_regs_b="0" c_has_mux_output_regs_a="0" c_has_mux_output_regs_b="0" c_has_regcea="0" c_has_regceb="0" c_has_rsta="0" c_has_rstb="0" c_has_softecc_input_regs_a="0" c_has_softecc_output_regs_b="0" c_init_file="BlankString" c_init_file_name="no_coe_file_loaded" c_inita_val="0" c_initb_val="0" c_interface_type="0" c_load_init_file="0" c_mem_type="1" c_mux_pipeline_stages="0" c_prim_type="1" c_read_depth_a="128" c_read_depth_b="128" c_read_width_a="32" c_read_width_b="32" c_rst_priority_a="CE" c_rst_priority_b="CE" c_rst_type="SYNC" c_rstram_a="0" c_rstram_b="0" c_sim_collision_check="ALL" c_use_bram_block="0" c_use_byte_wea="1" c_use_byte_web="1" c_use_default_data="0" c_use_ecc="0" c_use_softecc="0" c_wea_width="4" c_web_width="4" c_write_depth_a="128" c_write_depth_b="128" c_write_mode_a="READ_FIRST" c_write_mode_b="READ_FIRST" c_write_width_a="32" c_write_width_b="32" c_xdevicefamily="spartan6" stringID="NGDBUILD_CORE_PARAMETERS" value="PrefetchDataRAM"/>
|
||||
</scope>
|
||||
<scope stringID="NGDBUILD_CORE_INSTANCE" value="PrefetchTagRAM">
|
||||
<item stringID="NGDBUILD_CORE_INFO" type="dist_mem_gen_v7_2" value="PrefetchTagRAM"/>
|
||||
<item c_addr_width="5" c_default_data="0" c_depth="32" c_elaboration_dir="masked_value" c_family="spartan6" c_has_clk="1" c_has_d="1" c_has_dpo="1" c_has_dpra="1" c_has_i_ce="0" c_has_qdpo="0" c_has_qdpo_ce="0" c_has_qdpo_clk="0" c_has_qdpo_rst="0" c_has_qdpo_srst="0" c_has_qspo="0" c_has_qspo_ce="0" c_has_qspo_rst="0" c_has_qspo_srst="0" c_has_spo="1" c_has_spra="0" c_has_we="1" c_mem_init_file="no_coe_file_loaded" c_mem_type="2" c_parser_type="1" c_pipeline_stages="0" c_qce_joined="0" c_qualify_we="0" c_read_mif="0" c_reg_a_d_inputs="0" c_reg_dpra_input="0" c_sync_enable="1" c_width="22" stringID="NGDBUILD_CORE_PARAMETERS" value="PrefetchTagRAM"/>
|
||||
</scope>
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
</task>
|
||||
|
||||
287
fpga/WarpLC_pad.csv
Normal file
287
fpga/WarpLC_pad.csv
Normal file
@ -0,0 +1,287 @@
|
||||
#Release 14.7 - par P.20131013 (nt64)
|
||||
#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
#Sun Oct 31 15:38:33 2021
|
||||
|
||||
#
|
||||
## NOTE: This file is designed to be imported into a spreadsheet program
|
||||
# such as Microsoft Excel for viewing, printing and sorting. The |
|
||||
# character is used as the data field separator. This file is also designed
|
||||
# to support parsing.
|
||||
#
|
||||
#INPUT FILE: WarpLC_map.ncd
|
||||
#OUTPUT FILE: WarpLC_pad.csv
|
||||
#PART TYPE: xc6slx9
|
||||
#SPEED GRADE: -2
|
||||
#PACKAGE: ftg256
|
||||
#
|
||||
# Pinout by Pin Number:
|
||||
#
|
||||
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
|
||||
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
|
||||
A1,,,GND,,,,,,,,,,,,
|
||||
A2,,IOBS,IO_L52N_M3A9_3,UNUSED,,3,,,,,,,,,
|
||||
A3,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,,
|
||||
A4,CLKFB_OUT,IOB,IO_L1N_VREF_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
A5,FSB_D<0>,IOB,IO_L2N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A6,FSB_D<4>,IOB,IO_L4N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A7,FSB_D<6>,IOB,IO_L6N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A8,FSB_D<12>,IOB,IO_L33N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A9,FSB_D<14>,IOB,IO_L34N_GCLK18_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A10,FSB_D<16>,IOB,IO_L35N_GCLK16_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A11,FSB_D<22>,IOB,IO_L39N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A12,FSB_D<28>,IOB,IO_L62N_VREF_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A13,FSB_D<30>,IOB,IO_L63N_SCP6_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
A14,RAMCLK0,IOB,IO_L65N_SCP2_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
A15,,,TMS,,,,,,,,,,,,
|
||||
A16,,,GND,,,,,,,,,,,,
|
||||
B1,,IOBS,IO_L50N_M3BA2_3,UNUSED,,3,,,,,,,,,
|
||||
B2,,IOBM,IO_L52P_M3A8_3,UNUSED,,3,,,,,,,,,
|
||||
B3,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,,
|
||||
B4,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
B5,CPUCLK,IOB,IO_L2P_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
B6,FSB_D<3>,IOB,IO_L4P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
B7,,,GND,,,,,,,,,,,,
|
||||
B8,FSB_D<11>,IOB,IO_L33P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
B9,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
B10,FSB_D<15>,IOB,IO_L35P_GCLK17_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
B11,,,GND,,,,,,,,,,,,
|
||||
B12,FSB_D<27>,IOB,IO_L62P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
B13,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
B14,FSB_A<2>,IOB,IO_L65P_SCP3_0,INPUT,LVCMOS33,0,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
B15,FSB_A<6>,IOB,IO_L29P_A23_M1A13_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
B16,FSB_A<7>,IOB,IO_L29N_A22_M1A14_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
C1,,IOBM,IO_L50P_M3WE_3,UNUSED,,3,,,,,,,,,
|
||||
C2,,IOBS,IO_L48N_M3BA1_3,UNUSED,,3,,,,,,,,,
|
||||
C3,,IOBM,IO_L48P_M3BA0_3,UNUSED,,3,,,,,,,,,
|
||||
C4,RAMCLK1,IOB,IO_L1P_HSWAPEN_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
C5,FSB_D<2>,IOB,IO_L3N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C6,FSB_D<10>,IOB,IO_L7N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C7,FSB_D<7>,IOB,IO_L6P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C8,FSB_D<24>,IOB,IO_L38N_VREF_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C9,FSB_D<13>,IOB,IO_L34P_GCLK19_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C10,FSB_D<20>,IOB,IO_L37N_GCLK12_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C11,FSB_D<23>,IOB,IO_L39P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C12,,,TDI,,,,,,,,,,,,
|
||||
C13,FSB_D<29>,IOB,IO_L63P_SCP7_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
C14,,,TCK,,,,,,,,,,,,
|
||||
C15,FSB_A<14>,IOB,IO_L33P_A15_M1A10_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
C16,FSB_A<20>,IOB,IO_L33N_A14_M1A4_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
D1,,IOBS,IO_L49N_M3A2_3,UNUSED,,3,,,,,,,,,
|
||||
D2,,,VCCO_3,,,3,,,,,any******,,,,
|
||||
D3,,IOBM,IO_L49P_M3A7_3,UNUSED,,3,,,,,,,,,
|
||||
D4,,,GND,,,,,,,,,,,,
|
||||
D5,FSB_D<1>,IOB,IO_L3P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
D6,FSB_D<9>,IOB,IO_L7P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
D7,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
D8,FSB_D<21>,IOB,IO_L38P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
D9,FSB_D<26>,IOB,IO_L40N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
D10,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
D11,FPUCLK,IOB,IO_L66P_SCP1_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE,
|
||||
D12,CPU_nSTERM,IOB,IO_L66N_SCP0_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,NO,NONE,
|
||||
D13,,,GND,,,,,,,,,,,,
|
||||
D14,FSB_A<10>,IOB,IO_L31P_A19_M1CKE_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
D15,,,VCCO_1,,,1,,,,,any******,,,,
|
||||
D16,FSB_A<11>,IOB,IO_L31N_A18_M1A12_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
E1,,IOBS,IO_L46N_M3CLKN_3,UNUSED,,3,,,,,,,,,
|
||||
E2,,IOBM,IO_L46P_M3CLK_3,UNUSED,,3,,,,,,,,,
|
||||
E3,,IOBS,IO_L54N_M3A11_3,UNUSED,,3,,,,,,,,,
|
||||
E4,,IOBM,IO_L54P_M3RESET_3,UNUSED,,3,,,,,,,,,
|
||||
E5,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
E6,FSB_D<8>,IOB,IO_L5N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
E7,FSB_D<17>,IOB,IO_L36P_GCLK15_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
E8,FSB_D<18>,IOB,IO_L36N_GCLK14_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
E9,,,GND,,,,,,,,,,,,
|
||||
E10,FSB_D<19>,IOB,IO_L37P_GCLK13_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
E11,FSB_A<3>,IOB,IO_L64N_SCP4_0,INPUT,LVCMOS33,0,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
E12,FSB_A<5>,IOB,IO_L1N_A24_VREF_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
E13,FSB_A<4>,IOB,IO_L1P_A25_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
E14,,,TDO,,,,,,,,,,,,
|
||||
E15,FSB_A<21>,IOB,IO_L34P_A13_M1WE_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
E16,FSB_A<22>,IOB,IO_L34N_A12_M1BA2_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
F1,,IOBS,IO_L41N_GCLK26_M3DQ5_3,UNUSED,,3,,,,,,,,,
|
||||
F2,,IOBM,IO_L41P_GCLK27_M3DQ4_3,UNUSED,,3,,,,,,,,,
|
||||
F3,,IOBS,IO_L53N_M3A12_3,UNUSED,,3,,,,,,,,,
|
||||
F4,,IOBM,IO_L53P_M3CKE_3,UNUSED,,3,,,,,,,,,
|
||||
F5,,IOBS,IO_L55N_M3A14_3,UNUSED,,3,,,,,,,,,
|
||||
F6,,IOBM,IO_L55P_M3A13_3,UNUSED,,3,,,,,,,,,
|
||||
F7,FSB_D<5>,IOB,IO_L5P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
F8,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
F9,FSB_D<25>,IOB,IO_L40P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
F10,FSB_D<31>,IOB,IO_L64P_SCP5_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE,
|
||||
F11,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
F12,FSB_A<8>,IOB,IO_L30P_A21_M1RESET_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
F13,FSB_A<12>,IOB,IO_L32P_A17_M1A8_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
F14,FSB_A<13>,IOB,IO_L32N_A16_M1A9_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
F15,FSB_A<23>,IOB,IO_L35P_A11_M1A7_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
F16,FSB_A<19>,IOB,IO_L35N_A10_M1A2_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
G1,,IOBS,IO_L40N_M3DQ7_3,UNUSED,,3,,,,,,,,,
|
||||
G2,,,GND,,,,,,,,,,,,
|
||||
G3,,IOBM,IO_L40P_M3DQ6_3,UNUSED,,3,,,,,,,,,
|
||||
G4,,,VCCO_3,,,3,,,,,any******,,,,
|
||||
G5,,IOBS,IO_L51N_M3A4_3,UNUSED,,3,,,,,,,,,
|
||||
G6,,IOBM,IO_L51P_M3A10_3,UNUSED,,3,,,,,,,,,
|
||||
G7,,,VCCINT,,,,,,,,1.2,,,,
|
||||
G8,,,GND,,,,,,,,,,,,
|
||||
G9,,,VCCINT,,,,,,,,1.2,,,,
|
||||
G10,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
G11,FSB_A<9>,IOB,IO_L30N_A20_M1A11_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
G12,FSB_A<24>,IOB,IO_L38P_A5_M1CLK_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
G13,,,VCCO_1,,,1,,,,,any******,,,,
|
||||
G14,FSB_A<15>,IOB,IO_L36P_A9_M1BA0_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
G15,,,GND,,,,,,,,,,,,
|
||||
G16,FSB_A<16>,IOB,IO_L36N_A8_M1BA1_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H1,,IOBS,IO_L39N_M3LDQSN_3,UNUSED,,3,,,,,,,,,
|
||||
H2,,IOBM,IO_L39P_M3LDQS_3,UNUSED,,3,,,,,,,,,
|
||||
H3,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,,
|
||||
H4,CLKFB_IN,IOB,IO_L44P_GCLK21_M3A5_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H5,,IOBS,IO_L43N_GCLK22_IRDY2_M3CASN_3,UNUSED,,3,,,,,,,,,
|
||||
H6,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
H7,,,GND,,,,,,,,,,,,
|
||||
H8,,,VCCINT,,,,,,,,1.2,,,,
|
||||
H9,,,GND,,,,,,,,,,,,
|
||||
H10,,,VCCINT,,,,,,,,1.2,,,,
|
||||
H11,FSB_A<25>,IOB,IO_L38N_A4_M1CLKN_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H12,,,GND,,,,,,,,,,,,
|
||||
H13,FSB_A<26>,IOB,IO_L39P_M1A3_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H14,FSB_A<27>,IOB,IO_L39N_M1ODT_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H15,FSB_A<17>,IOB,IO_L37P_A7_M1A0_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
H16,FSB_A<18>,IOB,IO_L37N_A6_M1A1_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
J1,,IOBS,IO_L38N_M3DQ3_3,UNUSED,,3,,,,,,,,,
|
||||
J2,,,VCCO_3,,,3,,,,,any******,,,,
|
||||
J3,,IOBM,IO_L38P_M3DQ2_3,UNUSED,,3,,,,,,,,,
|
||||
J4,CLKIN,IOB,IO_L42N_GCLK24_M3LDM_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
|
||||
J5,,,GND,,,,,,,,,,,,
|
||||
J6,,IOBM,IO_L43P_GCLK23_M3RASN_3,UNUSED,,3,,,,,,,,,
|
||||
J7,,,VCCINT,,,,,,,,1.2,,,,
|
||||
J8,,,GND,,,,,,,,,,,,
|
||||
J9,,,VCCINT,,,,,,,,1.2,,,,
|
||||
J10,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
J11,,IOBM,IO_L40P_GCLK11_M1A5_1,UNUSED,,1,,,,,,,,,
|
||||
J12,,IOBS,IO_L40N_GCLK10_M1A6_1,UNUSED,,1,,,,,,,,,
|
||||
J13,,IOBM,IO_L41P_GCLK9_IRDY1_M1RASN_1,UNUSED,,1,,,,,,,,,
|
||||
J14,,IOBM,IO_L43P_GCLK5_M1DQ4_1,UNUSED,,1,,,,,,,,,
|
||||
J15,,,VCCO_1,,,1,,,,,any******,,,,
|
||||
J16,,IOBS,IO_L43N_GCLK4_M1DQ5_1,UNUSED,,1,,,,,,,,,
|
||||
K1,,IOBS,IO_L37N_M3DQ1_3,UNUSED,,3,,,,,,,,,
|
||||
K2,,IOBM,IO_L37P_M3DQ0_3,UNUSED,,3,,,,,,,,,
|
||||
K3,,IOBM,IO_L42P_GCLK25_TRDY2_M3UDM_3,UNUSED,,3,,,,,,,,,
|
||||
K4,,,VCCO_3,,,3,,,,,any******,,,,
|
||||
K5,,IOBM,IO_L47P_M3A0_3,UNUSED,,3,,,,,,,,,
|
||||
K6,,IOBS,IO_L47N_M3A1_3,UNUSED,,3,,,,,,,,,
|
||||
K7,,,GND,,,,,,,,,,,,
|
||||
K8,,,VCCINT,,,,,,,,1.2,,,,
|
||||
K9,,,GND,,,,,,,,,,,,
|
||||
K10,,,VCCINT,,,,,,,,1.2,,,,
|
||||
K11,,IOBS,IO_L42N_GCLK6_TRDY1_M1LDM_1,UNUSED,,1,,,,,,,,,
|
||||
K12,,IOBM,IO_L42P_GCLK7_M1UDM_1,UNUSED,,1,,,,,,,,,
|
||||
K13,,,VCCO_1,,,1,,,,,any******,,,,
|
||||
K14,,IOBS,IO_L41N_GCLK8_M1CASN_1,UNUSED,,1,,,,,,,,,
|
||||
K15,,IOBM,IO_L44P_A3_M1DQ6_1,UNUSED,,1,,,,,,,,,
|
||||
K16,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,,
|
||||
L1,,IOBS,IO_L36N_M3DQ9_3,UNUSED,,3,,,,,,,,,
|
||||
L2,,,GND,,,,,,,,,,,,
|
||||
L3,,IOBM,IO_L36P_M3DQ8_3,UNUSED,,3,,,,,,,,,
|
||||
L4,,IOBM,IO_L45P_M3A3_3,UNUSED,,3,,,,,,,,,
|
||||
L5,,IOBS,IO_L45N_M3ODT_3,UNUSED,,3,,,,,,,,,
|
||||
L6,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
L7,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,,
|
||||
L8,,IOBM,IO_L62P_D5_2,UNUSED,,2,,,,,,,,,
|
||||
L9,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
L10,,IOBM,IO_L16P_2,UNUSED,,2,,,,,,,,,
|
||||
L11,,,CMPCS_B_2,,,,,,,,,,,,
|
||||
L12,,IOBM,IO_L53P_1,UNUSED,,1,,,,,,,,,
|
||||
L13,,IOBS,IO_L53N_VREF_1,UNUSED,,1,,,,,,,,,
|
||||
L14,,IOBM,IO_L47P_FWE_B_M1DQ0_1,UNUSED,,1,,,,,,,,,
|
||||
L15,,,GND,,,,,,,,,,,,
|
||||
L16,,IOBS,IO_L47N_LDC_M1DQ1_1,UNUSED,,1,,,,,,,,,
|
||||
M1,,IOBS,IO_L35N_M3DQ11_3,UNUSED,,3,,,,,,,,,
|
||||
M2,,IOBM,IO_L35P_M3DQ10_3,UNUSED,,3,,,,,,,,,
|
||||
M3,,IOBS,IO_L1N_VREF_3,UNUSED,,3,,,,,,,,,
|
||||
M4,,IOBM,IO_L1P_3,UNUSED,,3,,,,,,,,,
|
||||
M5,,IOBM,IO_L2P_3,UNUSED,,3,,,,,,,,,
|
||||
M6,,IOBM,IO_L64P_D8_2,UNUSED,,2,,,,,,,,,
|
||||
M7,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,,
|
||||
M8,,,GND,,,,,,,,,,,,
|
||||
M9,,IOBM,IO_L29P_GCLK3_2,UNUSED,,2,,,,,,,,,
|
||||
M10,,IOBS,IO_L16N_VREF_2,UNUSED,,2,,,,,,,,,
|
||||
M11,,IOBS,IO_L2N_CMPMOSI_2,UNUSED,,2,,,,,,,,,
|
||||
M12,,IOBM,IO_L2P_CMPCLK_2,UNUSED,,2,,,,,,,,,
|
||||
M13,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,,
|
||||
M14,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,,
|
||||
M15,,IOBM,IO_L46P_FCS_B_M1DQ2_1,UNUSED,,1,,,,,,,,,
|
||||
M16,,IOBS,IO_L46N_FOE_B_M1DQ3_1,UNUSED,,1,,,,,,,,,
|
||||
N1,,IOBS,IO_L34N_M3UDQSN_3,UNUSED,,3,,,,,,,,,
|
||||
N2,,,VCCO_3,,,3,,,,,any******,,,,
|
||||
N3,,IOBM,IO_L34P_M3UDQS_3,UNUSED,,3,,,,,,,,,
|
||||
N4,,IOBS,IO_L2N_3,UNUSED,,3,,,,,,,,,
|
||||
N5,,IOBM,IO_L49P_D3_2,UNUSED,,2,,,,,,,,,
|
||||
N6,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,,
|
||||
N7,,,VCCO_2,,,2,,,,,any******,,,,
|
||||
N8,,IOBS,IO_L29N_GCLK2_2,UNUSED,,2,,,,,,,,,
|
||||
N9,,IOBM,IO_L14P_D11_2,UNUSED,,2,,,,,,,,,
|
||||
N10,,,VCCO_2,,,2,,,,,any******,,,,
|
||||
N11,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,,,,
|
||||
N12,,IOBM,IO_L12P_D1_MISO2_2,UNUSED,,2,,,,,,,,,
|
||||
N13,,,GND,,,,,,,,,,,,
|
||||
N14,,IOBM,IO_L45P_A1_M1LDQS_1,UNUSED,,1,,,,,,,,,
|
||||
N15,,,VCCO_1,,,1,,,,,any******,,,,
|
||||
N16,,IOBS,IO_L45N_A0_M1LDQSN_1,UNUSED,,1,,,,,,,,,
|
||||
P1,,IOBS,IO_L33N_M3DQ13_3,UNUSED,,3,,,,,,,,,
|
||||
P2,,IOBM,IO_L33P_M3DQ12_3,UNUSED,,3,,,,,,,,,
|
||||
P3,,,GND,,,,,,,,,,,,
|
||||
P4,,IOBM,IO_L63P_2,UNUSED,,2,,,,,,,,,
|
||||
P5,,IOBS,IO_L49N_D4_2,UNUSED,,2,,,,,,,,,
|
||||
P6,,IOBM,IO_L47P_2,UNUSED,,2,,,,,,,,,
|
||||
P7,,IOBM,IO_L31P_GCLK31_D14_2,UNUSED,,2,,,,,,,,,
|
||||
P8,,IOBM,IO_L30P_GCLK1_D13_2,UNUSED,,2,,,,,,,,,
|
||||
P9,,IOBS,IO_L14N_D12_2,UNUSED,,2,,,,,,,,,
|
||||
P10,,IOBM,IO_L3P_D0_DIN_MISO_MISO1_2,UNUSED,,2,,,,,,,,,
|
||||
P11,,IOBS,IO_L13N_D10_2,UNUSED,,2,,,,,,,,,
|
||||
P12,,IOBS,IO_L12N_D2_MISO3_2,UNUSED,,2,,,,,,,,,
|
||||
P13,,,DONE_2,,,,,,,,,,,,
|
||||
P14,,,SUSPEND,,,,,,,,,,,,
|
||||
P15,,IOBM,IO_L48P_HDC_M1DQ8_1,UNUSED,,1,,,,,,,,,
|
||||
P16,,IOBS,IO_L48N_M1DQ9_1,UNUSED,,1,,,,,,,,,
|
||||
R1,,IOBS,IO_L32N_M3DQ15_3,UNUSED,,3,,,,,,,,,
|
||||
R2,,IOBM,IO_L32P_M3DQ14_3,UNUSED,,3,,,,,,,,,
|
||||
R3,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,,
|
||||
R4,,,VCCO_2,,,2,,,,,any******,,,,
|
||||
R5,,IOBM,IO_L48P_D7_2,UNUSED,,2,,,,,,,,,
|
||||
R6,,,GND,,,,,,,,,,,,
|
||||
R7,,IOBM,IO_L32P_GCLK29_2,UNUSED,,2,,,,,,,,,
|
||||
R8,,,VCCO_2,,,2,,,,,any******,,,,
|
||||
R9,,IOBM,IO_L23P_2,UNUSED,,2,,,,,,,,,
|
||||
R10,,,GND,,,,,,,,,,,,
|
||||
R11,,IOBM,IO_L1P_CCLK_2,UNUSED,,2,,,,,,,,,
|
||||
R12,,IOBM,IO_L52P_M1DQ14_1,UNUSED,,1,,,,,,,,,
|
||||
R13,,,VCCO_1,,,1,,,,,any******,,,,
|
||||
R14,,IOBM,IO_L50P_M1UDQS_1,UNUSED,,1,,,,,,,,,
|
||||
R15,,IOBM,IO_L49P_M1DQ10_1,UNUSED,,1,,,,,,,,,
|
||||
R16,,IOBS,IO_L49N_M1DQ11_1,UNUSED,,1,,,,,,,,,
|
||||
T1,,,GND,,,,,,,,,,,,
|
||||
T2,,,PROGRAM_B_2,,,,,,,,,,,,
|
||||
T3,,IOBS,IO_L65N_CSO_B_2,UNUSED,,2,,,,,,,,,
|
||||
T4,,IOBS,IO_L63N_2,UNUSED,,2,,,,,,,,,
|
||||
T5,,IOBS,IO_L48N_RDWR_B_VREF_2,UNUSED,,2,,,,,,,,,
|
||||
T6,,IOBS,IO_L47N_2,UNUSED,,2,,,,,,,,,
|
||||
T7,,IOBS,IO_L32N_GCLK28_2,UNUSED,,2,,,,,,,,,
|
||||
T8,,IOBS,IO_L30N_GCLK0_USERCCLK_2,UNUSED,,2,,,,,,,,,
|
||||
T9,,IOBS,IO_L23N_2,UNUSED,,2,,,,,,,,,
|
||||
T10,,IOBS,IO_L3N_MOSI_CSI_B_MISO0_2,UNUSED,,2,,,,,,,,,
|
||||
T11,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,,,,
|
||||
T12,,IOBS,IO_L52N_M1DQ15_1,UNUSED,,1,,,,,,,,,
|
||||
T13,,IOBS,IO_L51N_M1DQ13_1,UNUSED,,1,,,,,,,,,
|
||||
T14,,IOBM,IO_L51P_M1DQ12_1,UNUSED,,1,,,,,,,,,
|
||||
T15,,IOBS,IO_L50N_M1UDQSN_1,UNUSED,,1,,,,,,,,,
|
||||
T16,,,GND,,,,,,,,,,,,
|
||||
|
||||
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
|
||||
#
|
||||
#* Default value.
|
||||
#** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
#****** Special VCCO requirements may apply. Please consult the device
|
||||
# family datasheet for specific guideline on VCCO requirements.
|
||||
#
|
||||
#
|
||||
#
|
||||
|
@ -1,7 +1,7 @@
|
||||
Release 14.7 - par P.20131013 (nt)
|
||||
Release 14.7 - par P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Fri Oct 29 17:59:53 2021
|
||||
Sun Oct 31 15:38:33 2021
|
||||
|
||||
|
||||
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
|
||||
@ -23,137 +23,137 @@ Pinout by Pin Number:
|
||||
|A1 | | |GND | | | | | | | | | | | |
|
||||
|A2 | |IOBS |IO_L52N_M3A9_3 |UNUSED | |3 | | | | | | | | |
|
||||
|A3 | |IOBS |IO_L83N_VREF_3 |UNUSED | |3 | | | | | | | | |
|
||||
|A4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A5 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A6 | |IOBS |IO_L4N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A7 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A8 | |IOBS |IO_L33N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A9 | |IOBS |IO_L34N_GCLK18_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A10 | |IOBS |IO_L35N_GCLK16_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A11 | |IOBS |IO_L39N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A12 | |IOBS |IO_L62N_VREF_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A13 | |IOBS |IO_L63N_SCP6_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A14 | |IOBS |IO_L65N_SCP2_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A4 |CLKFB_OUT |IOB |IO_L1N_VREF_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|A5 |FSB_D<0> |IOB |IO_L2N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A6 |FSB_D<4> |IOB |IO_L4N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A7 |FSB_D<6> |IOB |IO_L6N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A8 |FSB_D<12> |IOB |IO_L33N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A9 |FSB_D<14> |IOB |IO_L34N_GCLK18_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A10 |FSB_D<16> |IOB |IO_L35N_GCLK16_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A11 |FSB_D<22> |IOB |IO_L39N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A12 |FSB_D<28> |IOB |IO_L62N_VREF_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A13 |FSB_D<30> |IOB |IO_L63N_SCP6_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|A14 |RAMCLK0 |IOB |IO_L65N_SCP2_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|A15 | | |TMS | | | | | | | | | | | |
|
||||
|A16 | | |GND | | | | | | | | | | | |
|
||||
|B1 |CPUCLK |IOB |IO_L50N_M3BA2_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|B1 | |IOBS |IO_L50N_M3BA2_3 |UNUSED | |3 | | | | | | | | |
|
||||
|B2 | |IOBM |IO_L52P_M3A8_3 |UNUSED | |3 | | | | | | | | |
|
||||
|B3 | |IOBM |IO_L83P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|B4 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|B5 | |IOBM |IO_L2P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B6 | |IOBM |IO_L4P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B4 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|B5 |CPUCLK |IOB |IO_L2P_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|B6 |FSB_D<3> |IOB |IO_L4P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|B7 | | |GND | | | | | | | | | | | |
|
||||
|B8 | |IOBM |IO_L33P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B9 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|B10 | |IOBM |IO_L35P_GCLK17_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B8 |FSB_D<11> |IOB |IO_L33P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|B9 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|B10 |FSB_D<15> |IOB |IO_L35P_GCLK17_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|B11 | | |GND | | | | | | | | | | | |
|
||||
|B12 | |IOBM |IO_L62P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B13 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|B14 | |IOBM |IO_L65P_SCP3_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B15 | |IOBM |IO_L29P_A23_M1A13_1 |UNUSED | |1 | | | | | | | | |
|
||||
|B16 | |IOBS |IO_L29N_A22_M1A14_1 |UNUSED | |1 | | | | | | | | |
|
||||
|C1 |FPUCLK |IOB |IO_L50P_M3WE_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|C2 |INt |IOB |IO_L48N_M3BA1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|C3 |OUTt |IOB |IO_L48P_M3BA0_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |NO |NONE |
|
||||
|C4 | |IOBM |IO_L1P_HSWAPEN_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C5 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C6 | |IOBS |IO_L7N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C7 | |IOBM |IO_L6P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C8 | |IOBS |IO_L38N_VREF_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C9 | |IOBM |IO_L34P_GCLK19_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C10 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C11 | |IOBM |IO_L39P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B12 |FSB_D<27> |IOB |IO_L62P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|B13 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|B14 |FSB_A<2> |IOB |IO_L65P_SCP3_0 |INPUT |LVCMOS33 |0 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|B15 |FSB_A<6> |IOB |IO_L29P_A23_M1A13_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|B16 |FSB_A<7> |IOB |IO_L29N_A22_M1A14_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|C1 | |IOBM |IO_L50P_M3WE_3 |UNUSED | |3 | | | | | | | | |
|
||||
|C2 | |IOBS |IO_L48N_M3BA1_3 |UNUSED | |3 | | | | | | | | |
|
||||
|C3 | |IOBM |IO_L48P_M3BA0_3 |UNUSED | |3 | | | | | | | | |
|
||||
|C4 |RAMCLK1 |IOB |IO_L1P_HSWAPEN_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|C5 |FSB_D<2> |IOB |IO_L3N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C6 |FSB_D<10> |IOB |IO_L7N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C7 |FSB_D<7> |IOB |IO_L6P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C8 |FSB_D<24> |IOB |IO_L38N_VREF_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C9 |FSB_D<13> |IOB |IO_L34P_GCLK19_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C10 |FSB_D<20> |IOB |IO_L37N_GCLK12_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C11 |FSB_D<23> |IOB |IO_L39P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C12 | | |TDI | | | | | | | | | | | |
|
||||
|C13 | |IOBM |IO_L63P_SCP7_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C13 |FSB_D<29> |IOB |IO_L63P_SCP7_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|C14 | | |TCK | | | | | | | | | | | |
|
||||
|C15 | |IOBM |IO_L33P_A15_M1A10_1 |UNUSED | |1 | | | | | | | | |
|
||||
|C16 | |IOBS |IO_L33N_A14_M1A4_1 |UNUSED | |1 | | | | | | | | |
|
||||
|D1 |RAMCLK0 |IOB |IO_L49N_M3A2_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|D2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|D3 |RAMCLK1 |IOB |IO_L49P_M3A7_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|C15 |FSB_A<14> |IOB |IO_L33P_A15_M1A10_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|C16 |FSB_A<20> |IOB |IO_L33N_A14_M1A4_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|D1 | |IOBS |IO_L49N_M3A2_3 |UNUSED | |3 | | | | | | | | |
|
||||
|D2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|
||||
|D3 | |IOBM |IO_L49P_M3A7_3 |UNUSED | |3 | | | | | | | | |
|
||||
|D4 | | |GND | | | | | | | | | | | |
|
||||
|D5 | |IOBM |IO_L3P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D6 | |IOBM |IO_L7P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D7 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|D8 | |IOBM |IO_L38P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D9 | |IOBS |IO_L40N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D10 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|D11 | |IOBM |IO_L66P_SCP1_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D12 | |IOBS |IO_L66N_SCP0_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D5 |FSB_D<1> |IOB |IO_L3P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|D6 |FSB_D<9> |IOB |IO_L7P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|D7 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|D8 |FSB_D<21> |IOB |IO_L38P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|D9 |FSB_D<26> |IOB |IO_L40N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|D10 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|D11 |FPUCLK |IOB |IO_L66P_SCP1_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|D12 |CPU_nSTERM |IOB |IO_L66N_SCP0_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |NO |NONE |
|
||||
|D13 | | |GND | | | | | | | | | | | |
|
||||
|D14 | |IOBM |IO_L31P_A19_M1CKE_1 |UNUSED | |1 | | | | | | | | |
|
||||
|D14 |FSB_A<10> |IOB |IO_L31P_A19_M1CKE_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|D15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|D16 | |IOBS |IO_L31N_A18_M1A12_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E1 |FSB_A<27> |IOB |IO_L46N_M3CLKN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E2 |FSB_A<24> |IOB |IO_L46P_M3CLK_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|D16 |FSB_A<11> |IOB |IO_L31N_A18_M1A12_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E1 | |IOBS |IO_L46N_M3CLKN_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E2 | |IOBM |IO_L46P_M3CLK_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E3 | |IOBS |IO_L54N_M3A11_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E4 | |IOBM |IO_L54P_M3RESET_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E5 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|E6 | |IOBS |IO_L5N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E7 | |IOBM |IO_L36P_GCLK15_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E8 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E6 |FSB_D<8> |IOB |IO_L5N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|E7 |FSB_D<17> |IOB |IO_L36P_GCLK15_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|E8 |FSB_D<18> |IOB |IO_L36N_GCLK14_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|E9 | | |GND | | | | | | | | | | | |
|
||||
|E10 | |IOBM |IO_L37P_GCLK13_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E11 | |IOBS |IO_L64N_SCP4_0 |UNUSED | |0 | | | | | | | | |
|
||||
|E12 | |IOBS |IO_L1N_A24_VREF_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E13 | |IOBM |IO_L1P_A25_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E10 |FSB_D<19> |IOB |IO_L37P_GCLK13_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|E11 |FSB_A<3> |IOB |IO_L64N_SCP4_0 |INPUT |LVCMOS33 |0 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E12 |FSB_A<5> |IOB |IO_L1N_A24_VREF_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E13 |FSB_A<4> |IOB |IO_L1P_A25_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E14 | | |TDO | | | | | | | | | | | |
|
||||
|E15 | |IOBM |IO_L34P_A13_M1WE_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E16 | |IOBS |IO_L34N_A12_M1BA2_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F1 |FSB_A<23> |IOB |IO_L41N_GCLK26_M3DQ5_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F2 |FSB_A<22> |IOB |IO_L41P_GCLK27_M3DQ4_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E15 |FSB_A<21> |IOB |IO_L34P_A13_M1WE_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E16 |FSB_A<22> |IOB |IO_L34N_A12_M1BA2_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F1 | |IOBS |IO_L41N_GCLK26_M3DQ5_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F2 | |IOBM |IO_L41P_GCLK27_M3DQ4_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F3 | |IOBS |IO_L53N_M3A12_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F4 | |IOBM |IO_L53P_M3CKE_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F5 | |IOBS |IO_L55N_M3A14_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F6 | |IOBM |IO_L55P_M3A13_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F7 | |IOBM |IO_L5P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|F7 |FSB_D<5> |IOB |IO_L5P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|F8 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|F9 | |IOBM |IO_L40P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|F10 | |IOBM |IO_L64P_SCP5_0 |UNUSED | |0 | | | | | | | | |
|
||||
|F9 |FSB_D<25> |IOB |IO_L40P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|F10 |FSB_D<31> |IOB |IO_L64P_SCP5_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE |
|
||||
|F11 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|F12 | |IOBM |IO_L30P_A21_M1RESET_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F13 | |IOBM |IO_L32P_A17_M1A8_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F14 | |IOBS |IO_L32N_A16_M1A9_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F15 | |IOBM |IO_L35P_A11_M1A7_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F16 | |IOBS |IO_L35N_A10_M1A2_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G1 |FSB_A<29> |IOB |IO_L40N_M3DQ7_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F12 |FSB_A<8> |IOB |IO_L30P_A21_M1RESET_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F13 |FSB_A<12> |IOB |IO_L32P_A17_M1A8_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F14 |FSB_A<13> |IOB |IO_L32N_A16_M1A9_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F15 |FSB_A<23> |IOB |IO_L35P_A11_M1A7_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F16 |FSB_A<19> |IOB |IO_L35N_A10_M1A2_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G1 | |IOBS |IO_L40N_M3DQ7_3 |UNUSED | |3 | | | | | | | | |
|
||||
|G2 | | |GND | | | | | | | | | | | |
|
||||
|G3 |FSB_A<19> |IOB |IO_L40P_M3DQ6_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G4 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|G3 | |IOBM |IO_L40P_M3DQ6_3 |UNUSED | |3 | | | | | | | | |
|
||||
|G4 | | |VCCO_3 | | |3 | | | | |any******| | | |
|
||||
|G5 | |IOBS |IO_L51N_M3A4_3 |UNUSED | |3 | | | | | | | | |
|
||||
|G6 |CLKFB_OUT |IOB |IO_L51P_M3A10_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|G6 | |IOBM |IO_L51P_M3A10_3 |UNUSED | |3 | | | | | | | | |
|
||||
|G7 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|G8 | | |GND | | | | | | | | | | | |
|
||||
|G9 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|G10 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|G11 | |IOBS |IO_L30N_A20_M1A11_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G12 | |IOBM |IO_L38P_A5_M1CLK_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G11 |FSB_A<9> |IOB |IO_L30N_A20_M1A11_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G12 |FSB_A<24> |IOB |IO_L38P_A5_M1CLK_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G13 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|G14 | |IOBM |IO_L36P_A9_M1BA0_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G14 |FSB_A<15> |IOB |IO_L36P_A9_M1BA0_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G15 | | |GND | | | | | | | | | | | |
|
||||
|G16 | |IOBS |IO_L36N_A8_M1BA1_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H1 |FSB_A<26> |IOB |IO_L39N_M3LDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H2 |FSB_A<25> |IOB |IO_L39P_M3LDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H3 |CPU_nAS |IOB |IO_L44N_GCLK20_M3A6_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G16 |FSB_A<16> |IOB |IO_L36N_A8_M1BA1_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H1 | |IOBS |IO_L39N_M3LDQSN_3 |UNUSED | |3 | | | | | | | | |
|
||||
|H2 | |IOBM |IO_L39P_M3LDQS_3 |UNUSED | |3 | | | | | | | | |
|
||||
|H3 | |IOBS |IO_L44N_GCLK20_M3A6_3 |UNUSED | |3 | | | | | | | | |
|
||||
|H4 |CLKFB_IN |IOB |IO_L44P_GCLK21_M3A5_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H5 |FSB_A<30> |IOB |IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H5 | |IOBS |IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED | |3 | | | | | | | | |
|
||||
|H6 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|H7 | | |GND | | | | | | | | | | | |
|
||||
|H8 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|H9 | | |GND | | | | | | | | | | | |
|
||||
|H10 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|H11 | |IOBS |IO_L38N_A4_M1CLKN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H11 |FSB_A<25> |IOB |IO_L38N_A4_M1CLKN_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H12 | | |GND | | | | | | | | | | | |
|
||||
|H13 | |IOBM |IO_L39P_M1A3_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H14 | |IOBS |IO_L39N_M1ODT_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H15 | |IOBM |IO_L37P_A7_M1A0_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H16 | |IOBS |IO_L37N_A6_M1A1_1 |UNUSED | |1 | | | | | | | | |
|
||||
|J1 |FSB_A<17> |IOB |IO_L38N_M3DQ3_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|J3 |FSB_A<16> |IOB |IO_L38P_M3DQ2_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H13 |FSB_A<26> |IOB |IO_L39P_M1A3_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H14 |FSB_A<27> |IOB |IO_L39N_M1ODT_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H15 |FSB_A<17> |IOB |IO_L37P_A7_M1A0_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H16 |FSB_A<18> |IOB |IO_L37N_A6_M1A1_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J1 | |IOBS |IO_L38N_M3DQ3_3 |UNUSED | |3 | | | | | | | | |
|
||||
|J2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|
||||
|J3 | |IOBM |IO_L38P_M3DQ2_3 |UNUSED | |3 | | | | | | | | |
|
||||
|J4 |CLKIN |IOB |IO_L42N_GCLK24_M3LDM_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J5 | | |GND | | | | | | | | | | | |
|
||||
|J6 |FSB_A<21> |IOB |IO_L43P_GCLK23_M3RASN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J6 | |IOBM |IO_L43P_GCLK23_M3RASN_3 |UNUSED | |3 | | | | | | | | |
|
||||
|J7 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|J8 | | |GND | | | | | | | | | | | |
|
||||
|J9 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
@ -164,12 +164,12 @@ Pinout by Pin Number:
|
||||
|J14 | |IOBM |IO_L43P_GCLK5_M1DQ4_1 |UNUSED | |1 | | | | | | | | |
|
||||
|J15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|J16 | |IOBS |IO_L43N_GCLK4_M1DQ5_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K1 |FSB_A<5> |IOB |IO_L37N_M3DQ1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K2 |FSB_A<14> |IOB |IO_L37P_M3DQ0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K3 |FSB_A<28> |IOB |IO_L42P_GCLK25_TRDY2_M3UDM_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K4 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|K5 |CPUCLKi |IOB |IO_L47P_M3A0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K6 |FSB_A<18> |IOB |IO_L47N_M3A1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K1 | |IOBS |IO_L37N_M3DQ1_3 |UNUSED | |3 | | | | | | | | |
|
||||
|K2 | |IOBM |IO_L37P_M3DQ0_3 |UNUSED | |3 | | | | | | | | |
|
||||
|K3 | |IOBM |IO_L42P_GCLK25_TRDY2_M3UDM_3 |UNUSED | |3 | | | | | | | | |
|
||||
|K4 | | |VCCO_3 | | |3 | | | | |any******| | | |
|
||||
|K5 | |IOBM |IO_L47P_M3A0_3 |UNUSED | |3 | | | | | | | | |
|
||||
|K6 | |IOBS |IO_L47N_M3A1_3 |UNUSED | |3 | | | | | | | | |
|
||||
|K7 | | |GND | | | | | | | | | | | |
|
||||
|K8 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|K9 | | |GND | | | | | | | | | | | |
|
||||
@ -180,11 +180,11 @@ Pinout by Pin Number:
|
||||
|K14 | |IOBS |IO_L41N_GCLK8_M1CASN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K15 | |IOBM |IO_L44P_A3_M1DQ6_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K16 | |IOBS |IO_L44N_A2_M1DQ7_1 |UNUSED | |1 | | | | | | | | |
|
||||
|L1 |FSB_A<11> |IOB |IO_L36N_M3DQ9_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L1 | |IOBS |IO_L36N_M3DQ9_3 |UNUSED | |3 | | | | | | | | |
|
||||
|L2 | | |GND | | | | | | | | | | | |
|
||||
|L3 |FSB_A<4> |IOB |IO_L36P_M3DQ8_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L4 |FSB_A<31> |IOB |IO_L45P_M3A3_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L5 |FSB_A<20> |IOB |IO_L45N_M3ODT_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L3 | |IOBM |IO_L36P_M3DQ8_3 |UNUSED | |3 | | | | | | | | |
|
||||
|L4 | |IOBM |IO_L45P_M3A3_3 |UNUSED | |3 | | | | | | | | |
|
||||
|L5 | |IOBS |IO_L45N_M3ODT_3 |UNUSED | |3 | | | | | | | | |
|
||||
|L6 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|L7 | |IOBS |IO_L62N_D6_2 |UNUSED | |2 | | | | | | | | |
|
||||
|L8 | |IOBM |IO_L62P_D5_2 |UNUSED | |2 | | | | | | | | |
|
||||
@ -196,11 +196,11 @@ Pinout by Pin Number:
|
||||
|L14 | |IOBM |IO_L47P_FWE_B_M1DQ0_1 |UNUSED | |1 | | | | | | | | |
|
||||
|L15 | | |GND | | | | | | | | | | | |
|
||||
|L16 | |IOBS |IO_L47N_LDC_M1DQ1_1 |UNUSED | |1 | | | | | | | | |
|
||||
|M1 |FSB_A<1> |IOB |IO_L35N_M3DQ11_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M2 |FSB_A<2> |IOB |IO_L35P_M3DQ10_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M3 |FSB_A<6> |IOB |IO_L1N_VREF_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M4 |FSB_A<8> |IOB |IO_L1P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M5 |FSB_A<15> |IOB |IO_L2P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M1 | |IOBS |IO_L35N_M3DQ11_3 |UNUSED | |3 | | | | | | | | |
|
||||
|M2 | |IOBM |IO_L35P_M3DQ10_3 |UNUSED | |3 | | | | | | | | |
|
||||
|M3 | |IOBS |IO_L1N_VREF_3 |UNUSED | |3 | | | | | | | | |
|
||||
|M4 | |IOBM |IO_L1P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|M5 | |IOBM |IO_L2P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|M6 | |IOBM |IO_L64P_D8_2 |UNUSED | |2 | | | | | | | | |
|
||||
|M7 | |IOBS |IO_L31N_GCLK30_D15_2 |UNUSED | |2 | | | | | | | | |
|
||||
|M8 | | |GND | | | | | | | | | | | |
|
||||
@ -212,10 +212,10 @@ Pinout by Pin Number:
|
||||
|M14 | |IOBS |IO_L74N_DOUT_BUSY_1 |UNUSED | |1 | | | | | | | | |
|
||||
|M15 | |IOBM |IO_L46P_FCS_B_M1DQ2_1 |UNUSED | |1 | | | | | | | | |
|
||||
|M16 | |IOBS |IO_L46N_FOE_B_M1DQ3_1 |UNUSED | |1 | | | | | | | | |
|
||||
|N1 |FSB_A<10> |IOB |IO_L34N_M3UDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|N3 |FSB_A<13> |IOB |IO_L34P_M3UDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N4 |FSB_A<0> |IOB |IO_L2N_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N1 | |IOBS |IO_L34N_M3UDQSN_3 |UNUSED | |3 | | | | | | | | |
|
||||
|N2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|
||||
|N3 | |IOBM |IO_L34P_M3UDQS_3 |UNUSED | |3 | | | | | | | | |
|
||||
|N4 | |IOBS |IO_L2N_3 |UNUSED | |3 | | | | | | | | |
|
||||
|N5 | |IOBM |IO_L49P_D3_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N6 | |IOBS |IO_L64N_D9_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N7 | | |VCCO_2 | | |2 | | | | |any******| | | |
|
||||
@ -228,8 +228,8 @@ Pinout by Pin Number:
|
||||
|N14 | |IOBM |IO_L45P_A1_M1LDQS_1 |UNUSED | |1 | | | | | | | | |
|
||||
|N15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|N16 | |IOBS |IO_L45N_A0_M1LDQSN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P1 |FSB_A<7> |IOB |IO_L33N_M3DQ13_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|P2 |FSB_A<12> |IOB |IO_L33P_M3DQ12_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|P1 | |IOBS |IO_L33N_M3DQ13_3 |UNUSED | |3 | | | | | | | | |
|
||||
|P2 | |IOBM |IO_L33P_M3DQ12_3 |UNUSED | |3 | | | | | | | | |
|
||||
|P3 | | |GND | | | | | | | | | | | |
|
||||
|P4 | |IOBM |IO_L63P_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P5 | |IOBS |IO_L49N_D4_2 |UNUSED | |2 | | | | | | | | |
|
||||
@ -244,8 +244,8 @@ Pinout by Pin Number:
|
||||
|P14 | | |SUSPEND | | | | | | | | | | | |
|
||||
|P15 | |IOBM |IO_L48P_HDC_M1DQ8_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P16 | |IOBS |IO_L48N_M1DQ9_1 |UNUSED | |1 | | | | | | | | |
|
||||
|R1 |FSB_A<9> |IOB |IO_L32N_M3DQ15_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|R2 |FSB_A<3> |IOB |IO_L32P_M3DQ14_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|R1 | |IOBS |IO_L32N_M3DQ15_3 |UNUSED | |3 | | | | | | | | |
|
||||
|R2 | |IOBM |IO_L32P_M3DQ14_3 |UNUSED | |3 | | | | | | | | |
|
||||
|R3 | |IOBM |IO_L65P_INIT_B_2 |UNUSED | |2 | | | | | | | | |
|
||||
|R4 | | |VCCO_2 | | |2 | | | | |any******| | | |
|
||||
|R5 | |IOBM |IO_L48P_D7_2 |UNUSED | |2 | | | | | | | | |
|
||||
|
||||
1299
fpga/WarpLC_par.xrpt
1299
fpga/WarpLC_par.xrpt
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@ -2,7 +2,7 @@
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>WarpLC Project Status (10/29/2021 - 17:39:15)</B></TD></TR>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>ClkGen Project Status (10/31/2021 - 15:38:40)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>WarpLC.xise</TD>
|
||||
@ -19,13 +19,12 @@
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
|
||||
<TD>xc6slx9-2ftg256</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
|
||||
<TD>
|
||||
No Errors</TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/*.xmsgs?&DataKey=Warning'>7 Warnings (0 new)</A></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
@ -60,13 +59,13 @@ System Settings</A>
|
||||
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
|
||||
<TD ALIGN=RIGHT>34</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>11,440</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD>
|
||||
<TD ALIGN=RIGHT>34</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
@ -90,31 +89,31 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
|
||||
<TD ALIGN=RIGHT>17</TD>
|
||||
<TD ALIGN=RIGHT>33</TD>
|
||||
<TD ALIGN=RIGHT>5,720</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
|
||||
<TD ALIGN=RIGHT>13</TD>
|
||||
<TD ALIGN=RIGHT>9</TD>
|
||||
<TD ALIGN=RIGHT>5,720</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
|
||||
<TD ALIGN=RIGHT>11</TD>
|
||||
<TD ALIGN=RIGHT>8</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
@ -126,87 +125,99 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>24</TD>
|
||||
<TD ALIGN=RIGHT>1,440</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Dual Port RAM</TD>
|
||||
<TD ALIGN=RIGHT>24</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
|
||||
<TD ALIGN=RIGHT>20</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Single Port RAM</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Shift Register</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
|
||||
<TD ALIGN=RIGHT>11</TD>
|
||||
<TD ALIGN=RIGHT>9</TD>
|
||||
<TD ALIGN=RIGHT>1,430</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
|
||||
<TD ALIGN=RIGHT>12</TD>
|
||||
<TD ALIGN=RIGHT>8</TD>
|
||||
<TD ALIGN=RIGHT>2,860</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
|
||||
<TD ALIGN=RIGHT>41</TD>
|
||||
<TD ALIGN=RIGHT>33</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD>
|
||||
<TD ALIGN=RIGHT>11</TD>
|
||||
<TD ALIGN=RIGHT>41</TD>
|
||||
<TD ALIGN=RIGHT>26%</TD>
|
||||
<TD ALIGN=RIGHT>32</TD>
|
||||
<TD ALIGN=RIGHT>33</TD>
|
||||
<TD ALIGN=RIGHT>96%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD>
|
||||
<TD ALIGN=RIGHT>24</TD>
|
||||
<TD ALIGN=RIGHT>41</TD>
|
||||
<TD ALIGN=RIGHT>58%</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>33</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD>
|
||||
<TD ALIGN=RIGHT>6</TD>
|
||||
<TD ALIGN=RIGHT>41</TD>
|
||||
<TD ALIGN=RIGHT>14%</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>33</TD>
|
||||
<TD ALIGN=RIGHT>3%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD>
|
||||
<TD ALIGN=RIGHT>6</TD>
|
||||
<TD ALIGN=RIGHT>11</TD>
|
||||
<TD ALIGN=RIGHT>11,440</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
|
||||
<TD ALIGN=RIGHT>43</TD>
|
||||
<TD ALIGN=RIGHT>66</TD>
|
||||
<TD ALIGN=RIGHT>186</TD>
|
||||
<TD ALIGN=RIGHT>23%</TD>
|
||||
<TD ALIGN=RIGHT>35%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Flip Flops</TD>
|
||||
@ -222,9 +233,9 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>64</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
|
||||
@ -390,7 +401,7 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
|
||||
<TD ALIGN=RIGHT>1.41</TD>
|
||||
<TD ALIGN=RIGHT>1.67</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
@ -427,20 +438,21 @@ System Settings</A>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Oct 30 17:25:53 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>7 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Oct 30 17:25:53 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sat Oct 30 17:25:53 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/map.xmsgs?&DataKey=Info'>6 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sat Oct 30 17:25:53 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sun Oct 31 15:37:53 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>17 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sun Oct 31 15:37:59 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>9 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sun Oct 31 15:38:27 2021</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sun Oct 31 15:38:33 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/par.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sat Oct 30 17:25:53 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sun Oct 31 15:38:38 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat Oct 30 17:25:53 2021</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Oct 31 14:40:54 2021</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Dog/Documents/GitHub/Warp-LC/fpga\WarpLC_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Oct 31 15:38:26 2021</TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 10/30/2021 - 17:26:36</center>
|
||||
<br><center><b>Date Generated:</b> 10/31/2021 - 15:38:40</center>
|
||||
</BODY></HTML>
|
||||
10
fpga/WarpLC_summary.xml
Normal file
10
fpga/WarpLC_summary.xml
Normal file
@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<DesignSummary rev="33">
|
||||
<CmdHistory>
|
||||
</CmdHistory>
|
||||
</DesignSummary>
|
||||
73
fpga/WarpLC_usage.xml
Normal file
73
fpga/WarpLC_usage.xml
Normal file
@ -0,0 +1,73 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<DeviceUsageSummary rev="33">
|
||||
<DesignStatistics TimeStamp="Sun Oct 31 15:38:26 2021"><group name="MiscellaneousStatistics">
|
||||
<item name="AGG_BONDED_IO" rev="33">
|
||||
<attrib name="value" value="66"/></item>
|
||||
<item name="AGG_IO" rev="33">
|
||||
<attrib name="value" value="66"/></item>
|
||||
<item name="AGG_SLICE" rev="33">
|
||||
<attrib name="value" value="9"/></item>
|
||||
<item name="NUM_BONDED_IOB" rev="33">
|
||||
<attrib name="value" value="66"/></item>
|
||||
<item name="NUM_BSFULL" rev="33">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_BSLUTONLY" rev="33">
|
||||
<attrib name="value" value="32"/></item>
|
||||
<item name="NUM_BSUSED" rev="33">
|
||||
<attrib name="value" value="33"/></item>
|
||||
<item name="NUM_BUFG" rev="33">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NUM_BUFIO2" rev="33">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_BUFIO2FB" rev="33">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_DPRAM_O5ANDO6" rev="33">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="NUM_DPRAM_O6ONLY" rev="33">
|
||||
<attrib name="value" value="4"/></item>
|
||||
<item name="NUM_IOB_FF" rev="33">
|
||||
<attrib name="value" value="5"/></item>
|
||||
<item name="NUM_LOGIC_O5ONLY" rev="33">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_LOGIC_O6ONLY" rev="33">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="NUM_LUT_RT_O6" rev="33">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_OLOGIC2" rev="33">
|
||||
<attrib name="value" value="5"/></item>
|
||||
<item name="NUM_PLL_ADV" rev="33">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_RAMB8BWER" rev="33">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_SLICEL" rev="33">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NUM_SLICEM" rev="33">
|
||||
<attrib name="value" value="6"/></item>
|
||||
<item name="NUM_SLICEX" rev="33">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_SLICE_CARRY4" rev="33">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NUM_SLICE_CONTROLSET" rev="33">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NUM_SLICE_CYINIT" rev="33">
|
||||
<attrib name="value" value="55"/></item>
|
||||
<item name="NUM_SLICE_FF" rev="33">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_SLICE_UNUSEDCTRL" rev="33">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NUM_UNUSABLE_FF_BELS" rev="33">
|
||||
<attrib name="value" value="11"/></item>
|
||||
<item name="Xilinx Core blk_mem_gen_v7_3, Xilinx CORE Generator 14.7" rev="33">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="Xilinx Core dist_mem_gen_v7_2, Xilinx CORE Generator 14.7" rev="33">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
</DesignStatistics>
|
||||
<CmdHistory>
|
||||
</CmdHistory>
|
||||
</DeviceUsageSummary>
|
||||
@ -1,18 +1,18 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="nt" product="ISE" version="14.7">
|
||||
<document OS="nt64" product="ISE" version="14.7">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Fri Oct 29 17:59:37 2021">
|
||||
<application stringID="Xst" timeStamp="Sun Oct 31 15:37:47 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files\Microchip\xc8\v2.31\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\PuTTY\;C:\Program Files\WinMerge;C:\Program Files\dotnet\;C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;C:\Users\zanek\AppData\Local\GitHubDesktop\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\zanek\.dotnet\tools;C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ispLEVER_Classic2_0\ispcpld\bin;C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;C:\ispLEVER_Classic2_0\active-hdl\BIN;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\PuTTY\;C:\Program Files (x86)\WinMerge;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\Microchip\xc8\v2.31\bin;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\Dog\AppData\Local\GitHubDesktop\bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
@ -36,16 +36,16 @@
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
|
||||
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="ZanePC"/>
|
||||
<item stringID="User_EnvHost" value="Dog-PC"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz"/>
|
||||
<item stringID="speed" value="3500 MHz"/>
|
||||
<item stringID="arch" value="Intel(R) Xeon(R) CPU W3680 @ 3.33GHz"/>
|
||||
<item stringID="speed" value="3316 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
@ -56,13 +56,13 @@
|
||||
<item DEFAULT="" label="-p" stringID="XST_P" value="xc6slx9-2-ftg256"/>
|
||||
<item DEFAULT="" label="-top" stringID="XST_TOP" value="WarpLC"/>
|
||||
<item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
|
||||
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
|
||||
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="2"/>
|
||||
<item DEFAULT="No" label="-power" stringID="XST_POWER" value="NO"/>
|
||||
<item DEFAULT="No" label="-iuc" stringID="XST_IUC" value="NO"/>
|
||||
<item DEFAULT="No" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
|
||||
<item DEFAULT="As_Optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
|
||||
<item DEFAULT="No" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
|
||||
<item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
|
||||
<item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="Inpad_To_Outpad"/>
|
||||
<item DEFAULT="Yes" label="-read_cores" stringID="XST_READCORES" value="YES"/>
|
||||
<item DEFAULT="" label="-sd" stringID="XST_SD" value="{"ipcore_dir" }"/>
|
||||
<item DEFAULT="No" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
|
||||
@ -109,25 +109,20 @@
|
||||
<item dataType="int" stringID="XST_NUM_ODDR2" value="5"/>
|
||||
</section>
|
||||
<section stringID="XST_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="3">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="2"/>
|
||||
<item dataType="int" stringID="XST_32BIT_REGISTER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="1">
|
||||
<item dataType="int" stringID="XST_32BIT_COMPARATOR_EQUAL" value="1"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="1">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="1"></item>
|
||||
</section>
|
||||
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="34">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="34"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="1">
|
||||
<item dataType="int" stringID="XST_32BIT_COMPARATOR_EQUAL" value="1"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="1">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="1"></item>
|
||||
</section>
|
||||
<section stringID="XST_FINAL_REGISTER_REPORT">
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="34">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="34"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="1">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="1"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_REPORT">
|
||||
@ -140,42 +135,46 @@
|
||||
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="WarpLC.ngc"/>
|
||||
</section>
|
||||
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="29">
|
||||
<item dataType="int" stringID="XST_GND" value="1"/>
|
||||
<item dataType="int" stringID="XST_BELS" value="22">
|
||||
<item dataType="int" stringID="XST_GND" value="2"/>
|
||||
<item dataType="int" stringID="XST_INV" value="3"/>
|
||||
<item dataType="int" stringID="XST_LUT3" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT4" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT6" value="10"/>
|
||||
<item dataType="int" stringID="XST_MUXCY" value="12"/>
|
||||
<item dataType="int" stringID="XST_LUT1" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT6" value="7"/>
|
||||
<item dataType="int" stringID="XST_MUXCY" value="8"/>
|
||||
<item dataType="int" stringID="XST_VCC" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="39">
|
||||
<item dataType="int" stringID="XST_FD" value="34"/>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="50">
|
||||
<item dataType="int" stringID="XST_FD" value="44"/>
|
||||
<item dataType="int" stringID="XST_FDR" value="1"/>
|
||||
<item dataType="int" stringID="XST_ODDR2" value="5"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_RAMS" value="23"></item>
|
||||
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="2">
|
||||
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="2"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="43">
|
||||
<item dataType="int" stringID="XST_IBUF" value="35"/>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="66">
|
||||
<item dataType="int" stringID="XST_IBUF" value="26"/>
|
||||
<item dataType="int" stringID="XST_IBUFG" value="2"/>
|
||||
<item dataType="int" stringID="XST_OBUF" value="6"/>
|
||||
<item dataType="int" stringID="XST_OBUF" value="38"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_OTHERS" value="2"></item>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
|
||||
<item stringID="XST_SELECTED_DEVICE" value="6slx9ftg256-2"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="39"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="15"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="15"/>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="52"/>
|
||||
<item AVAILABLE="52" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="13"/>
|
||||
<item AVAILABLE="52" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="37"/>
|
||||
<item AVAILABLE="52" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="2"/>
|
||||
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="1"/>
|
||||
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="43"/>
|
||||
<item AVAILABLE="186" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="43"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="50"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="55"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="11"/>
|
||||
<item AVAILABLE="1440" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="44"/>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="105"/>
|
||||
<item AVAILABLE="105" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="55"/>
|
||||
<item AVAILABLE="105" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="50"/>
|
||||
<item AVAILABLE="105" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="0"/>
|
||||
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="2"/>
|
||||
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="75"/>
|
||||
<item AVAILABLE="186" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="66"/>
|
||||
<item AVAILABLE="32" dataType="int" label="Number of Block RAM/FIFO" stringID="XST_NUMBER_OF_BLOCK_RAMFIFO" value="1"/>
|
||||
<item dataType="int" label="Number using Block RAM only" stringID="XST_NUMBER_USING_BLOCK_RAM_ONLY" value="1"/>
|
||||
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="2"/>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
|
||||
@ -183,8 +182,8 @@
|
||||
</section>
|
||||
<section stringID="XST_ERRORS_STATISTICS">
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="7"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="2"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="17"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="3"/>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
|
||||
@ -1,2 +1,4 @@
|
||||
C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.ngc 1635544779
|
||||
C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.ngc 1635709073
|
||||
ipcore_dir/PrefetchTagRAM.ngc 1635704546
|
||||
ipcore_dir/PrefetchDataRAM.ngc 1635685742
|
||||
OK
|
||||
|
||||
@ -5,10 +5,22 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
|
||||
<msg type="info" file="Map" num="284" delta="old" >Map is running with the multi-threading option on. Map currently supports the use of up to 2 processors. Based on the the user options and machine load, Map will use 2 processors during this run.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="MapLib" num="159" delta="old" >Net Timing constraints on signal <arg fmt="%s" index="1">CLKIN</arg> are pushed forward through input buffer.
|
||||
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">FSB_A<31></arg> has no load.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">54</arg> more times for the following (max. 5 shown):
|
||||
<arg fmt="%s" index="3">FSB_A<30>,
|
||||
FSB_A<29>,
|
||||
FSB_A<28>,
|
||||
FSB_A<1>,
|
||||
FSB_A<0></arg>
|
||||
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
|
||||
@ -23,5 +35,8 @@
|
||||
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="2410" delta="old" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
||||
@ -5,7 +5,39 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="ConstraintSystem" num="0" >The Period constraint <NET CLKIN PERIOD = 30ns HIGH;> [PLL.ucf(3)], is specified using the Net Period method which is not recommended. Please use the Timespec PERIOD method.
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nAS" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nAS</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_SIZ<0>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_SIZ<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_SIZ<1>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_SIZ<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<0>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<1>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<28>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<28></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<29>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<29></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<30>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<30></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<31>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<31></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">CLKIN</arg>', used in period specification '<arg fmt="%s" index="3">TS_CLKIN</arg>', was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">PLL_ADV</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
|
||||
<arg fmt="%s" index="7">CLKFBOUT</arg>: <arg fmt="%s" index="8"><TIMESPEC TS_cg_pll_clkfbout = PERIOD "cg_pll_clkfbout" TS_CLKIN HIGH 50%></arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">CLKIN</arg>', used in period specification '<arg fmt="%s" index="3">TS_CLKIN</arg>', was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">PLL_ADV</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
|
||||
<arg fmt="%s" index="7">CLKOUT0</arg>: <arg fmt="%s" index="8"><TIMESPEC TS_cg_pll_clkout0 = PERIOD "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%></arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
@ -5,5 +5,9 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="Par" num="338" delta="old" >
|
||||
Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are not meeting timing but where the designer wants the tools to continue iterating on the design until no further design speed improvements are possible. This can result in very long runtimes since the tools will continue improving the design even if the time specs can not be met. If you are looking for the best possible design speed available from a long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design speed improvements have shrunk to the point that the time specs are not expected to be met.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
||||
@ -11,8 +11,5 @@
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/PrefetchBuf.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="error" file="ProjectMgmt" num="806" >"<arg fmt="%s" index="1">C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/PrefetchBuf.v</arg>" Line <arg fmt="%d" index="2">36</arg>. <arg fmt="%s" index="3">Syntax error near ")".</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
||||
@ -5,9 +5,9 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
|
||||
<msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
|
||||
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
|
||||
|
||||
|
||||
@ -5,28 +5,61 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 128: Assignment to <arg fmt="%s" index="1">clkout1_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1016" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port <arg fmt="%s" index="1">LOCKED</arg> is not connected to this instance
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 129: Assignment to <arg fmt="%s" index="1">clkout2_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to <arg fmt="%s" index="1">clkout1_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 130: Assignment to <arg fmt="%s" index="1">clkout3_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to <arg fmt="%s" index="1">clkout2_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 131: Assignment to <arg fmt="%s" index="1">clkout4_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to <arg fmt="%s" index="1">clkout3_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 132: Assignment to <arg fmt="%s" index="1">clkout5_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to <arg fmt="%s" index="1">clkout4_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 133: Assignment to <arg fmt="%s" index="1">locked_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to <arg fmt="%s" index="1">clkout5_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 84: Assignment to <arg fmt="%s" index="1">CPUCLKr</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to <arg fmt="%s" index="1">FSB_B</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%s" index="2">79</arg>: Output port <<arg fmt="%s" index="3">CPUCLKr</arg>> of the instance <<arg fmt="%s" index="4">CLKGEN_inst</arg>> is unconnected or connected to loadless signal.
|
||||
<msg type="warning" file="HDLCompiler" num="1499" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module <<arg fmt="%s" index="1">PrefetchTagRAM</arg>> remains a black box.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 33: Size mismatch in connection of port <<arg fmt="%s" index="3">a</arg>>. Formal port size is <arg fmt="%d" index="2">5</arg>-bit while actual signal size is <arg fmt="%d" index="1">7</arg>-bit.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 36: Size mismatch in connection of port <<arg fmt="%s" index="3">dpra</arg>>. Formal port size is <arg fmt="%d" index="2">5</arg>-bit while actual signal size is <arg fmt="%d" index="1">7</arg>-bit.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1499" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" Line 39: Empty module <<arg fmt="%s" index="1">PrefetchDataRAM</arg>> remains a black box.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 44: Size mismatch in connection of port <<arg fmt="%s" index="3">addra</arg>>. Formal port size is <arg fmt="%d" index="2">7</arg>-bit while actual signal size is <arg fmt="%d" index="1">5</arg>-bit.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2972" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%d" index="2">91</arg>. All outputs of instance <<arg fmt="%s" index="3">sd</arg>> of block <<arg fmt="%s" index="4">SizeDecode</arg>> are unconnected in block <<arg fmt="%s" index="5">WarpLC</arg>>. Underlying logic will be removed.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">FSB_A<31:29></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CPU_nAS</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%s" index="2">91</arg>: Output port <<arg fmt="%s" index="3">B</arg>> of the instance <<arg fmt="%s" index="4">sd</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v</arg>" line <arg fmt="%s" index="2">32</arg>: Output port <<arg fmt="%s" index="3">LOCKED</arg>> of the instance <<arg fmt="%s" index="4">pll</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">RDA<28:28></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">WRA<28:28></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="1901" delta="old" >Instance <arg fmt="%s" index="1">pll_base_inst</arg> in unit <arg fmt="%s" index="2">pll_base_inst</arg> of type <arg fmt="%s" index="3">PLL_BASE</arg> has been replaced by <arg fmt="%s" index="4">PLL_ADV</arg>
|
||||
|
||||
@ -1,2 +0,0 @@
|
||||
verilog work ../../CLK.v
|
||||
verilog work ../example_design/CLK_exdes.v
|
||||
@ -1,15 +0,0 @@
|
||||
gui_open_window Wave
|
||||
gui_sg_create CLK_group
|
||||
gui_list_add_group -id Wave.1 {CLK_group}
|
||||
gui_sg_addsignal -group CLK_group {CLK_tb.test_phase}
|
||||
gui_set_radix -radix {ascii} -signals {CLK_tb.test_phase}
|
||||
gui_sg_addsignal -group CLK_group {{Input_clocks}} -divider
|
||||
gui_sg_addsignal -group CLK_group {CLK_tb.CLK_IN1}
|
||||
gui_sg_addsignal -group CLK_group {{Output_clocks}} -divider
|
||||
gui_sg_addsignal -group CLK_group {CLK_tb.dut.clk}
|
||||
gui_list_expand -id Wave.1 CLK_tb.dut.clk
|
||||
gui_sg_addsignal -group CLK_group {{Counters}} -divider
|
||||
gui_sg_addsignal -group CLK_group {CLK_tb.COUNT}
|
||||
gui_sg_addsignal -group CLK_group {CLK_tb.dut.counter}
|
||||
gui_list_expand -id Wave.1 CLK_tb.dut.counter
|
||||
gui_zoom -window Wave.1 -full
|
||||
@ -1,55 +0,0 @@
|
||||
# Output products list for <CLK>
|
||||
CLK.asy
|
||||
CLK.gise
|
||||
CLK.sym
|
||||
CLK.ucf
|
||||
CLK.v
|
||||
CLK.veo
|
||||
CLK.xco
|
||||
CLK.xdc
|
||||
CLK.xise
|
||||
CLK\clk_wiz_v3_6_readme.txt
|
||||
CLK\doc\clk_wiz_v3_6_readme.txt
|
||||
CLK\doc\clk_wiz_v3_6_vinfo.html
|
||||
CLK\doc\pg065_clk_wiz.pdf
|
||||
CLK\example_design\CLK_exdes.ucf
|
||||
CLK\example_design\CLK_exdes.v
|
||||
CLK\example_design\CLK_exdes.xdc
|
||||
CLK\implement\implement.bat
|
||||
CLK\implement\implement.sh
|
||||
CLK\implement\planAhead_ise.bat
|
||||
CLK\implement\planAhead_ise.sh
|
||||
CLK\implement\planAhead_ise.tcl
|
||||
CLK\implement\planAhead_rdn.bat
|
||||
CLK\implement\planAhead_rdn.sh
|
||||
CLK\implement\planAhead_rdn.tcl
|
||||
CLK\implement\xst.prj
|
||||
CLK\implement\xst.scr
|
||||
CLK\simulation\CLK_tb.v
|
||||
CLK\simulation\functional\simcmds.tcl
|
||||
CLK\simulation\functional\simulate_isim.bat
|
||||
CLK\simulation\functional\simulate_isim.sh
|
||||
CLK\simulation\functional\simulate_mti.bat
|
||||
CLK\simulation\functional\simulate_mti.do
|
||||
CLK\simulation\functional\simulate_mti.sh
|
||||
CLK\simulation\functional\simulate_ncsim.sh
|
||||
CLK\simulation\functional\simulate_vcs.sh
|
||||
CLK\simulation\functional\ucli_commands.key
|
||||
CLK\simulation\functional\vcs_session.tcl
|
||||
CLK\simulation\functional\wave.do
|
||||
CLK\simulation\functional\wave.sv
|
||||
CLK\simulation\timing\CLK_tb.v
|
||||
CLK\simulation\timing\sdf_cmd_file
|
||||
CLK\simulation\timing\simcmds.tcl
|
||||
CLK\simulation\timing\simulate_isim.sh
|
||||
CLK\simulation\timing\simulate_mti.bat
|
||||
CLK\simulation\timing\simulate_mti.do
|
||||
CLK\simulation\timing\simulate_mti.sh
|
||||
CLK\simulation\timing\simulate_ncsim.sh
|
||||
CLK\simulation\timing\simulate_vcs.sh
|
||||
CLK\simulation\timing\ucli_commands.key
|
||||
CLK\simulation\timing\vcs_session.tcl
|
||||
CLK\simulation\timing\wave.do
|
||||
CLK_flist.txt
|
||||
CLK_xmdf.tcl
|
||||
_xmsgs\pn_parser.xmsgs
|
||||
@ -1,6 +1,6 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 CLK
|
||||
TEXT 32 32 LEFT 4 PLL
|
||||
RECTANGLE Normal 32 32 576 1088
|
||||
LINE Normal 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
@ -18,4 +18,8 @@ LINE Normal 608 752 576 752
|
||||
PIN 608 752 RIGHT 36
|
||||
PINATTR PinName clkfb_out
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 976 576 976
|
||||
PIN 608 976 RIGHT 36
|
||||
PINATTR PinName locked
|
||||
PINATTR Polarity OUT
|
||||
|
||||
@ -19,31 +19,31 @@
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="CLK.xise"/>
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="PLL.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="CLK.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="CLK.veo" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="PLL.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="PLL.veo" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1635507384" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635507384">
|
||||
<transform xil_pn:end_ts="1635708800" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635708800">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1194492726557041007" xil_pn:start_ts="1635544541">
|
||||
<transform xil_pn:end_ts="1635709065" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3888609537775819197" xil_pn:start_ts="1635709065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6061207241259343081" xil_pn:start_ts="1635544541">
|
||||
<transform xil_pn:end_ts="1635709065" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6060603849343674715" xil_pn:start_ts="1635709065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635544541">
|
||||
<transform xil_pn:end_ts="1635709065" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635709065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1097761553319033393" xil_pn:start_ts="1635544541">
|
||||
<transform xil_pn:end_ts="1635709065" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3791878364537811583" xil_pn:start_ts="1635709065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
@ -1,4 +1,4 @@
|
||||
# file: CLK.ucf
|
||||
# file: PLL.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
@ -51,7 +51,7 @@
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 250.0ps;
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.000 ns HIGH 50% INPUT_JITTER 300.0ps;
|
||||
|
||||
|
||||
# Constraints for external feedback.
|
||||
@ -1,13 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<symbol version="7" name="CLK">
|
||||
<symbol version="7" name="PLL">
|
||||
<symboltype>BLOCK</symboltype>
|
||||
<timestamp>2021-10-29T21:49:45</timestamp>
|
||||
<timestamp>2021-10-31T17:58:31</timestamp>
|
||||
<pin polarity="Input" x="0" y="80" name="clk_in1" />
|
||||
<pin polarity="Input" x="0" y="304" name="clkfb_in" />
|
||||
<pin polarity="Output" x="608" y="80" name="clk_out1" />
|
||||
<pin polarity="Output" x="608" y="752" name="clkfb_out" />
|
||||
<pin polarity="Output" x="608" y="976" name="locked" />
|
||||
<graph>
|
||||
<text style="fontsize:40;fontname:Arial" x="32" y="32">CLK</text>
|
||||
<text style="fontsize:40;fontname:Arial" x="32" y="32">PLL</text>
|
||||
<rect width="544" x="32" y="32" height="1056" />
|
||||
<line x2="32" y1="80" y2="80" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin clk_in1" />
|
||||
@ -17,5 +18,7 @@
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="80" type="pin clk_out1" />
|
||||
<line x2="576" y1="752" y2="752" x1="608" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="752" type="pin clkfb_out" />
|
||||
<line x2="576" y1="976" y2="976" x1="608" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="976" type="pin locked" />
|
||||
</graph>
|
||||
</symbol>
|
||||
@ -1,4 +1,4 @@
|
||||
# file: CLK.ucf
|
||||
# file: PLL.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
@ -51,7 +51,7 @@
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 250.0ps;
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.000 ns HIGH 50% INPUT_JITTER 300.0ps;
|
||||
|
||||
|
||||
# Constraints for external feedback.
|
||||
@ -1,4 +1,4 @@
|
||||
// file: CLK.v
|
||||
// file: PLL.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
@ -55,23 +55,25 @@
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____66.667______0.000______50.0______300.590____267.927
|
||||
// CLK_OUT1____66.667______0.000______50.0______252.559____182.342
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_________33.3333___________0.00833333333333
|
||||
// __primary_________33.3333____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "CLK,clk_wiz_v3_6,{component_name=CLK,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO_OFFCHIP,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=30.0,clkin2_period=30.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
|
||||
module CLK
|
||||
(* CORE_GENERATION_INFO = "PLL,clk_wiz_v3_6,{component_name=PLL,use_phase_alignment=true,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO_OFFCHIP,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=30.000,clkin2_period=30.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
|
||||
module PLL
|
||||
(// Clock in ports
|
||||
input CLKIN,
|
||||
input CLKFB_IN,
|
||||
// Clock out ports
|
||||
output FSBCLK,
|
||||
output CLKFB_OUT
|
||||
output CLKFB_OUT,
|
||||
// Status and control signals
|
||||
output LOCKED
|
||||
);
|
||||
|
||||
// Input buffering
|
||||
@ -100,7 +102,6 @@ module CLK
|
||||
// * Unused outputs are labeled unused
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire locked_unused;
|
||||
wire clkfbout;
|
||||
wire clkfbout_buf;
|
||||
wire clkout1_unused;
|
||||
@ -110,17 +111,17 @@ module CLK
|
||||
wire clkout5_unused;
|
||||
|
||||
PLL_BASE
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
#(.BANDWIDTH ("HIGH"),
|
||||
.CLK_FEEDBACK ("CLKFBOUT"),
|
||||
.COMPENSATION ("EXTERNAL"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT (12),
|
||||
.CLKFBOUT_MULT (28),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKOUT0_DIVIDE (6),
|
||||
.CLKOUT0_DIVIDE (14),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKIN_PERIOD (30.0),
|
||||
.REF_JITTER (0.008))
|
||||
.CLKIN_PERIOD (30.000),
|
||||
.REF_JITTER (0.010))
|
||||
pll_base_inst
|
||||
// Output clocks
|
||||
(.CLKFBOUT (clkfbout),
|
||||
@ -130,7 +131,8 @@ module CLK
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.LOCKED (locked_unused),
|
||||
// Status and control signals
|
||||
.LOCKED (LOCKED),
|
||||
.RST (1'b0),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfb_in_buf_out),
|
||||
@ -54,12 +54,12 @@
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____66.667______0.000______50.0______300.590____267.927
|
||||
// CLK_OUT1____66.667______0.000______50.0______252.559____182.342
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_________33.3333___________0.00833333333333
|
||||
// __primary_________33.3333____________0.010
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
@ -67,11 +67,13 @@
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
CLK instance_name
|
||||
PLL instance_name
|
||||
(// Clock in ports
|
||||
.CLKIN(CLKIN), // IN
|
||||
.CLKFB_IN(CLKFB_IN), // IN
|
||||
// Clock out ports
|
||||
.FSBCLK(FSBCLK), // OUT
|
||||
.CLKFB_OUT(CLKFB_OUT)); // OUT
|
||||
.CLKFB_OUT(CLKFB_OUT), // OUT
|
||||
// Status and control signals
|
||||
.LOCKED(LOCKED)); // OUT
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
@ -1,7 +1,7 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.7
|
||||
# Date: Fri Oct 29 21:49:29 2021
|
||||
# Date: Sun Oct 31 17:58:14 2021
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
@ -43,13 +43,13 @@ CSET calc_done=DONE
|
||||
CSET clk_in_sel_port=CLK_IN_SEL
|
||||
CSET clk_out1_port=FSBCLK
|
||||
CSET clk_out1_use_fine_ps_gui=false
|
||||
CSET clk_out2_port=RAMCLK
|
||||
CSET clk_out2_port=CLK_OUT2
|
||||
CSET clk_out2_use_fine_ps_gui=false
|
||||
CSET clk_out3_port=CPUCLK
|
||||
CSET clk_out3_port=CLK_OUT3
|
||||
CSET clk_out3_use_fine_ps_gui=false
|
||||
CSET clk_out4_port=C80M
|
||||
CSET clk_out4_port=CLK_OUT4
|
||||
CSET clk_out4_use_fine_ps_gui=false
|
||||
CSET clk_out5_port=C50M
|
||||
CSET clk_out5_port=CLK_OUT5
|
||||
CSET clk_out5_use_fine_ps_gui=false
|
||||
CSET clk_out6_port=CLK_OUT6
|
||||
CSET clk_out6_use_fine_ps_gui=false
|
||||
@ -64,66 +64,66 @@ CSET clkfb_out_n_port=CLKFB_OUT_N
|
||||
CSET clkfb_out_p_port=CLKFB_OUT_P
|
||||
CSET clkfb_out_port=CLKFB_OUT
|
||||
CSET clkfb_stopped_port=CLKFB_STOPPED
|
||||
CSET clkin1_jitter_ps=250.0
|
||||
CSET clkin1_ui_jitter=250.000
|
||||
CSET clkin2_jitter_ps=40.0
|
||||
CSET clkin2_ui_jitter=100.000
|
||||
CSET clkin1_jitter_ps=300.0
|
||||
CSET clkin1_ui_jitter=0.010
|
||||
CSET clkin2_jitter_ps=100.0
|
||||
CSET clkin2_ui_jitter=0.010
|
||||
CSET clkout1_drives=BUFG
|
||||
CSET clkout1_requested_duty_cycle=50.0
|
||||
CSET clkout1_requested_out_freq=66.667
|
||||
CSET clkout1_requested_phase=0.000
|
||||
CSET clkout2_drives=BUFG
|
||||
CSET clkout2_requested_duty_cycle=50.0
|
||||
CSET clkout2_requested_out_freq=33.3333
|
||||
CSET clkout2_requested_phase=0
|
||||
CSET clkout2_requested_out_freq=33.333
|
||||
CSET clkout2_requested_phase=0.000
|
||||
CSET clkout2_used=false
|
||||
CSET clkout3_drives=BUFG
|
||||
CSET clkout3_requested_duty_cycle=50.0
|
||||
CSET clkout3_requested_out_freq=33.3333
|
||||
CSET clkout3_requested_phase=-72
|
||||
CSET clkout3_requested_out_freq=100.000
|
||||
CSET clkout3_requested_phase=0.000
|
||||
CSET clkout3_used=false
|
||||
CSET clkout4_drives=BUFG
|
||||
CSET clkout4_requested_duty_cycle=50.0
|
||||
CSET clkout4_requested_out_freq=33.3333
|
||||
CSET clkout4_requested_phase=0
|
||||
CSET clkout4_requested_out_freq=100.000
|
||||
CSET clkout4_requested_phase=0.000
|
||||
CSET clkout4_used=false
|
||||
CSET clkout5_drives=BUFG
|
||||
CSET clkout5_requested_duty_cycle=50.0
|
||||
CSET clkout5_requested_out_freq=33.3333
|
||||
CSET clkout5_requested_out_freq=100.000
|
||||
CSET clkout5_requested_phase=0.000
|
||||
CSET clkout5_used=false
|
||||
CSET clkout6_drives=BUFG
|
||||
CSET clkout6_requested_duty_cycle=50.0
|
||||
CSET clkout6_requested_out_freq=33.3333
|
||||
CSET clkout6_requested_out_freq=100.000
|
||||
CSET clkout6_requested_phase=0.000
|
||||
CSET clkout6_used=false
|
||||
CSET clkout7_drives=BUFG
|
||||
CSET clkout7_requested_duty_cycle=50.0
|
||||
CSET clkout7_requested_out_freq=33.3333
|
||||
CSET clkout7_requested_out_freq=100.000
|
||||
CSET clkout7_requested_phase=0.000
|
||||
CSET clkout7_used=false
|
||||
CSET clock_mgr_type=MANUAL
|
||||
CSET component_name=CLK
|
||||
CSET component_name=PLL
|
||||
CSET daddr_port=DADDR
|
||||
CSET dclk_port=DCLK
|
||||
CSET dcm_clk_feedback=1X
|
||||
CSET dcm_clk_out1_port=CLK0
|
||||
CSET dcm_clk_out2_port=CLK2X
|
||||
CSET dcm_clk_feedback=2X
|
||||
CSET dcm_clk_out1_port=CLK2X
|
||||
CSET dcm_clk_out2_port=CLK0
|
||||
CSET dcm_clk_out3_port=CLKFX
|
||||
CSET dcm_clk_out4_port=CLKFX
|
||||
CSET dcm_clk_out5_port=CLKFX
|
||||
CSET dcm_clk_out4_port=CLK0
|
||||
CSET dcm_clk_out5_port=CLK0
|
||||
CSET dcm_clk_out6_port=CLK0
|
||||
CSET dcm_clkdv_divide=2.0
|
||||
CSET dcm_clkfx_divide=1
|
||||
CSET dcm_clkfx_multiply=4
|
||||
CSET dcm_clkgen_clk_out1_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out2_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out3_port=CLKFX180
|
||||
CSET dcm_clkgen_clkfx_divide=2
|
||||
CSET dcm_clkgen_clk_out3_port=CLKFX
|
||||
CSET dcm_clkgen_clkfx_divide=1
|
||||
CSET dcm_clkgen_clkfx_md_max=0.000
|
||||
CSET dcm_clkgen_clkfx_multiply=2
|
||||
CSET dcm_clkgen_clkfx_multiply=4
|
||||
CSET dcm_clkgen_clkfxdv_divide=2
|
||||
CSET dcm_clkgen_clkin_period=30.303
|
||||
CSET dcm_clkgen_clkin_period=10.000
|
||||
CSET dcm_clkgen_notes=None
|
||||
CSET dcm_clkgen_spread_spectrum=NONE
|
||||
CSET dcm_clkgen_startup_wait=false
|
||||
@ -144,10 +144,10 @@ CSET feedback_source=FDBK_AUTO_OFFCHIP
|
||||
CSET in_freq_units=Units_MHz
|
||||
CSET in_jitter_units=Units_UI
|
||||
CSET input_clk_stopped_port=INPUT_CLK_STOPPED
|
||||
CSET jitter_options=PS
|
||||
CSET jitter_sel=No_Jitter
|
||||
CSET jitter_options=UI
|
||||
CSET jitter_sel=Min_O_Jitter
|
||||
CSET locked_port=LOCKED
|
||||
CSET mmcm_bandwidth=OPTIMIZED
|
||||
CSET mmcm_bandwidth=HIGH
|
||||
CSET mmcm_clkfbout_mult_f=4.000
|
||||
CSET mmcm_clkfbout_phase=0.000
|
||||
CSET mmcm_clkfbout_use_fine_ps=false
|
||||
@ -195,24 +195,24 @@ CSET override_dcm_clkgen=false
|
||||
CSET override_mmcm=false
|
||||
CSET override_pll=false
|
||||
CSET platform=nt
|
||||
CSET pll_bandwidth=OPTIMIZED
|
||||
CSET pll_bandwidth=HIGH
|
||||
CSET pll_clk_feedback=CLKFBOUT
|
||||
CSET pll_clkfbout_mult=12
|
||||
CSET pll_clkfbout_mult=28
|
||||
CSET pll_clkfbout_phase=0.000
|
||||
CSET pll_clkin_period=30.0
|
||||
CSET pll_clkout0_divide=6
|
||||
CSET pll_clkin_period=30.000
|
||||
CSET pll_clkout0_divide=14
|
||||
CSET pll_clkout0_duty_cycle=0.500
|
||||
CSET pll_clkout0_phase=0.000
|
||||
CSET pll_clkout1_divide=10
|
||||
CSET pll_clkout1_divide=12
|
||||
CSET pll_clkout1_duty_cycle=0.500
|
||||
CSET pll_clkout1_phase=0.000
|
||||
CSET pll_clkout2_divide=10
|
||||
CSET pll_clkout2_divide=4
|
||||
CSET pll_clkout2_duty_cycle=0.500
|
||||
CSET pll_clkout2_phase=-72.000
|
||||
CSET pll_clkout3_divide=10
|
||||
CSET pll_clkout2_phase=0.000
|
||||
CSET pll_clkout3_divide=1
|
||||
CSET pll_clkout3_duty_cycle=0.500
|
||||
CSET pll_clkout3_phase=0.000
|
||||
CSET pll_clkout4_divide=16
|
||||
CSET pll_clkout4_divide=1
|
||||
CSET pll_clkout4_duty_cycle=0.500
|
||||
CSET pll_clkout4_phase=0.000
|
||||
CSET pll_clkout5_divide=1
|
||||
@ -221,10 +221,10 @@ CSET pll_clkout5_phase=0.000
|
||||
CSET pll_compensation=EXTERNAL
|
||||
CSET pll_divclk_divide=1
|
||||
CSET pll_notes=None
|
||||
CSET pll_ref_jitter=0.008
|
||||
CSET pll_ref_jitter=0.010
|
||||
CSET power_down_port=POWER_DOWN
|
||||
CSET prim_in_freq=33.3333
|
||||
CSET prim_in_jitter=0.00833333333333
|
||||
CSET prim_in_jitter=0.010
|
||||
CSET prim_source=Single_ended_clock_capable_pin
|
||||
CSET primary_port=CLKIN
|
||||
CSET primitive=MMCM
|
||||
@ -236,7 +236,7 @@ CSET psincdec_port=PSINCDEC
|
||||
CSET relative_inclk=REL_PRIMARY
|
||||
CSET reset_port=RESET
|
||||
CSET secondary_in_freq=100.000
|
||||
CSET secondary_in_jitter=0.004
|
||||
CSET secondary_in_jitter=0.010
|
||||
CSET secondary_port=CLK_IN2
|
||||
CSET secondary_source=Single_ended_clock_capable_pin
|
||||
CSET ss_mod_freq=250
|
||||
@ -251,7 +251,7 @@ CSET use_freeze=false
|
||||
CSET use_freq_synth=true
|
||||
CSET use_inclk_stopped=false
|
||||
CSET use_inclk_switchover=false
|
||||
CSET use_locked=false
|
||||
CSET use_locked=true
|
||||
CSET use_max_i_jitter=false
|
||||
CSET use_min_o_jitter=false
|
||||
CSET use_min_power=false
|
||||
@ -266,4 +266,4 @@ CSET use_status=false
|
||||
MISC pkg_timestamp=2012-05-10T12:44:55Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 51d6f701
|
||||
# CRC: 8225559f
|
||||
@ -1,4 +1,4 @@
|
||||
# file: CLK.xdc
|
||||
# file: PLL.xdc
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
@ -50,9 +50,9 @@
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
create_clock -name CLK_IN1 -period 30.0 [get_ports CLK_IN1]
|
||||
create_clock -name CLK_IN1 -period 30.000 [get_ports CLK_IN1]
|
||||
set_propagated_clock CLK_IN1
|
||||
set_input_jitter CLK_IN1 0.25
|
||||
set_input_jitter CLK_IN1 0.3
|
||||
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
403
fpga/ipcore_dir/PLL.xise
Normal file
403
fpga/ipcore_dir/PLL.xise
Normal file
@ -0,0 +1,403 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="PLL.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="PLL.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|PLL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="PLL.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/PLL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="PLL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ftg256" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="PLL_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="PLL_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="PLL_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="PLL_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="PLL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-10-31T13:58:33" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="91EB3D98921C40729D5589D0E666D471" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/PLL" xil_pn:name="PLL.ucf"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@ -1,4 +1,4 @@
|
||||
# file: CLK_exdes.ucf
|
||||
# file: PLL_exdes.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
@ -51,7 +51,7 @@
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 250.0ps;
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.000 ns HIGH 50% INPUT_JITTER 300.0ps;
|
||||
|
||||
|
||||
# Constraints for external feedback.
|
||||
@ -1,4 +1,4 @@
|
||||
// file: CLK_exdes.v
|
||||
// file: PLL_exdes.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
@ -56,7 +56,7 @@
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module CLK_exdes
|
||||
module PLL_exdes
|
||||
#(
|
||||
parameter TCQ = 100
|
||||
)
|
||||
@ -68,15 +68,17 @@ module CLK_exdes
|
||||
output [1:1] CLK_OUT,
|
||||
// High bits of counters driven by clocks
|
||||
output COUNT,
|
||||
output CLKFB_OUT
|
||||
output CLKFB_OUT,
|
||||
// Status and control signals
|
||||
output LOCKED
|
||||
);
|
||||
|
||||
// Parameters for the counters
|
||||
//-------------------------------
|
||||
// Counter width
|
||||
localparam C_W = 16;
|
||||
// Create reset for the counters
|
||||
wire reset_int = COUNTER_RESET;
|
||||
// When the clock goes out of lock, reset the counters
|
||||
wire reset_int = !LOCKED || COUNTER_RESET;
|
||||
|
||||
reg rst_sync;
|
||||
reg rst_sync_int;
|
||||
@ -93,13 +95,15 @@ module CLK_exdes
|
||||
|
||||
// Instantiation of the clocking network
|
||||
//--------------------------------------
|
||||
CLK clknetwork
|
||||
PLL clknetwork
|
||||
(// Clock in ports
|
||||
.CLKIN (CLK_IN1),
|
||||
.CLKFB_IN (CLKFB_IN),
|
||||
// Clock out ports
|
||||
.FSBCLK (clk_int),
|
||||
.CLKFB_OUT (CLKFB_OUT));
|
||||
.CLKFB_OUT (CLKFB_OUT),
|
||||
// Status and control signals
|
||||
.LOCKED (LOCKED));
|
||||
|
||||
assign clk_n = ~clk;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# file: CLK_exdes.xdc
|
||||
# file: PLL_exdes.xdc
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
@ -50,9 +50,9 @@
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
create_clock -name CLK_IN1 -period 30.0 [get_ports CLK_IN1]
|
||||
create_clock -name CLK_IN1 -period 30.000 [get_ports CLK_IN1]
|
||||
set_propagated_clock CLK_IN1
|
||||
set_input_jitter CLK_IN1 0.25
|
||||
set_input_jitter CLK_IN1 0.3
|
||||
|
||||
# FALSE PATH constraint added on COUNTER_RESET
|
||||
set_false_path -from [get_ports "COUNTER_RESET"]
|
||||
@ -61,19 +61,19 @@ copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
|
||||
REM Synthesize the Verilog Wrapper Files
|
||||
echo 'Synthesizing Clocking Wizard design with XST'
|
||||
xst -ifn xst.scr
|
||||
move CLK_exdes.ngc results\
|
||||
move PLL_exdes.ngc results\
|
||||
|
||||
REM Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\CLK_exdes.ucf results\
|
||||
copy ..\example_design\PLL_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -uc CLK_exdes.ucf CLK_exdes
|
||||
ngdbuild -uc PLL_exdes.ucf PLL_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map -timing -pr b CLK_exdes -o mapped.ncd
|
||||
map -timing -pr b PLL_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par -w mapped.ncd routed mapped.pcf
|
||||
@ -85,6 +85,6 @@ echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level model for the clocking wizard example design'
|
||||
netgen -ofmt verilog -sim -sdf_anno false -tm CLK_exdes -w routed.ncd routed.v
|
||||
netgen -ofmt verilog -sim -sdf_anno false -tm PLL_exdes -w routed.ncd routed.v
|
||||
cd ..
|
||||
|
||||
@ -62,19 +62,19 @@ cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
|
||||
# Synthesize the Verilog Wrapper Files
|
||||
echo 'Synthesizing Clocking Wizard design with XST'
|
||||
xst -ifn xst.scr
|
||||
mv CLK_exdes.ngc results/
|
||||
mv PLL_exdes.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/CLK_exdes.ucf results/
|
||||
cp ../example_design/PLL_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -uc CLK_exdes.ucf CLK_exdes
|
||||
ngdbuild -uc PLL_exdes.ucf PLL_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map -timing CLK_exdes -o mapped.ncd
|
||||
map -timing PLL_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par -w mapped.ncd routed mapped.pcf
|
||||
@ -86,6 +86,6 @@ echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level model for the clocking wizard example design'
|
||||
netgen -ofmt verilog -sim -sdf_anno false -tm CLK_exdes -w routed.ncd routed.v
|
||||
netgen -ofmt verilog -sim -sdf_anno false -tm PLL_exdes -w routed.ncd routed.v
|
||||
|
||||
cd ..
|
||||
@ -48,8 +48,8 @@
|
||||
#
|
||||
|
||||
set projDir [file dirname [info script]]
|
||||
set projName CLK
|
||||
set topName CLK_exdes
|
||||
set projName PLL
|
||||
set topName PLL_exdes
|
||||
set device xc6slx9ftg256-2
|
||||
|
||||
create_project $projName $projDir/results/$projName -part $device
|
||||
@ -58,12 +58,12 @@ set_property design_mode RTL [get_filesets sources_1]
|
||||
|
||||
## Source files
|
||||
#set verilogSources [glob $srcDir/*.v]
|
||||
import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/CLK_exdes.v
|
||||
import_files -fileset [get_filesets sources_1] -force -norecurse ../../../CLK.v
|
||||
import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/PLL_exdes.v
|
||||
import_files -fileset [get_filesets sources_1] -force -norecurse ../../../PLL.v
|
||||
|
||||
|
||||
#UCF file
|
||||
import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/CLK_exdes.ucf
|
||||
import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/PLL_exdes.ucf
|
||||
|
||||
set_property top $topName [get_property srcset [current_run]]
|
||||
|
||||
@ -48,22 +48,22 @@
|
||||
#
|
||||
|
||||
set device xc6slx9ftg256-2
|
||||
set projName CLK
|
||||
set design CLK
|
||||
set projName PLL
|
||||
set design PLL
|
||||
set projDir [file dirname [info script]]
|
||||
create_project $projName $projDir/results/$projName -part $device -force
|
||||
set_property design_mode RTL [current_fileset -srcset]
|
||||
set top_module CLK_exdes
|
||||
set_property top CLK_exdes [get_property srcset [current_run]]
|
||||
add_files -norecurse {../../../CLK.v}
|
||||
add_files -norecurse {../../example_design/CLK_exdes.v}
|
||||
import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/CLK_exdes.xdc}
|
||||
set top_module PLL_exdes
|
||||
set_property top PLL_exdes [get_property srcset [current_run]]
|
||||
add_files -norecurse {../../../PLL.v}
|
||||
add_files -norecurse {../../example_design/PLL_exdes.v}
|
||||
import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/PLL_exdes.xdc}
|
||||
synth_design
|
||||
opt_design
|
||||
place_design
|
||||
route_design
|
||||
write_sdf -rename_top_module CLK_exdes -file routed.sdf
|
||||
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module CLK_exdes -file routed.v
|
||||
write_sdf -rename_top_module PLL_exdes -file routed.sdf
|
||||
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module PLL_exdes -file routed.v
|
||||
report_timing -nworst 30 -path_type full -file routed.twr
|
||||
report_drc -file report.drc
|
||||
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
|
||||
2
fpga/ipcore_dir/PLL/implement/xst.prj
Normal file
2
fpga/ipcore_dir/PLL/implement/xst.prj
Normal file
@ -0,0 +1,2 @@
|
||||
verilog work ../../PLL.v
|
||||
verilog work ../example_design/PLL_exdes.v
|
||||
@ -1,9 +1,9 @@
|
||||
run
|
||||
-ifmt MIXED
|
||||
-top CLK_exdes
|
||||
-top PLL_exdes
|
||||
-p xc6slx9-ftg256-2
|
||||
-ifn xst.prj
|
||||
-ofn CLK_exdes
|
||||
-ofn PLL_exdes
|
||||
-keep_hierarchy soft
|
||||
-equivalent_register_removal no
|
||||
-max_fanout 65535
|
||||
@ -1,4 +1,4 @@
|
||||
// file: CLK_tb.v
|
||||
// file: PLL_tb.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
@ -57,9 +57,9 @@
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`define wait_lock @(posedge dut.clknetwork.pll_base_inst.LOCKED)
|
||||
`define wait_lock @(posedge LOCKED)
|
||||
|
||||
module CLK_tb ();
|
||||
module PLL_tb ();
|
||||
|
||||
// Clock to Q delay of 100ps
|
||||
localparam TCQ = 100;
|
||||
@ -71,7 +71,7 @@ module CLK_tb ();
|
||||
// how many cycles to run
|
||||
localparam COUNT_PHASE = 1024;
|
||||
// we'll be using the period in many locations
|
||||
localparam time PER1 = 30.0*ONE_NS;
|
||||
localparam time PER1 = 30.000*ONE_NS;
|
||||
localparam time PER1_1 = PER1/2;
|
||||
localparam time PER1_2 = PER1 - PER1/2;
|
||||
|
||||
@ -83,6 +83,8 @@ module CLK_tb ();
|
||||
// Connect the feedback
|
||||
wire CLKFB_OUT;
|
||||
wire CLKFB_IN = CLKFB_OUT;
|
||||
// Status and control signals
|
||||
wire LOCKED;
|
||||
reg COUNTER_RESET = 0;
|
||||
wire [1:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
@ -119,7 +121,7 @@ wire [1:1] CLK_OUT;
|
||||
// Instantiation of the example design containing the clock
|
||||
// network and sampling counters
|
||||
//---------------------------------------------------------
|
||||
CLK_exdes
|
||||
PLL_exdes
|
||||
#(
|
||||
.TCQ (TCQ)
|
||||
) dut
|
||||
@ -131,7 +133,9 @@ wire [1:1] CLK_OUT;
|
||||
.CLK_OUT (CLK_OUT),
|
||||
// High bits of the counters
|
||||
.COUNT (COUNT),
|
||||
.CLKFB_OUT (CLKFB_OUT));
|
||||
.CLKFB_OUT (CLKFB_OUT),
|
||||
// Status and control signals
|
||||
.LOCKED (LOCKED));
|
||||
|
||||
// Freq Check
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
|
||||
# create the simulation script
|
||||
vcd dumpfile isim.vcd
|
||||
vcd dumpvars -m /CLK_tb -l 0
|
||||
vcd dumpvars -m /PLL_tb -l 0
|
||||
wave add /
|
||||
run 50000ns
|
||||
quit
|
||||
@ -48,12 +48,12 @@ REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
vlogcomp -work work %XILINX%\verilog\src\glbl.v
|
||||
vlogcomp -work work ..\..\..\CLK.v
|
||||
vlogcomp -work work ..\..\example_design\CLK_exdes.v
|
||||
vlogcomp -work work ..\CLK_tb.v
|
||||
vlogcomp -work work ..\..\..\PLL.v
|
||||
vlogcomp -work work ..\..\example_design\PLL_exdes.v
|
||||
vlogcomp -work work ..\PLL_tb.v
|
||||
|
||||
REM compile the project
|
||||
fuse work.CLK_tb work.glbl -L unisims_ver -o CLK_isim.exe
|
||||
fuse work.PLL_tb work.glbl -L unisims_ver -o PLL_isim.exe
|
||||
|
||||
REM run the simulation script
|
||||
.\CLK_isim.exe -gui -tclbatch simcmds.tcl
|
||||
.\PLL_isim.exe -gui -tclbatch simcmds.tcl
|
||||
@ -50,12 +50,12 @@
|
||||
# nt
|
||||
# create the project
|
||||
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
|
||||
vlogcomp -work work ../../../CLK.v
|
||||
vlogcomp -work work ../../example_design/CLK_exdes.v
|
||||
vlogcomp -work work ../CLK_tb.v
|
||||
vlogcomp -work work ../../../PLL.v
|
||||
vlogcomp -work work ../../example_design/PLL_exdes.v
|
||||
vlogcomp -work work ../PLL_tb.v
|
||||
|
||||
# compile the project
|
||||
fuse work.CLK_tb work.glbl -L unisims_ver -o CLK_isim.exe
|
||||
fuse work.PLL_tb work.glbl -L unisims_ver -o PLL_isim.exe
|
||||
|
||||
# run the simulation script
|
||||
./CLK_isim.exe -gui -tclbatch simcmds.tcl
|
||||
./PLL_isim.exe -gui -tclbatch simcmds.tcl
|
||||
@ -52,10 +52,10 @@ vlib work
|
||||
|
||||
REM compile all of the files
|
||||
vlog -work work %XILINX%\verilog\src\glbl.v
|
||||
vlog -work work ..\..\..\CLK.v
|
||||
vlog -work work ..\..\example_design\CLK_exdes.v
|
||||
vlog -work work ..\CLK_tb.v
|
||||
vlog -work work ..\..\..\PLL.v
|
||||
vlog -work work ..\..\example_design\PLL_exdes.v
|
||||
vlog -work work ..\PLL_tb.v
|
||||
|
||||
REM run the simulation
|
||||
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.CLK_tb work.glbl
|
||||
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.PLL_tb work.glbl
|
||||
|
||||
@ -53,13 +53,13 @@ vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $env(XILINX)/verilog/src/glbl.v
|
||||
vlog -work work ../../../CLK.v
|
||||
vlog -work work ../../example_design/CLK_exdes.v
|
||||
vlog -work work ../CLK_tb.v
|
||||
vlog -work work ../../../PLL.v
|
||||
vlog -work work ../../example_design/PLL_exdes.v
|
||||
vlog -work work ../PLL_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -t ps -voptargs="+acc" -L unisims_ver work.CLK_tb work.glbl
|
||||
vsim -t ps -voptargs="+acc" -L unisims_ver work.PLL_tb work.glbl
|
||||
do wave.do
|
||||
log CLK_tb/dut/counter
|
||||
log PLL_tb/dut/counter
|
||||
log -r /*
|
||||
run 50000ns
|
||||
@ -53,9 +53,9 @@ vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $XILINX/verilog/src/glbl.v
|
||||
vlog -work work ../../../CLK.v
|
||||
vlog -work work ../../example_design/CLK_exdes.v
|
||||
vlog -work work ../CLK_tb.v
|
||||
vlog -work work ../../../PLL.v
|
||||
vlog -work work ../../example_design/PLL_exdes.v
|
||||
vlog -work work ../PLL_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.CLK_tb work.glbl
|
||||
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.PLL_tb work.glbl
|
||||
@ -53,10 +53,10 @@ mkdir work
|
||||
|
||||
# compile all of the files
|
||||
ncvlog -work work ${XILINX}/verilog/src/glbl.v
|
||||
ncvlog -work work ../../../CLK.v
|
||||
ncvlog -work work ../../example_design/CLK_exdes.v
|
||||
ncvlog -work work ../CLK_tb.v
|
||||
ncvlog -work work ../../../PLL.v
|
||||
ncvlog -work work ../../example_design/PLL_exdes.v
|
||||
ncvlog -work work ../PLL_tb.v
|
||||
|
||||
# elaborate and run the simulation
|
||||
ncelab -work work -access +wc work.CLK_tb work.glbl
|
||||
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.CLK_tb
|
||||
ncelab -work work -access +wc work.PLL_tb work.glbl
|
||||
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.PLL_tb
|
||||
@ -58,12 +58,12 @@ rm -rf simv* csrc DVEfiles AN.DB
|
||||
# [63:0] from time
|
||||
vlogan -sverilog \
|
||||
${XILINX}/verilog/src/glbl.v \
|
||||
../../../CLK.v \
|
||||
../../example_design/CLK_exdes.v \
|
||||
../CLK_tb.v
|
||||
../../../PLL.v \
|
||||
../../example_design/PLL_exdes.v \
|
||||
../PLL_tb.v
|
||||
|
||||
# prepare the simulation
|
||||
vcs +vcs+lic+wait -debug CLK_tb glbl
|
||||
vcs +vcs+lic+wait -debug PLL_tb glbl
|
||||
|
||||
# run the simulation
|
||||
./simv -ucli -i ucli_commands.key
|
||||
@ -1,5 +1,5 @@
|
||||
call {$vcdpluson}
|
||||
call {$vcdplusmemon(CLK_tb.dut.counter)}
|
||||
call {$vcdplusmemon(PLL_tb.dut.counter)}
|
||||
run
|
||||
call {$vcdplusclose}
|
||||
quit
|
||||
17
fpga/ipcore_dir/PLL/simulation/functional/vcs_session.tcl
Normal file
17
fpga/ipcore_dir/PLL/simulation/functional/vcs_session.tcl
Normal file
@ -0,0 +1,17 @@
|
||||
gui_open_window Wave
|
||||
gui_sg_create PLL_group
|
||||
gui_list_add_group -id Wave.1 {PLL_group}
|
||||
gui_sg_addsignal -group PLL_group {PLL_tb.test_phase}
|
||||
gui_set_radix -radix {ascii} -signals {PLL_tb.test_phase}
|
||||
gui_sg_addsignal -group PLL_group {{Input_clocks}} -divider
|
||||
gui_sg_addsignal -group PLL_group {PLL_tb.CLK_IN1}
|
||||
gui_sg_addsignal -group PLL_group {{Output_clocks}} -divider
|
||||
gui_sg_addsignal -group PLL_group {PLL_tb.dut.clk}
|
||||
gui_list_expand -id Wave.1 PLL_tb.dut.clk
|
||||
gui_sg_addsignal -group PLL_group {{Status_control}} -divider
|
||||
gui_sg_addsignal -group PLL_group {PLL_tb.LOCKED}
|
||||
gui_sg_addsignal -group PLL_group {{Counters}} -divider
|
||||
gui_sg_addsignal -group PLL_group {PLL_tb.COUNT}
|
||||
gui_sg_addsignal -group PLL_group {PLL_tb.dut.counter}
|
||||
gui_list_expand -id Wave.1 PLL_tb.dut.counter
|
||||
gui_zoom -window Wave.1 -full
|
||||
@ -47,11 +47,13 @@
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
add wave -noupdate -format Literal -radix ascii /CLK_tb/test_phase
|
||||
add wave -noupdate -format Literal -radix ascii /PLL_tb/test_phase
|
||||
add wave -noupdate -divider {Input clocks}
|
||||
add wave -noupdate -format Logic /CLK_tb/CLK_IN1
|
||||
add wave -noupdate -format Logic /PLL_tb/CLK_IN1
|
||||
add wave -noupdate -divider {Output clocks}
|
||||
add wave -noupdate -format Logic /CLK_tb/dut/clk
|
||||
add wave -noupdate -format Logic /PLL_tb/dut/clk
|
||||
add wave -noupdate -divider Status/control
|
||||
add wave -noupdate -format Logic /PLL_tb/LOCKED
|
||||
add wave -noupdate -divider Counters
|
||||
add wave -noupdate -format Literal -radix hexadecimal /CLK_tb/COUNT
|
||||
add wave -noupdate -format Literal -radix hexadecimal /CLK_tb/dut/counter
|
||||
add wave -noupdate -format Literal -radix hexadecimal /PLL_tb/COUNT
|
||||
add wave -noupdate -format Literal -radix hexadecimal /PLL_tb/dut/counter
|
||||
@ -54,8 +54,8 @@ if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536
|
||||
window target "Design Browser 1" on
|
||||
browser using {Design Browser 1}
|
||||
browser set \
|
||||
-scope nc::CLK_tb
|
||||
browser yview see nc::CLK_tb
|
||||
-scope nc::PLL_tb
|
||||
browser yview see nc::PLL_tb
|
||||
browser timecontrol set -lock 0
|
||||
|
||||
if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
|
||||
@ -81,7 +81,7 @@ catch {group new -name {Output clocks} -overlay 0}
|
||||
catch {group new -name {Status/control} -overlay 0}
|
||||
catch {group new -name {Counters} -overlay 0}
|
||||
|
||||
set id [waveform add -signals [list {nc::CLK_tb.CLK_IN1}]]
|
||||
set id [waveform add -signals [list {nc::PLL_tb.CLK_IN1}]]
|
||||
|
||||
group using {Output clocks}
|
||||
group set -overlay 0
|
||||
@ -89,7 +89,7 @@ group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{CLK_tb.dut.clk} \
|
||||
{PLL_tb.dut.clk} \
|
||||
|
||||
group using {Counters}
|
||||
group set -overlay 0
|
||||
@ -97,12 +97,20 @@ group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{CLK_tb.dut.counter} \
|
||||
{PLL_tb.dut.counter} \
|
||||
|
||||
group using {Status/control}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{nc::PLL_tb.LOCKED}
|
||||
|
||||
|
||||
set id [waveform add -signals [list {nc::CLK_tb.COUNT} ]]
|
||||
set id [waveform add -signals [list {nc::PLL_tb.COUNT} ]]
|
||||
|
||||
set id [waveform add -signals [list {nc::CLK_tb.test_phase} ]]
|
||||
set id [waveform add -signals [list {nc::PLL_tb.test_phase} ]]
|
||||
waveform format $id -radix %a
|
||||
|
||||
set groupId [waveform add -groups {{Input clocks}}]
|
||||
@ -1,4 +1,4 @@
|
||||
// file: CLK_tb.v
|
||||
// file: PLL_tb.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
@ -57,8 +57,9 @@
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`define wait_lock @(posedge LOCKED)
|
||||
|
||||
module CLK_tb ();
|
||||
module PLL_tb ();
|
||||
|
||||
// Clock to Q delay of 100ps
|
||||
localparam TCQ = 100;
|
||||
@ -70,7 +71,7 @@ module CLK_tb ();
|
||||
// how many cycles to run
|
||||
localparam COUNT_PHASE = 1024;
|
||||
// we'll be using the period in many locations
|
||||
localparam time PER1 = 30.0*ONE_NS;
|
||||
localparam time PER1 = 30.000*ONE_NS;
|
||||
localparam time PER1_1 = PER1/2;
|
||||
localparam time PER1_2 = PER1 - PER1/2;
|
||||
|
||||
@ -82,6 +83,8 @@ module CLK_tb ();
|
||||
// Connect the feedback
|
||||
wire CLKFB_OUT;
|
||||
wire CLKFB_IN = CLKFB_OUT;
|
||||
// Status and control signals
|
||||
wire LOCKED;
|
||||
reg COUNTER_RESET = 0;
|
||||
wire [1:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
@ -103,7 +106,7 @@ wire [1:1] CLK_OUT;
|
||||
$display ("Timing checks are not valid");
|
||||
COUNTER_RESET = 0;
|
||||
test_phase = "wait lock";
|
||||
#(PER1*50);
|
||||
`wait_lock;
|
||||
#(PER1*6);
|
||||
COUNTER_RESET = 1;
|
||||
#(PER1*19.5)
|
||||
@ -119,11 +122,21 @@ wire [1:1] CLK_OUT;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge CLK_IN1) begin
|
||||
timeout_counter <= timeout_counter + 1'b1;
|
||||
if (timeout_counter == 14'b10000000000000) begin
|
||||
if (LOCKED != 1'b1) begin
|
||||
$display("ERROR : NO LOCK signal");
|
||||
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Instantiation of the example design containing the clock
|
||||
// network and sampling counters
|
||||
//---------------------------------------------------------
|
||||
CLK_exdes
|
||||
PLL_exdes
|
||||
dut
|
||||
(// Clock in ports
|
||||
.CLK_IN1 (CLK_IN1),
|
||||
@ -133,7 +146,9 @@ wire [1:1] CLK_OUT;
|
||||
.CLK_OUT (CLK_OUT),
|
||||
// High bits of the counters
|
||||
.COUNT (COUNT),
|
||||
.CLKFB_OUT (CLKFB_OUT));
|
||||
.CLKFB_OUT (CLKFB_OUT),
|
||||
// Status and control signals
|
||||
.LOCKED (LOCKED));
|
||||
|
||||
|
||||
// Freq Check
|
||||
@ -1,2 +1,2 @@
|
||||
COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
|
||||
SCOPE = CLK_tb.dut;
|
||||
SCOPE = PLL_tb.dut;
|
||||
@ -2,7 +2,7 @@
|
||||
|
||||
# create the simulation script
|
||||
vcd dumpfile isim.vcd
|
||||
vcd dumpvars -m /CLK_tb -l 0
|
||||
vcd dumpvars -m /PLL_tb -l 0
|
||||
wave add /
|
||||
run 50000ns
|
||||
quit
|
||||
@ -50,13 +50,13 @@
|
||||
# create the project
|
||||
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
|
||||
vlogcomp -work work ../../implement/results/routed.v
|
||||
vlogcomp -work work CLK_tb.v
|
||||
vlogcomp -work work PLL_tb.v
|
||||
|
||||
# compile the project
|
||||
fuse work.CLK_tb work.glbl -L secureip -L simprims_ver -o CLK_isim.exe
|
||||
fuse work.PLL_tb work.glbl -L secureip -L simprims_ver -o PLL_isim.exe
|
||||
|
||||
# run the simulation script
|
||||
./CLK_isim.exe -tclbatch simcmds.tcl -sdfmax /CLK_tb/dut=../../implement/results/routed.sdf
|
||||
./PLL_isim.exe -tclbatch simcmds.tcl -sdfmax /PLL_tb/dut=../../implement/results/routed.sdf
|
||||
|
||||
# run the simulation script
|
||||
#./CLK_isim.exe -gui -tclbatch simcmds.tcl
|
||||
#./PLL_isim.exe -gui -tclbatch simcmds.tcl
|
||||
@ -53,7 +53,7 @@ vlib work
|
||||
REM compile all of the files
|
||||
vlog -work work %XILINX%\verilog\src\glbl.v
|
||||
vlog -work work ..\..\implement\results\routed.v
|
||||
vlog -work work CLK_tb.v
|
||||
vlog -work work PLL_tb.v
|
||||
|
||||
REM run the simulation
|
||||
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax CLK_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.CLK_tb work.glbl
|
||||
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax PLL_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.PLL_tb work.glbl
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
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Reference in New Issue
Block a user