mirror of
https://github.com/garrettsworkshop/Warp-LC.git
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74 lines
2.1 KiB
Plaintext
74 lines
2.1 KiB
Plaintext
##############################################################
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#
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# Xilinx Core Generator version 14.7
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# Date: Tue Nov 02 04:32:07 2021
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:dist_mem_gen:7.2
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc6slx9
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SET devicefamily = spartan6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = ftg256
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = true
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SET vhdlsim = false
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# END Project Options
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# BEGIN Select
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SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
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# END Select
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# BEGIN Parameters
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CSET ce_overrides=ce_overrides_sync_controls
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CSET coefficient_file=no_coe_file_loaded
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CSET common_output_ce=false
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CSET common_output_clk=false
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CSET component_name=PrefetchTagRAM
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CSET data_width=20
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CSET default_data=0
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CSET default_data_radix=16
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CSET depth=128
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CSET dual_port_address=non_registered
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CSET dual_port_output_clock_enable=false
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CSET input_clock_enable=false
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CSET input_options=non_registered
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CSET memory_type=dual_port_ram
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CSET output_options=non_registered
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CSET pipeline_stages=0
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CSET qualify_we_with_i_ce=false
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CSET reset_qdpo=false
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CSET reset_qsdpo=false
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CSET reset_qspo=false
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CSET simple_dual_port_address=non_registered
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CSET simple_dual_port_output_clock_enable=false
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CSET single_port_output_clock_enable=false
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CSET sync_reset_qdpo=false
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CSET sync_reset_qsdpo=false
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CSET sync_reset_qspo=false
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-11-21T20:07:40Z
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# END Extra information
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GENERATE
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# CRC: c3055252
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