Warp-LC/fpga/ipcore_dir/coregen.cgp
2021-10-29 10:04:15 -04:00

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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET package = ftg256
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false