mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2024-06-10 07:29:31 +00:00
40 lines
2.4 KiB
XML
40 lines
2.4 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated -->
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<!-- by the Xilinx ISE software. Any direct editing or -->
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<!-- changes made to this file may result in unpredictable -->
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<!-- behavior or data corruption. It is strongly advised that -->
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<!-- users do not edit the contents of this file. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<messages>
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<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/CS.v" into library work</arg>
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</msg>
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<msg type="error" file="ProjectMgmt" num="806" >"<arg fmt="%s" index="1">C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/CS.v</arg>" Line <arg fmt="%d" index="2">3</arg>. <arg fmt="%s" index="3">Syntax error near "output".</arg>
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</msg>
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<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ClkGen.v" into library work</arg>
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</msg>
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<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/L2Cache.v" into library work</arg>
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</msg>
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<msg type="error" file="ProjectMgmt" num="806" >"<arg fmt="%s" index="1">C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/L2Cache.v</arg>" Line <arg fmt="%d" index="2">34</arg>. <arg fmt="%s" index="3">Syntax error near "==".</arg>
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</msg>
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<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/L2CacheWay.v" into library work</arg>
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</msg>
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<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/Prefetch.v" into library work</arg>
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</msg>
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<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/SizeDecode.v" into library work</arg>
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</msg>
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<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.v" into library work</arg>
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</msg>
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</messages>
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