Warp-LC/fpga/ipcore_dir/L2WayRAM/implement/implement.sh
2021-11-01 12:12:16 -04:00

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#!/bin/sh
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp L2WayRAM_exdes.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../L2WayRAM.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/L2WayRAM_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6slx9-ftg256-2 L2WayRAM_exdes
echo 'Running map'
map L2WayRAM_exdes -o mapped.ncd -pr i
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm L2WayRAM_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v