Warp-LC/fpga/ipcore_dir/L2WayRAM/simulation/timing/vcs_session.tcl
2021-11-01 12:12:16 -04:00

90 lines
3.9 KiB
Tcl

#--------------------------------------------------------------------------------
#--
#-- BMG Generator v8.4 Core Demo Testbench
#--
#--------------------------------------------------------------------------------
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
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# Filename: vcs_session.tcl
#
# Description:
# This is the VCS wave form file.
#
#--------------------------------------------------------------------------------
if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
gui_open_db -design V1 -file bmg_vcs.vpd -nosource
}
gui_set_precision 1ps
gui_set_time_units 1ps
gui_open_window Wave
gui_sg_create L2WayRAM_Group
gui_list_add_group -id Wave.1 {L2WayRAM_Group}
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/status
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/CLKA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ADDRA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DINA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/WEA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ENA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DOUTA
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/CLKB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ADDRB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/ENB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DINB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/WEB
gui_sg_addsignal -group L2WayRAM_Group /L2WayRAM_tb/L2WayRAM_synth_inst/bmg_port/DOUTB
gui_zoom -window Wave.1 -full