mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2024-06-10 07:29:31 +00:00
175 lines
7.6 KiB
Plaintext
175 lines
7.6 KiB
Plaintext
Release 14.7 Map P.20131013 (nt)
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Xilinx Map Application Log File for Design 'WarpLC'
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Design Information
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------------------
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Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol
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high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
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-pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
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Target Device : xc6slx9
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Target Package : ftg256
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Target Speed : -2
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Mapper Version : spartan6 -- $Revision: 1.55 $
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Mapped Date : Fri Oct 29 17:59:44 2021
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vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
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INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
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INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
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'C:\ispLEVER_Classic2_0\license\license.dat;C:\lscc\diamond\3.12\license\license
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.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'.
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INFO:Security:54 - 'xc6slx9' is a WebPack part.
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INFO:Security:66 - Your license for 'ISE' is for evaluation use only.
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WARNING:Security:43 - No license file was found in the standard Xilinx license
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directory.
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WARNING:Security:44 - Since no license file was found,
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please run the Xilinx License Configuration Manager
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(xlcm or "Manage Xilinx Licenses")
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to assist in obtaining a license.
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WARNING:Security:40 - Your license for 'ISE' expires in 4 days.
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----------------------------------------------------------------------
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Mapping design into LUTs...
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Running directed packing...
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Running delay-based LUT packing...
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Updating timing models...
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INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
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(.mrp).
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Running timing-driven placement...
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Total REAL time at the beginning of Placer: 2 secs
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Total CPU time at the beginning of Placer: 2 secs
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Phase 1.1 Initial Placement Analysis
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Phase 1.1 Initial Placement Analysis (Checksum:18bd) REAL time: 2 secs
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Phase 2.7 Design Feasibility Check
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Phase 2.7 Design Feasibility Check (Checksum:18bd) REAL time: 2 secs
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Phase 3.31 Local Placement Optimization
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Phase 3.31 Local Placement Optimization (Checksum:18bd) REAL time: 2 secs
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Phase 4.2 Initial Placement for Architecture Specific Features
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...
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Phase 4.2 Initial Placement for Architecture Specific Features
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(Checksum:4099679c) REAL time: 3 secs
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Phase 5.36 Local Placement Optimization
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Phase 5.36 Local Placement Optimization (Checksum:4099679c) REAL time: 3 secs
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Phase 6.30 Global Clock Region Assignment
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Phase 6.30 Global Clock Region Assignment (Checksum:4099679c) REAL time: 3 secs
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Phase 7.3 Local Placement Optimization
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...
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Phase 7.3 Local Placement Optimization (Checksum:432b55c8) REAL time: 3 secs
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Phase 8.5 Local Placement Optimization
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Phase 8.5 Local Placement Optimization (Checksum:432b55c8) REAL time: 3 secs
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Phase 9.8 Global Placement
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..
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................
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................
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..
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Phase 9.8 Global Placement (Checksum:8bf5099b) REAL time: 3 secs
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Phase 10.5 Local Placement Optimization
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Phase 10.5 Local Placement Optimization (Checksum:8bf5099b) REAL time: 3 secs
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Phase 11.18 Placement Optimization
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Phase 11.18 Placement Optimization (Checksum:8bd6219d) REAL time: 3 secs
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Phase 12.5 Local Placement Optimization
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Phase 12.5 Local Placement Optimization (Checksum:8bd6219d) REAL time: 3 secs
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Phase 13.34 Placement Validation
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Phase 13.34 Placement Validation (Checksum:8bd2a88c) REAL time: 3 secs
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Total REAL time to Placer completion: 3 secs
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Total CPU time to Placer completion: 3 secs
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Running post-placement packing...
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Writing output files...
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Design Summary
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--------------
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Design Summary:
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Number of errors: 0
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Number of warnings: 0
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Slice Logic Utilization:
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Number of Slice Registers: 34 out of 11,440 1%
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Number used as Flip Flops: 34
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 17 out of 5,720 1%
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Number used as logic: 13 out of 5,720 1%
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Number using O6 output only: 11
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Number using O5 output only: 0
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Number using O5 and O6: 2
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Number used as ROM: 0
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Number used as Memory: 0 out of 1,440 0%
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Number used exclusively as route-thrus: 4
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Number with same-slice register load: 4
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Number with same-slice carry load: 0
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Number with other load: 0
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Slice Logic Distribution:
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Number of occupied Slices: 11 out of 1,430 1%
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Number of MUXCYs used: 12 out of 2,860 1%
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Number of LUT Flip Flop pairs used: 41
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Number with an unused Flip Flop: 11 out of 41 26%
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Number with an unused LUT: 24 out of 41 58%
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Number of fully used LUT-FF pairs: 6 out of 41 14%
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Number of unique control sets: 1
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Number of slice register sites lost
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to control set restrictions: 6 out of 11,440 1%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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Number of bonded IOBs: 43 out of 186 23%
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IOB Flip Flops: 5
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Specific Feature Utilization:
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Number of RAMB16BWERs: 0 out of 32 0%
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Number of RAMB8BWERs: 0 out of 64 0%
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Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
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Number used as BUFIO2s: 1
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Number used as BUFIO2_2CLKs: 0
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Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
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Number used as BUFIO2FBs: 1
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Number used as BUFIO2FB_2CLKs: 0
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Number of BUFG/BUFGMUXs: 2 out of 16 12%
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Number used as BUFGs: 2
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Number used as BUFGMUX: 0
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Number of DCM/DCM_CLKGENs: 0 out of 4 0%
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Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
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Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
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Number of OLOGIC2/OSERDES2s: 5 out of 200 2%
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Number used as OLOGIC2s: 5
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Number used as OSERDES2s: 0
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHs: 0 out of 128 0%
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Number of BUFPLLs: 0 out of 8 0%
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Number of BUFPLL_MCBs: 0 out of 4 0%
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Number of DSP48A1s: 0 out of 16 0%
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Number of ICAPs: 0 out of 1 0%
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Number of MCBs: 0 out of 2 0%
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Number of PCILOGICSEs: 0 out of 2 0%
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Number of PLL_ADVs: 1 out of 2 50%
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Number of PMVs: 0 out of 1 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of SUSPEND_SYNCs: 0 out of 1 0%
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Average Fanout of Non-Clock Nets: 1.41
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Peak Memory Usage: 276 MB
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Total REAL time to MAP completion: 3 secs
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Total CPU time to MAP completion: 3 secs
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Mapping completed.
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See MAP report file "WarpLC_map.mrp" for details.
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