mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2025-04-09 19:37:58 +00:00
Clock stuff
This commit is contained in:
Zane Kaminski
parent
8c91d823f7
commit
54053a7eda
0
fpga/CLKGEN.ucf
Normal file
0
fpga/CLKGEN.ucf
Normal file
64
fpga/CLKGEN.v
Normal file
64
fpga/CLKGEN.v
Normal file
@ -0,0 +1,64 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 16:47:14 10/29/2021
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// Design Name:
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// Module Name: CLKGEN
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module CLKGEN(
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input CLKIN,
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input CLKFB_IN,
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output CLKFB_OUT,
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output FSBCLK,
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output reg CPUCLKr,
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output CPUCLK,
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output FPUCLK,
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output RAMCLK0,
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output RAMCLK1);
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CLK instance_name (
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.CLKIN(CLKIN),
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.CLKFB_IN(CLKFB_IN),
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.CLKFB_OUT(CLKFB_OUT),
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.FSBCLK(FSBCLK));
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always @(posedge FSBCLK) CPUCLKr <= ~CPUCLKr;
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ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(1'b0), .SRTYPE("ASYNC"))
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CPUCLK_inst (.Q(CPUCLK), .CE(1'b1),
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.C0(FSBCLK), .C1(~FSBCLK),
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.D0(1'b0), .D1(1'b1),
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.R(1'b0), .S(1'b0));
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ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(1'b0), .SRTYPE("ASYNC"))
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FPUCLK_inst (.Q(FPUCLK), .CE(1'b1),
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.C0(FSBCLK), .C1(~FSBCLK),
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.D0(CPUCLKr), .D1(CPUCLKr),
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.R(1'b0), .S(1'b0));
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ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(1'b0), .SRTYPE("ASYNC"))
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RAMCLK0_inst (.Q(RAMCLK0), .CE(1'b1),
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.C0(FSBCLK), .C1(~FSBCLK),
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.D0(1'b0), .D1(1'b1),
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.R(1'b0), .S(1'b0));
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ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(1'b0), .SRTYPE("ASYNC"))
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RAMCLK1_inst (.Q(RAMCLK1), .CE(1'b1),
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.C0(FSBCLK), .C1(~FSBCLK),
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.D0(1'b0), .D1(1'b1),
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.R(1'b0), .S(1'b0));
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endmodule
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43
fpga/PLL.ucf
43
fpga/PLL.ucf
@ -1,6 +1,39 @@
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NET CLKFB_OUT FEEDBACK = 160ps NET CLKFB_IN;
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NET FSBCLK FEEDBACK = 160ps NET CLKFB_IN;
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NET CPUCLKi FEEDBACK = 160ps NET CLKFB_IN;
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NET nRESOE SLEW = "QUIETIO";
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NET CLKIN PERIOD = 20ns HIGH;
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NET CPU_nAS OFFSET = IN 10ns VALID 11ns BEFORE FSBCLK;
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NET CLKIN PERIOD = 30ns HIGH;
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NET INt OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[31] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[30] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[29] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[28] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[27] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[26] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[25] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[24] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[23] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[22] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[21] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[20] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[19] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[18] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[17] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[16] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[15] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[14] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[13] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[12] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[11] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[10] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[9] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[8] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[7] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[6] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[5] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[4] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[3] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[2] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[1] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET FSB_A[0] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET CPU_nAS OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
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NET OUTt OFFSET = OUT 5ns AFTER CLKIN;
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835
fpga/WarpLC.bld
835
fpga/WarpLC.bld
@ -12,838 +12,13 @@ Done.
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Annotating constraints to design from ucf file "PLL.ucf" ...
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Resolving constraint associations...
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Checking Constraint Associations...
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<9>" IOBDELAY = NONE>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<9>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<9>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<9>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<10>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<10>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<10>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<10>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<11>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<11>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<11>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<11>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<12>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<12>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<12>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<12>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<13>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<13>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<13>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<13>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<14>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<14>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<14>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<14>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<15>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<15>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<15>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<15>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<16>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<16>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<16>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<16>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<17>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<17>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<17>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<17>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<18>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<18>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<18>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<18>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<19>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<19>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<19>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<19>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<20>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<20>' because those design objects do not
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contain or drive any instances of the correct type.
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<20>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<20>' because those design objects do not
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contain or drive any instances of the correct type.
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|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<21>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/FSB_D<21>' because those design objects do not
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contain or drive any instances of the correct type.
|
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|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<21>" SLEW = FAST>: This
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constraint cannot be distributed from the design objects matching 'NET:
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UniqueName: /WarpLC/EXPANDED/FSB_D<21>' because those design objects do not
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contain or drive any instances of the correct type.
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|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<22>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/FSB_D<22>' because those design objects do not
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contain or drive any instances of the correct type.
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|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<22>" SLEW = FAST>: This
|
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constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/FSB_D<22>' because those design objects do not
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contain or drive any instances of the correct type.
|
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|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<23>" IOBDELAY = NONE>:
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This constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/FSB_D<23>' because those design objects do not
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contain or drive any instances of the correct type.
|
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|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<23>" SLEW = FAST>: This
|
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constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/FSB_D<23>' because those design objects do not
|
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contain or drive any instances of the correct type.
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||||
|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<24>" IOBDELAY = NONE>:
|
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This constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/FSB_D<24>' because those design objects do not
|
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contain or drive any instances of the correct type.
|
||||
|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<24>" SLEW = FAST>: This
|
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constraint cannot be distributed from the design objects matching 'NET:
|
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UniqueName: /WarpLC/EXPANDED/FSB_D<24>' because those design objects do not
|
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contain or drive any instances of the correct type.
|
||||
|
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WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<25>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<25>' because those design objects do not
|
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contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<25>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<25>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<26>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<26>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<26>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<26>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<27>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<27>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<27>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<27>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<28>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<28>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<28>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<28>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<29>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<29>' because those design objects do not
|
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contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<29>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<29>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<30>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<30>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<30>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<30>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<31>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<31>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<31>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<31>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_nBERR" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_nBERR' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOBCLK" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOBCLK' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "nRES" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/nRES' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nCBREQ" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nCBREQ' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nDS" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nDS' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nECS" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nECS' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nCIOUT" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nCIOUT' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_nDSACK<0>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_nDSACK<0>' because those design objects do
|
||||
not contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_nDSACK<1>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_nDSACK<1>' because those design objects do
|
||||
not contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_SIZ<0>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_SIZ<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_SIZ<1>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_SIZ<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_A<0>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_A<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_CLK23" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_CLK23' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_CKE" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_CKE' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_nWE" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_nWE' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_nCAS" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_nCAS' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_nRAS" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_nRAS' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_nCS" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_nCS' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nCIIN" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nCIIN' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nCBACK" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nCBACK' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_DDIR" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_DDIR' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nDOE" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nDOE' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "CPU_nDSACKOE" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/CPU_nDSACKOE' because those design objects do
|
||||
not contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_nRMC" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_nRMC' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<0>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<1>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<2>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<2>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<3>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<3>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<4>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<4>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<5>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<5>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<6>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<6>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<7>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<7>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<8>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<8>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<9>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<9>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<10>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<10>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<11>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<11>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<12>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<12>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<13>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<13>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<14>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<14>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<15>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<15>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<16>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<16>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<17>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<17>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<18>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<18>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<19>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<19>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<20>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<20>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<21>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<21>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<22>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<22>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<23>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<23>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<24>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<24>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<25>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<25>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<26>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<26>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<27>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<27>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<28>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<28>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<29>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<29>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<30>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<30>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "IOB_D<31>" IOBDELAY = NONE>:
|
||||
This constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/IOB_D<31>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_DQM<0>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_DQM<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_DQM<1>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_DQM<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_DQM<2>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_DQM<2>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_DQM<3>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_DQM<3>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<0>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<1>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<2>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<2>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<3>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<3>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<4>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<4>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<5>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<5>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<6>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<6>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<7>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<7>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<8>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<8>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<9>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<9>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<10>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<10>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<11>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<11>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_A<12>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_A<12>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_BA<0>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_BA<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "RAM_BA<1>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/RAM_BA<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<0>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<0>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<0>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<1>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<1>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<1>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<2>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<2>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<2>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<2>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<3>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<3>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<3>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<3>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<4>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<4>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<4>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<4>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<5>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<5>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<5>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<5>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<6>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<6>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<6>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<6>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<7>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<7>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<7>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<7>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<8>" IOBDELAY = NONE>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<8>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:119 - Constraint <NET "FSB_D<8>" SLEW = FAST>: This
|
||||
constraint cannot be distributed from the design objects matching 'NET:
|
||||
UniqueName: /WarpLC/EXPANDED/FSB_D<8>' because those design objects do not
|
||||
contain or drive any instances of the correct type.
|
||||
|
||||
WARNING:ConstraintSystem:130 - Constraint <NET FSBCLK FEEDBACK = 160ps NET
|
||||
CLKFB_IN;> [PLL.ucf(2)]: NET "FSBCLK" is not connected to an input or output
|
||||
pad.
|
||||
|
||||
WARNING:ConstraintSystem:85 - Constraint <NET FSBCLK FEEDBACK = 160ps NET
|
||||
CLKFB_IN;> [PLL.ucf(2)]: This constraint will be ignored because NET "FSBCLK"
|
||||
could not be found.
|
||||
|
||||
WARNING:ConstraintSystem:130 - Constraint <NET CPUCLKi FEEDBACK = 160ps NET
|
||||
CLKFB_IN;> [PLL.ucf(3)]: NET "CPUCLKi" is not connected to an input or output
|
||||
pad.
|
||||
|
||||
WARNING:ConstraintSystem:85 - Constraint <NET CPUCLKi FEEDBACK = 160ps NET
|
||||
CLKFB_IN;> [PLL.ucf(3)]: This constraint will be ignored because NET
|
||||
"CPUCLKi" could not be found.
|
||||
|
||||
WARNING:ConstraintSystem:168 - Constraint <NET CPU_nAS OFFSET = IN 10ns VALID
|
||||
11ns BEFORE FSBCLK;> [PLL.ucf(6)]: This constraint will be ignored because
|
||||
NET "FSBCLK" could not be found or was not connected to a PAD.
|
||||
|
||||
INFO:ConstraintSystem - The Period constraint <NET CLKIN PERIOD = 20ns HIGH;>
|
||||
[PLL.ucf(5)], is specified using the Net Period method which is not
|
||||
INFO:ConstraintSystem - The Period constraint <NET CLKIN PERIOD = 30ns HIGH;>
|
||||
[PLL.ucf(3)], is specified using the Net Period method which is not
|
||||
recommended. Please use the Timespec PERIOD method.
|
||||
|
||||
Done...
|
||||
|
||||
Checking expanded design ...
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_A<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<31>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<30>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<29>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<28>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<27>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<26>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<25>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<24>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<23>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<22>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<21>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<20>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<19>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<18>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<17>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<16>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<15>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<14>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<13>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<12>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<11>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<10>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<9>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<8>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<7>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<6>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<5>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<4>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<3>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<2>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_D<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_BA<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_BA<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<12>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<11>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<10>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<9>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<8>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<7>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<6>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<5>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<4>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<3>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<2>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_A<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_DQM<3>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_DQM<2>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_DQM<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_DQM<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_A<3>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_A<2>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_A<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_A<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_SIZ<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_SIZ<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<31>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<30>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<29>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<28>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<27>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<26>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<25>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<24>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<23>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<22>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<21>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<20>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<19>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<18>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<17>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<16>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<15>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<14>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<13>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<12>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<11>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<10>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<9>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<8>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<7>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<6>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<5>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<4>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<3>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<2>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<1>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_D<0>' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'FSB_nRMC' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_nAOE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_nDSACKOE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_nDOE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_DDIR' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_nCBACK' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_nCIIN' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'CPU_nHALT' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_nCS' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_nRAS' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_nCAS' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_nWE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_CKE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'RAM_CLK23' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_nAOE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_ADoutLE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_nAS' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_nDS' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_nDOE' has no driver
|
||||
WARNING:NgdBuild:452 - logical net 'IOB_DDIR' has no driver
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
@ -854,12 +29,12 @@ Partition Implementation Status
|
||||
|
||||
NGDBUILD Design Results Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 254
|
||||
Number of warnings: 0
|
||||
|
||||
Total memory usage is 134032 kilobytes
|
||||
Total memory usage is 133904 kilobytes
|
||||
|
||||
Writing NGD file "WarpLC.ngd" ...
|
||||
Total REAL time to NGDBUILD completion: 3 sec
|
||||
Total REAL time to NGDBUILD completion: 1 sec
|
||||
Total CPU time to NGDBUILD completion: 1 sec
|
||||
|
||||
Writing NGDBUILD log file "WarpLC.bld"...
|
||||
|
||||
@ -279,3 +279,225 @@ ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6s
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd
|
||||
map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
|
||||
@ -72,35 +72,35 @@
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635516166">
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635544541">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3515295135630071778" xil_pn:start_ts="1635516166">
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3515295135630071778" xil_pn:start_ts="1635544541">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:in_ck="-7186897629097209311" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4864019295268560826" xil_pn:start_ts="1635516166">
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:in_ck="-7186897629097209311" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4864019295268560826" xil_pn:start_ts="1635544541">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="ipcore_dir/CLK.v"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:in_ck="2640051198016270512" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635516166">
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:in_ck="2640051198016270512" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635544541">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6691162141195559328" xil_pn:start_ts="1635516166">
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6691162141195559328" xil_pn:start_ts="1635544541">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:in_ck="2640051198016270512" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745411629038" xil_pn:start_ts="1635516166">
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:in_ck="2640051198016270512" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745411629038" xil_pn:start_ts="1635544541">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="5917552782042024336" xil_pn:start_ts="1635516166">
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="5917552782042024336" xil_pn:start_ts="1635544541">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516171" xil_pn:in_ck="-5185463249901030118" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7414298865524902037" xil_pn:start_ts="1635516166">
|
||||
<transform xil_pn:end_ts="1635544781" xil_pn:in_ck="-4595070235146848110" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7414298865524902037" xil_pn:start_ts="1635544776">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
@ -118,13 +118,12 @@
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516171" xil_pn:in_ck="-7789573454286277367" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704523" xil_pn:start_ts="1635516171">
|
||||
<transform xil_pn:end_ts="1635544781" xil_pn:in_ck="-7789573454286277367" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704523" xil_pn:start_ts="1635544781">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516176" xil_pn:in_ck="5584679923051828355" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2511870374322119143" xil_pn:start_ts="1635516171">
|
||||
<transform xil_pn:end_ts="1635544784" xil_pn:in_ck="5584679923051828355" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2511870374322119143" xil_pn:start_ts="1635544781">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="WarpLC.bld"/>
|
||||
<outfile xil_pn:name="WarpLC.ngd"/>
|
||||
@ -132,9 +131,8 @@
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516182" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="111412226054857016" xil_pn:start_ts="1635516176">
|
||||
<transform xil_pn:end_ts="1635544789" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="111412226054857016" xil_pn:start_ts="1635544784">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="WarpLC.pcf"/>
|
||||
<outfile xil_pn:name="WarpLC_map.map"/>
|
||||
@ -146,7 +144,7 @@
|
||||
<outfile xil_pn:name="WarpLC_usage.xml"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516187" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1635516182">
|
||||
<transform xil_pn:end_ts="1635544794" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1635544789">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="WarpLC.ncd"/>
|
||||
@ -168,15 +166,15 @@
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516191" xil_pn:in_ck="5584679923051828224" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1635516187">
|
||||
<transform xil_pn:end_ts="1635544798" xil_pn:in_ck="5584679923051828224" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1635544794">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="WarpLC.twr"/>
|
||||
<outfile xil_pn:name="WarpLC.twx"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635510526" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791352" xil_pn:start_ts="1635510523">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<transform xil_pn:end_ts="1635517529" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791352" xil_pn:start_ts="1635517526">
|
||||
<status xil_pn:value="AbortedRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
100
fpga/WarpLC.pad
100
fpga/WarpLC.pad
@ -1,7 +1,7 @@
|
||||
Release 14.7 - par P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Fri Oct 29 10:03:06 2021
|
||||
Fri Oct 29 17:59:53 2021
|
||||
|
||||
|
||||
# NOTE: This file is designed to be imported into a spreadsheet program
|
||||
@ -20,7 +20,7 @@ Pinout by Pin Number:
|
||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
|
||||
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
|
||||
A1|||GND||||||||||||
|
||||
A2|CLKFB_OUT|IOB|IO_L52N_M3A9_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
A2||IOBS|IO_L52N_M3A9_3|UNUSED||3|||||||||
|
||||
A3||IOBS|IO_L83N_VREF_3|UNUSED||3|||||||||
|
||||
A4||IOBS|IO_L1N_VREF_0|UNUSED||0|||||||||
|
||||
A5||IOBS|IO_L2N_0|UNUSED||0|||||||||
|
||||
@ -36,7 +36,7 @@ A14||IOBS|IO_L65N_SCP2_0|UNUSED||0|||||||||
|
||||
A15|||TMS||||||||||||
|
||||
A16|||GND||||||||||||
|
||||
B1|CPUCLK|IOB|IO_L50N_M3BA2_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
B2|RAM_CLK01|IOB|IO_L52P_M3A8_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
B2||IOBM|IO_L52P_M3A8_3|UNUSED||3|||||||||
|
||||
B3||IOBM|IO_L83P_3|UNUSED||3|||||||||
|
||||
B4|||VCCO_0|||0|||||any******||||
|
||||
B5||IOBM|IO_L2P_0|UNUSED||0|||||||||
|
||||
@ -51,9 +51,9 @@ B13|||VCCO_0|||0|||||any******||||
|
||||
B14||IOBM|IO_L65P_SCP3_0|UNUSED||0|||||||||
|
||||
B15||IOBM|IO_L29P_A23_M1A13_1|UNUSED||1|||||||||
|
||||
B16||IOBS|IO_L29N_A22_M1A14_1|UNUSED||1|||||||||
|
||||
C1|CPU_nDSACK|IOB|IO_L50P_M3WE_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|NO|NONE|
|
||||
C2|CPU_nSTERM|IOB|IO_L48N_M3BA1_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|NO|NONE|
|
||||
C3|FSB_FC<2>|IOB|IO_L48P_M3BA0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
C1|FPUCLK|IOB|IO_L50P_M3WE_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
C2|INt|IOB|IO_L48N_M3BA1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
C3|OUTt|IOB|IO_L48P_M3BA0_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|NO|NONE|
|
||||
C4||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0|||||||||
|
||||
C5||IOBS|IO_L3N_0|UNUSED||0|||||||||
|
||||
C6||IOBS|IO_L7N_0|UNUSED||0|||||||||
|
||||
@ -67,9 +67,9 @@ C13||IOBM|IO_L63P_SCP7_0|UNUSED||0|||||||||
|
||||
C14|||TCK||||||||||||
|
||||
C15||IOBM|IO_L33P_A15_M1A10_1|UNUSED||1|||||||||
|
||||
C16||IOBS|IO_L33N_A14_M1A4_1|UNUSED||1|||||||||
|
||||
D1|FSB_RnW|IOB|IO_L49N_M3A2_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
D1|RAMCLK0|IOB|IO_L49N_M3A2_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
D2|||VCCO_3|||3|||||3.30||||
|
||||
D3|CPU_nAS|IOB|IO_L49P_M3A7_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
D3|RAMCLK1|IOB|IO_L49P_M3A7_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
D4|||GND||||||||||||
|
||||
D5||IOBM|IO_L3P_0|UNUSED||0|||||||||
|
||||
D6||IOBM|IO_L7P_0|UNUSED||0|||||||||
|
||||
@ -83,8 +83,8 @@ D13|||GND||||||||||||
|
||||
D14||IOBM|IO_L31P_A19_M1CKE_1|UNUSED||1|||||||||
|
||||
D15|||VCCO_1|||1|||||any******||||
|
||||
D16||IOBS|IO_L31N_A18_M1A12_1|UNUSED||1|||||||||
|
||||
E1|nFPUCS|IOB|IO_L46N_M3CLKN_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|NO|NONE|
|
||||
E2|FSB_A<31>|IOB|IO_L46P_M3CLK_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
E1|FSB_A<27>|IOB|IO_L46N_M3CLKN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
E2|FSB_A<24>|IOB|IO_L46P_M3CLK_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
E3||IOBS|IO_L54N_M3A11_3|UNUSED||3|||||||||
|
||||
E4||IOBM|IO_L54P_M3RESET_3|UNUSED||3|||||||||
|
||||
E5|||VCCAUX||||||||2.5||||
|
||||
@ -99,9 +99,9 @@ E13||IOBM|IO_L1P_A25_1|UNUSED||1|||||||||
|
||||
E14|||TDO||||||||||||
|
||||
E15||IOBM|IO_L34P_A13_M1WE_1|UNUSED||1|||||||||
|
||||
E16||IOBS|IO_L34N_A12_M1BA2_1|UNUSED||1|||||||||
|
||||
F1|FSB_A<27>|IOB|IO_L41N_GCLK26_M3DQ5_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
F2|FSB_A<25>|IOB|IO_L41P_GCLK27_M3DQ4_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
F3|nRESOE|IOB|IO_L53N_M3A12_3|OUTPUT|LVCMOS33|3|2|QUIETIO||||UNLOCATED|NO|NONE|
|
||||
F1|FSB_A<23>|IOB|IO_L41N_GCLK26_M3DQ5_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
F2|FSB_A<22>|IOB|IO_L41P_GCLK27_M3DQ4_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
F3||IOBS|IO_L53N_M3A12_3|UNUSED||3|||||||||
|
||||
F4||IOBM|IO_L53P_M3CKE_3|UNUSED||3|||||||||
|
||||
F5||IOBS|IO_L55N_M3A14_3|UNUSED||3|||||||||
|
||||
F6||IOBM|IO_L55P_M3A13_3|UNUSED||3|||||||||
|
||||
@ -115,12 +115,12 @@ F13||IOBM|IO_L32P_A17_M1A8_1|UNUSED||1|||||||||
|
||||
F14||IOBS|IO_L32N_A16_M1A9_1|UNUSED||1|||||||||
|
||||
F15||IOBM|IO_L35P_A11_M1A7_1|UNUSED||1|||||||||
|
||||
F16||IOBS|IO_L35N_A10_M1A2_1|UNUSED||1|||||||||
|
||||
G1|FSB_A<15>|IOB|IO_L40N_M3DQ7_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
G1|FSB_A<29>|IOB|IO_L40N_M3DQ7_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
G2|||GND||||||||||||
|
||||
G3|FSB_A<16>|IOB|IO_L40P_M3DQ6_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
G3|FSB_A<19>|IOB|IO_L40P_M3DQ6_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
G4|||VCCO_3|||3|||||3.30||||
|
||||
G5|CPUCLKIN|IOB|IO_L51N_M3A4_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
G6|CPU_nBERR|IOB|IO_L51P_M3A10_3|OUTPUT|LVCMOS33|3|2|SLOW||||UNLOCATED|YES|NONE|
|
||||
G5||IOBS|IO_L51N_M3A4_3|UNUSED||3|||||||||
|
||||
G6|CLKFB_OUT|IOB|IO_L51P_M3A10_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE|
|
||||
G7|||VCCINT||||||||1.2||||
|
||||
G8|||GND||||||||||||
|
||||
G9|||VCCINT||||||||1.2||||
|
||||
@ -131,11 +131,11 @@ G13|||VCCO_1|||1|||||any******||||
|
||||
G14||IOBM|IO_L36P_A9_M1BA0_1|UNUSED||1|||||||||
|
||||
G15|||GND||||||||||||
|
||||
G16||IOBS|IO_L36N_A8_M1BA1_1|UNUSED||1|||||||||
|
||||
H1|FSB_A<20>|IOB|IO_L39N_M3LDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H2|FSB_A<22>|IOB|IO_L39P_M3LDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H3|FSB_A<28>|IOB|IO_L44N_GCLK20_M3A6_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H1|FSB_A<26>|IOB|IO_L39N_M3LDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H2|FSB_A<25>|IOB|IO_L39P_M3LDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H3|CPU_nAS|IOB|IO_L44N_GCLK20_M3A6_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H4|CLKFB_IN|IOB|IO_L44P_GCLK21_M3A5_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H5|FSB_A<19>|IOB|IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H5|FSB_A<30>|IOB|IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
H6|||VCCAUX||||||||2.5||||
|
||||
H7|||GND||||||||||||
|
||||
H8|||VCCINT||||||||1.2||||
|
||||
@ -147,12 +147,12 @@ H13||IOBM|IO_L39P_M1A3_1|UNUSED||1|||||||||
|
||||
H14||IOBS|IO_L39N_M1ODT_1|UNUSED||1|||||||||
|
||||
H15||IOBM|IO_L37P_A7_M1A0_1|UNUSED||1|||||||||
|
||||
H16||IOBS|IO_L37N_A6_M1A1_1|UNUSED||1|||||||||
|
||||
J1|FSB_A<23>|IOB|IO_L38N_M3DQ3_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J1|FSB_A<17>|IOB|IO_L38N_M3DQ3_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J2|||VCCO_3|||3|||||3.30||||
|
||||
J3|FSB_A<17>|IOB|IO_L38P_M3DQ2_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J3|FSB_A<16>|IOB|IO_L38P_M3DQ2_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J4|CLKIN|IOB|IO_L42N_GCLK24_M3LDM_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J5|||GND||||||||||||
|
||||
J6|FSB_A<26>|IOB|IO_L43P_GCLK23_M3RASN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J6|FSB_A<21>|IOB|IO_L43P_GCLK23_M3RASN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
J7|||VCCINT||||||||1.2||||
|
||||
J8|||GND||||||||||||
|
||||
J9|||VCCINT||||||||1.2||||
|
||||
@ -163,12 +163,12 @@ J13||IOBM|IO_L41P_GCLK9_IRDY1_M1RASN_1|UNUSED||1|||||||||
|
||||
J14||IOBM|IO_L43P_GCLK5_M1DQ4_1|UNUSED||1|||||||||
|
||||
J15|||VCCO_1|||1|||||any******||||
|
||||
J16||IOBS|IO_L43N_GCLK4_M1DQ5_1|UNUSED||1|||||||||
|
||||
K1|FSB_A<21>|IOB|IO_L37N_M3DQ1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K2|FSB_A<24>|IOB|IO_L37P_M3DQ0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K3|FSB_A<18>|IOB|IO_L42P_GCLK25_TRDY2_M3UDM_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K1|FSB_A<5>|IOB|IO_L37N_M3DQ1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K2|FSB_A<14>|IOB|IO_L37P_M3DQ0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K3|FSB_A<28>|IOB|IO_L42P_GCLK25_TRDY2_M3UDM_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K4|||VCCO_3|||3|||||3.30||||
|
||||
K5|FSB_FC<0>|IOB|IO_L47P_M3A0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K6|FSB_FC<1>|IOB|IO_L47N_M3A1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K5|CPUCLKi|IOB|IO_L47P_M3A0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K6|FSB_A<18>|IOB|IO_L47N_M3A1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
K7|||GND||||||||||||
|
||||
K8|||VCCINT||||||||1.2||||
|
||||
K9|||GND||||||||||||
|
||||
@ -179,11 +179,11 @@ K13|||VCCO_1|||1|||||any******||||
|
||||
K14||IOBS|IO_L41N_GCLK8_M1CASN_1|UNUSED||1|||||||||
|
||||
K15||IOBM|IO_L44P_A3_M1DQ6_1|UNUSED||1|||||||||
|
||||
K16||IOBS|IO_L44N_A2_M1DQ7_1|UNUSED||1|||||||||
|
||||
L1|FSB_A<14>|IOB|IO_L36N_M3DQ9_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L1|FSB_A<11>|IOB|IO_L36N_M3DQ9_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L2|||GND||||||||||||
|
||||
L3|FSB_A<13>|IOB|IO_L36P_M3DQ8_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L4|FSB_A<29>|IOB|IO_L45P_M3A3_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L5|FSB_A<30>|IOB|IO_L45N_M3ODT_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L3|FSB_A<4>|IOB|IO_L36P_M3DQ8_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L4|FSB_A<31>|IOB|IO_L45P_M3A3_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L5|FSB_A<20>|IOB|IO_L45N_M3ODT_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
L6|||VCCAUX||||||||2.5||||
|
||||
L7||IOBS|IO_L62N_D6_2|UNUSED||2|||||||||
|
||||
L8||IOBM|IO_L62P_D5_2|UNUSED||2|||||||||
|
||||
@ -195,11 +195,11 @@ L13||IOBS|IO_L53N_VREF_1|UNUSED||1|||||||||
|
||||
L14||IOBM|IO_L47P_FWE_B_M1DQ0_1|UNUSED||1|||||||||
|
||||
L15|||GND||||||||||||
|
||||
L16||IOBS|IO_L47N_LDC_M1DQ1_1|UNUSED||1|||||||||
|
||||
M1|FSB_A<12>|IOB|IO_L35N_M3DQ11_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M2|FSB_A<11>|IOB|IO_L35P_M3DQ10_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M3|FSB_A<2>|IOB|IO_L1N_VREF_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M4|FSB_A<1>|IOB|IO_L1P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M5|FSB_A<3>|IOB|IO_L2P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M1|FSB_A<1>|IOB|IO_L35N_M3DQ11_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M2|FSB_A<2>|IOB|IO_L35P_M3DQ10_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M3|FSB_A<6>|IOB|IO_L1N_VREF_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M4|FSB_A<8>|IOB|IO_L1P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M5|FSB_A<15>|IOB|IO_L2P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
M6||IOBM|IO_L64P_D8_2|UNUSED||2|||||||||
|
||||
M7||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2|||||||||
|
||||
M8|||GND||||||||||||
|
||||
@ -213,22 +213,22 @@ M15||IOBM|IO_L46P_FCS_B_M1DQ2_1|UNUSED||1|||||||||
|
||||
M16||IOBS|IO_L46N_FOE_B_M1DQ3_1|UNUSED||1|||||||||
|
||||
N1|FSB_A<10>|IOB|IO_L34N_M3UDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N2|||VCCO_3|||3|||||3.30||||
|
||||
N3|FSB_A<9>|IOB|IO_L34P_M3UDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N4|FSB_A<4>|IOB|IO_L2N_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N3|FSB_A<13>|IOB|IO_L34P_M3UDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N4|FSB_A<0>|IOB|IO_L2N_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
N5||IOBM|IO_L49P_D3_2|UNUSED||2|||||||||
|
||||
N6||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
|
||||
N7|||VCCO_2|||2|||||3.30||||
|
||||
N7|||VCCO_2|||2|||||any******||||
|
||||
N8||IOBS|IO_L29N_GCLK2_2|UNUSED||2|||||||||
|
||||
N9||IOBM|IO_L14P_D11_2|UNUSED||2|||||||||
|
||||
N10|||VCCO_2|||2|||||3.30||||
|
||||
N10|||VCCO_2|||2|||||any******||||
|
||||
N11||IOBM|IO_L13P_M1_2|UNUSED||2|||||||||
|
||||
N12||IOBM|IO_L12P_D1_MISO2_2|UNUSED||2|||||||||
|
||||
N13|||GND||||||||||||
|
||||
N14||IOBM|IO_L45P_A1_M1LDQS_1|UNUSED||1|||||||||
|
||||
N15|||VCCO_1|||1|||||any******||||
|
||||
N16||IOBS|IO_L45N_A0_M1LDQSN_1|UNUSED||1|||||||||
|
||||
P1|FSB_A<8>|IOB|IO_L33N_M3DQ13_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
P2|FSB_A<7>|IOB|IO_L33P_M3DQ12_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
P1|FSB_A<7>|IOB|IO_L33N_M3DQ13_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
P2|FSB_A<12>|IOB|IO_L33P_M3DQ12_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
P3|||GND||||||||||||
|
||||
P4||IOBM|IO_L63P_2|UNUSED||2|||||||||
|
||||
P5||IOBS|IO_L49N_D4_2|UNUSED||2|||||||||
|
||||
@ -243,14 +243,14 @@ P13|||DONE_2||||||||||||
|
||||
P14|||SUSPEND||||||||||||
|
||||
P15||IOBM|IO_L48P_HDC_M1DQ8_1|UNUSED||1|||||||||
|
||||
P16||IOBS|IO_L48N_M1DQ9_1|UNUSED||1|||||||||
|
||||
R1|FSB_A<6>|IOB|IO_L32N_M3DQ15_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
R2|FSB_A<5>|IOB|IO_L32P_M3DQ14_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
R1|FSB_A<9>|IOB|IO_L32N_M3DQ15_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
R2|FSB_A<3>|IOB|IO_L32P_M3DQ14_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE|
|
||||
R3||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
|
||||
R4|||VCCO_2|||2|||||3.30||||
|
||||
R4|||VCCO_2|||2|||||any******||||
|
||||
R5||IOBM|IO_L48P_D7_2|UNUSED||2|||||||||
|
||||
R6|||GND||||||||||||
|
||||
R7|IOB_nHALT|IOB|IO_L32P_GCLK29_2|INPUT|LVCMOS33|2||||NONE||UNLOCATED|YES|NONE|
|
||||
R8|||VCCO_2|||2|||||3.30||||
|
||||
R7||IOBM|IO_L32P_GCLK29_2|UNUSED||2|||||||||
|
||||
R8|||VCCO_2|||2|||||any******||||
|
||||
R9||IOBM|IO_L23P_2|UNUSED||2|||||||||
|
||||
R10|||GND||||||||||||
|
||||
R11||IOBM|IO_L1P_CCLK_2|UNUSED||2|||||||||
|
||||
@ -265,7 +265,7 @@ T3||IOBS|IO_L65N_CSO_B_2|UNUSED||2|||||||||
|
||||
T4||IOBS|IO_L63N_2|UNUSED||2|||||||||
|
||||
T5||IOBS|IO_L48N_RDWR_B_VREF_2|UNUSED||2|||||||||
|
||||
T6||IOBS|IO_L47N_2|UNUSED||2|||||||||
|
||||
T7|FPUCLK|IOB|IO_L32N_GCLK28_2|OUTPUT|LVCMOS33|2|24|FAST||||UNLOCATED|YES|NONE|
|
||||
T7||IOBS|IO_L32N_GCLK28_2|UNUSED||2|||||||||
|
||||
T8||IOBS|IO_L30N_GCLK0_USERCCLK_2|UNUSED||2|||||||||
|
||||
T9||IOBS|IO_L23N_2|UNUSED||2|||||||||
|
||||
T10||IOBS|IO_L3N_MOSI_CSI_B_MISO0_2|UNUSED||2|||||||||
|
||||
|
||||
215
fpga/WarpLC.par
215
fpga/WarpLC.par
@ -1,7 +1,7 @@
|
||||
Release 14.7 par P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
ZANEPC:: Fri Oct 29 10:03:03 2021
|
||||
ZANEPC:: Fri Oct 29 17:59:50 2021
|
||||
|
||||
par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
|
||||
|
||||
@ -35,30 +35,30 @@ Device speed data version: "PRODUCTION 1.23 2013-10-13".
|
||||
Device Utilization Summary:
|
||||
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 56 out of 11,440 1%
|
||||
Number used as Flip Flops: 56
|
||||
Number of Slice Registers: 34 out of 11,440 1%
|
||||
Number used as Flip Flops: 34
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 59 out of 5,720 1%
|
||||
Number used as logic: 56 out of 5,720 1%
|
||||
Number using O6 output only: 24
|
||||
Number using O5 output only: 29
|
||||
Number using O5 and O6: 3
|
||||
Number of Slice LUTs: 17 out of 5,720 1%
|
||||
Number used as logic: 13 out of 5,720 1%
|
||||
Number using O6 output only: 11
|
||||
Number using O5 output only: 0
|
||||
Number using O5 and O6: 2
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 0 out of 1,440 0%
|
||||
Number used exclusively as route-thrus: 3
|
||||
Number with same-slice register load: 2
|
||||
Number with same-slice carry load: 1
|
||||
Number used exclusively as route-thrus: 4
|
||||
Number with same-slice register load: 4
|
||||
Number with same-slice carry load: 0
|
||||
Number with other load: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 25 out of 1,430 1%
|
||||
Number of MUXCYs used: 56 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 76
|
||||
Number with an unused Flip Flop: 22 out of 76 28%
|
||||
Number with an unused LUT: 17 out of 76 22%
|
||||
Number of fully used LUT-FF pairs: 37 out of 76 48%
|
||||
Number of occupied Slices: 11 out of 1,430 1%
|
||||
Number of MUXCYs used: 12 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 41
|
||||
Number with an unused Flip Flop: 11 out of 41 26%
|
||||
Number with an unused LUT: 24 out of 41 58%
|
||||
Number of fully used LUT-FF pairs: 6 out of 41 14%
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 0 out of 11,440 0%
|
||||
|
||||
@ -69,9 +69,8 @@ Slice Logic Distribution:
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 49 out of 186 26%
|
||||
Number of bonded IOBs: 43 out of 186 23%
|
||||
IOB Flip Flops: 5
|
||||
IOB Latches: 1
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 0 out of 32 0%
|
||||
@ -82,13 +81,11 @@ Specific Feature Utilization:
|
||||
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2FBs: 1
|
||||
Number used as BUFIO2FB_2CLKs: 0
|
||||
Number of BUFG/BUFGMUXs: 3 out of 16 18%
|
||||
Number used as BUFGs: 3
|
||||
Number of BUFG/BUFGMUXs: 2 out of 16 12%
|
||||
Number used as BUFGs: 2
|
||||
Number used as BUFGMUX: 0
|
||||
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
|
||||
Number of ILOGIC2/ISERDES2s: 1 out of 200 1%
|
||||
Number used as ILOGIC2s: 1
|
||||
Number used as ISERDES2s: 0
|
||||
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
|
||||
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
|
||||
Number of OLOGIC2/OSERDES2s: 5 out of 200 2%
|
||||
Number used as OLOGIC2s: 5
|
||||
@ -116,23 +113,23 @@ Finished initial Timing Analysis. REAL time: 2 secs
|
||||
Starting Router
|
||||
|
||||
|
||||
Phase 1 : 315 unrouted; REAL time: 2 secs
|
||||
Phase 1 : 164 unrouted; REAL time: 2 secs
|
||||
|
||||
Phase 2 : 228 unrouted; REAL time: 2 secs
|
||||
Phase 2 : 120 unrouted; REAL time: 2 secs
|
||||
|
||||
Phase 3 : 98 unrouted; REAL time: 2 secs
|
||||
Phase 3 : 68 unrouted; REAL time: 2 secs
|
||||
|
||||
Phase 4 : 98 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
Phase 4 : 68 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs
|
||||
|
||||
Updating file: WarpLC.ncd with current fully routed design.
|
||||
|
||||
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
Phase 5 : 0 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs
|
||||
|
||||
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
Phase 6 : 0 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs
|
||||
|
||||
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
Phase 7 : 0 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs
|
||||
|
||||
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
Phase 8 : 0 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs
|
||||
|
||||
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
|
||||
|
||||
@ -156,14 +153,11 @@ Generating Clock Report
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
|instance_name/clkfb_ | | | | | |
|
||||
| bufg_out | BUFGMUX_X2Y3| No | 2 | 0.000 | 2.163 |
|
||||
|CLKGEN_inst/instance | | | | | |
|
||||
|_name/clkfb_bufg_out | | | | | |
|
||||
| | BUFGMUX_X3Y13| No | 2 | 0.000 | 2.077 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| CPUCLKi | BUFGMUX_X3Y13| No | 3 | 0.633 | 2.069 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| FSBCLK | BUFGMUX_X2Y2| No | 21 | 0.728 | 2.163 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| LE | Local| | 2 | 0.000 | 0.979 |
|
||||
| FSBCLK | BUFGMUX_X2Y3| No | 17 | 0.700 | 2.135 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
|
||||
* Net Skew is the difference between the minimum and maximum routing
|
||||
@ -185,20 +179,123 @@ Asterisk (*) preceding a constraint indicates it was not met.
|
||||
Constraint | Check | Worst Case | Best Case | Timing | Timing
|
||||
| | Slack | Achievable | Errors | Score
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
PERIOD analysis for net "instance_name/cl | SETUP | 1.459ns| 7.082ns| 0| 0
|
||||
kout1" derived from NET "instance_name/c | HOLD | 4.848ns| | 0| 0
|
||||
lkin1" PERIOD = 20 ns HIGH 50% | | | | |
|
||||
COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 1 | SETUP | 1.520ns| 10.480ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.772ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
PERIOD analysis for net "instance_name/cl | SETUP | 5.303ns| 4.697ns| 0| 0
|
||||
kout0" derived from NET "instance_name/c | HOLD | 0.414ns| | 0| 0
|
||||
lkin1" PERIOD = 20 ns HIGH 50% | | | | |
|
||||
COMP "FSB_A<27>" OFFSET = IN 12 ns VALID | SETUP | 1.666ns| 10.334ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.698ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns | MINLOWPULSE | 15.000ns| 5.000ns| 0| 0
|
||||
HIGH 50% | | | | |
|
||||
COMP "INt" OFFSET = IN 12 ns VALID 12 ns | SETUP | 1.668ns| 10.332ns| 0| 0
|
||||
BEFORE COMP "CLKIN" | HOLD | 4.292ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
PERIOD analysis for net "instance_name/cl | MINPERIOD | 17.334ns| 2.666ns| 0| 0
|
||||
kfbout" derived from NET "instance_name/ | | | | |
|
||||
clkin1" PERIOD = 20 ns HIGH 50% | | | | |
|
||||
COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 1 | SETUP | 1.713ns| 10.287ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.756ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<21>" OFFSET = IN 12 ns VALID | SETUP | 1.725ns| 10.275ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.718ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<28>" OFFSET = IN 12 ns VALID | SETUP | 1.739ns| 10.261ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.510ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<31>" OFFSET = IN 12 ns VALID | SETUP | 1.753ns| 10.247ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.707ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<15>" OFFSET = IN 12 ns VALID | SETUP | 1.904ns| 10.096ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.834ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<20>" OFFSET = IN 12 ns VALID | SETUP | 1.936ns| 10.064ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.578ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 1 | SETUP | 1.972ns| 10.028ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.706ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<24>" OFFSET = IN 12 ns VALID | SETUP | 1.974ns| 10.026ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.679ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<13>" OFFSET = IN 12 ns VALID | SETUP | 1.989ns| 10.011ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.709ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 1 | SETUP | 1.991ns| 10.009ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.618ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<19>" OFFSET = IN 12 ns VALID | SETUP | 2.005ns| 9.995ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.722ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.081ns| 9.919ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.621ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<22>" OFFSET = IN 12 ns VALID | SETUP | 2.093ns| 9.907ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.637ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<25>" OFFSET = IN 12 ns VALID | SETUP | 2.117ns| 9.883ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.244ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.124ns| 9.876ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.242ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<18>" OFFSET = IN 12 ns VALID | SETUP | 2.132ns| 9.868ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.829ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<29>" OFFSET = IN 12 ns VALID | SETUP | 2.136ns| 9.864ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.448ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<30>" OFFSET = IN 12 ns VALID | SETUP | 2.153ns| 9.847ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.725ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.158ns| 9.842ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.237ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<12>" OFFSET = IN 12 ns VALID | SETUP | 2.179ns| 9.821ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.605ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.234ns| 9.766ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.288ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.243ns| 9.757ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.464ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<23>" OFFSET = IN 12 ns VALID | SETUP | 2.263ns| 9.737ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.472ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<26>" OFFSET = IN 12 ns VALID | SETUP | 2.343ns| 9.657ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.292ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 | SETUP | 2.359ns| 9.641ns| 0| 0
|
||||
ns BEFORE COMP "CLKIN" | HOLD | 3.896ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<16>" OFFSET = IN 12 ns VALID | SETUP | 2.435ns| 9.565ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.493ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<10>" OFFSET = IN 12 ns VALID | SETUP | 2.438ns| 9.562ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.463ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<11>" OFFSET = IN 12 ns VALID | SETUP | 2.478ns| 9.522ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.200ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.735ns| 9.265ns| 0| 0
|
||||
2 ns BEFORE COMP "CLKIN" | HOLD | 3.204ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<17>" OFFSET = IN 12 ns VALID | SETUP | 2.739ns| 9.261ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.474ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "FSB_A<14>" OFFSET = IN 12 ns VALID | SETUP | 2.916ns| 9.084ns| 0| 0
|
||||
12 ns BEFORE COMP "CLKIN" | HOLD | 3.242ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP | MAXDELAY | 2.960ns| 2.040ns| 0| 0
|
||||
"CLKIN" | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
PERIOD analysis for net "CLKGEN_inst/inst | SETUP | 12.300ns| 2.700ns| 0| 0
|
||||
ance_name/clkout0" derived from NET "CLK | HOLD | 0.457ns| | 0| 0
|
||||
GEN_inst/instance_name/clkin1" PERIOD = 3 | | | | |
|
||||
0 ns HIGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
NET "CLKGEN_inst/instance_name/clkin1" PE | MINLOWPULSE | 20.000ns| 10.000ns| 0| 0
|
||||
RIOD = 30 ns HIGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
PERIOD analysis for net "CLKGEN_inst/inst | MINPERIOD | 27.334ns| 2.666ns| 0| 0
|
||||
ance_name/clkfbout" derived from NET "CL | | | | |
|
||||
KGEN_inst/instance_name/clkin1" PERIOD = | | | | |
|
||||
30 ns HIGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@ -206,16 +303,18 @@ Derived Constraint Report
|
||||
Review Timing Report for more details on the following derived constraints.
|
||||
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
|
||||
or "Run Timing Analysis" from Timing Analyzer (timingan).
|
||||
Derived Constraints for instance_name/clkin1
|
||||
Derived Constraints for CLKGEN_inst/instance_name/clkin1
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
| | Period | Actual Period | Timing Errors | Paths Analyzed |
|
||||
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|
||||
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|instance_name/clkin1 | 20.000ns| 5.000ns| 14.164ns| 0| 0| 0| 57|
|
||||
| instance_name/clkfbout | 20.000ns| 2.666ns| N/A| 0| 0| 0| 0|
|
||||
| instance_name/clkout1 | 10.000ns| 7.082ns| N/A| 0| 0| 3| 0|
|
||||
| instance_name/clkout0 | 10.000ns| 4.697ns| N/A| 0| 0| 54| 0|
|
||||
|CLKGEN_inst/instance_name/clkin| 30.000ns| 10.000ns| 5.400ns| 0| 0| 0| 35|
|
||||
|1 | | | | | | | |
|
||||
| CLKGEN_inst/instance_name/clko| 15.000ns| 2.700ns| N/A| 0| 0| 35| 0|
|
||||
| ut0 | | | | | | | |
|
||||
| CLKGEN_inst/instance_name/clkf| 30.000ns| 2.666ns| N/A| 0| 0| 0| 0|
|
||||
| bout | | | | | | | |
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|
||||
All constraints were met.
|
||||
@ -225,10 +324,10 @@ Generating Pad Report.
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
Total REAL time to PAR completion: 2 secs
|
||||
Total CPU time to PAR completion: 2 secs
|
||||
Total REAL time to PAR completion: 3 secs
|
||||
Total CPU time to PAR completion: 3 secs
|
||||
|
||||
Peak Memory Usage: 256 MB
|
||||
Peak Memory Usage: 257 MB
|
||||
|
||||
Placer: Placement generated during map.
|
||||
Routing: Completed - No errors found.
|
||||
|
||||
@ -1,9 +1,44 @@
|
||||
//! **************************************************************************
|
||||
// Written by: Map P.20131013 on Fri Oct 29 10:03:01 2021
|
||||
// Written by: Map P.20131013 on Fri Oct 29 17:59:48 2021
|
||||
//! **************************************************************************
|
||||
|
||||
SCHEMATIC START;
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%;
|
||||
COMP "FSB_A<31>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<30>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<29>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<28>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "INt" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
||||
COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP "CLKIN";
|
||||
BEL "CLKFB_OUT" FEEDBACK = 0.16 ns BEL "CLKFB_IN";
|
||||
SCHEMATIC END;
|
||||
|
||||
|
||||
@ -1,2 +1,3 @@
|
||||
verilog work "ipcore_dir/CLK.v"
|
||||
verilog work "CLKGEN.v"
|
||||
verilog work "WarpLC.v"
|
||||
|
||||
File diff suppressed because one or more lines are too long
825
fpga/WarpLC.syr
825
fpga/WarpLC.syr
@ -110,6 +110,8 @@ Cores Search Directories : {"ipcore_dir" }
|
||||
=========================================================================
|
||||
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" into library work
|
||||
Parsing module <CLK>.
|
||||
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\CLKGEN.v" into library work
|
||||
Parsing module <CLKGEN>.
|
||||
Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" into library work
|
||||
Parsing module <WarpLC>.
|
||||
|
||||
@ -119,25 +121,28 @@ Parsing module <WarpLC>.
|
||||
|
||||
Elaborating module <WarpLC>.
|
||||
|
||||
Elaborating module <CLKGEN>.
|
||||
|
||||
Elaborating module <CLK>.
|
||||
|
||||
Elaborating module <IBUFG>.
|
||||
|
||||
Elaborating module <BUFIO2FB(DIVIDE_BYPASS="TRUE")>.
|
||||
|
||||
Elaborating module <PLL_BASE(BANDWIDTH="OPTIMIZED",CLK_FEEDBACK="CLKFBOUT",COMPENSATION="EXTERNAL",DIVCLK_DIVIDE=1,CLKFBOUT_MULT=12,CLKFBOUT_PHASE=0.0,CLKOUT0_DIVIDE=6,CLKOUT0_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,CLKOUT1_DIVIDE=6,CLKOUT1_PHASE=0.0,CLKOUT1_DUTY_CYCLE=0.5,CLKIN_PERIOD=30.0,REF_JITTER=0.01)>.
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 133: Assignment to clkout2_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 134: Assignment to clkout3_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 135: Assignment to clkout4_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 136: Assignment to clkout5_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 137: Assignment to locked_unused ignored, since the identifier is never used
|
||||
Elaborating module <PLL_BASE(BANDWIDTH="OPTIMIZED",CLK_FEEDBACK="CLKFBOUT",COMPENSATION="EXTERNAL",DIVCLK_DIVIDE=1,CLKFBOUT_MULT=12,CLKFBOUT_PHASE=0.0,CLKOUT0_DIVIDE=6,CLKOUT0_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,CLKIN_PERIOD=30.0,REF_JITTER=0.008)>.
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 128: Assignment to clkout1_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 129: Assignment to clkout2_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 130: Assignment to clkout3_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 131: Assignment to clkout4_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 132: Assignment to clkout5_unused ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 133: Assignment to locked_unused ignored, since the identifier is never used
|
||||
|
||||
Elaborating module <BUFG>.
|
||||
|
||||
Elaborating module <ODDR2>.
|
||||
|
||||
Elaborating module <ODDR2(DDR_ALIGNMENT="NONE",INIT=1'b0,SRTYPE="SYNC")>.
|
||||
WARNING:HDLCompiler:413 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 352: Result of 31-bit expression is truncated to fit in 30-bit target.
|
||||
Elaborating module <ODDR2(DDR_ALIGNMENT="C0",INIT=1'b0,SRTYPE="ASYNC")>.
|
||||
WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 84: Assignment to CPUCLKr ignored, since the identifier is never used
|
||||
|
||||
=========================================================================
|
||||
* HDL Synthesis *
|
||||
@ -145,206 +150,53 @@ WARNING:HDLCompiler:413 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v
|
||||
|
||||
Synthesizing Unit <WarpLC>.
|
||||
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v".
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <FSB_FC>.
|
||||
Set property "DRIVE = 2" for signal <FSB_FC>.
|
||||
Set property "IOBDELAY = NONE" for signal <FSB_FC>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <FSB_A>.
|
||||
Set property "DRIVE = 2" for signal <FSB_A>.
|
||||
Set property "IOBDELAY = NONE" for signal <FSB_A>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <FSB_SIZ>.
|
||||
Set property "IOBDELAY = NONE" for signal <FSB_SIZ>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAM_BA>.
|
||||
Set property "DRIVE = 24" for signal <RAM_BA>.
|
||||
Set property "SLOW = FALSE" for signal <RAM_BA>.
|
||||
Set property "FAST = TRUE" for signal <RAM_BA>.
|
||||
Set property "SLEW = FAST" for signal <RAM_BA>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAM_A>.
|
||||
Set property "DRIVE = 24" for signal <RAM_A>.
|
||||
Set property "SLOW = FALSE" for signal <RAM_A>.
|
||||
Set property "FAST = TRUE" for signal <RAM_A>.
|
||||
Set property "SLEW = FAST" for signal <RAM_A>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAM_DQM>.
|
||||
Set property "DRIVE = 24" for signal <RAM_DQM>.
|
||||
Set property "SLOW = FALSE" for signal <RAM_DQM>.
|
||||
Set property "FAST = TRUE" for signal <RAM_DQM>.
|
||||
Set property "SLEW = FAST" for signal <RAM_DQM>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <IOB_A>.
|
||||
Set property "DRIVE = 2" for signal <IOB_A>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <IOB_SIZ>.
|
||||
Set property "DRIVE = 2" for signal <IOB_SIZ>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <IOB_nDSACK>.
|
||||
Set property "IOBDELAY = NONE" for signal <IOB_nDSACK>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <FSB_RnW>.
|
||||
Set property "DRIVE = 2" for signal <FSB_RnW>.
|
||||
Set property "IOBDELAY = NONE" for signal <FSB_RnW>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nCIOUT>.
|
||||
Set property "IOBDELAY = NONE" for signal <CPU_nCIOUT>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nAOE>.
|
||||
Set property "DRIVE = 2" for signal <CPU_nAOE>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nECS>.
|
||||
Set property "IOBDELAY = NONE" for signal <CPU_nECS>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nAS>.
|
||||
Set property "IOBDELAY = NONE" for signal <CPU_nAS>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nDS>.
|
||||
Set property "IOBDELAY = NONE" for signal <CPU_nDS>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nCBREQ>.
|
||||
Set property "IOBDELAY = NONE" for signal <CPU_nCBREQ>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nDSACK>.
|
||||
Set property "DRIVE = 24" for signal <CPU_nDSACK>.
|
||||
Set property "SLOW = FALSE" for signal <CPU_nDSACK>.
|
||||
Set property "FAST = TRUE" for signal <CPU_nDSACK>.
|
||||
Set property "SLEW = FAST" for signal <CPU_nDSACK>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nDSACKOE>.
|
||||
Set property "DRIVE = 24" for signal <CPU_nDSACKOE>.
|
||||
Set property "SLOW = FALSE" for signal <CPU_nDSACKOE>.
|
||||
Set property "FAST = TRUE" for signal <CPU_nDSACKOE>.
|
||||
Set property "SLEW = FAST" for signal <CPU_nDSACKOE>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nDOE>.
|
||||
Set property "DRIVE = 24" for signal <CPU_nDOE>.
|
||||
Set property "SLOW = FALSE" for signal <CPU_nDOE>.
|
||||
Set property "FAST = TRUE" for signal <CPU_nDOE>.
|
||||
Set property "SLEW = FAST" for signal <CPU_nDOE>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_DDIR>.
|
||||
Set property "DRIVE = 24" for signal <CPU_DDIR>.
|
||||
Set property "SLOW = FALSE" for signal <CPU_DDIR>.
|
||||
Set property "FAST = TRUE" for signal <CPU_DDIR>.
|
||||
Set property "IOB = FORCE" for signal <CPUCLK>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <INt>.
|
||||
Set property "IOBDELAY = NONE" for signal <INt>.
|
||||
Set property "IOB = FALSE" for signal <OUTt>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <OUTt>.
|
||||
Set property "DRIVE = 24" for signal <OUTt>.
|
||||
Set property "SLEW = FAST" for signal <OUTt>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPUCLK>.
|
||||
Set property "DRIVE = 24" for signal <CPUCLK>.
|
||||
Set property "SLOW = FALSE" for signal <CPUCLK>.
|
||||
Set property "FAST = TRUE" for signal <CPUCLK>.
|
||||
Set property "SLEW = FAST" for signal <CPUCLK>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPUCLKIN>.
|
||||
Set property "IOBDELAY = NONE" for signal <CPUCLKIN>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CLKIN>.
|
||||
Set property "IOBDELAY = NONE" for signal <CLKIN>.
|
||||
Set property "IOB = FORCE" for signal <FPUCLK>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <FPUCLK>.
|
||||
Set property "DRIVE = 24" for signal <FPUCLK>.
|
||||
Set property "SLOW = FALSE" for signal <FPUCLK>.
|
||||
Set property "FAST = TRUE" for signal <FPUCLK>.
|
||||
Set property "SLEW = FAST" for signal <FPUCLK>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <nFPUCS>.
|
||||
Set property "DRIVE = 24" for signal <nFPUCS>.
|
||||
Set property "SLOW = FALSE" for signal <nFPUCS>.
|
||||
Set property "FAST = TRUE" for signal <nFPUCS>.
|
||||
Set property "SLEW = FAST" for signal <nFPUCS>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nSTERM>.
|
||||
Set property "DRIVE = 24" for signal <CPU_nSTERM>.
|
||||
Set property "SLOW = FALSE" for signal <CPU_nSTERM>.
|
||||
Set property "FAST = TRUE" for signal <CPU_nSTERM>.
|
||||
Set property "SLEW = FAST" for signal <CPU_nSTERM>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nCBACK>.
|
||||
Set property "DRIVE = 24" for signal <CPU_nCBACK>.
|
||||
Set property "SLOW = FALSE" for signal <CPU_nCBACK>.
|
||||
Set property "FAST = TRUE" for signal <CPU_nCBACK>.
|
||||
Set property "SLEW = FAST" for signal <CPU_nCBACK>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nCIIN>.
|
||||
Set property "DRIVE = 24" for signal <CPU_nCIIN>.
|
||||
Set property "SLOW = FALSE" for signal <CPU_nCIIN>.
|
||||
Set property "FAST = TRUE" for signal <CPU_nCIIN>.
|
||||
Set property "SLEW = FAST" for signal <CPU_nCIIN>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nHALT>.
|
||||
Set property "DRIVE = 2" for signal <CPU_nHALT>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nBERR>.
|
||||
Set property "DRIVE = 2" for signal <CPU_nBERR>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAM_nCS>.
|
||||
Set property "DRIVE = 24" for signal <RAM_nCS>.
|
||||
Set property "SLOW = FALSE" for signal <RAM_nCS>.
|
||||
Set property "FAST = TRUE" for signal <RAM_nCS>.
|
||||
Set property "SLEW = FAST" for signal <RAM_nCS>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAM_nRAS>.
|
||||
Set property "DRIVE = 24" for signal <RAM_nRAS>.
|
||||
Set property "SLOW = FALSE" for signal <RAM_nRAS>.
|
||||
Set property "FAST = TRUE" for signal <RAM_nRAS>.
|
||||
Set property "SLEW = FAST" for signal <RAM_nRAS>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAM_nCAS>.
|
||||
Set property "DRIVE = 24" for signal <RAM_nCAS>.
|
||||
Set property "SLOW = FALSE" for signal <RAM_nCAS>.
|
||||
Set property "FAST = TRUE" for signal <RAM_nCAS>.
|
||||
Set property "SLEW = FAST" for signal <RAM_nCAS>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAM_nWE>.
|
||||
Set property "DRIVE = 24" for signal <RAM_nWE>.
|
||||
Set property "SLOW = FALSE" for signal <RAM_nWE>.
|
||||
Set property "FAST = TRUE" for signal <RAM_nWE>.
|
||||
Set property "SLEW = FAST" for signal <RAM_nWE>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAM_CKE>.
|
||||
Set property "DRIVE = 24" for signal <RAM_CKE>.
|
||||
Set property "SLOW = FALSE" for signal <RAM_CKE>.
|
||||
Set property "FAST = TRUE" for signal <RAM_CKE>.
|
||||
Set property "SLEW = FAST" for signal <RAM_CKE>.
|
||||
Set property "IOB = FORCE" for signal <RAM_CLK01>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAM_CLK01>.
|
||||
Set property "DRIVE = 24" for signal <RAM_CLK01>.
|
||||
Set property "SLOW = FALSE" for signal <RAM_CLK01>.
|
||||
Set property "FAST = TRUE" for signal <RAM_CLK01>.
|
||||
Set property "SLEW = FAST" for signal <RAM_CLK01>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAM_CLK23>.
|
||||
Set property "DRIVE = 24" for signal <RAM_CLK23>.
|
||||
Set property "SLOW = FALSE" for signal <RAM_CLK23>.
|
||||
Set property "FAST = TRUE" for signal <RAM_CLK23>.
|
||||
Set property "SLEW = FAST" for signal <RAM_CLK23>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <IOB_nAOE>.
|
||||
Set property "DRIVE = 2" for signal <IOB_nAOE>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <IOB_ADoutLE>.
|
||||
Set property "DRIVE = 2" for signal <IOB_ADoutLE>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <IOB_nAS>.
|
||||
Set property "DRIVE = 2" for signal <IOB_nAS>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <IOB_nDS>.
|
||||
Set property "DRIVE = 2" for signal <IOB_nDS>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <IOB_nDOE>.
|
||||
Set property "DRIVE = 2" for signal <IOB_nDOE>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <IOB_DDIR>.
|
||||
Set property "DRIVE = 2" for signal <IOB_DDIR>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <nRESOE>.
|
||||
Set property "DRIVE = 2" for signal <nRESOE>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <nRES>.
|
||||
Set property "IOBDELAY = NONE" for signal <nRES>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <IOBCLK>.
|
||||
Set property "IOBDELAY = NONE" for signal <IOBCLK>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <IOB_nHALT>.
|
||||
Set property "IOBDELAY = NONE" for signal <IOB_nHALT>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <IOB_nBERR>.
|
||||
Set property "IOBDELAY = NONE" for signal <IOB_nBERR>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAMCLK0>.
|
||||
Set property "DRIVE = 24" for signal <RAMCLK0>.
|
||||
Set property "SLEW = FAST" for signal <RAMCLK0>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <RAMCLK1>.
|
||||
Set property "DRIVE = 24" for signal <RAMCLK1>.
|
||||
Set property "SLEW = FAST" for signal <RAMCLK1>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CPUCLKi>.
|
||||
Set property "IOBDELAY = NONE" for signal <CPUCLKi>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CLKIN>.
|
||||
Set property "IOBDELAY = NONE" for signal <CLKIN>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CLKFB_IN>.
|
||||
Set property "IOBDELAY = NONE" for signal <CLKFB_IN>.
|
||||
Set property "IOSTANDARD = LVCMOS33" for signal <CLKFB_OUT>.
|
||||
Set property "DRIVE = 24" for signal <CLKFB_OUT>.
|
||||
Set property "SLOW = FALSE" for signal <CLKFB_OUT>.
|
||||
Set property "FAST = TRUE" for signal <CLKFB_OUT>.
|
||||
Set property "SLEW = FAST" for signal <CLKFB_OUT>.
|
||||
Set property "IOB = FORCE" for signal <LHALT>.
|
||||
WARNING:Xst:647 - Input <FSB_A<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <FSB_SIZ> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <IOB_nDSACK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <CPU_nCIOUT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <CPU_nECS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <CPU_nDS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <CPU_nCBREQ> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <nRES> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <IOBCLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <IOB_nBERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
Found 1-bit register for signal <CPUCLKr1>.
|
||||
Found 1-bit register for signal <CPUCLK>.
|
||||
Found 1-bit register for signal <FPUCLK>.
|
||||
Found 30-bit register for signal <LastA>.
|
||||
Found 21-bit register for signal <LastAWR>.
|
||||
Found 1-bit register for signal <CPU_nSTERM>.
|
||||
Found 1-bit register for signal <nRESOE>.
|
||||
Found 1-bit register for signal <LE>.
|
||||
Found 1-bit register for signal <CPU_nBERR>.
|
||||
Found 1-bit register for signal <CPUCLKr0>.
|
||||
Found 30-bit adder for signal <FSB_A[31]_GND_1_o_add_6_OUT> created at line 352.
|
||||
WARNING:Xst:737 - Found 1-bit latch for signal <LHALT>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
||||
Found 30-bit comparator equal for signal <FSB_A[31]_LastA[31]_equal_4_o> created at line 347
|
||||
Found 31-bit comparator equal for signal <FSB_A[31]_GND_1_o_equal_5_o> created at line 347
|
||||
INFO:Xst:3210 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 79: Output port <CPUCLKr> of the instance <CLKGEN_inst> is unconnected or connected to loadless signal.
|
||||
Found 32-bit register for signal <AR>.
|
||||
Found 1-bit register for signal <OUTt>.
|
||||
Found 32-bit comparator equal for signal <FSB_A[31]_AR[31]_equal_2_o> created at line 92
|
||||
Summary:
|
||||
inferred 1 Adder/Subtractor(s).
|
||||
inferred 59 D-type flip-flop(s).
|
||||
inferred 1 Latch(s).
|
||||
inferred 2 Comparator(s).
|
||||
inferred 33 D-type flip-flop(s).
|
||||
inferred 1 Comparator(s).
|
||||
Unit <WarpLC> synthesized.
|
||||
|
||||
Synthesizing Unit <CLKGEN>.
|
||||
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\CLKGEN.v".
|
||||
Found 1-bit register for signal <CPUCLKr>.
|
||||
Summary:
|
||||
inferred 1 D-type flip-flop(s).
|
||||
Unit <CLKGEN> synthesized.
|
||||
|
||||
Synthesizing Unit <CLK>.
|
||||
Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v".
|
||||
Summary:
|
||||
@ -355,17 +207,11 @@ Unit <CLK> synthesized.
|
||||
HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Adders/Subtractors : 1
|
||||
30-bit adder : 1
|
||||
# Registers : 10
|
||||
1-bit register : 8
|
||||
21-bit register : 1
|
||||
30-bit register : 1
|
||||
# Latches : 1
|
||||
1-bit latch : 1
|
||||
# Comparators : 2
|
||||
30-bit comparator equal : 1
|
||||
31-bit comparator equal : 1
|
||||
# Registers : 3
|
||||
1-bit register : 2
|
||||
32-bit register : 1
|
||||
# Comparators : 1
|
||||
32-bit comparator equal : 1
|
||||
|
||||
=========================================================================
|
||||
|
||||
@ -378,13 +224,10 @@ Macro Statistics
|
||||
Advanced HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Adders/Subtractors : 1
|
||||
30-bit adder : 1
|
||||
# Registers : 59
|
||||
Flip-Flops : 59
|
||||
# Comparators : 2
|
||||
30-bit comparator equal : 1
|
||||
31-bit comparator equal : 1
|
||||
# Registers : 34
|
||||
Flip-Flops : 34
|
||||
# Comparators : 1
|
||||
32-bit comparator equal : 1
|
||||
|
||||
=========================================================================
|
||||
|
||||
@ -399,7 +242,7 @@ Optimizing unit <CLK> ...
|
||||
|
||||
Mapping all equations...
|
||||
Building and optimizing final netlist ...
|
||||
Found area constraint ratio of 100 (+ 5) on block WarpLC, actual ratio is 2.
|
||||
Found area constraint ratio of 100 (+ 5) on block WarpLC, actual ratio is 1.
|
||||
|
||||
Final Macro Processing ...
|
||||
|
||||
@ -407,8 +250,8 @@ Final Macro Processing ...
|
||||
Final Register Report
|
||||
|
||||
Macro Statistics
|
||||
# Registers : 59
|
||||
Flip-Flops : 59
|
||||
# Registers : 34
|
||||
Flip-Flops : 34
|
||||
|
||||
=========================================================================
|
||||
|
||||
@ -431,29 +274,23 @@ Top Level Output File Name : WarpLC.ngc
|
||||
|
||||
Primitive and Black Box Usage:
|
||||
------------------------------
|
||||
# BELS : 141
|
||||
# BELS : 29
|
||||
# GND : 1
|
||||
# INV : 6
|
||||
# LUT1 : 29
|
||||
# LUT2 : 3
|
||||
# LUT3 : 2
|
||||
# INV : 3
|
||||
# LUT3 : 1
|
||||
# LUT4 : 1
|
||||
# LUT6 : 20
|
||||
# MUXCY : 48
|
||||
# LUT6 : 10
|
||||
# MUXCY : 12
|
||||
# VCC : 1
|
||||
# XORCY : 30
|
||||
# FlipFlops/Latches : 62
|
||||
# FD : 7
|
||||
# FD_1 : 1
|
||||
# FDE : 51
|
||||
# LD_1 : 1
|
||||
# ODDR2 : 2
|
||||
# Clock Buffers : 3
|
||||
# BUFG : 3
|
||||
# IO Buffers : 49
|
||||
# IBUF : 38
|
||||
# FlipFlops/Latches : 39
|
||||
# FD : 34
|
||||
# ODDR2 : 5
|
||||
# Clock Buffers : 2
|
||||
# BUFG : 2
|
||||
# IO Buffers : 43
|
||||
# IBUF : 35
|
||||
# IBUFG : 2
|
||||
# OBUF : 9
|
||||
# OBUF : 6
|
||||
# Others : 2
|
||||
# BUFIO2FB : 1
|
||||
# PLL_ADV : 1
|
||||
@ -465,24 +302,23 @@ Selected Device : 6slx9ftg256-2
|
||||
|
||||
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 61 out of 11440 0%
|
||||
Number of Slice LUTs: 61 out of 5720 1%
|
||||
Number used as Logic: 61 out of 5720 1%
|
||||
Number of Slice Registers: 39 out of 11440 0%
|
||||
Number of Slice LUTs: 15 out of 5720 0%
|
||||
Number used as Logic: 15 out of 5720 0%
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of LUT Flip Flop pairs used: 114
|
||||
Number with an unused Flip Flop: 53 out of 114 46%
|
||||
Number with an unused LUT: 53 out of 114 46%
|
||||
Number of fully used LUT-FF pairs: 8 out of 114 7%
|
||||
Number of unique control sets: 5
|
||||
Number of LUT Flip Flop pairs used: 52
|
||||
Number with an unused Flip Flop: 13 out of 52 25%
|
||||
Number with an unused LUT: 37 out of 52 71%
|
||||
Number of fully used LUT-FF pairs: 2 out of 52 3%
|
||||
Number of unique control sets: 1
|
||||
|
||||
IO Utilization:
|
||||
Number of IOs: 170
|
||||
Number of bonded IOBs: 49 out of 186 26%
|
||||
IOB Flip Flops/Latches: 1
|
||||
Number of IOs: 43
|
||||
Number of bonded IOBs: 43 out of 186 23%
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of BUFG/BUFGCTRLs: 3 out of 16 18%
|
||||
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
|
||||
Number of PLL_ADVs: 1 out of 2 50%
|
||||
|
||||
---------------------------
|
||||
@ -503,15 +339,12 @@ NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
||||
|
||||
Clock Information:
|
||||
------------------
|
||||
------------------------------------+------------------------+-------+
|
||||
Clock Signal | Clock buffer(FF name) | Load |
|
||||
------------------------------------+------------------------+-------+
|
||||
instance_name/pll_base_inst/CLKOUT0 | BUFG | 58 |
|
||||
LE | NONE(LHALT) | 1 |
|
||||
instance_name/pll_base_inst/CLKOUT1 | BUFG | 3 |
|
||||
instance_name/pll_base_inst/CLKFBOUT| BUFG | 2 |
|
||||
------------------------------------+------------------------+-------+
|
||||
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
||||
------------------------------------------------+------------------------+-------+
|
||||
Clock Signal | Clock buffer(FF name) | Load |
|
||||
------------------------------------------------+------------------------+-------+
|
||||
CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 | BUFG | 42 |
|
||||
CLKGEN_inst/instance_name/pll_base_inst/CLKFBOUT| BUFG | 2 |
|
||||
------------------------------------------------+------------------------+-------+
|
||||
|
||||
Asynchronous Control Signals Information:
|
||||
----------------------------------------
|
||||
@ -521,483 +354,129 @@ Timing Summary:
|
||||
---------------
|
||||
Speed Grade: -2
|
||||
|
||||
Minimum period: 3.441ns (Maximum Frequency: 290.613MHz)
|
||||
Minimum input arrival time before clock: 4.574ns
|
||||
Maximum output required time after clock: 7.088ns
|
||||
Maximum combinational path delay: 8.227ns
|
||||
Minimum period: 2.580ns (Maximum Frequency: 387.597MHz)
|
||||
Minimum input arrival time before clock: 3.547ns
|
||||
Maximum output required time after clock: 4.118ns
|
||||
Maximum combinational path delay: 1.328ns
|
||||
|
||||
Timing Details:
|
||||
---------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default period analysis for Clock 'instance_name/pll_base_inst/CLKOUT0'
|
||||
Clock period: 3.441ns (frequency: 290.613MHz)
|
||||
Total number of paths / destination ports: 54 / 4
|
||||
Timing constraint: Default period analysis for Clock 'CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0'
|
||||
Clock period: 2.580ns (frequency: 387.597MHz)
|
||||
Total number of paths / destination ports: 35 / 4
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 3.441ns (Levels of Logic = 11)
|
||||
Source: LastAWR_13 (FF)
|
||||
Destination: CPU_nSTERM (FF)
|
||||
Source Clock: instance_name/pll_base_inst/CLKOUT0 rising
|
||||
Destination Clock: instance_name/pll_base_inst/CLKOUT0 rising
|
||||
Delay: 1.290ns (Levels of Logic = 0)
|
||||
Source: CLKGEN_inst/CPUCLKr (FF)
|
||||
Destination: CLKGEN_inst/FPUCLK_inst (FF)
|
||||
Source Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 rising
|
||||
Destination Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 falling
|
||||
|
||||
Data Path: LastAWR_13 to CPU_nSTERM
|
||||
Data Path: CLKGEN_inst/CPUCLKr to CLKGEN_inst/FPUCLK_inst
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FDE:C->Q 1 0.525 0.910 LastAWR_13 (LastAWR_13)
|
||||
LUT6:I3->O 1 0.235 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_lut<0> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_lut<0>)
|
||||
MUXCY:S->O 1 0.215 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<0> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<0>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<1> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<1>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<2> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<2>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<4> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<4>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<5> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<5>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<6> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<6>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7>)
|
||||
MUXCY:CI->O 2 0.235 0.834 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<8> (FSB_A[31]_GND_1_o_equal_5_o)
|
||||
LUT3:I1->O 1 0.250 0.000 CPU_nSTERM_rstpot1 (CPU_nSTERM_rstpot)
|
||||
FD:D 0.074 CPU_nSTERM
|
||||
FD:C->Q 3 0.525 0.765 CLKGEN_inst/CPUCLKr (CLKGEN_inst/CPUCLKr)
|
||||
ODDR2:D1 0.000 CLKGEN_inst/FPUCLK_inst
|
||||
----------------------------------------
|
||||
Total 3.441ns (1.697ns logic, 1.744ns route)
|
||||
(49.3% logic, 50.7% route)
|
||||
Total 1.290ns (0.525ns logic, 0.765ns route)
|
||||
(40.7% logic, 59.3% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default period analysis for Clock 'instance_name/pll_base_inst/CLKOUT1'
|
||||
Clock period: 2.648ns (frequency: 377.644MHz)
|
||||
Total number of paths / destination ports: 2 / 2
|
||||
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0'
|
||||
Total number of paths / destination ports: 67 / 33
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 1.324ns (Levels of Logic = 0)
|
||||
Source: CPUCLKr1 (FF)
|
||||
Destination: CPUCLK (FF)
|
||||
Source Clock: instance_name/pll_base_inst/CLKOUT1 falling
|
||||
Destination Clock: instance_name/pll_base_inst/CLKOUT1 rising
|
||||
Offset: 3.547ns (Levels of Logic = 14)
|
||||
Source: FSB_A<2> (PAD)
|
||||
Destination: OUTt (FF)
|
||||
Destination Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 rising
|
||||
|
||||
Data Path: CPUCLKr1 to CPUCLK
|
||||
Data Path: FSB_A<2> to OUTt
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FD_1:C->Q 2 0.525 0.725 CPUCLKr1 (CPUCLKr1)
|
||||
FD:D 0.074 CPUCLK
|
||||
IBUF:I->O 2 1.328 1.181 FSB_A_2_IBUF (FSB_A_2_IBUF)
|
||||
LUT6:I0->O 1 0.254 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0>)
|
||||
MUXCY:S->O 1 0.215 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<0> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<0>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<1> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<1>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<2> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<2>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<4> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<4>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<5> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<5>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<6> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<6>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<8> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<8>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<9> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<9>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<10> (FSB_A[31]_AR[31]_equal_2_o)
|
||||
MUXCY:CI->O 1 0.262 0.000 CPU_nAS_FSB_A[31]_AND_3_o1_cy (CPU_nAS_FSB_A[31]_AND_3_o)
|
||||
FD:D 0.074 OUTt
|
||||
----------------------------------------
|
||||
Total 1.324ns (0.599ns logic, 0.725ns route)
|
||||
(45.2% logic, 54.8% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET IN BEFORE for Clock 'instance_name/pll_base_inst/CLKOUT0'
|
||||
Total number of paths / destination ports: 650 / 103
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 4.574ns (Levels of Logic = 12)
|
||||
Source: FSB_A<3> (PAD)
|
||||
Destination: CPU_nSTERM (FF)
|
||||
Destination Clock: instance_name/pll_base_inst/CLKOUT0 rising
|
||||
|
||||
Data Path: FSB_A<3> to CPU_nSTERM
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 3 1.328 1.221 FSB_A_3_IBUF (FSB_A_3_IBUF)
|
||||
LUT6:I0->O 1 0.254 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_lut<0> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_lut<0>)
|
||||
MUXCY:S->O 1 0.215 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<0> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<0>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<1> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<1>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<2> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<2>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<3>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<4> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<4>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<5> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<5>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<6> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<6>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7> (Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<7>)
|
||||
MUXCY:CI->O 2 0.235 0.834 Mcompar_FSB_A[31]_GND_1_o_equal_5_o_cy<8> (FSB_A[31]_GND_1_o_equal_5_o)
|
||||
LUT3:I1->O 1 0.250 0.000 CPU_nSTERM_rstpot1 (CPU_nSTERM_rstpot)
|
||||
FD:D 0.074 CPU_nSTERM
|
||||
----------------------------------------
|
||||
Total 4.574ns (2.519ns logic, 2.055ns route)
|
||||
(55.1% logic, 44.9% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET IN BEFORE for Clock 'LE'
|
||||
Total number of paths / destination ports: 1 / 1
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 2.045ns (Levels of Logic = 1)
|
||||
Source: IOB_nHALT (PAD)
|
||||
Destination: LHALT (LATCH)
|
||||
Destination Clock: LE rising
|
||||
|
||||
Data Path: IOB_nHALT to LHALT
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 1 1.328 0.681 IOB_nHALT_IBUF (IOB_nHALT_IBUF)
|
||||
LD_1:D 0.036 LHALT
|
||||
----------------------------------------
|
||||
Total 2.045ns (1.364ns logic, 0.681ns route)
|
||||
Total 3.547ns (2.366ns logic, 1.181ns route)
|
||||
(66.7% logic, 33.3% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET OUT AFTER for Clock 'instance_name/pll_base_inst/CLKOUT0'
|
||||
Total number of paths / destination ports: 54 / 4
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 7.088ns (Levels of Logic = 13)
|
||||
Source: LastA_4 (FF)
|
||||
Destination: CPU_nDSACK (PAD)
|
||||
Source Clock: instance_name/pll_base_inst/CLKOUT0 rising
|
||||
|
||||
Data Path: LastA_4 to CPU_nDSACK
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FDE:C->Q 1 0.525 0.910 LastA_4 (LastA_4)
|
||||
LUT6:I3->O 1 0.235 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_lut<0> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_lut<0>)
|
||||
MUXCY:S->O 1 0.215 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<0> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<0>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<1> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<1>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<2> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<2>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<3> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<3>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<4> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<4>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<5> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<5>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<6> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<6>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<8> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<8>)
|
||||
MUXCY:CI->O 2 0.235 0.954 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<9> (FSB_A[31]_LastA[31]_equal_4_o)
|
||||
LUT3:I0->O 1 0.235 0.681 CPU_nDSACK1 (CPU_nDSACK_OBUF)
|
||||
OBUF:I->O 2.912 CPU_nDSACK_OBUF (CPU_nDSACK)
|
||||
----------------------------------------
|
||||
Total 7.088ns (4.543ns logic, 2.545ns route)
|
||||
(64.1% logic, 35.9% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET OUT AFTER for Clock 'instance_name/pll_base_inst/CLKOUT1'
|
||||
Total number of paths / destination ports: 2 / 2
|
||||
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0'
|
||||
Total number of paths / destination ports: 1 / 1
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 4.118ns (Levels of Logic = 1)
|
||||
Source: CPUCLK (FF)
|
||||
Destination: CPUCLK (PAD)
|
||||
Source Clock: instance_name/pll_base_inst/CLKOUT1 rising
|
||||
Source: OUTt (FF)
|
||||
Destination: OUTt (PAD)
|
||||
Source Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 rising
|
||||
|
||||
Data Path: CPUCLK to CPUCLK
|
||||
Data Path: OUTt to OUTt
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FD:C->Q 1 0.525 0.681 CPUCLK (CPUCLK_OBUF)
|
||||
OBUF:I->O 2.912 CPUCLK_OBUF (CPUCLK)
|
||||
FD:C->Q 1 0.525 0.681 OUTt (OUTt_OBUF)
|
||||
OBUF:I->O 2.912 OUTt_OBUF (OUTt)
|
||||
----------------------------------------
|
||||
Total 4.118ns (3.437ns logic, 0.681ns route)
|
||||
(83.5% logic, 16.5% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default path analysis
|
||||
Total number of paths / destination ports: 75 / 3
|
||||
Total number of paths / destination ports: 1 / 1
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 8.227ns (Levels of Logic = 11)
|
||||
Source: FSB_A<13> (PAD)
|
||||
Destination: CPU_nDSACK (PAD)
|
||||
Delay: 1.328ns (Levels of Logic = 1)
|
||||
Source: CLKFB_IN (PAD)
|
||||
Destination: CLKGEN_inst/instance_name/clkfb_bufio2fb:I (PAD)
|
||||
|
||||
Data Path: FSB_A<13> to CPU_nDSACK
|
||||
Data Path: CLKFB_IN to CLKGEN_inst/instance_name/clkfb_bufio2fb:I
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 5 1.328 1.296 FSB_A_13_IBUF (FSB_A_13_IBUF)
|
||||
LUT6:I0->O 1 0.254 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_lut<3> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_lut<3>)
|
||||
MUXCY:S->O 1 0.215 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<3> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<3>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<4> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<4>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<5> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<5>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<6> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<6>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<7>)
|
||||
MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<8> (Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<8>)
|
||||
MUXCY:CI->O 2 0.235 0.954 Mcompar_FSB_A[31]_LastA[31]_equal_4_o_cy<9> (FSB_A[31]_LastA[31]_equal_4_o)
|
||||
LUT3:I0->O 1 0.235 0.681 CPU_nDSACK1 (CPU_nDSACK_OBUF)
|
||||
OBUF:I->O 2.912 CPU_nDSACK_OBUF (CPU_nDSACK)
|
||||
IBUFG:I->O 0 1.328 0.000 CLKGEN_inst/instance_name/clkfb_ibufg (CLKGEN_inst/instance_name/clkfb_ibuf2bufio2fb)
|
||||
BUFIO2FB:I 0.000 CLKGEN_inst/instance_name/clkfb_bufio2fb
|
||||
----------------------------------------
|
||||
Total 8.227ns (5.296ns logic, 2.931ns route)
|
||||
(64.4% logic, 35.6% route)
|
||||
Total 1.328ns (1.328ns logic, 0.000ns route)
|
||||
(100.0% logic, 0.0% route)
|
||||
|
||||
=========================================================================
|
||||
|
||||
Cross Clock Domains Report:
|
||||
--------------------------
|
||||
|
||||
Clock to Setup on destination clock instance_name/pll_base_inst/CLKOUT0
|
||||
-----------------------------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
-----------------------------------+---------+---------+---------+---------+
|
||||
LE | 1.336| | | |
|
||||
instance_name/pll_base_inst/CLKOUT0| 3.441| | | |
|
||||
-----------------------------------+---------+---------+---------+---------+
|
||||
|
||||
Clock to Setup on destination clock instance_name/pll_base_inst/CLKOUT1
|
||||
-----------------------------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
-----------------------------------+---------+---------+---------+---------+
|
||||
instance_name/pll_base_inst/CLKOUT0| | | 1.324| |
|
||||
instance_name/pll_base_inst/CLKOUT1| | 1.324| | |
|
||||
-----------------------------------+---------+---------+---------+---------+
|
||||
Clock to Setup on destination clock CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0
|
||||
-----------------------------------------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
-----------------------------------------------+---------+---------+---------+---------+
|
||||
CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0| 2.454| | 1.290| |
|
||||
-----------------------------------------------+---------+---------+---------+---------+
|
||||
|
||||
=========================================================================
|
||||
WARNING:Xst:615 - Flip flop associated with net RAM_CLK01_OBUF not found, property IOB not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_FC<2> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_FC<1> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_FC<0> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<31> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<30> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<29> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<28> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<27> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<26> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<25> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<24> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<23> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<22> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<21> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<20> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<19> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<18> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<17> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<16> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<15> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<14> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<13> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<12> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<11> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<10> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<9> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<8> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<7> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<6> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<5> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<4> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<3> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<2> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<1> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_A<0> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_RnW not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<31> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<31> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<30> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<30> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<29> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<29> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<28> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<28> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<27> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<27> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<26> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<26> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<25> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<25> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<24> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<24> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<23> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<23> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<22> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<22> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<21> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<21> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<20> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<20> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<19> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<19> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<18> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<18> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<17> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<17> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<16> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<16> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<15> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<15> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<14> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<14> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<13> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<13> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<12> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<12> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<11> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<11> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<10> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<10> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<9> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<9> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<8> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<8> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<7> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<7> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<6> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<6> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<5> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<5> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<4> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<4> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<3> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<3> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<2> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<2> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<1> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<1> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<0> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_D<0> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_BA<1> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_BA<1> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_BA<0> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_BA<0> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<12> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<12> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<11> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<11> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<10> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<10> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<9> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<9> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<8> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<8> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<7> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<7> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<6> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<6> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<5> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<5> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<4> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<4> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<3> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<3> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<2> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<2> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<1> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<1> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<0> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_A<0> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_DQM<3> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_DQM<3> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_DQM<2> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_DQM<2> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_DQM<1> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_DQM<1> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_DQM<0> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_DQM<0> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_A<3> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_A<3> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_A<2> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_A<2> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_A<1> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_A<1> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_A<0> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_A<0> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_SIZ<1> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_SIZ<1> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_SIZ<0> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_SIZ<0> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<31> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<31> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<30> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<30> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<29> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<29> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<28> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<28> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<27> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<27> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<26> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<26> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<25> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<25> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<24> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<24> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<23> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<23> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<22> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<22> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<21> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<21> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<20> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<20> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<19> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<19> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<18> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<18> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<17> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<17> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<16> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<16> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<15> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<15> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<14> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<14> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<13> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<13> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<12> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<12> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<11> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<11> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<10> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<10> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<9> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<9> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<8> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<8> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<7> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<7> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<6> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<6> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<5> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<5> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<4> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<4> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<3> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<3> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<2> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<2> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<1> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<1> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<0> not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_D<0> not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_nRMC not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port FSB_nRMC not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_nAOE not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_nAOE not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_nDSACKOE not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_nDSACKOE not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_nDOE not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_nDOE not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_DDIR not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_DDIR not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_nCBACK not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_nCBACK not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_nCIIN not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_nCIIN not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_nHALT not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port CPU_nHALT not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_nCS not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_nCS not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_nRAS not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_nRAS not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_nCAS not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_nCAS not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_nWE not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_nWE not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_CKE not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_CKE not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_CLK23 not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port RAM_CLK23 not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_nAOE not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_nAOE not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_ADoutLE not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_ADoutLE not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_nAS not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_nAS not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_nDS not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_nDS not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_nDOE not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_nDOE not found, property DRIVE not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_DDIR not found, property IOSTANDARD not attached.
|
||||
WARNING:Xst:615 - Instance associated with port IOB_DDIR not found, property DRIVE not attached.
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 3.00 secs
|
||||
Total CPU time to Xst completion: 3.02 secs
|
||||
Total REAL time to Xst completion: 2.00 secs
|
||||
Total CPU time to Xst completion: 2.72 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 225340 kilobytes
|
||||
Total memory usage is 225148 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 272 ( 0 filtered)
|
||||
Number of warnings : 7 ( 0 filtered)
|
||||
Number of infos : 2 ( 0 filtered)
|
||||
|
||||
|
||||
9367
fpga/WarpLC.twr
9367
fpga/WarpLC.twr
File diff suppressed because it is too large
Load Diff
216
fpga/WarpLC.twx
216
fpga/WarpLC.twx
File diff suppressed because one or more lines are too long
@ -1,7 +1,7 @@
|
||||
Release 14.7 - par P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Fri Oct 29 10:03:06 2021
|
||||
Fri Oct 29 17:59:53 2021
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
353
fpga/WarpLC.v
353
fpga/WarpLC.v
@ -19,359 +19,78 @@
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module WarpLC(
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
inout [2:0] FSB_FC,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
inout [31:0] FSB_A,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
inout FSB_RnW,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
inout FSB_nRMC,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input [1:0] FSB_SIZ,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CPU_nCIOUT,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output CPU_nAOE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CPU_nECS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
(* IOBDELAY = "NONE" *)
|
||||
input CPU_nAS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CPU_nDS,
|
||||
(* IOBDELAY = "NONE" *)
|
||||
input [31:0] FSB_A,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CPU_nCBREQ,
|
||||
(* IOBDELAY = "NONE" *)
|
||||
input INt,
|
||||
|
||||
(* IOB = "FALSE" *)
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLEW = "FAST" *)
|
||||
output reg OUTt,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output CPU_nDSACK,
|
||||
(* SLEW = "FAST" *)
|
||||
output CPUCLK,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output CPU_nDSACKOE,
|
||||
(* SLEW = "FAST" *)
|
||||
output FPUCLK,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output CPU_nDOE,
|
||||
(* SLEW = "FAST" *)
|
||||
output RAMCLK0,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
output CPU_DDIR,
|
||||
(* SLEW = "FAST" *)
|
||||
output RAMCLK1,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
inout [31:0] FSB_D,
|
||||
|
||||
(* IOB = "FORCE" *)
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output reg CPUCLK,
|
||||
(* IOBDELAY = "NONE" *)
|
||||
input CPUCLKi,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input CPUCLKIN,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
(* IOBDELAY = "NONE" *)
|
||||
input CLKIN,
|
||||
|
||||
(* IOB = "FORCE" *)
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output reg FPUCLK,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output nFPUCS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output reg CPU_nSTERM,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output CPU_nCBACK,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output CPU_nCIIN,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output reg CPU_nHALT,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output reg CPU_nBERR,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_nCS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_nRAS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_nCAS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_nWE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_CKE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output [1:0] RAM_BA,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output [12:0] RAM_A,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output [3:0] RAM_DQM,
|
||||
|
||||
(* IOB = "FORCE" *)
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_CLK01,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
output RAM_CLK23,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output [3:0] IOB_A,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output [1:0] IOB_SIZ,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output IOB_nAOE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output IOB_ADoutLE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output IOB_nAS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output IOB_nDS,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input [1:0] IOB_nDSACK,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output IOB_nDOE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output IOB_DDIR,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
inout [31:0] IOB_D,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "2" *)
|
||||
output reg nRESOE,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input nRES,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input IOBCLK,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input IOB_nHALT,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
input IOB_nBERR,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* IOBDELAY ="NONE" *)
|
||||
(* IOBDELAY = "NONE" *)
|
||||
input CLKFB_IN,
|
||||
|
||||
(* IOSTANDARD = "LVCMOS33" *)
|
||||
(* DRIVE = "24" *)
|
||||
(* SLOW = "FALSE" *)
|
||||
(* FAST = "TRUE" *)
|
||||
(* SLEW="FAST" *)
|
||||
(* SLEW = "FAST" *)
|
||||
output CLKFB_OUT);
|
||||
|
||||
wire FSBCLK, CPUCLKi;
|
||||
CLK instance_name (
|
||||
wire FSBCLK;
|
||||
wire CPUCLKr;
|
||||
CLKGEN CLKGEN_inst(
|
||||
.CLKIN(CLKIN),
|
||||
.CLKFB_IN(CLKFB_IN),
|
||||
.CLKFB_OUT(CLKFB_OUT),
|
||||
.FSBCLK(FSBCLK),
|
||||
.CPUCLK(CPUCLKi),
|
||||
.CLKFB_OUT(CLKFB_OUT));
|
||||
.CPUCLKr(CPUCLKr),
|
||||
.CPUCLK(CPUCLK),
|
||||
.FPUCLK(FPUCLK),
|
||||
.RAMCLK0(RAMCLK0),
|
||||
.RAMCLK1(RAMCLK1));
|
||||
|
||||
reg CPUCLKr0 = 0;
|
||||
reg CPUCLKr1 = 0;
|
||||
reg CPUCLKd = 0;
|
||||
reg [31:0] AR;
|
||||
always @(posedge FSBCLK) begin
|
||||
CPUCLKr0 <= ~CPUCLKr0;
|
||||
end
|
||||
always @(negedge CPUCLKi) begin
|
||||
CPUCLKr1 <= CPUCLKr0;
|
||||
end
|
||||
always @(posedge CPUCLKi) begin
|
||||
CPUCLK <= CPUCLKr1;
|
||||
FPUCLK <= CPUCLKr1;
|
||||
end
|
||||
|
||||
wire RAM_CLK01_ODDR;
|
||||
assign RAM_CLK01 = RAM_CLK01_ODDR;
|
||||
ODDR2 #(
|
||||
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
||||
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
|
||||
.SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
|
||||
RAM_CLK01_ODDR_inst (
|
||||
.Q(RAM_CLK01_ODDR), // 1-bit DDR output data
|
||||
.C0(FSBCLK), // 1-bit clock input
|
||||
.C1(~FSBCLK), // 1-bit clock input
|
||||
.CE(1'b1), // 1-bit clock enable input
|
||||
.D0(1'b0), // 1-bit data input (associated with C0)
|
||||
.D1(1'b1), // 1-bit data input (associated with C1)
|
||||
.R(1'b0), // 1-bit reset input
|
||||
.S(1'b0)); // 1-bit set input
|
||||
|
||||
assign CPU_nDSACK = ~((FSB_A[31:2]==LastA[31:2] || FSB_A[31:1]==LastAWR[31:11]) && FSB_RnW);
|
||||
|
||||
reg [31:2] LastA;
|
||||
reg [31:11] LastAWR;
|
||||
always @(posedge FSBCLK) begin
|
||||
if (FSB_RnW && ~CPU_nAS) LastA[31:2] <= FSB_A[31:2] + 1;
|
||||
if (~FSB_RnW && ~CPU_nAS) LastAWR[31:11] <= FSB_A[31:11];
|
||||
CPU_nSTERM <= ~((FSB_A[31:2]==LastA[31:2] || FSB_A[31:1]==LastAWR[31:11]) && FSB_RnW);
|
||||
nRESOE <= ~nRESOE;
|
||||
end
|
||||
|
||||
wire FPUCS = FSB_FC[02:00]==3'h7 && FSB_A[19:16]==4'h2 && FSB_A[15:13]==3'h1;
|
||||
assign nFPUCS = ~((FPUCS && ~CPUCLKIN) || (FPUCS && ~CPU_nAS));
|
||||
|
||||
(* IOB = "FORCE" *)
|
||||
reg LHALT;
|
||||
reg LE;
|
||||
always @(posedge FSBCLK) begin
|
||||
LE <= ~LE;
|
||||
end
|
||||
always @(LE, IOB_nHALT) begin
|
||||
if (~LE) begin
|
||||
LHALT <= IOB_nHALT;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge FSBCLK) begin
|
||||
CPU_nBERR <= LHALT;
|
||||
OUTt <= ~CPU_nAS && INt && CPUCLKi && FSB_A[31:0]==AR[31:0];
|
||||
AR[31:0] <= FSB_A[31:0];
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
<files>
|
||||
<file xil_pn:name="WarpLC.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/CLK.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
|
||||
@ -26,6 +26,10 @@
|
||||
<file xil_pn:name="PLL.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="CLKGEN.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/CLK.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
|
||||
349
fpga/WarpLC_2021-10-29-10-29-11.twx
Normal file
349
fpga/WarpLC_2021-10-29-10-29-11.twx
Normal file
@ -0,0 +1,349 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE twReport [
|
||||
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
|
||||
twDebug*, twFoot?, twClientInfo?)>
|
||||
<!ATTLIST twReport version CDATA "10,4">
|
||||
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
|
||||
<!ELEMENT twExecVer (#PCDATA)>
|
||||
<!ELEMENT twCopyright (#PCDATA)>
|
||||
<!ELEMENT twCmdLine (#PCDATA)>
|
||||
<!ELEMENT twDesign (#PCDATA)>
|
||||
<!ELEMENT twPCF (#PCDATA)>
|
||||
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
|
||||
<!ELEMENT twDevName (#PCDATA)>
|
||||
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
|
||||
<!ELEMENT twSpeedGrade (#PCDATA)>
|
||||
<!ELEMENT twSpeedVer (#PCDATA)>
|
||||
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
|
||||
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
|
||||
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
|
||||
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
|
||||
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
|
||||
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twItemLimit (#PCDATA)>
|
||||
<!ELEMENT twUnconst EMPTY>
|
||||
<!ELEMENT twUnconstLimit (#PCDATA)>
|
||||
<!ELEMENT twEnvVar EMPTY>
|
||||
<!ATTLIST twEnvVar name CDATA #REQUIRED>
|
||||
<!ATTLIST twEnvVar description CDATA #REQUIRED>
|
||||
<!ELEMENT twWarn (#PCDATA)>
|
||||
<!ELEMENT twInfo (#PCDATA)>
|
||||
<!ELEMENT twDebug (#PCDATA)>
|
||||
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
|
||||
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
|
||||
<!ELEMENT twProc (#PCDATA)>
|
||||
<!ELEMENT twTemp (#PCDATA)>
|
||||
<!ELEMENT twVolt (#PCDATA)>
|
||||
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
|
||||
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
|
||||
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twCycles (twSigConn+)>
|
||||
<!ATTLIST twCycles twNum CDATA #REQUIRED>
|
||||
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
|
||||
<!ELEMENT twSig (#PCDATA)>
|
||||
<!ELEMENT twDriver (#PCDATA)>
|
||||
<!ELEMENT twLoad (#PCDATA)>
|
||||
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
|
||||
<!ATTLIST twConst twConstType (NET |
|
||||
NETDELAY |
|
||||
NETSKEW |
|
||||
PATH |
|
||||
DEFPERIOD |
|
||||
UNCONSTPATH |
|
||||
DEFPATH |
|
||||
PATH2SETUP |
|
||||
UNCONSTPATH2SETUP |
|
||||
PATHCLASS |
|
||||
PATHDELAY |
|
||||
PERIOD |
|
||||
FREQUENCY |
|
||||
PATHBLOCK |
|
||||
OFFSET |
|
||||
OFFSETIN |
|
||||
OFFSETINCLOCK |
|
||||
UNCONSTOFFSETINCLOCK |
|
||||
OFFSETINDELAY |
|
||||
OFFSETINMOD |
|
||||
OFFSETOUT |
|
||||
OFFSETOUTCLOCK |
|
||||
UNCONSTOFFSETOUTCLOCK |
|
||||
OFFSETOUTDELAY |
|
||||
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
|
||||
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
|
||||
twEndPtCnt?,
|
||||
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
|
||||
<!ELEMENT twConstName (#PCDATA)>
|
||||
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
|
||||
<!ATTLIST twConstHead uID CDATA #IMPLIED>
|
||||
<!ELEMENT twItemCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCntEndPt (#PCDATA)>
|
||||
<!ELEMENT twErrCntSetup (#PCDATA)>
|
||||
<!ELEMENT twErrCntHold (#PCDATA)>
|
||||
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twEndPtCnt (#PCDATA)>
|
||||
<!ELEMENT twPathErrCnt (#PCDATA)>
|
||||
<!ELEMENT twMinPer (#PCDATA) >
|
||||
<!ELEMENT twFootnote EMPTY>
|
||||
<!ATTLIST twFootnote number CDATA #REQUIRED>
|
||||
<!ELEMENT twMaxDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFreq (#PCDATA)>
|
||||
<!ELEMENT twMinOff (#PCDATA)>
|
||||
<!ELEMENT twMaxOff (#PCDATA)>
|
||||
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
|
||||
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
|
||||
<!ELEMENT twTIGName (#PCDATA)>
|
||||
<!ELEMENT twInstantiated (#PCDATA)>
|
||||
<!ELEMENT twBlocked (#PCDATA)>
|
||||
<!ELEMENT twRacePathRpt (twRacePath+)>
|
||||
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
|
||||
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
|
||||
twSimpleMinPath CDATA #IMPLIED>
|
||||
<!ELEMENT twTotDel (#PCDATA)>
|
||||
<!ELEMENT twSrc (#PCDATA)>
|
||||
<!ATTLIST twSrc BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDest (#PCDATA)>
|
||||
<!ATTLIST twDest BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDel (#PCDATA)>
|
||||
<!ELEMENT twSUTime (#PCDATA)>
|
||||
<!ELEMENT twTotPathDel (#PCDATA)>
|
||||
<!ELEMENT twClkSkew (#PCDATA)>
|
||||
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
|
||||
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
|
||||
<!ELEMENT twSlack (#PCDATA)>
|
||||
<!ELEMENT twDelConst (#PCDATA)>
|
||||
<!ELEMENT tw2Phase EMPTY>
|
||||
<!ELEMENT twClkUncert (#PCDATA)>
|
||||
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
|
||||
fDCMJit CDATA #IMPLIED
|
||||
fPhaseErr CDATA #IMPLIED
|
||||
sEqu CDATA #IMPLIED>
|
||||
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
|
||||
<!ELEMENT twPathRptBanner (#PCDATA)>
|
||||
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twOff (#PCDATA)>
|
||||
<!ELEMENT twGuaranteed EMPTY>
|
||||
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
|
||||
<!ELEMENT twClkDel (#PCDATA)>
|
||||
<!ELEMENT twClkSrc (#PCDATA)>
|
||||
<!ELEMENT twClkDest (#PCDATA)>
|
||||
<!ELEMENT twGuarInSetup (#PCDATA)>
|
||||
<!ELEMENT twOffSrc (#PCDATA)>
|
||||
<!ELEMENT twOffDest (#PCDATA)>
|
||||
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ELEMENT twDataDel (#PCDATA)>
|
||||
<!ELEMENT twDataSrc (#PCDATA)>
|
||||
<!ELEMENT twDataDest (#PCDATA)>
|
||||
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
|
||||
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twLogLvls (#PCDATA)>
|
||||
<!ELEMENT twSrcSite (#PCDATA)>
|
||||
<!ELEMENT twSrcClk (#PCDATA)>
|
||||
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
|
||||
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twDelInfo (#PCDATA)>
|
||||
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twSite (#PCDATA)>
|
||||
<!ELEMENT twDelType (#PCDATA)>
|
||||
<!ELEMENT twFanCnt (#PCDATA)>
|
||||
<!ELEMENT twComp (#PCDATA)>
|
||||
<!ELEMENT twNet (#PCDATA)>
|
||||
<!ELEMENT twBEL (#PCDATA)>
|
||||
<!ELEMENT twLogDel (#PCDATA)>
|
||||
<!ELEMENT twRouteDel (#PCDATA)>
|
||||
<!ELEMENT twDestClk (#PCDATA)>
|
||||
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPctLog (#PCDATA)>
|
||||
<!ELEMENT twPctRoute (#PCDATA)>
|
||||
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
|
||||
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
|
||||
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
|
||||
<!ELEMENT twTimeConst (#PCDATA)>
|
||||
<!ELEMENT twAbsSlack (#PCDATA)>
|
||||
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
|
||||
<!ELEMENT twSkew (#PCDATA)>
|
||||
<!ELEMENT twDetNet (twNetDel*)>
|
||||
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
|
||||
<!ELEMENT twNetDelInfo (#PCDATA)>
|
||||
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twDetSkewNet (twNetSkew*)>
|
||||
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
|
||||
<!ELEMENT twClkSkewLimit EMPTY>
|
||||
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
|
||||
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollupTable (twConstRollup*)>
|
||||
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollup EMPTY>
|
||||
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
|
||||
<!ELEMENT twConstList (twConstListItem)*>
|
||||
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
|
||||
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
|
||||
<!ELEMENT twNotMet EMPTY>
|
||||
<!ELEMENT twReqVal (#PCDATA)>
|
||||
<!ELEMENT twActVal (#PCDATA)>
|
||||
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
|
||||
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
|
||||
<!ELEMENT twConstStats (twConstName)>
|
||||
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
|
||||
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
|
||||
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
|
||||
<!ELEMENT twConstData EMPTY>
|
||||
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
|
||||
best CDATA #IMPLIED requested CDATA #IMPLIED
|
||||
errors CDATA #IMPLIED
|
||||
score CDATA #IMPLIED>
|
||||
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
|
||||
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
|
||||
<!ELEMENT twTimeGrpName (#PCDATA)>
|
||||
<!ELEMENT twCompList (twCompName+)>
|
||||
<!ELEMENT twCompName (#PCDATA)>
|
||||
<!ELEMENT twSigList (twSigName+)>
|
||||
<!ELEMENT twSigName (#PCDATA)>
|
||||
<!ELEMENT twBELList (twBELName+)>
|
||||
<!ELEMENT twBELName (#PCDATA)>
|
||||
<!ELEMENT twBlockList (twBlockName+)>
|
||||
<!ELEMENT twBlockName (#PCDATA)>
|
||||
<!ELEMENT twMacList (twMacName+)>
|
||||
<!ELEMENT twMacName (#PCDATA)>
|
||||
<!ELEMENT twPinList (twPinName+)>
|
||||
<!ELEMENT twPinName (#PCDATA)>
|
||||
<!ELEMENT twUnmetConstCnt (#PCDATA)>
|
||||
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
|
||||
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
|
||||
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
|
||||
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
|
||||
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
|
||||
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
|
||||
<!ELEMENT twSU2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twH2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
|
||||
<!ELEMENT twClk2Pad (twDest, twTime)>
|
||||
<!ELEMENT twTime (#PCDATA)>
|
||||
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
|
||||
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2Out EMPTY>
|
||||
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
|
||||
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
|
||||
<!ELEMENT twRiseRise (#PCDATA)>
|
||||
<!ELEMENT twFallRise (#PCDATA)>
|
||||
<!ELEMENT twRiseFall (#PCDATA)>
|
||||
<!ELEMENT twFallFall (#PCDATA)>
|
||||
<!ELEMENT twPad2PadList (twPad2Pad+)>
|
||||
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
|
||||
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
|
||||
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
|
||||
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
|
||||
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
|
||||
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffOutTblRow EMPTY>
|
||||
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
|
||||
<!ELEMENT twNonDedClk (#PCDATA)>
|
||||
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
|
||||
<!ELEMENT twScore (#PCDATA)>
|
||||
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
|
||||
<!ELEMENT twPathCnt (#PCDATA)>
|
||||
<!ELEMENT twNetCnt (#PCDATA)>
|
||||
<!ELEMENT twConnCnt (#PCDATA)>
|
||||
<!ELEMENT twPct (#PCDATA)>
|
||||
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
|
||||
<!ELEMENT twMaxCombDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFromToDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetSkew (#PCDATA)>
|
||||
<!ELEMENT twMaxInAfterClk (#PCDATA)>
|
||||
<!ELEMENT twMinInBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMinOutAfterClk (#PCDATA)>
|
||||
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
|
||||
<!ELEMENT twTimestamp (#PCDATA)>
|
||||
<!ELEMENT twFootnoteExplanation EMPTY>
|
||||
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
|
||||
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
|
||||
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
|
||||
<!ELEMENT twClientName (#PCDATA)>
|
||||
<!ELEMENT twAttrList (twAttrListItem)*>
|
||||
<!ELEMENT twAttrListItem (twName, twValue*)>
|
||||
<!ELEMENT twName (#PCDATA)>
|
||||
<!ELEMENT twValue (#PCDATA)>
|
||||
]>
|
||||
<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (nt)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
|
||||
3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
|
||||
</twCmdLine><twDesign>WarpLC.ncd</twDesign><twDesignPath>WarpLC.ncd</twDesignPath><twPCF>WarpLC.pcf</twPCF><twPcfPath>WarpLC.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="ftg256"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twWarn anchorID="2">WARNING:Timing:3175 - CPUCLK does not clock data from CPU_nAS</twWarn><twWarn anchorID="3">WARNING:Timing:3225 - Timing constraint COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CPUCLK"; ignored during timing analysis</twWarn><twWarn anchorID="4">WARNING:Timing:3175 - CPUCLK does not clock data from INt</twWarn><twWarn anchorID="5">WARNING:Timing:3225 - Timing constraint COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CPUCLK"; ignored during timing analysis</twWarn><twWarn anchorID="6">WARNING:Timing:3175 - CPUCLK does not clock data to OUTt</twWarn><twWarn anchorID="7">WARNING:Timing:3225 - Timing constraint COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CPUCLK"; ignored during timing analysis</twWarn><twInfo anchorID="8">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="9">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="10">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="11" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="NET FSBCLK PERIOD = 10ns HIGH;" ScopeName="">NET "FSBCLK" PERIOD = 10 ns HIGH 50%;</twConstName><twItemCnt>2</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>2</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.489</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point OUTt (SLICE_X1Y7.B1), 1 path
|
||||
</twPathRptBanner><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>8.511</twSlack><twSrc BELType="FF">CPUCLK</twSrc><twDest BELType="FF">OUTt</twDest><twTotPathDel>1.341</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="14" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>CPUCLK</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X1Y7.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X1Y7.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPUCLK</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y7.B1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.538</twDelInfo><twComp>CPUCLK_OBUF</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPU_nAS_CPUCLKi_AND_2_o1</twBEL><twBEL>OUTt</twBEL></twPathDel><twLogDel>0.803</twLogDel><twRouteDel>0.538</twRouteDel><twTotDel>1.341</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>59.9</twPctLog><twPctRoute>40.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point CPUCLK (SLICE_X1Y7.A6), 1 path
|
||||
</twPathRptBanner><twPathRpt anchorID="14"><twConstPath anchorID="15" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>8.889</twSlack><twSrc BELType="FF">CPUCLK</twSrc><twDest BELType="FF">CPUCLK</twDest><twTotPathDel>0.963</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="14" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>CPUCLK</twSrc><twDest BELType='FF'>CPUCLK</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X1Y7.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X1Y7.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPUCLK</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y7.A6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.160</twDelInfo><twComp>CPUCLK_OBUF</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPUCLK_rstpot1_INV_0</twBEL><twBEL>CPUCLK</twBEL></twPathDel><twLogDel>0.803</twLogDel><twRouteDel>0.160</twRouteDel><twTotDel>0.963</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>83.4</twPctLog><twPctRoute>16.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: NET "FSBCLK" PERIOD = 10 ns HIGH 50%;
|
||||
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point CPUCLK (SLICE_X1Y7.A6), 1 path
|
||||
</twPathRptBanner><twPathRpt anchorID="16"><twConstPath anchorID="17" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.444</twSlack><twSrc BELType="FF">CPUCLK</twSrc><twDest BELType="FF">CPUCLK</twDest><twTotPathDel>0.444</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="14" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>CPUCLK</twSrc><twDest BELType='FF'>CPUCLK</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X1Y7.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X1Y7.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPUCLK</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y7.A6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twFalling">0.031</twDelInfo><twComp>CPUCLK_OBUF</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X1Y7.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPUCLK_rstpot1_INV_0</twBEL><twBEL>CPUCLK</twBEL></twPathDel><twLogDel>0.413</twLogDel><twRouteDel>0.031</twRouteDel><twTotDel>0.444</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>93.0</twPctLog><twPctRoute>7.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point OUTt (SLICE_X1Y7.B1), 1 path
|
||||
</twPathRptBanner><twPathRpt anchorID="18"><twConstPath anchorID="19" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.684</twSlack><twSrc BELType="FF">CPUCLK</twSrc><twDest BELType="FF">OUTt</twDest><twTotPathDel>0.684</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="14" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>CPUCLK</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X1Y7.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X1Y7.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPUCLK</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y7.B1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twFalling">0.271</twDelInfo><twComp>CPUCLK_OBUF</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X1Y7.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPU_nAS_CPUCLKi_AND_2_o1</twBEL><twBEL>OUTt</twBEL></twPathDel><twLogDel>0.413</twLogDel><twRouteDel>0.271</twRouteDel><twTotDel>0.684</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>60.4</twPctLog><twPctRoute>39.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="20"><twPinLimitBanner>Component Switching Limit Checks: NET "FSBCLK" PERIOD = 10 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="21" type="MINPERIOD" name="Tcp" slack="9.530" period="10.000" constraintValue="10.000" deviceLimit="0.470" freqLimit="2127.660" physResource="OUTt_OBUF/CLK" logResource="CPUCLK/CK" locationPin="SLICE_X1Y7.CLK" clockNet="FSBCLK"/><twPinLimit anchorID="22" type="MINPERIOD" name="Tcp" slack="9.530" period="10.000" constraintValue="10.000" deviceLimit="0.470" freqLimit="2127.660" physResource="OUTt_OBUF/CLK" logResource="OUTt/CK" locationPin="SLICE_X1Y7.CLK" clockNet="FSBCLK"/></twPinLimitRpt></twConst><twConst anchorID="23" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="NET CLKIN PERIOD = 20ns HIGH;" ScopeName="">NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>5.000</twMinPer></twConstHead><twPinLimitRpt anchorID="24"><twPinLimitBanner>Component Switching Limit Checks: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="25" type="MINLOWPULSE" name="Tdcmpw_CLKIN_50_100" slack="15.000" period="20.000" constraintValue="10.000" deviceLimit="2.500" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN2" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/><twPinLimit anchorID="26" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_50_100" slack="15.000" period="20.000" constraintValue="10.000" deviceLimit="2.500" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN2" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/><twPinLimit anchorID="27" type="MINPERIOD" name="Tpllper_CLKIN(Finmax)" slack="17.780" period="20.000" constraintValue="20.000" deviceLimit="2.220" freqLimit="450.450" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN2" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/></twPinLimitRpt></twConst><twConst anchorID="28" twConstType="PERIOD" ><twConstHead uID="7"><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS </twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.666</twMinPer></twConstHead><twPinLimitRpt anchorID="29"><twPinLimitBanner>Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkfbout" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
duty cycle corrected to 20 nS HIGH 10 nS
|
||||
</twPinLimitBanner><twPinLimit anchorID="30" type="MINPERIOD" name="Tbcper_I" slack="17.334" period="20.000" constraintValue="20.000" deviceLimit="2.666" freqLimit="375.094" physResource="instance_name/clkfbout_bufg/I0" logResource="instance_name/clkfbout_bufg/I0" locationPin="BUFGMUX_X2Y3.I0" clockNet="instance_name/clkfbout"/><twPinLimit anchorID="31" type="MINPERIOD" name="Tockper" slack="17.751" period="20.000" constraintValue="20.000" deviceLimit="2.249" freqLimit="444.642" physResource="CLKFB_OUT_OBUF/CLK0" logResource="instance_name/clkfbout_oddr/CK0" locationPin="OLOGIC_X0Y7.CLK0" clockNet="instance_name/clkfb_bufg_out"/><twPinLimit anchorID="32" type="MINPERIOD" name="Tpllper_CLKFB" slack="17.780" period="20.000" constraintValue="20.000" deviceLimit="2.220" freqLimit="450.450" physResource="instance_name/pll_base_inst/PLL_ADV/CLKFBOUT" logResource="instance_name/pll_base_inst/PLL_ADV/CLKFBOUT" locationPin="PLL_ADV_X0Y1.CLKFBOUT" clockNet="instance_name/clkfbout"/></twPinLimitRpt></twConst><twConst anchorID="33" twConstType="PERIOD" ><twConstHead uID="6"><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS </twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.666</twMinPer></twConstHead><twPinLimitRpt anchorID="34"><twPinLimitBanner>Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout0" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
divided by 2.00 to 10 nS
|
||||
</twPinLimitBanner><twPinLimit anchorID="35" type="MINPERIOD" name="Tbcper_I" slack="7.334" period="10.000" constraintValue="10.000" deviceLimit="2.666" freqLimit="375.094" physResource="instance_name/clkout1_buf/I0" logResource="instance_name/clkout1_buf/I0" locationPin="BUFGMUX_X3Y13.I0" clockNet="instance_name/clkout0"/><twPinLimit anchorID="36" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="8.948" period="10.000" constraintValue="10.000" deviceLimit="1.052" freqLimit="950.570" physResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" logResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" locationPin="PLL_ADV_X0Y1.CLKOUT0" clockNet="instance_name/clkout0"/><twPinLimit anchorID="37" type="MAXPERIOD" name="Tpllper_CLKOUT(Foutmin)" slack="310.000" period="10.000" constraintValue="10.000" deviceLimit="320.000" freqLimit="3.125" physResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" logResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" locationPin="PLL_ADV_X0Y1.CLKOUT0" clockNet="instance_name/clkout0"/></twPinLimitRpt></twConst><twConst anchorID="38" twConstType="OFFSETINDELAY" ><twConstHead uID="3"><twConstName UCFConstName="NET CPU_nAS OFFSET = IN 10ns VALID 11ns BEFORE CPUCLK;" ScopeName="">COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CPUCLK";</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt></twConstHead></twConst><twConst anchorID="39" twConstType="OFFSETINDELAY" ><twConstHead uID="4"><twConstName UCFConstName="NET INt OFFSET = IN 10ns VALID 11ns BEFORE CPUCLK;" ScopeName="">COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CPUCLK";</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt></twConstHead></twConst><twConst anchorID="40" twConstType="OFFSETOUTDELAY" ><twConstHead uID="5"><twConstName UCFConstName="NET OUTt OFFSET = OUT 4ns AFTER CPUCLK;" ScopeName="">COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CPUCLK";</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt></twConstHead></twConst><twConstRollupTable uID="2" anchorID="41"><twConstRollup name="instance_name/clkin1" fullName="NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="5.000" actualRollup="5.332" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="instance_name/clkfbout" fullName="PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS " type="child" depth="1" requirement="20.000" prefType="period" actual="2.666" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="instance_name/clkout0" fullName="PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS " type="child" depth="1" requirement="10.000" prefType="period" actual="2.666" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="42">0</twUnmetConstCnt><twDataSheet anchorID="43" twNameLen="15"><twClk2SUList anchorID="44" twDestWidth="5"><twDest>CLKIN</twDest><twClk2SU><twSrc>CLKIN</twSrc><twRiseRise>1.489</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="45"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>2</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>11</twConnCnt></twConstCov><twStats anchorID="46"><twMinPer>5.000</twMinPer><twFootnote number="1" /><twMaxFreq>200.000</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Fri Oct 29 10:29:11 2021 </twTimestamp></twFoot><twClientInfo anchorID="47"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
|
||||
|
||||
Peak Memory Usage: 168 MB
|
||||
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
|
||||
349
fpga/WarpLC_2021-10-29-10-30-9.twx
Normal file
349
fpga/WarpLC_2021-10-29-10-30-9.twx
Normal file
@ -0,0 +1,349 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE twReport [
|
||||
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
|
||||
twDebug*, twFoot?, twClientInfo?)>
|
||||
<!ATTLIST twReport version CDATA "10,4">
|
||||
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
|
||||
<!ELEMENT twExecVer (#PCDATA)>
|
||||
<!ELEMENT twCopyright (#PCDATA)>
|
||||
<!ELEMENT twCmdLine (#PCDATA)>
|
||||
<!ELEMENT twDesign (#PCDATA)>
|
||||
<!ELEMENT twPCF (#PCDATA)>
|
||||
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
|
||||
<!ELEMENT twDevName (#PCDATA)>
|
||||
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
|
||||
<!ELEMENT twSpeedGrade (#PCDATA)>
|
||||
<!ELEMENT twSpeedVer (#PCDATA)>
|
||||
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
|
||||
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
|
||||
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
|
||||
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
|
||||
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
|
||||
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twItemLimit (#PCDATA)>
|
||||
<!ELEMENT twUnconst EMPTY>
|
||||
<!ELEMENT twUnconstLimit (#PCDATA)>
|
||||
<!ELEMENT twEnvVar EMPTY>
|
||||
<!ATTLIST twEnvVar name CDATA #REQUIRED>
|
||||
<!ATTLIST twEnvVar description CDATA #REQUIRED>
|
||||
<!ELEMENT twWarn (#PCDATA)>
|
||||
<!ELEMENT twInfo (#PCDATA)>
|
||||
<!ELEMENT twDebug (#PCDATA)>
|
||||
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
|
||||
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
|
||||
<!ELEMENT twProc (#PCDATA)>
|
||||
<!ELEMENT twTemp (#PCDATA)>
|
||||
<!ELEMENT twVolt (#PCDATA)>
|
||||
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
|
||||
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
|
||||
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twCycles (twSigConn+)>
|
||||
<!ATTLIST twCycles twNum CDATA #REQUIRED>
|
||||
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
|
||||
<!ELEMENT twSig (#PCDATA)>
|
||||
<!ELEMENT twDriver (#PCDATA)>
|
||||
<!ELEMENT twLoad (#PCDATA)>
|
||||
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
|
||||
<!ATTLIST twConst twConstType (NET |
|
||||
NETDELAY |
|
||||
NETSKEW |
|
||||
PATH |
|
||||
DEFPERIOD |
|
||||
UNCONSTPATH |
|
||||
DEFPATH |
|
||||
PATH2SETUP |
|
||||
UNCONSTPATH2SETUP |
|
||||
PATHCLASS |
|
||||
PATHDELAY |
|
||||
PERIOD |
|
||||
FREQUENCY |
|
||||
PATHBLOCK |
|
||||
OFFSET |
|
||||
OFFSETIN |
|
||||
OFFSETINCLOCK |
|
||||
UNCONSTOFFSETINCLOCK |
|
||||
OFFSETINDELAY |
|
||||
OFFSETINMOD |
|
||||
OFFSETOUT |
|
||||
OFFSETOUTCLOCK |
|
||||
UNCONSTOFFSETOUTCLOCK |
|
||||
OFFSETOUTDELAY |
|
||||
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
|
||||
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
|
||||
twEndPtCnt?,
|
||||
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
|
||||
<!ELEMENT twConstName (#PCDATA)>
|
||||
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
|
||||
<!ATTLIST twConstHead uID CDATA #IMPLIED>
|
||||
<!ELEMENT twItemCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCntEndPt (#PCDATA)>
|
||||
<!ELEMENT twErrCntSetup (#PCDATA)>
|
||||
<!ELEMENT twErrCntHold (#PCDATA)>
|
||||
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twEndPtCnt (#PCDATA)>
|
||||
<!ELEMENT twPathErrCnt (#PCDATA)>
|
||||
<!ELEMENT twMinPer (#PCDATA) >
|
||||
<!ELEMENT twFootnote EMPTY>
|
||||
<!ATTLIST twFootnote number CDATA #REQUIRED>
|
||||
<!ELEMENT twMaxDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFreq (#PCDATA)>
|
||||
<!ELEMENT twMinOff (#PCDATA)>
|
||||
<!ELEMENT twMaxOff (#PCDATA)>
|
||||
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
|
||||
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
|
||||
<!ELEMENT twTIGName (#PCDATA)>
|
||||
<!ELEMENT twInstantiated (#PCDATA)>
|
||||
<!ELEMENT twBlocked (#PCDATA)>
|
||||
<!ELEMENT twRacePathRpt (twRacePath+)>
|
||||
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
|
||||
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
|
||||
twSimpleMinPath CDATA #IMPLIED>
|
||||
<!ELEMENT twTotDel (#PCDATA)>
|
||||
<!ELEMENT twSrc (#PCDATA)>
|
||||
<!ATTLIST twSrc BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDest (#PCDATA)>
|
||||
<!ATTLIST twDest BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDel (#PCDATA)>
|
||||
<!ELEMENT twSUTime (#PCDATA)>
|
||||
<!ELEMENT twTotPathDel (#PCDATA)>
|
||||
<!ELEMENT twClkSkew (#PCDATA)>
|
||||
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
|
||||
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
|
||||
<!ELEMENT twSlack (#PCDATA)>
|
||||
<!ELEMENT twDelConst (#PCDATA)>
|
||||
<!ELEMENT tw2Phase EMPTY>
|
||||
<!ELEMENT twClkUncert (#PCDATA)>
|
||||
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
|
||||
fDCMJit CDATA #IMPLIED
|
||||
fPhaseErr CDATA #IMPLIED
|
||||
sEqu CDATA #IMPLIED>
|
||||
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
|
||||
<!ELEMENT twPathRptBanner (#PCDATA)>
|
||||
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twOff (#PCDATA)>
|
||||
<!ELEMENT twGuaranteed EMPTY>
|
||||
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
|
||||
<!ELEMENT twClkDel (#PCDATA)>
|
||||
<!ELEMENT twClkSrc (#PCDATA)>
|
||||
<!ELEMENT twClkDest (#PCDATA)>
|
||||
<!ELEMENT twGuarInSetup (#PCDATA)>
|
||||
<!ELEMENT twOffSrc (#PCDATA)>
|
||||
<!ELEMENT twOffDest (#PCDATA)>
|
||||
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ELEMENT twDataDel (#PCDATA)>
|
||||
<!ELEMENT twDataSrc (#PCDATA)>
|
||||
<!ELEMENT twDataDest (#PCDATA)>
|
||||
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
|
||||
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twLogLvls (#PCDATA)>
|
||||
<!ELEMENT twSrcSite (#PCDATA)>
|
||||
<!ELEMENT twSrcClk (#PCDATA)>
|
||||
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
|
||||
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twDelInfo (#PCDATA)>
|
||||
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twSite (#PCDATA)>
|
||||
<!ELEMENT twDelType (#PCDATA)>
|
||||
<!ELEMENT twFanCnt (#PCDATA)>
|
||||
<!ELEMENT twComp (#PCDATA)>
|
||||
<!ELEMENT twNet (#PCDATA)>
|
||||
<!ELEMENT twBEL (#PCDATA)>
|
||||
<!ELEMENT twLogDel (#PCDATA)>
|
||||
<!ELEMENT twRouteDel (#PCDATA)>
|
||||
<!ELEMENT twDestClk (#PCDATA)>
|
||||
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPctLog (#PCDATA)>
|
||||
<!ELEMENT twPctRoute (#PCDATA)>
|
||||
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
|
||||
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
|
||||
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
|
||||
<!ELEMENT twTimeConst (#PCDATA)>
|
||||
<!ELEMENT twAbsSlack (#PCDATA)>
|
||||
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
|
||||
<!ELEMENT twSkew (#PCDATA)>
|
||||
<!ELEMENT twDetNet (twNetDel*)>
|
||||
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
|
||||
<!ELEMENT twNetDelInfo (#PCDATA)>
|
||||
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twDetSkewNet (twNetSkew*)>
|
||||
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
|
||||
<!ELEMENT twClkSkewLimit EMPTY>
|
||||
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
|
||||
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollupTable (twConstRollup*)>
|
||||
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollup EMPTY>
|
||||
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
|
||||
<!ELEMENT twConstList (twConstListItem)*>
|
||||
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
|
||||
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
|
||||
<!ELEMENT twNotMet EMPTY>
|
||||
<!ELEMENT twReqVal (#PCDATA)>
|
||||
<!ELEMENT twActVal (#PCDATA)>
|
||||
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
|
||||
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
|
||||
<!ELEMENT twConstStats (twConstName)>
|
||||
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
|
||||
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
|
||||
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
|
||||
<!ELEMENT twConstData EMPTY>
|
||||
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
|
||||
best CDATA #IMPLIED requested CDATA #IMPLIED
|
||||
errors CDATA #IMPLIED
|
||||
score CDATA #IMPLIED>
|
||||
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
|
||||
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
|
||||
<!ELEMENT twTimeGrpName (#PCDATA)>
|
||||
<!ELEMENT twCompList (twCompName+)>
|
||||
<!ELEMENT twCompName (#PCDATA)>
|
||||
<!ELEMENT twSigList (twSigName+)>
|
||||
<!ELEMENT twSigName (#PCDATA)>
|
||||
<!ELEMENT twBELList (twBELName+)>
|
||||
<!ELEMENT twBELName (#PCDATA)>
|
||||
<!ELEMENT twBlockList (twBlockName+)>
|
||||
<!ELEMENT twBlockName (#PCDATA)>
|
||||
<!ELEMENT twMacList (twMacName+)>
|
||||
<!ELEMENT twMacName (#PCDATA)>
|
||||
<!ELEMENT twPinList (twPinName+)>
|
||||
<!ELEMENT twPinName (#PCDATA)>
|
||||
<!ELEMENT twUnmetConstCnt (#PCDATA)>
|
||||
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
|
||||
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
|
||||
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
|
||||
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
|
||||
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
|
||||
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
|
||||
<!ELEMENT twSU2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twH2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
|
||||
<!ELEMENT twClk2Pad (twDest, twTime)>
|
||||
<!ELEMENT twTime (#PCDATA)>
|
||||
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
|
||||
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2Out EMPTY>
|
||||
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
|
||||
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
|
||||
<!ELEMENT twRiseRise (#PCDATA)>
|
||||
<!ELEMENT twFallRise (#PCDATA)>
|
||||
<!ELEMENT twRiseFall (#PCDATA)>
|
||||
<!ELEMENT twFallFall (#PCDATA)>
|
||||
<!ELEMENT twPad2PadList (twPad2Pad+)>
|
||||
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
|
||||
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
|
||||
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
|
||||
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
|
||||
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
|
||||
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffOutTblRow EMPTY>
|
||||
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
|
||||
<!ELEMENT twNonDedClk (#PCDATA)>
|
||||
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
|
||||
<!ELEMENT twScore (#PCDATA)>
|
||||
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
|
||||
<!ELEMENT twPathCnt (#PCDATA)>
|
||||
<!ELEMENT twNetCnt (#PCDATA)>
|
||||
<!ELEMENT twConnCnt (#PCDATA)>
|
||||
<!ELEMENT twPct (#PCDATA)>
|
||||
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
|
||||
<!ELEMENT twMaxCombDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFromToDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetSkew (#PCDATA)>
|
||||
<!ELEMENT twMaxInAfterClk (#PCDATA)>
|
||||
<!ELEMENT twMinInBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMinOutAfterClk (#PCDATA)>
|
||||
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
|
||||
<!ELEMENT twTimestamp (#PCDATA)>
|
||||
<!ELEMENT twFootnoteExplanation EMPTY>
|
||||
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
|
||||
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
|
||||
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
|
||||
<!ELEMENT twClientName (#PCDATA)>
|
||||
<!ELEMENT twAttrList (twAttrListItem)*>
|
||||
<!ELEMENT twAttrListItem (twName, twValue*)>
|
||||
<!ELEMENT twName (#PCDATA)>
|
||||
<!ELEMENT twValue (#PCDATA)>
|
||||
]>
|
||||
<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (nt)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
|
||||
3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf
|
||||
|
||||
</twCmdLine><twDesign>WarpLC.ncd</twDesign><twDesignPath>WarpLC.ncd</twDesignPath><twPCF>WarpLC.pcf</twPCF><twPcfPath>WarpLC.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="ftg256"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="NET FSBCLK PERIOD = 10ns HIGH;" ScopeName="">NET "FSBCLK" PERIOD = 10 ns HIGH 50%;</twConstName><twItemCnt>2</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>2</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.489</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point OUTt (SLICE_X1Y7.B1), 1 path
|
||||
</twPathRptBanner><twPathRpt anchorID="6"><twConstPath anchorID="7" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>8.511</twSlack><twSrc BELType="FF">CPUCLK</twSrc><twDest BELType="FF">OUTt</twDest><twTotPathDel>1.341</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="14" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>CPUCLK</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X1Y7.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X1Y7.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPUCLK</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y7.B1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.538</twDelInfo><twComp>CPUCLK_OBUF</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPU_nAS_CPUCLKi_AND_2_o1</twBEL><twBEL>OUTt</twBEL></twPathDel><twLogDel>0.803</twLogDel><twRouteDel>0.538</twRouteDel><twTotDel>1.341</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>59.9</twPctLog><twPctRoute>40.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point CPUCLK (SLICE_X1Y7.A6), 1 path
|
||||
</twPathRptBanner><twPathRpt anchorID="8"><twConstPath anchorID="9" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>8.889</twSlack><twSrc BELType="FF">CPUCLK</twSrc><twDest BELType="FF">CPUCLK</twDest><twTotPathDel>0.963</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="14" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>CPUCLK</twSrc><twDest BELType='FF'>CPUCLK</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X1Y7.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X1Y7.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPUCLK</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y7.A6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.160</twDelInfo><twComp>CPUCLK_OBUF</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPUCLK_rstpot1_INV_0</twBEL><twBEL>CPUCLK</twBEL></twPathDel><twLogDel>0.803</twLogDel><twRouteDel>0.160</twRouteDel><twTotDel>0.963</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>83.4</twPctLog><twPctRoute>16.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: NET "FSBCLK" PERIOD = 10 ns HIGH 50%;
|
||||
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point CPUCLK (SLICE_X1Y7.A6), 1 path
|
||||
</twPathRptBanner><twPathRpt anchorID="10"><twConstPath anchorID="11" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.444</twSlack><twSrc BELType="FF">CPUCLK</twSrc><twDest BELType="FF">CPUCLK</twDest><twTotPathDel>0.444</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="14" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>CPUCLK</twSrc><twDest BELType='FF'>CPUCLK</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X1Y7.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X1Y7.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPUCLK</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y7.A6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twFalling">0.031</twDelInfo><twComp>CPUCLK_OBUF</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X1Y7.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPUCLK_rstpot1_INV_0</twBEL><twBEL>CPUCLK</twBEL></twPathDel><twLogDel>0.413</twLogDel><twRouteDel>0.031</twRouteDel><twTotDel>0.444</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>93.0</twPctLog><twPctRoute>7.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point OUTt (SLICE_X1Y7.B1), 1 path
|
||||
</twPathRptBanner><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.684</twSlack><twSrc BELType="FF">CPUCLK</twSrc><twDest BELType="FF">OUTt</twDest><twTotPathDel>0.684</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="14" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>CPUCLK</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X1Y7.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X1Y7.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPUCLK</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y7.B1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twFalling">0.271</twDelInfo><twComp>CPUCLK_OBUF</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X1Y7.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>CPU_nAS_CPUCLKi_AND_2_o1</twBEL><twBEL>OUTt</twBEL></twPathDel><twLogDel>0.413</twLogDel><twRouteDel>0.271</twRouteDel><twTotDel>0.684</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">FSBCLK</twDestClk><twPctLog>60.4</twPctLog><twPctRoute>39.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="14"><twPinLimitBanner>Component Switching Limit Checks: NET "FSBCLK" PERIOD = 10 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="15" type="MINPERIOD" name="Tcp" slack="9.530" period="10.000" constraintValue="10.000" deviceLimit="0.470" freqLimit="2127.660" physResource="OUTt_OBUF/CLK" logResource="CPUCLK/CK" locationPin="SLICE_X1Y7.CLK" clockNet="FSBCLK"/><twPinLimit anchorID="16" type="MINPERIOD" name="Tcp" slack="9.530" period="10.000" constraintValue="10.000" deviceLimit="0.470" freqLimit="2127.660" physResource="OUTt_OBUF/CLK" logResource="OUTt/CK" locationPin="SLICE_X1Y7.CLK" clockNet="FSBCLK"/></twPinLimitRpt></twConst><twConst anchorID="17" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="NET CLKIN PERIOD = 20ns HIGH;" ScopeName="">NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>5.000</twMinPer></twConstHead><twPinLimitRpt anchorID="18"><twPinLimitBanner>Component Switching Limit Checks: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="19" type="MINLOWPULSE" name="Tdcmpw_CLKIN_50_100" slack="15.000" period="20.000" constraintValue="10.000" deviceLimit="2.500" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN2" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/><twPinLimit anchorID="20" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_50_100" slack="15.000" period="20.000" constraintValue="10.000" deviceLimit="2.500" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN2" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/><twPinLimit anchorID="21" type="MINPERIOD" name="Tpllper_CLKIN(Finmax)" slack="17.780" period="20.000" constraintValue="20.000" deviceLimit="2.220" freqLimit="450.450" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN2" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/></twPinLimitRpt></twConst><twConst anchorID="22" twConstType="PERIOD" ><twConstHead uID="4"><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS </twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.666</twMinPer></twConstHead><twPinLimitRpt anchorID="23"><twPinLimitBanner>Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkfbout" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
duty cycle corrected to 20 nS HIGH 10 nS
|
||||
</twPinLimitBanner><twPinLimit anchorID="24" type="MINPERIOD" name="Tbcper_I" slack="17.334" period="20.000" constraintValue="20.000" deviceLimit="2.666" freqLimit="375.094" physResource="instance_name/clkfbout_bufg/I0" logResource="instance_name/clkfbout_bufg/I0" locationPin="BUFGMUX_X2Y3.I0" clockNet="instance_name/clkfbout"/><twPinLimit anchorID="25" type="MINPERIOD" name="Tockper" slack="17.751" period="20.000" constraintValue="20.000" deviceLimit="2.249" freqLimit="444.642" physResource="CLKFB_OUT_OBUF/CLK0" logResource="instance_name/clkfbout_oddr/CK0" locationPin="OLOGIC_X0Y7.CLK0" clockNet="instance_name/clkfb_bufg_out"/><twPinLimit anchorID="26" type="MINPERIOD" name="Tpllper_CLKFB" slack="17.780" period="20.000" constraintValue="20.000" deviceLimit="2.220" freqLimit="450.450" physResource="instance_name/pll_base_inst/PLL_ADV/CLKFBOUT" logResource="instance_name/pll_base_inst/PLL_ADV/CLKFBOUT" locationPin="PLL_ADV_X0Y1.CLKFBOUT" clockNet="instance_name/clkfbout"/></twPinLimitRpt></twConst><twConst anchorID="27" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS </twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.666</twMinPer></twConstHead><twPinLimitRpt anchorID="28"><twPinLimitBanner>Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout0" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
divided by 2.00 to 10 nS
|
||||
</twPinLimitBanner><twPinLimit anchorID="29" type="MINPERIOD" name="Tbcper_I" slack="7.334" period="10.000" constraintValue="10.000" deviceLimit="2.666" freqLimit="375.094" physResource="instance_name/clkout1_buf/I0" logResource="instance_name/clkout1_buf/I0" locationPin="BUFGMUX_X3Y13.I0" clockNet="instance_name/clkout0"/><twPinLimit anchorID="30" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="8.948" period="10.000" constraintValue="10.000" deviceLimit="1.052" freqLimit="950.570" physResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" logResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" locationPin="PLL_ADV_X0Y1.CLKOUT0" clockNet="instance_name/clkout0"/><twPinLimit anchorID="31" type="MAXPERIOD" name="Tpllper_CLKOUT(Foutmin)" slack="310.000" period="10.000" constraintValue="10.000" deviceLimit="320.000" freqLimit="3.125" physResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" logResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" locationPin="PLL_ADV_X0Y1.CLKOUT0" clockNet="instance_name/clkout0"/></twPinLimitRpt></twConst><twConstRollupTable uID="2" anchorID="32"><twConstRollup name="instance_name/clkin1" fullName="NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="5.000" actualRollup="5.332" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="instance_name/clkfbout" fullName="PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS " type="child" depth="1" requirement="20.000" prefType="period" actual="2.666" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="instance_name/clkout0" fullName="PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS " type="child" depth="1" requirement="10.000" prefType="period" actual="2.666" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="33">0</twUnmetConstCnt><twDataSheet anchorID="34" twNameLen="15"><twClk2SUList anchorID="35" twDestWidth="5"><twDest>CLKIN</twDest><twClk2SU><twSrc>CLKIN</twSrc><twRiseRise>1.489</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="36"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>2</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>11</twConnCnt></twConstCov><twStats anchorID="37"><twMinPer>5.000</twMinPer><twFootnote number="1" /><twMaxFreq>200.000</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Fri Oct 29 10:30:09 2021 </twTimestamp></twFoot><twClientInfo anchorID="38"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
|
||||
|
||||
Peak Memory Usage: 168 MB
|
||||
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
|
||||
361
fpga/WarpLC_2021-10-29-10-38-22.twx
Normal file
361
fpga/WarpLC_2021-10-29-10-38-22.twx
Normal file
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -10,7 +10,7 @@ Target Device : xc6slx9
|
||||
Target Package : ftg256
|
||||
Target Speed : -2
|
||||
Mapper Version : spartan6 -- $Revision: 1.55 $
|
||||
Mapped Date : Fri Oct 29 10:02:57 2021
|
||||
Mapped Date : Fri Oct 29 17:59:44 2021
|
||||
|
||||
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
|
||||
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
|
||||
@ -28,9 +28,6 @@ WARNING:Security:44 - Since no license file was found,
|
||||
WARNING:Security:40 - Your license for 'ISE' expires in 4 days.
|
||||
----------------------------------------------------------------------
|
||||
Mapping design into LUTs...
|
||||
WARNING:MapLib:53 - The offset specification "OFFSET=IN 10000 pS VALID 11000 pS
|
||||
BEFORE FSBCLK" has been discarded because the referenced clock pad net
|
||||
(FSBCLK) was optimized away.
|
||||
Running directed packing...
|
||||
Running delay-based LUT packing...
|
||||
Updating timing models...
|
||||
@ -41,53 +38,53 @@ Total REAL time at the beginning of Placer: 2 secs
|
||||
Total CPU time at the beginning of Placer: 2 secs
|
||||
|
||||
Phase 1.1 Initial Placement Analysis
|
||||
Phase 1.1 Initial Placement Analysis (Checksum:67ca) REAL time: 2 secs
|
||||
Phase 1.1 Initial Placement Analysis (Checksum:18bd) REAL time: 2 secs
|
||||
|
||||
Phase 2.7 Design Feasibility Check
|
||||
Phase 2.7 Design Feasibility Check (Checksum:67ca) REAL time: 2 secs
|
||||
Phase 2.7 Design Feasibility Check (Checksum:18bd) REAL time: 2 secs
|
||||
|
||||
Phase 3.31 Local Placement Optimization
|
||||
Phase 3.31 Local Placement Optimization (Checksum:67ca) REAL time: 2 secs
|
||||
Phase 3.31 Local Placement Optimization (Checksum:18bd) REAL time: 2 secs
|
||||
|
||||
Phase 4.2 Initial Placement for Architecture Specific Features
|
||||
...
|
||||
......
|
||||
Phase 4.2 Initial Placement for Architecture Specific Features
|
||||
(Checksum:2cdc04b) REAL time: 3 secs
|
||||
(Checksum:4099679c) REAL time: 3 secs
|
||||
|
||||
Phase 5.36 Local Placement Optimization
|
||||
Phase 5.36 Local Placement Optimization (Checksum:2cdc04b) REAL time: 3 secs
|
||||
Phase 5.36 Local Placement Optimization (Checksum:4099679c) REAL time: 3 secs
|
||||
|
||||
Phase 6.30 Global Clock Region Assignment
|
||||
Phase 6.30 Global Clock Region Assignment (Checksum:2cdc04b) REAL time: 3 secs
|
||||
Phase 6.30 Global Clock Region Assignment (Checksum:4099679c) REAL time: 3 secs
|
||||
|
||||
Phase 7.3 Local Placement Optimization
|
||||
....
|
||||
Phase 7.3 Local Placement Optimization (Checksum:c5a22b64) REAL time: 3 secs
|
||||
...
|
||||
Phase 7.3 Local Placement Optimization (Checksum:432b55c8) REAL time: 3 secs
|
||||
|
||||
Phase 8.5 Local Placement Optimization
|
||||
Phase 8.5 Local Placement Optimization (Checksum:c5a22b64) REAL time: 3 secs
|
||||
Phase 8.5 Local Placement Optimization (Checksum:432b55c8) REAL time: 3 secs
|
||||
|
||||
Phase 9.8 Global Placement
|
||||
..
|
||||
................
|
||||
................
|
||||
..
|
||||
Phase 9.8 Global Placement (Checksum:3e86b47) REAL time: 3 secs
|
||||
Phase 9.8 Global Placement (Checksum:8bf5099b) REAL time: 3 secs
|
||||
|
||||
Phase 10.5 Local Placement Optimization
|
||||
Phase 10.5 Local Placement Optimization (Checksum:3e86b47) REAL time: 3 secs
|
||||
Phase 10.5 Local Placement Optimization (Checksum:8bf5099b) REAL time: 3 secs
|
||||
|
||||
Phase 11.18 Placement Optimization
|
||||
Phase 11.18 Placement Optimization (Checksum:8081ee) REAL time: 4 secs
|
||||
Phase 11.18 Placement Optimization (Checksum:8bd6219d) REAL time: 3 secs
|
||||
|
||||
Phase 12.5 Local Placement Optimization
|
||||
Phase 12.5 Local Placement Optimization (Checksum:8081ee) REAL time: 4 secs
|
||||
Phase 12.5 Local Placement Optimization (Checksum:8bd6219d) REAL time: 3 secs
|
||||
|
||||
Phase 13.34 Placement Validation
|
||||
Phase 13.34 Placement Validation (Checksum:8081ee) REAL time: 4 secs
|
||||
Phase 13.34 Placement Validation (Checksum:8bd2a88c) REAL time: 3 secs
|
||||
|
||||
Total REAL time to Placer completion: 4 secs
|
||||
Total CPU time to Placer completion: 4 secs
|
||||
Total REAL time to Placer completion: 3 secs
|
||||
Total CPU time to Placer completion: 3 secs
|
||||
Running post-placement packing...
|
||||
Writing output files...
|
||||
|
||||
@ -96,35 +93,35 @@ Design Summary
|
||||
|
||||
Design Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 1
|
||||
Number of warnings: 0
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 56 out of 11,440 1%
|
||||
Number used as Flip Flops: 56
|
||||
Number of Slice Registers: 34 out of 11,440 1%
|
||||
Number used as Flip Flops: 34
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 59 out of 5,720 1%
|
||||
Number used as logic: 56 out of 5,720 1%
|
||||
Number using O6 output only: 24
|
||||
Number using O5 output only: 29
|
||||
Number using O5 and O6: 3
|
||||
Number of Slice LUTs: 17 out of 5,720 1%
|
||||
Number used as logic: 13 out of 5,720 1%
|
||||
Number using O6 output only: 11
|
||||
Number using O5 output only: 0
|
||||
Number using O5 and O6: 2
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 0 out of 1,440 0%
|
||||
Number used exclusively as route-thrus: 3
|
||||
Number with same-slice register load: 2
|
||||
Number with same-slice carry load: 1
|
||||
Number used exclusively as route-thrus: 4
|
||||
Number with same-slice register load: 4
|
||||
Number with same-slice carry load: 0
|
||||
Number with other load: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 25 out of 1,430 1%
|
||||
Number of MUXCYs used: 56 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 76
|
||||
Number with an unused Flip Flop: 22 out of 76 28%
|
||||
Number with an unused LUT: 17 out of 76 22%
|
||||
Number of fully used LUT-FF pairs: 37 out of 76 48%
|
||||
Number of unique control sets: 4
|
||||
Number of occupied Slices: 11 out of 1,430 1%
|
||||
Number of MUXCYs used: 12 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 41
|
||||
Number with an unused Flip Flop: 11 out of 41 26%
|
||||
Number with an unused LUT: 24 out of 41 58%
|
||||
Number of fully used LUT-FF pairs: 6 out of 41 14%
|
||||
Number of unique control sets: 1
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 16 out of 11,440 1%
|
||||
to control set restrictions: 6 out of 11,440 1%
|
||||
|
||||
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
||||
one Flip Flop within a slice. A control set is a unique combination of
|
||||
@ -133,9 +130,8 @@ Slice Logic Distribution:
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 49 out of 186 26%
|
||||
Number of bonded IOBs: 43 out of 186 23%
|
||||
IOB Flip Flops: 5
|
||||
IOB Latches: 1
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 0 out of 32 0%
|
||||
@ -146,13 +142,11 @@ Specific Feature Utilization:
|
||||
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2FBs: 1
|
||||
Number used as BUFIO2FB_2CLKs: 0
|
||||
Number of BUFG/BUFGMUXs: 3 out of 16 18%
|
||||
Number used as BUFGs: 3
|
||||
Number of BUFG/BUFGMUXs: 2 out of 16 12%
|
||||
Number used as BUFGs: 2
|
||||
Number used as BUFGMUX: 0
|
||||
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
|
||||
Number of ILOGIC2/ISERDES2s: 1 out of 200 1%
|
||||
Number used as ILOGIC2s: 1
|
||||
Number used as ISERDES2s: 0
|
||||
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
|
||||
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
|
||||
Number of OLOGIC2/OSERDES2s: 5 out of 200 2%
|
||||
Number used as OLOGIC2s: 5
|
||||
@ -170,11 +164,11 @@ Specific Feature Utilization:
|
||||
Number of STARTUPs: 0 out of 1 0%
|
||||
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 2.16
|
||||
Average Fanout of Non-Clock Nets: 1.41
|
||||
|
||||
Peak Memory Usage: 272 MB
|
||||
Total REAL time to MAP completion: 4 secs
|
||||
Total CPU time to MAP completion: 4 secs
|
||||
Peak Memory Usage: 276 MB
|
||||
Total REAL time to MAP completion: 3 secs
|
||||
Total CPU time to MAP completion: 3 secs
|
||||
|
||||
Mapping completed.
|
||||
See MAP report file "WarpLC_map.mrp" for details.
|
||||
|
||||
@ -10,40 +10,40 @@ Target Device : xc6slx9
|
||||
Target Package : ftg256
|
||||
Target Speed : -2
|
||||
Mapper Version : spartan6 -- $Revision: 1.55 $
|
||||
Mapped Date : Fri Oct 29 10:02:57 2021
|
||||
Mapped Date : Fri Oct 29 17:59:44 2021
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
Number of errors: 0
|
||||
Number of warnings: 1
|
||||
Number of warnings: 0
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 56 out of 11,440 1%
|
||||
Number used as Flip Flops: 56
|
||||
Number of Slice Registers: 34 out of 11,440 1%
|
||||
Number used as Flip Flops: 34
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 59 out of 5,720 1%
|
||||
Number used as logic: 56 out of 5,720 1%
|
||||
Number using O6 output only: 24
|
||||
Number using O5 output only: 29
|
||||
Number using O5 and O6: 3
|
||||
Number of Slice LUTs: 17 out of 5,720 1%
|
||||
Number used as logic: 13 out of 5,720 1%
|
||||
Number using O6 output only: 11
|
||||
Number using O5 output only: 0
|
||||
Number using O5 and O6: 2
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 0 out of 1,440 0%
|
||||
Number used exclusively as route-thrus: 3
|
||||
Number with same-slice register load: 2
|
||||
Number with same-slice carry load: 1
|
||||
Number used exclusively as route-thrus: 4
|
||||
Number with same-slice register load: 4
|
||||
Number with same-slice carry load: 0
|
||||
Number with other load: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 25 out of 1,430 1%
|
||||
Number of MUXCYs used: 56 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 76
|
||||
Number with an unused Flip Flop: 22 out of 76 28%
|
||||
Number with an unused LUT: 17 out of 76 22%
|
||||
Number of fully used LUT-FF pairs: 37 out of 76 48%
|
||||
Number of unique control sets: 4
|
||||
Number of occupied Slices: 11 out of 1,430 1%
|
||||
Number of MUXCYs used: 12 out of 2,860 1%
|
||||
Number of LUT Flip Flop pairs used: 41
|
||||
Number with an unused Flip Flop: 11 out of 41 26%
|
||||
Number with an unused LUT: 24 out of 41 58%
|
||||
Number of fully used LUT-FF pairs: 6 out of 41 14%
|
||||
Number of unique control sets: 1
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 16 out of 11,440 1%
|
||||
to control set restrictions: 6 out of 11,440 1%
|
||||
|
||||
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
||||
one Flip Flop within a slice. A control set is a unique combination of
|
||||
@ -52,9 +52,8 @@ Slice Logic Distribution:
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 49 out of 186 26%
|
||||
Number of bonded IOBs: 43 out of 186 23%
|
||||
IOB Flip Flops: 5
|
||||
IOB Latches: 1
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 0 out of 32 0%
|
||||
@ -65,13 +64,11 @@ Specific Feature Utilization:
|
||||
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2FBs: 1
|
||||
Number used as BUFIO2FB_2CLKs: 0
|
||||
Number of BUFG/BUFGMUXs: 3 out of 16 18%
|
||||
Number used as BUFGs: 3
|
||||
Number of BUFG/BUFGMUXs: 2 out of 16 12%
|
||||
Number used as BUFGs: 2
|
||||
Number used as BUFGMUX: 0
|
||||
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
|
||||
Number of ILOGIC2/ISERDES2s: 1 out of 200 1%
|
||||
Number used as ILOGIC2s: 1
|
||||
Number used as ISERDES2s: 0
|
||||
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
|
||||
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
|
||||
Number of OLOGIC2/OSERDES2s: 5 out of 200 2%
|
||||
Number used as OLOGIC2s: 5
|
||||
@ -89,11 +86,11 @@ Specific Feature Utilization:
|
||||
Number of STARTUPs: 0 out of 1 0%
|
||||
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 2.16
|
||||
Average Fanout of Non-Clock Nets: 1.41
|
||||
|
||||
Peak Memory Usage: 272 MB
|
||||
Total REAL time to MAP completion: 4 secs
|
||||
Total CPU time to MAP completion: 4 secs
|
||||
Peak Memory Usage: 276 MB
|
||||
Total REAL time to MAP completion: 3 secs
|
||||
Total CPU time to MAP completion: 3 secs
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
@ -120,9 +117,6 @@ WARNING:Security:43 - No license file was found in the standard Xilinx license
|
||||
directory.
|
||||
WARNING:Security:44 - Since no license file was found,
|
||||
WARNING:Security:40 - Your license for 'ISE' expires in 4 days.
|
||||
WARNING:MapLib:53 - The offset specification "OFFSET=IN 10000 pS VALID 11000 pS
|
||||
BEFORE FSBCLK" has been discarded because the referenced clock pad net
|
||||
(FSBCLK) was optimized away.
|
||||
|
||||
Section 3 - Informational
|
||||
-------------------------
|
||||
@ -132,15 +126,6 @@ INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
|
||||
.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'.
|
||||
INFO:Security:54 - 'xc6slx9' is a WebPack part.
|
||||
INFO:Security:66 - Your license for 'ISE' is for evaluation use only.
|
||||
INFO:LIT:243 - Logical network FSB_A<0> has no load.
|
||||
INFO:LIT:395 - The above info message is repeated 120 more times for the
|
||||
following (max. 5 shown):
|
||||
FSB_SIZ<1>,
|
||||
FSB_SIZ<0>,
|
||||
IOB_nDSACK<1>,
|
||||
IOB_nDSACK<0>,
|
||||
CPU_nCIOUT
|
||||
To see the details of these info messages, please use the -detail switch.
|
||||
INFO:MapLib:562 - No environment variables are currently set.
|
||||
INFO:MapLib:159 - Net Timing constraints on signal CLKIN are pushed forward
|
||||
through input buffer.
|
||||
@ -177,13 +162,11 @@ Section 6 - IOB Properties
|
||||
| CLKFB_IN | IOB | INPUT | LVCMOS25 | | | | | | |
|
||||
| CLKFB_OUT | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
| CLKIN | IOB | INPUT | LVCMOS25 | | | | | | |
|
||||
| CPUCLK | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | OFF | | |
|
||||
| CPUCLKIN | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| CPUCLK | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
| CPUCLKi | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| CPU_nAS | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| CPU_nBERR | IOB | OUTPUT | LVCMOS33 | | 2 | SLOW | OFF | | |
|
||||
| CPU_nDSACK | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | | | |
|
||||
| CPU_nSTERM | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | | | |
|
||||
| FPUCLK | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | OFF | | |
|
||||
| FPUCLK | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
| FSB_A<0> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<1> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<2> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<3> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
@ -215,14 +198,10 @@ Section 6 - IOB Properties
|
||||
| FSB_A<29> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<30> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_A<31> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_FC<0> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_FC<1> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_FC<2> | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| FSB_RnW | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| IOB_nHALT | IOB | INPUT | LVCMOS33 | | | | ILATCH | | |
|
||||
| RAM_CLK01 | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
| nFPUCS | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | | | |
|
||||
| nRESOE | IOB | OUTPUT | LVCMOS33 | | 2 | QUIE | | | |
|
||||
| INt | IOB | INPUT | LVCMOS33 | | | | | | |
|
||||
| OUTt | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | | | |
|
||||
| RAMCLK0 | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
| RAMCLK1 | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
Section 7 - RPMs
|
||||
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Map" timeStamp="Fri Oct 29 10:03:01 2021">
|
||||
<application stringID="Map" timeStamp="Fri Oct 29 17:59:48 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@ -65,16 +65,16 @@
|
||||
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx9-ftg256-2"/>
|
||||
</section>
|
||||
<task stringID="MAP_PACK_REPORT">
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="56">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="56"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="34">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="34"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="57">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="29"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="24"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="3"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="13">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="0"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="11"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="2"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
|
||||
@ -87,17 +87,17 @@
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="1"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="1"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="49"/>
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="43"/>
|
||||
<item AVAILABLE="14" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="5"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="1"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
|
||||
<item AVAILABLE="7" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
|
||||
<item AVAILABLE="93" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
|
||||
<item AVAILABLE="7" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
|
||||
@ -116,22 +116,22 @@
|
||||
<section stringID="MAP_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="1"/>
|
||||
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="278280"/>
|
||||
<item stringID="MAP_TOTAL_REAL_TIME" value="4 secs "/>
|
||||
<item stringID="MAP_TOTAL_CPU_TIME" value="4 secs "/>
|
||||
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
|
||||
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="282568"/>
|
||||
<item stringID="MAP_TOTAL_REAL_TIME" value="3 secs "/>
|
||||
<item stringID="MAP_TOTAL_CPU_TIME" value="3 secs "/>
|
||||
</section>
|
||||
<section stringID="MAP_SLICE_REPORTING">
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="56">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="56"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="34">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="34"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="59">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="29"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="24"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="3"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="17">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="0"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="11"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="2"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
|
||||
@ -144,29 +144,29 @@
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="1"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="2"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="4"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="2"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="1"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="4"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="25">
|
||||
<item AVAILABLE="355" dataType="int" stringID="MAP_NUM_SLICEL" value="14"/>
|
||||
<item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="11">
|
||||
<item AVAILABLE="355" dataType="int" stringID="MAP_NUM_SLICEL" value="3"/>
|
||||
<item AVAILABLE="360" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
|
||||
<item AVAILABLE="715" dataType="int" stringID="MAP_NUM_SLICEX" value="11"/>
|
||||
<item AVAILABLE="715" dataType="int" stringID="MAP_NUM_SLICEX" value="8"/>
|
||||
</item>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="76">
|
||||
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="22"/>
|
||||
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="17"/>
|
||||
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="37"/>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="41">
|
||||
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="11"/>
|
||||
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="24"/>
|
||||
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="6"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="MAP_IOB_REPORTING">
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="49"/>
|
||||
<item AVAILABLE="186" dataType="int" stringID="MAP_AGG_BONDED_IO" value="43"/>
|
||||
<item AVAILABLE="14" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="5"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="1"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
|
||||
<item AVAILABLE="7" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
|
||||
<item AVAILABLE="93" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
|
||||
<item AVAILABLE="7" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
|
||||
@ -198,7 +198,7 @@
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_BUFG_DATA">
|
||||
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="3"/>
|
||||
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="2"/>
|
||||
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
|
||||
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
|
||||
</section>
|
||||
@ -246,10 +246,10 @@
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="ODDR"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPUCLKIN"/>
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPUCLKi"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
@ -261,286 +261,243 @@
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="7">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPU_nBERR"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="2"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="8">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPU_nDSACK"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
</row>
|
||||
<row stringID="row" value="9">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CPU_nSTERM"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
</row>
|
||||
<row stringID="row" value="10">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FPUCLK"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="11">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<1>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="12">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<2>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="13">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<3>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="14">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<4>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="15">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<5>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="16">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<6>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="17">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<7>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="18">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<8>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="19">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<9>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="20">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<10>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="21">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<11>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="22">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<12>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="23">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<13>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="24">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<14>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="25">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<15>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="26">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<16>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="27">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<17>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="28">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<18>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="29">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<19>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="30">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<20>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="31">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<21>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="32">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<22>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="33">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<23>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="34">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<24>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="35">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<25>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="36">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<26>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="37">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<27>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="38">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<28>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="39">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<29>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="40">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<30>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="41">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<31>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="42">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_FC<0>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="43">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_FC<1>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="44">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_FC<2>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="45">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_RnW"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="46">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="IOB_nHALT"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="ILATCH"/>
|
||||
</row>
|
||||
<row stringID="row" value="47">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RAM_CLK01"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="ODDR"/>
|
||||
</row>
|
||||
<row stringID="row" value="48">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="nFPUCS"/>
|
||||
<row stringID="row" value="8">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<0>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="9">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<1>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="10">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<2>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="11">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<3>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="12">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<4>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="13">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<5>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="14">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<6>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="15">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<7>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="16">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<8>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="17">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<9>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="18">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<10>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="19">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<11>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="20">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<12>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="21">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<13>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="22">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<14>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="23">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<15>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="24">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<16>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="25">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<17>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="26">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<18>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="27">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<19>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="28">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<20>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="29">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<21>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="30">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<22>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="31">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<23>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="32">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<24>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="33">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<25>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="34">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<26>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="35">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<27>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="36">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<28>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="37">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<29>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="38">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<30>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="39">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="FSB_A<31>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="40">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="INt"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
</row>
|
||||
<row stringID="row" value="41">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="OUTt"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
</row>
|
||||
<row stringID="row" value="49">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="nRESOE"/>
|
||||
<row stringID="row" value="42">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RAMCLK0"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="2"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="QUIETIO"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="ODDR"/>
|
||||
</row>
|
||||
<row stringID="row" value="43">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RAMCLK1"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="24"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="ODDR"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="MAP_RPM_MACROS">
|
||||
<section stringID="MAP_SHAPE_SECTION">
|
||||
<item dataType="int" stringID="MAP_NUM_SHAPE" value="3"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SHAPE" value="1"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="MAP_GUIDE_REPORT"/>
|
||||
@ -556,7 +513,7 @@
|
||||
<item stringID="MAP_CLKIN2_PERIOD" value="30"/>
|
||||
<item stringID="MAP_CLKOUT0_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT0_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT1_DIVIDE" value="6"/>
|
||||
<item stringID="MAP_CLKOUT1_DIVIDE" value="1"/>
|
||||
<item stringID="MAP_CLKOUT1_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT1_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT2_DIVIDE" value="1"/>
|
||||
@ -574,7 +531,7 @@
|
||||
<item stringID="MAP_DIVCLK_DIVIDE" value="1"/>
|
||||
</section>
|
||||
<section stringID="MAP_CONTROL_SET_INFORMATION">
|
||||
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="4"/>
|
||||
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="1"/>
|
||||
<tree stringID="MAP_CONTROL_SET_HIERARCHY">
|
||||
<property stringID="MAP_CLOCK_SIGNAL"/>
|
||||
<property stringID="MAP_RESET_SIGNAL"/>
|
||||
@ -606,7 +563,7 @@
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_BUFG_DATA">
|
||||
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="3"/>
|
||||
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="2"/>
|
||||
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
|
||||
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
|
||||
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
|
||||
@ -619,7 +576,7 @@
|
||||
<item stringID="MAP_CLKIN2_PERIOD" value="30"/>
|
||||
<item stringID="MAP_CLKOUT0_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT0_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT1_DIVIDE" value="6"/>
|
||||
<item stringID="MAP_CLKOUT1_DIVIDE" value="1"/>
|
||||
<item stringID="MAP_CLKOUT1_DUTY_CYCLE" value="0.5"/>
|
||||
<item stringID="MAP_CLKOUT1_PHASE" value="0.0"/>
|
||||
<item stringID="MAP_CLKOUT2_DIVIDE" value="1"/>
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Fri Oct 29 10:02:55 2021">
|
||||
<application stringID="NgdBuild" timeStamp="Fri Oct 29 17:59:43 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@ -62,60 +62,48 @@
|
||||
<section stringID="NGDBUILD_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="254"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="1"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFIO2FB" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="51"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="34"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="38"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LD_1" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="29"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="20"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="48"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="9"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ODDR2" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="12"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ODDR2" value="5"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="30"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFIO2FB" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="51"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="34"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="38"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LD_1" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="29"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="20"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="48"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="9"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ODDR2" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="12"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ODDR2" value="5"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_PLL_ADV" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="30"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
|
||||
<section stringID="NGDBUILD_CORE_INSTANCES">
|
||||
<scope stringID="NGDBUILD_CORE_INSTANCE" value="CLK">
|
||||
<item stringID="NGDBUILD_CORE_INFO" type="clk_wiz_v3_6" value="CLK"/>
|
||||
<item clkin1_period="30.0" clkin2_period="30.0" clock_mgr_type="MANUAL" component_name="CLK" feedback_source="FDBK_AUTO_OFFCHIP" feedback_type="SINGLE" manual_override="false" num_out_clk="2" primtype_sel="PLL_BASE" stringID="NGDBUILD_CORE_PARAMETERS" use_clk_valid="false" use_dyn_phase_shift="false" use_dyn_reconfig="false" use_freeze="false" use_inclk_stopped="false" use_inclk_switchover="false" use_locked="false" use_max_i_jitter="false" use_min_o_jitter="false" use_phase_alignment="true" use_power_down="false" use_reset="false" use_status="false" value="CLK"/>
|
||||
<item clkin1_period="30.0" clkin2_period="30.0" clock_mgr_type="MANUAL" component_name="CLK" feedback_source="FDBK_AUTO_OFFCHIP" feedback_type="SINGLE" manual_override="false" num_out_clk="1" primtype_sel="PLL_BASE" stringID="NGDBUILD_CORE_PARAMETERS" use_clk_valid="false" use_dyn_phase_shift="false" use_dyn_reconfig="false" use_freeze="false" use_inclk_stopped="false" use_inclk_switchover="false" use_locked="false" use_max_i_jitter="false" use_min_o_jitter="false" use_phase_alignment="true" use_power_down="false" use_reset="false" use_status="false" value="CLK"/>
|
||||
</scope>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
Release 14.7 - par P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Fri Oct 29 10:03:06 2021
|
||||
Fri Oct 29 17:59:53 2021
|
||||
|
||||
|
||||
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
|
||||
@ -21,7 +21,7 @@ Pinout by Pin Number:
|
||||
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|A1 | | |GND | | | | | | | | | | | |
|
||||
|A2 |CLKFB_OUT |IOB |IO_L52N_M3A9_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|A2 | |IOBS |IO_L52N_M3A9_3 |UNUSED | |3 | | | | | | | | |
|
||||
|A3 | |IOBS |IO_L83N_VREF_3 |UNUSED | |3 | | | | | | | | |
|
||||
|A4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A5 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | |
|
||||
@ -37,7 +37,7 @@ Pinout by Pin Number:
|
||||
|A15 | | |TMS | | | | | | | | | | | |
|
||||
|A16 | | |GND | | | | | | | | | | | |
|
||||
|B1 |CPUCLK |IOB |IO_L50N_M3BA2_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|B2 |RAM_CLK01 |IOB |IO_L52P_M3A8_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|B2 | |IOBM |IO_L52P_M3A8_3 |UNUSED | |3 | | | | | | | | |
|
||||
|B3 | |IOBM |IO_L83P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|B4 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|B5 | |IOBM |IO_L2P_0 |UNUSED | |0 | | | | | | | | |
|
||||
@ -52,9 +52,9 @@ Pinout by Pin Number:
|
||||
|B14 | |IOBM |IO_L65P_SCP3_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B15 | |IOBM |IO_L29P_A23_M1A13_1 |UNUSED | |1 | | | | | | | | |
|
||||
|B16 | |IOBS |IO_L29N_A22_M1A14_1 |UNUSED | |1 | | | | | | | | |
|
||||
|C1 |CPU_nDSACK |IOB |IO_L50P_M3WE_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |NO |NONE |
|
||||
|C2 |CPU_nSTERM |IOB |IO_L48N_M3BA1_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |NO |NONE |
|
||||
|C3 |FSB_FC<2> |IOB |IO_L48P_M3BA0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|C1 |FPUCLK |IOB |IO_L50P_M3WE_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|C2 |INt |IOB |IO_L48N_M3BA1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|C3 |OUTt |IOB |IO_L48P_M3BA0_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |NO |NONE |
|
||||
|C4 | |IOBM |IO_L1P_HSWAPEN_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C5 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C6 | |IOBS |IO_L7N_0 |UNUSED | |0 | | | | | | | | |
|
||||
@ -68,9 +68,9 @@ Pinout by Pin Number:
|
||||
|C14 | | |TCK | | | | | | | | | | | |
|
||||
|C15 | |IOBM |IO_L33P_A15_M1A10_1 |UNUSED | |1 | | | | | | | | |
|
||||
|C16 | |IOBS |IO_L33N_A14_M1A4_1 |UNUSED | |1 | | | | | | | | |
|
||||
|D1 |FSB_RnW |IOB |IO_L49N_M3A2_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|D1 |RAMCLK0 |IOB |IO_L49N_M3A2_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|D2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|D3 |CPU_nAS |IOB |IO_L49P_M3A7_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|D3 |RAMCLK1 |IOB |IO_L49P_M3A7_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|D4 | | |GND | | | | | | | | | | | |
|
||||
|D5 | |IOBM |IO_L3P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|D6 | |IOBM |IO_L7P_0 |UNUSED | |0 | | | | | | | | |
|
||||
@ -84,8 +84,8 @@ Pinout by Pin Number:
|
||||
|D14 | |IOBM |IO_L31P_A19_M1CKE_1 |UNUSED | |1 | | | | | | | | |
|
||||
|D15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|D16 | |IOBS |IO_L31N_A18_M1A12_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E1 |nFPUCS |IOB |IO_L46N_M3CLKN_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |NO |NONE |
|
||||
|E2 |FSB_A<31> |IOB |IO_L46P_M3CLK_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E1 |FSB_A<27> |IOB |IO_L46N_M3CLKN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E2 |FSB_A<24> |IOB |IO_L46P_M3CLK_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|E3 | |IOBS |IO_L54N_M3A11_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E4 | |IOBM |IO_L54P_M3RESET_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E5 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
@ -100,9 +100,9 @@ Pinout by Pin Number:
|
||||
|E14 | | |TDO | | | | | | | | | | | |
|
||||
|E15 | |IOBM |IO_L34P_A13_M1WE_1 |UNUSED | |1 | | | | | | | | |
|
||||
|E16 | |IOBS |IO_L34N_A12_M1BA2_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F1 |FSB_A<27> |IOB |IO_L41N_GCLK26_M3DQ5_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F2 |FSB_A<25> |IOB |IO_L41P_GCLK27_M3DQ4_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F3 |nRESOE |IOB |IO_L53N_M3A12_3 |OUTPUT |LVCMOS33 |3 |2 |QUIETIO | | | |UNLOCATED |NO |NONE |
|
||||
|F1 |FSB_A<23> |IOB |IO_L41N_GCLK26_M3DQ5_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F2 |FSB_A<22> |IOB |IO_L41P_GCLK27_M3DQ4_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|F3 | |IOBS |IO_L53N_M3A12_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F4 | |IOBM |IO_L53P_M3CKE_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F5 | |IOBS |IO_L55N_M3A14_3 |UNUSED | |3 | | | | | | | | |
|
||||
|F6 | |IOBM |IO_L55P_M3A13_3 |UNUSED | |3 | | | | | | | | |
|
||||
@ -116,12 +116,12 @@ Pinout by Pin Number:
|
||||
|F14 | |IOBS |IO_L32N_A16_M1A9_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F15 | |IOBM |IO_L35P_A11_M1A7_1 |UNUSED | |1 | | | | | | | | |
|
||||
|F16 | |IOBS |IO_L35N_A10_M1A2_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G1 |FSB_A<15> |IOB |IO_L40N_M3DQ7_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G1 |FSB_A<29> |IOB |IO_L40N_M3DQ7_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G2 | | |GND | | | | | | | | | | | |
|
||||
|G3 |FSB_A<16> |IOB |IO_L40P_M3DQ6_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G3 |FSB_A<19> |IOB |IO_L40P_M3DQ6_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G4 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|G5 |CPUCLKIN |IOB |IO_L51N_M3A4_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|G6 |CPU_nBERR |IOB |IO_L51P_M3A10_3 |OUTPUT |LVCMOS33 |3 |2 |SLOW | | | |UNLOCATED |YES |NONE |
|
||||
|G5 | |IOBS |IO_L51N_M3A4_3 |UNUSED | |3 | | | | | | | | |
|
||||
|G6 |CLKFB_OUT |IOB |IO_L51P_M3A10_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|G7 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|G8 | | |GND | | | | | | | | | | | |
|
||||
|G9 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
@ -132,11 +132,11 @@ Pinout by Pin Number:
|
||||
|G14 | |IOBM |IO_L36P_A9_M1BA0_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G15 | | |GND | | | | | | | | | | | |
|
||||
|G16 | |IOBS |IO_L36N_A8_M1BA1_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H1 |FSB_A<20> |IOB |IO_L39N_M3LDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H2 |FSB_A<22> |IOB |IO_L39P_M3LDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H3 |FSB_A<28> |IOB |IO_L44N_GCLK20_M3A6_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H1 |FSB_A<26> |IOB |IO_L39N_M3LDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H2 |FSB_A<25> |IOB |IO_L39P_M3LDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H3 |CPU_nAS |IOB |IO_L44N_GCLK20_M3A6_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H4 |CLKFB_IN |IOB |IO_L44P_GCLK21_M3A5_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H5 |FSB_A<19> |IOB |IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H5 |FSB_A<30> |IOB |IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|H6 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|H7 | | |GND | | | | | | | | | | | |
|
||||
|H8 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
@ -148,12 +148,12 @@ Pinout by Pin Number:
|
||||
|H14 | |IOBS |IO_L39N_M1ODT_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H15 | |IOBM |IO_L37P_A7_M1A0_1 |UNUSED | |1 | | | | | | | | |
|
||||
|H16 | |IOBS |IO_L37N_A6_M1A1_1 |UNUSED | |1 | | | | | | | | |
|
||||
|J1 |FSB_A<23> |IOB |IO_L38N_M3DQ3_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J1 |FSB_A<17> |IOB |IO_L38N_M3DQ3_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|J3 |FSB_A<17> |IOB |IO_L38P_M3DQ2_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J3 |FSB_A<16> |IOB |IO_L38P_M3DQ2_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J4 |CLKIN |IOB |IO_L42N_GCLK24_M3LDM_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J5 | | |GND | | | | | | | | | | | |
|
||||
|J6 |FSB_A<26> |IOB |IO_L43P_GCLK23_M3RASN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J6 |FSB_A<21> |IOB |IO_L43P_GCLK23_M3RASN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|J7 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|J8 | | |GND | | | | | | | | | | | |
|
||||
|J9 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
@ -164,12 +164,12 @@ Pinout by Pin Number:
|
||||
|J14 | |IOBM |IO_L43P_GCLK5_M1DQ4_1 |UNUSED | |1 | | | | | | | | |
|
||||
|J15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|J16 | |IOBS |IO_L43N_GCLK4_M1DQ5_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K1 |FSB_A<21> |IOB |IO_L37N_M3DQ1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K2 |FSB_A<24> |IOB |IO_L37P_M3DQ0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K3 |FSB_A<18> |IOB |IO_L42P_GCLK25_TRDY2_M3UDM_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K1 |FSB_A<5> |IOB |IO_L37N_M3DQ1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K2 |FSB_A<14> |IOB |IO_L37P_M3DQ0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K3 |FSB_A<28> |IOB |IO_L42P_GCLK25_TRDY2_M3UDM_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K4 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|K5 |FSB_FC<0> |IOB |IO_L47P_M3A0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K6 |FSB_FC<1> |IOB |IO_L47N_M3A1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K5 |CPUCLKi |IOB |IO_L47P_M3A0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K6 |FSB_A<18> |IOB |IO_L47N_M3A1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|K7 | | |GND | | | | | | | | | | | |
|
||||
|K8 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|K9 | | |GND | | | | | | | | | | | |
|
||||
@ -180,11 +180,11 @@ Pinout by Pin Number:
|
||||
|K14 | |IOBS |IO_L41N_GCLK8_M1CASN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K15 | |IOBM |IO_L44P_A3_M1DQ6_1 |UNUSED | |1 | | | | | | | | |
|
||||
|K16 | |IOBS |IO_L44N_A2_M1DQ7_1 |UNUSED | |1 | | | | | | | | |
|
||||
|L1 |FSB_A<14> |IOB |IO_L36N_M3DQ9_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L1 |FSB_A<11> |IOB |IO_L36N_M3DQ9_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L2 | | |GND | | | | | | | | | | | |
|
||||
|L3 |FSB_A<13> |IOB |IO_L36P_M3DQ8_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L4 |FSB_A<29> |IOB |IO_L45P_M3A3_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L5 |FSB_A<30> |IOB |IO_L45N_M3ODT_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L3 |FSB_A<4> |IOB |IO_L36P_M3DQ8_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L4 |FSB_A<31> |IOB |IO_L45P_M3A3_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L5 |FSB_A<20> |IOB |IO_L45N_M3ODT_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|L6 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|L7 | |IOBS |IO_L62N_D6_2 |UNUSED | |2 | | | | | | | | |
|
||||
|L8 | |IOBM |IO_L62P_D5_2 |UNUSED | |2 | | | | | | | | |
|
||||
@ -196,11 +196,11 @@ Pinout by Pin Number:
|
||||
|L14 | |IOBM |IO_L47P_FWE_B_M1DQ0_1 |UNUSED | |1 | | | | | | | | |
|
||||
|L15 | | |GND | | | | | | | | | | | |
|
||||
|L16 | |IOBS |IO_L47N_LDC_M1DQ1_1 |UNUSED | |1 | | | | | | | | |
|
||||
|M1 |FSB_A<12> |IOB |IO_L35N_M3DQ11_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M2 |FSB_A<11> |IOB |IO_L35P_M3DQ10_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M3 |FSB_A<2> |IOB |IO_L1N_VREF_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M4 |FSB_A<1> |IOB |IO_L1P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M5 |FSB_A<3> |IOB |IO_L2P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M1 |FSB_A<1> |IOB |IO_L35N_M3DQ11_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M2 |FSB_A<2> |IOB |IO_L35P_M3DQ10_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M3 |FSB_A<6> |IOB |IO_L1N_VREF_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M4 |FSB_A<8> |IOB |IO_L1P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M5 |FSB_A<15> |IOB |IO_L2P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|M6 | |IOBM |IO_L64P_D8_2 |UNUSED | |2 | | | | | | | | |
|
||||
|M7 | |IOBS |IO_L31N_GCLK30_D15_2 |UNUSED | |2 | | | | | | | | |
|
||||
|M8 | | |GND | | | | | | | | | | | |
|
||||
@ -214,22 +214,22 @@ Pinout by Pin Number:
|
||||
|M16 | |IOBS |IO_L46N_FOE_B_M1DQ3_1 |UNUSED | |1 | | | | | | | | |
|
||||
|N1 |FSB_A<10> |IOB |IO_L34N_M3UDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N2 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|N3 |FSB_A<9> |IOB |IO_L34P_M3UDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N4 |FSB_A<4> |IOB |IO_L2N_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N3 |FSB_A<13> |IOB |IO_L34P_M3UDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N4 |FSB_A<0> |IOB |IO_L2N_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|N5 | |IOBM |IO_L49P_D3_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N6 | |IOBS |IO_L64N_D9_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N7 | | |VCCO_2 | | |2 | | | | |3.30 | | | |
|
||||
|N7 | | |VCCO_2 | | |2 | | | | |any******| | | |
|
||||
|N8 | |IOBS |IO_L29N_GCLK2_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N9 | |IOBM |IO_L14P_D11_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N10 | | |VCCO_2 | | |2 | | | | |3.30 | | | |
|
||||
|N10 | | |VCCO_2 | | |2 | | | | |any******| | | |
|
||||
|N11 | |IOBM |IO_L13P_M1_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N12 | |IOBM |IO_L12P_D1_MISO2_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N13 | | |GND | | | | | | | | | | | |
|
||||
|N14 | |IOBM |IO_L45P_A1_M1LDQS_1 |UNUSED | |1 | | | | | | | | |
|
||||
|N15 | | |VCCO_1 | | |1 | | | | |any******| | | |
|
||||
|N16 | |IOBS |IO_L45N_A0_M1LDQSN_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P1 |FSB_A<8> |IOB |IO_L33N_M3DQ13_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|P2 |FSB_A<7> |IOB |IO_L33P_M3DQ12_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|P1 |FSB_A<7> |IOB |IO_L33N_M3DQ13_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|P2 |FSB_A<12> |IOB |IO_L33P_M3DQ12_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|P3 | | |GND | | | | | | | | | | | |
|
||||
|P4 | |IOBM |IO_L63P_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P5 | |IOBS |IO_L49N_D4_2 |UNUSED | |2 | | | | | | | | |
|
||||
@ -244,14 +244,14 @@ Pinout by Pin Number:
|
||||
|P14 | | |SUSPEND | | | | | | | | | | | |
|
||||
|P15 | |IOBM |IO_L48P_HDC_M1DQ8_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P16 | |IOBS |IO_L48N_M1DQ9_1 |UNUSED | |1 | | | | | | | | |
|
||||
|R1 |FSB_A<6> |IOB |IO_L32N_M3DQ15_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|R2 |FSB_A<5> |IOB |IO_L32P_M3DQ14_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|R1 |FSB_A<9> |IOB |IO_L32N_M3DQ15_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|R2 |FSB_A<3> |IOB |IO_L32P_M3DQ14_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE |
|
||||
|R3 | |IOBM |IO_L65P_INIT_B_2 |UNUSED | |2 | | | | | | | | |
|
||||
|R4 | | |VCCO_2 | | |2 | | | | |3.30 | | | |
|
||||
|R4 | | |VCCO_2 | | |2 | | | | |any******| | | |
|
||||
|R5 | |IOBM |IO_L48P_D7_2 |UNUSED | |2 | | | | | | | | |
|
||||
|R6 | | |GND | | | | | | | | | | | |
|
||||
|R7 |IOB_nHALT |IOB |IO_L32P_GCLK29_2 |INPUT |LVCMOS33 |2 | | | |NONE | |UNLOCATED |YES |NONE |
|
||||
|R8 | | |VCCO_2 | | |2 | | | | |3.30 | | | |
|
||||
|R7 | |IOBM |IO_L32P_GCLK29_2 |UNUSED | |2 | | | | | | | | |
|
||||
|R8 | | |VCCO_2 | | |2 | | | | |any******| | | |
|
||||
|R9 | |IOBM |IO_L23P_2 |UNUSED | |2 | | | | | | | | |
|
||||
|R10 | | |GND | | | | | | | | | | | |
|
||||
|R11 | |IOBM |IO_L1P_CCLK_2 |UNUSED | |2 | | | | | | | | |
|
||||
@ -266,7 +266,7 @@ Pinout by Pin Number:
|
||||
|T4 | |IOBS |IO_L63N_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T5 | |IOBS |IO_L48N_RDWR_B_VREF_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T6 | |IOBS |IO_L47N_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T7 |FPUCLK |IOB |IO_L32N_GCLK28_2 |OUTPUT |LVCMOS33 |2 |24 |FAST | | | |UNLOCATED |YES |NONE |
|
||||
|T7 | |IOBS |IO_L32N_GCLK28_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T8 | |IOBS |IO_L30N_GCLK0_USERCCLK_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T9 | |IOBS |IO_L23N_2 |UNUSED | |2 | | | | | | | | |
|
||||
|T10 | |IOBS |IO_L3N_MOSI_CSI_B_MISO0_2 |UNUSED | |2 | | | | | | | | |
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="par" timeStamp="Fri Oct 29 10:03:05 2021">
|
||||
<application stringID="par" timeStamp="Fri Oct 29 17:59:52 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@ -63,8 +63,8 @@
|
||||
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="2 secs "/>
|
||||
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
|
||||
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
|
||||
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="2 secs "/>
|
||||
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="2 secs "/>
|
||||
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="3 secs "/>
|
||||
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="3 secs "/>
|
||||
</section>
|
||||
</task>
|
||||
<task stringID="PAR_par">
|
||||
@ -79,39 +79,22 @@
|
||||
<column label="Net Skew(ns)" stringID="NET_SKEW"/>
|
||||
<column label="Max Delay(ns)" stringID="MAX_DELAY"/>
|
||||
<row stringID="row" value="1">
|
||||
<item label="Clock Net" stringID="CLOCK_NET" value="instance_name/clkfb_bufg_out"/>
|
||||
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
|
||||
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y3"/>
|
||||
<item label="Locked" stringID="LOCKED" value="No"/>
|
||||
<item dataType="float" label="Fanout" stringID="FANOUT" value="2.000000"/>
|
||||
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
|
||||
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.163000"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item label="Clock Net" stringID="CLOCK_NET" value="CPUCLKi"/>
|
||||
<item label="Clock Net" stringID="CLOCK_NET" value="CLKGEN_inst/instance_name/clkfb_bufg_out"/>
|
||||
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
|
||||
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y13"/>
|
||||
<item label="Locked" stringID="LOCKED" value="No"/>
|
||||
<item dataType="float" label="Fanout" stringID="FANOUT" value="3.000000"/>
|
||||
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.633000"/>
|
||||
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.069000"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item label="Clock Net" stringID="CLOCK_NET" value="FSBCLK"/>
|
||||
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
|
||||
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y2"/>
|
||||
<item label="Locked" stringID="LOCKED" value="No"/>
|
||||
<item dataType="float" label="Fanout" stringID="FANOUT" value="21.000000"/>
|
||||
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.728000"/>
|
||||
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.163000"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item label="Clock Net" stringID="CLOCK_NET" value="LE"/>
|
||||
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
|
||||
<item label="Resource" stringID="RESOURCE" value="Local"/>
|
||||
<item dataType="float" label="Fanout" stringID="FANOUT" value="2.000000"/>
|
||||
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
|
||||
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.979000"/>
|
||||
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.077000"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item label="Clock Net" stringID="CLOCK_NET" value="FSBCLK"/>
|
||||
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
|
||||
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y3"/>
|
||||
<item label="Locked" stringID="LOCKED" value="No"/>
|
||||
<item dataType="float" label="Fanout" stringID="FANOUT" value="17.000000"/>
|
||||
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.700000"/>
|
||||
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.135000"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
@ -138,17 +121,10 @@
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="A2"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="CLKFB_OUT"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOBS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L52N_M3A9_3"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="24"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="FAST"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="A3"/>
|
||||
@ -258,17 +234,10 @@
|
||||
</row>
|
||||
<row stringID="row" value="18">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="B2"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="RAM_CLK01"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOBM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L52P_M3A8_3"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="24"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="FAST"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="19">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="B3"/>
|
||||
@ -361,7 +330,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="33">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="C1"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="CPU_nDSACK"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FPUCLK"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L50P_M3WE_3"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
@ -370,32 +339,32 @@
|
||||
<item label="Drive
(mA)" stringID="Drive" value="24"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="FAST"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="34">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="C2"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="CPU_nSTERM"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="INt"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L48N_M3BA1_3"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="24"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="FAST"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="NONE"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="35">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="C3"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_FC<2>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="OUTt"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L48P_M3BA0_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="NONE"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="24"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="FAST"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
@ -487,15 +456,16 @@
|
||||
</row>
|
||||
<row stringID="row" value="49">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="D1"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_RnW"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="RAMCLK0"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L49N_M3A2_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="NONE"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="24"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="FAST"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="50">
|
||||
@ -506,15 +476,16 @@
|
||||
</row>
|
||||
<row stringID="row" value="51">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="D3"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="CPU_nAS"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="RAMCLK1"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L49P_M3A7_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="NONE"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="24"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="FAST"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="52">
|
||||
@ -601,21 +572,20 @@
|
||||
</row>
|
||||
<row stringID="row" value="65">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="E1"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="nFPUCS"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<27>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L46N_M3CLKN_3"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="24"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="FAST"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="NONE"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="66">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="E2"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<31>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<24>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L46P_M3CLK_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -718,7 +688,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="81">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="F1"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<27>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<23>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L41N_GCLK26_M3DQ5_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -731,7 +701,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="82">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="F2"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<25>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<22>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L41P_GCLK27_M3DQ4_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -744,17 +714,10 @@
|
||||
</row>
|
||||
<row stringID="row" value="83">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="F3"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="nRESOE"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOBS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L53N_M3A12_3"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="2"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="QUIETIO"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="84">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="F4"/>
|
||||
@ -845,7 +808,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="97">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="G1"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<15>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<29>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L40N_M3DQ7_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -862,7 +825,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="99">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="G3"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<16>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<19>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L40P_M3DQ6_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -881,27 +844,21 @@
|
||||
</row>
|
||||
<row stringID="row" value="101">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="G5"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="CPUCLKIN"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOBS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L51N_M3A4_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="NONE"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="102">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="G6"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="CPU_nBERR"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="CLKFB_OUT"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L51P_M3A10_3"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="2"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="24"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="FAST"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
@ -965,7 +922,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="113">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="H1"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<20>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<26>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L39N_M3LDQSN_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -978,7 +935,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="114">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="H2"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<22>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<25>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L39P_M3LDQS_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -991,7 +948,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="115">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="H3"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<28>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="CPU_nAS"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L44N_GCLK20_M3A6_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1017,7 +974,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="117">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="H5"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<19>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<30>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L43N_GCLK22_IRDY2_M3CASN_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1092,7 +1049,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="129">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="J1"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<23>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<17>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L38N_M3DQ3_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1111,7 +1068,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="131">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="J3"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<17>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<16>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L38P_M3DQ2_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1141,7 +1098,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="134">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="J6"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<26>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<21>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L43P_GCLK23_M3RASN_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1214,7 +1171,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="145">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="K1"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<21>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<5>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L37N_M3DQ1_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1227,7 +1184,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="146">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="K2"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<24>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<14>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L37P_M3DQ0_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1240,7 +1197,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="147">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="K3"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<18>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<28>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L42P_GCLK25_TRDY2_M3UDM_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1259,7 +1216,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="149">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="K5"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_FC<0>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="CPUCLKi"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L47P_M3A0_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1272,7 +1229,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="150">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="K6"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_FC<1>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<18>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L47N_M3A1_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1344,7 +1301,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="161">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="L1"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<14>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<11>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L36N_M3DQ9_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1361,7 +1318,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="163">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="L3"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<13>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<4>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L36P_M3DQ8_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1374,7 +1331,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="164">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="L4"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<29>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<31>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L45P_M3A3_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1387,7 +1344,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="165">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="L5"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<30>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<20>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L45N_M3ODT_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1467,7 +1424,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="177">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="M1"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<12>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<1>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L35N_M3DQ11_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1480,7 +1437,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="178">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="M2"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<11>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<2>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L35P_M3DQ10_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1493,7 +1450,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="179">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="M3"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<2>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<6>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L1N_VREF_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1506,7 +1463,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="180">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="M4"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<1>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<8>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L1P_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1519,7 +1476,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="181">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="M5"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<3>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<15>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L2P_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1625,7 +1582,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="195">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="N3"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<9>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<13>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L34P_M3UDQS_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1638,7 +1595,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="196">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="N4"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<4>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<0>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L2N_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1667,7 +1624,7 @@
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="N7"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_2"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
<item label="Voltage" stringID="Voltage" value="3.30"/>
|
||||
<item label="Voltage" stringID="Voltage" value="any******"/>
|
||||
</row>
|
||||
<row stringID="row" value="200">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="N8"/>
|
||||
@ -1687,7 +1644,7 @@
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="N10"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_2"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
<item label="Voltage" stringID="Voltage" value="3.30"/>
|
||||
<item label="Voltage" stringID="Voltage" value="any******"/>
|
||||
</row>
|
||||
<row stringID="row" value="203">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="N11"/>
|
||||
@ -1729,7 +1686,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="209">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P1"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<8>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<7>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L33N_M3DQ13_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1742,7 +1699,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="210">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P2"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<7>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<12>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L33P_M3DQ12_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1844,7 +1801,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="225">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="R1"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<6>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<9>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L32N_M3DQ15_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1857,7 +1814,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="226">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="R2"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<5>"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FSB_A<3>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L32P_M3DQ14_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
@ -1879,7 +1836,7 @@
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="R4"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_2"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
<item label="Voltage" stringID="Voltage" value="3.30"/>
|
||||
<item label="Voltage" stringID="Voltage" value="any******"/>
|
||||
</row>
|
||||
<row stringID="row" value="229">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="R5"/>
|
||||
@ -1894,22 +1851,16 @@
|
||||
</row>
|
||||
<row stringID="row" value="231">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="R7"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="IOB_nHALT"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOBM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L32P_GCLK29_2"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="NONE"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="232">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="R8"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_2"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
<item label="Voltage" stringID="Voltage" value="3.30"/>
|
||||
<item label="Voltage" stringID="Voltage" value="any******"/>
|
||||
</row>
|
||||
<row stringID="row" value="233">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="R9"/>
|
||||
@ -2001,17 +1952,10 @@
|
||||
</row>
|
||||
<row stringID="row" value="247">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="T7"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="FPUCLK"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOBS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L32N_GCLK28_2"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="24"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="FAST"/>
|
||||
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="248">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="T8"/>
|
||||
@ -2088,7 +2032,7 @@
|
||||
</task>
|
||||
</application>
|
||||
|
||||
<application stringID="Par" timeStamp="Fri Oct 29 10:03:05 2021">
|
||||
<application stringID="Par" timeStamp="Fri Oct 29 17:59:52 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@ -2134,16 +2078,16 @@
|
||||
</section>
|
||||
<task label="Device Utilization Summary" stringID="PAR_DEVICE_UTLIZATION">
|
||||
<section stringID="PAR_SLICE_REPORTING">
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="56">
|
||||
<item dataType="int" stringID="PAR_NUM_SLICE_FF" value="56"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="34">
|
||||
<item dataType="int" stringID="PAR_NUM_SLICE_FF" value="34"/>
|
||||
<item dataType="int" stringID="PAR_NUM_SLICE_LATCH" value="0"/>
|
||||
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
|
||||
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="59">
|
||||
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="29"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="24"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="3"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="17">
|
||||
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="11"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="2"/>
|
||||
<item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/>
|
||||
@ -2156,29 +2100,29 @@
|
||||
<item dataType="int" stringID="PAR_NUM_SRL_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="PAR_NUM_SRL_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="PAR_NUM_SRL_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="1"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="2"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="0"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="4"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LUT_RT_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="2"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="1"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="4"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
|
||||
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="1430" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="25">
|
||||
<item AVAILABLE="355" dataType="int" stringID="PAR_NUM_SLICEL" value="14"/>
|
||||
<item AVAILABLE="1430" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="11">
|
||||
<item AVAILABLE="355" dataType="int" stringID="PAR_NUM_SLICEL" value="3"/>
|
||||
<item AVAILABLE="360" dataType="int" stringID="PAR_NUM_SLICEM" value="0"/>
|
||||
<item AVAILABLE="715" dataType="int" stringID="PAR_NUM_SLICEX" value="11"/>
|
||||
<item AVAILABLE="715" dataType="int" stringID="PAR_NUM_SLICEX" value="8"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="76">
|
||||
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="22"/>
|
||||
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="17"/>
|
||||
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="37"/>
|
||||
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="41">
|
||||
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="11"/>
|
||||
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="24"/>
|
||||
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="6"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="PAR_IOB_REPORTING">
|
||||
<item AVAILABLE="186" dataType="int" stringID="PAR_AGG_BONDED_IO" value="49"/>
|
||||
<item AVAILABLE="186" dataType="int" stringID="PAR_AGG_BONDED_IO" value="43"/>
|
||||
<item AVAILABLE="14" dataType="int" stringID="PAR_AGG_UNBONDED_IO" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_FF" value="5"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_LATCH" value="1"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_LATCH" value="0"/>
|
||||
<item AVAILABLE="7" dataType="int" stringID="PAR_NUM_IOBM" value="0"/>
|
||||
<item AVAILABLE="93" dataType="int" stringID="PAR_NUM_BONDED_IOBM" value="0"/>
|
||||
<item AVAILABLE="7" dataType="int" stringID="PAR_NUM_IOBS" value="0"/>
|
||||
@ -2210,7 +2154,7 @@
|
||||
<item AVAILABLE="1" dataType="int" stringID="PAR_NUM_SUSPEND_SYNC" value="0"/>
|
||||
</section>
|
||||
<section stringID="PAR_BUFG_DATA">
|
||||
<item dataType="int" stringID="PAR_NUM_BUFG" value="3"/>
|
||||
<item dataType="int" stringID="PAR_NUM_BUFG" value="2"/>
|
||||
<item dataType="int" stringID="PAR_NUM_BUFGMUX" value="0"/>
|
||||
<item dataType="int" stringID="PAR_AVAILABLE" value="16"/>
|
||||
</section>
|
||||
|
||||
@ -16,7 +16,6 @@ Environment Variable Effect
|
||||
NONE No environment variables were set
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
|
||||
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
|
||||
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
|
||||
option. All paths that are not constrained will be reported in the
|
||||
@ -29,6 +28,521 @@ INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
||||
and for more information on accounting for different loading conditions,
|
||||
please see the device datasheet.
|
||||
|
||||
================================================================================
|
||||
Timing constraint: NET "FSBCLK" PERIOD = 10 ns HIGH 50%;
|
||||
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
||||
0 timing errors detected. (0 component switching limit errors)
|
||||
Minimum period is 1.866ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Component Switching Limit Checks: NET "FSBCLK" PERIOD = 10 ns HIGH 50%;
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 8.134ns (period - min period limit)
|
||||
Period: 10.000ns
|
||||
Min period limit: 1.866ns (535.906MHz) (Tickper)
|
||||
Physical resource: OUTt_OBUF/CLK0
|
||||
Logical resource: OUTt/CLK0
|
||||
Location pin: ILOGIC_X0Y5.CLK0
|
||||
Clock network: FSBCLK
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
================================================================================
|
||||
Timing constraint: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
||||
0 timing errors detected. (0 component switching limit errors)
|
||||
Minimum period is 5.000ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Component Switching Limit Checks: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 15.000ns (period - (min low pulse limit / (low pulse / period)))
|
||||
Period: 20.000ns
|
||||
Low pulse: 10.000ns
|
||||
Low pulse limit: 2.500ns (Tdcmpw_CLKIN_50_100)
|
||||
Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
|
||||
Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
|
||||
Location pin: PLL_ADV_X0Y1.CLKIN1
|
||||
Clock network: instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 15.000ns (period - (min high pulse limit / (high pulse / period)))
|
||||
Period: 20.000ns
|
||||
High pulse: 10.000ns
|
||||
High pulse limit: 2.500ns (Tdcmpw_CLKIN_50_100)
|
||||
Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
|
||||
Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
|
||||
Location pin: PLL_ADV_X0Y1.CLKIN1
|
||||
Clock network: instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 17.780ns (period - min period limit)
|
||||
Period: 20.000ns
|
||||
Min period limit: 2.220ns (450.450MHz) (Tpllper_CLKIN(Finmax))
|
||||
Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
|
||||
Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1
|
||||
Location pin: PLL_ADV_X0Y1.CLKIN1
|
||||
Clock network: instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
================================================================================
|
||||
Timing constraint: PERIOD analysis for net "instance_name/clkfbout" derived
|
||||
from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected
|
||||
to 20 nS HIGH 10 nS
|
||||
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
||||
0 timing errors detected. (0 component switching limit errors)
|
||||
Minimum period is 2.666ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkfbout" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
duty cycle corrected to 20 nS HIGH 10 nS
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 17.334ns (period - min period limit)
|
||||
Period: 20.000ns
|
||||
Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
|
||||
Physical resource: instance_name/clkfbout_bufg/I0
|
||||
Logical resource: instance_name/clkfbout_bufg/I0
|
||||
Location pin: BUFGMUX_X2Y3.I0
|
||||
Clock network: instance_name/clkfbout
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 17.751ns (period - min period limit)
|
||||
Period: 20.000ns
|
||||
Min period limit: 2.249ns (444.642MHz) (Tockper)
|
||||
Physical resource: CLKFB_OUT_OBUF/CLK0
|
||||
Logical resource: instance_name/clkfbout_oddr/CK0
|
||||
Location pin: OLOGIC_X0Y7.CLK0
|
||||
Clock network: instance_name/clkfb_bufg_out
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 17.780ns (period - min period limit)
|
||||
Period: 20.000ns
|
||||
Min period limit: 2.220ns (450.450MHz) (Tpllper_CLKFB)
|
||||
Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKFBOUT
|
||||
Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKFBOUT
|
||||
Location pin: PLL_ADV_X0Y1.CLKFBOUT
|
||||
Clock network: instance_name/clkfbout
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
================================================================================
|
||||
Timing constraint: PERIOD analysis for net "instance_name/clkout0" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS
|
||||
|
||||
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
||||
0 timing errors detected. (0 component switching limit errors)
|
||||
Minimum period is 2.666ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout0" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
divided by 2.00 to 10 nS
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 7.334ns (period - min period limit)
|
||||
Period: 10.000ns
|
||||
Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
|
||||
Physical resource: instance_name/clkout1_buf/I0
|
||||
Logical resource: instance_name/clkout1_buf/I0
|
||||
Location pin: BUFGMUX_X3Y13.I0
|
||||
Clock network: instance_name/clkout0
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 8.948ns (period - min period limit)
|
||||
Period: 10.000ns
|
||||
Min period limit: 1.052ns (950.570MHz) (Tpllper_CLKOUT(Foutmax))
|
||||
Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKOUT0
|
||||
Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKOUT0
|
||||
Location pin: PLL_ADV_X0Y1.CLKOUT0
|
||||
Clock network: instance_name/clkout0
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 310.000ns (max period limit - period)
|
||||
Period: 10.000ns
|
||||
Max period limit: 320.000ns (3.125MHz) (Tpllper_CLKOUT(Foutmin))
|
||||
Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKOUT0
|
||||
Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKOUT0
|
||||
Location pin: PLL_ADV_X0Y1.CLKOUT0
|
||||
Clock network: instance_name/clkout0
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
================================================================================
|
||||
Timing constraint: COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP
|
||||
"CLKIN";
|
||||
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
|
||||
0 timing errors detected. (0 setup errors, 0 hold errors)
|
||||
Minimum allowable offset is 9.880ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point OUTt (ILOGIC_X0Y5.SR), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 0.120ns (requirement - (data path - clock path - clock arrival + uncertainty))
|
||||
Source: CPU_nAS (PAD)
|
||||
Destination: OUTt (FF)
|
||||
Destination Clock: FSBCLK rising at 0.000ns
|
||||
Requirement: 10.000ns
|
||||
Data Path Delay: 4.575ns (Levels of Logic = 1)
|
||||
Clock Path Delay: -4.891ns (Levels of Logic = 4)
|
||||
Clock Uncertainty: 0.414ns
|
||||
|
||||
Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.050ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.267ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: CPU_nAS to OUTt
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
N4.I Tiopi 1.557 CPU_nAS
|
||||
CPU_nAS
|
||||
CPU_nAS_IBUF
|
||||
ProtoComp0.IMUX.1
|
||||
ILOGIC_X0Y5.SR net (fanout=1) e 2.043 CPU_nAS_IBUF
|
||||
ILOGIC_X0Y5.CLK0 Tisrck 0.975 OUTt_OBUF
|
||||
OUTt
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 4.575ns (2.532ns logic, 2.043ns route)
|
||||
(55.3% logic, 44.7% route)
|
||||
|
||||
Minimum Clock Path at Slow Process Corner: CLKIN to OUTt
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
J4.I Tiopi 0.902 CLKIN
|
||||
CLKIN
|
||||
instance_name/clkin1_buf
|
||||
ProtoComp0.IMUX.3
|
||||
BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1
|
||||
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
||||
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
||||
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
||||
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 instance_name/pll_base_inst/PLL_ADV
|
||||
instance_name/pll_base_inst/PLL_ADV
|
||||
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0
|
||||
BUFGMUX_X3Y13.O Tgi0o 0.197 instance_name/clkout1_buf
|
||||
instance_name/clkout1_buf
|
||||
ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK
|
||||
------------------------------------------------- ---------------------------
|
||||
Total -4.891ns (-6.970ns logic, 2.079ns route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Hold Paths: COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point OUTt (ILOGIC_X0Y5.SR), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (hold path): 6.650ns (requirement - (clock path + clock arrival + uncertainty - data path))
|
||||
Source: CPU_nAS (PAD)
|
||||
Destination: OUTt (FF)
|
||||
Destination Clock: FSBCLK rising at 0.000ns
|
||||
Requirement: 1.000ns
|
||||
Data Path Delay: 2.965ns (Levels of Logic = 1)
|
||||
Clock Path Delay: -3.099ns (Levels of Logic = 4)
|
||||
Clock Uncertainty: 0.414ns
|
||||
|
||||
Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.050ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.267ns
|
||||
|
||||
Minimum Data Path at Fast Process Corner: CPU_nAS to OUTt
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
N4.I Tiopi 0.763 CPU_nAS
|
||||
CPU_nAS
|
||||
CPU_nAS_IBUF
|
||||
ProtoComp0.IMUX.1
|
||||
ILOGIC_X0Y5.SR net (fanout=1) e 2.043 CPU_nAS_IBUF
|
||||
ILOGIC_X0Y5.CLK0 Ticksr (-Th) -0.159 OUTt_OBUF
|
||||
OUTt
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 2.965ns (0.922ns logic, 2.043ns route)
|
||||
(31.1% logic, 68.9% route)
|
||||
|
||||
Maximum Clock Path at Fast Process Corner: CLKIN to OUTt
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
J4.I Tiopi 0.367 CLKIN
|
||||
CLKIN
|
||||
instance_name/clkin1_buf
|
||||
ProtoComp0.IMUX.3
|
||||
BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1
|
||||
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
||||
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
||||
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
||||
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 instance_name/pll_base_inst/PLL_ADV
|
||||
instance_name/pll_base_inst/PLL_ADV
|
||||
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0
|
||||
BUFGMUX_X3Y13.O Tgi0o 0.063 instance_name/clkout1_buf
|
||||
instance_name/clkout1_buf
|
||||
ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK
|
||||
------------------------------------------------- ---------------------------
|
||||
Total -3.099ns (-5.178ns logic, 2.079ns route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
================================================================================
|
||||
Timing constraint: COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP
|
||||
"CLKIN";
|
||||
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
|
||||
0 timing errors detected. (0 setup errors, 0 hold errors)
|
||||
Minimum allowable offset is 8.814ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point OUTt (ILOGIC_X0Y5.D), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 1.186ns (requirement - (data path - clock path - clock arrival + uncertainty))
|
||||
Source: INt (PAD)
|
||||
Destination: OUTt (FF)
|
||||
Destination Clock: FSBCLK rising at 0.000ns
|
||||
Requirement: 10.000ns
|
||||
Data Path Delay: 3.509ns (Levels of Logic = 2)
|
||||
Clock Path Delay: -4.891ns (Levels of Logic = 4)
|
||||
Clock Uncertainty: 0.414ns
|
||||
|
||||
Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.050ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.267ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: INt to OUTt
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
M4.I Tiopi 1.557 INt
|
||||
INt
|
||||
INt_IBUF
|
||||
ProtoComp0.IMUX.2
|
||||
ILOGIC_X0Y5.D net (fanout=1) e 0.229 CPU_nAS_INt_AND_1_o_norst
|
||||
ILOGIC_X0Y5.CLK0 Tidock 1.723 OUTt_OBUF
|
||||
ProtoComp3.D2OFFBYP_SRC
|
||||
OUTt
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 3.509ns (3.280ns logic, 0.229ns route)
|
||||
(93.5% logic, 6.5% route)
|
||||
|
||||
Minimum Clock Path at Slow Process Corner: CLKIN to OUTt
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
J4.I Tiopi 0.902 CLKIN
|
||||
CLKIN
|
||||
instance_name/clkin1_buf
|
||||
ProtoComp0.IMUX.3
|
||||
BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1
|
||||
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
||||
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
||||
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
||||
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 instance_name/pll_base_inst/PLL_ADV
|
||||
instance_name/pll_base_inst/PLL_ADV
|
||||
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0
|
||||
BUFGMUX_X3Y13.O Tgi0o 0.197 instance_name/clkout1_buf
|
||||
instance_name/clkout1_buf
|
||||
ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK
|
||||
------------------------------------------------- ---------------------------
|
||||
Total -4.891ns (-6.970ns logic, 2.079ns route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Hold Paths: COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point OUTt (ILOGIC_X0Y5.D), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (hold path): 5.307ns (requirement - (clock path + clock arrival + uncertainty - data path))
|
||||
Source: INt (PAD)
|
||||
Destination: OUTt (FF)
|
||||
Destination Clock: FSBCLK rising at 0.000ns
|
||||
Requirement: 1.000ns
|
||||
Data Path Delay: 1.622ns (Levels of Logic = 2)
|
||||
Clock Path Delay: -3.099ns (Levels of Logic = 4)
|
||||
Clock Uncertainty: 0.414ns
|
||||
|
||||
Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.050ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.267ns
|
||||
|
||||
Minimum Data Path at Fast Process Corner: INt to OUTt
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
M4.I Tiopi 0.763 INt
|
||||
INt
|
||||
INt_IBUF
|
||||
ProtoComp0.IMUX.2
|
||||
ILOGIC_X0Y5.D net (fanout=1) e 0.229 CPU_nAS_INt_AND_1_o_norst
|
||||
ILOGIC_X0Y5.CLK0 Tiockd (-Th) -0.630 OUTt_OBUF
|
||||
ProtoComp3.D2OFFBYP_SRC
|
||||
OUTt
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 1.622ns (1.393ns logic, 0.229ns route)
|
||||
(85.9% logic, 14.1% route)
|
||||
|
||||
Maximum Clock Path at Fast Process Corner: CLKIN to OUTt
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
J4.I Tiopi 0.367 CLKIN
|
||||
CLKIN
|
||||
instance_name/clkin1_buf
|
||||
ProtoComp0.IMUX.3
|
||||
BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1
|
||||
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
||||
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
||||
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
||||
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 instance_name/pll_base_inst/PLL_ADV
|
||||
instance_name/pll_base_inst/PLL_ADV
|
||||
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0
|
||||
BUFGMUX_X3Y13.O Tgi0o 0.063 instance_name/clkout1_buf
|
||||
instance_name/clkout1_buf
|
||||
ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK
|
||||
------------------------------------------------- ---------------------------
|
||||
Total -3.099ns (-5.178ns logic, 2.079ns route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
================================================================================
|
||||
Timing constraint: COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN";
|
||||
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
|
||||
0 timing errors detected.
|
||||
Minimum allowable offset is 1.412ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point OUTt (M3.PAD), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (slowest paths): 2.588ns (requirement - (clock arrival + clock path + data path + uncertainty))
|
||||
Source: OUTt (FF)
|
||||
Destination: OUTt (PAD)
|
||||
Source Clock: FSBCLK rising at 0.000ns
|
||||
Requirement: 4.000ns
|
||||
Data Path Delay: 6.068ns (Levels of Logic = 1)
|
||||
Clock Path Delay: -5.070ns (Levels of Logic = 4)
|
||||
Clock Uncertainty: 0.414ns
|
||||
|
||||
Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.050ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.267ns
|
||||
|
||||
Maximum Clock Path at Slow Process Corner: CLKIN to OUTt
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
J4.I Tiopi 1.037 CLKIN
|
||||
CLKIN
|
||||
instance_name/clkin1_buf
|
||||
ProtoComp0.IMUX.3
|
||||
BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1
|
||||
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
||||
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
||||
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
||||
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.585 instance_name/pll_base_inst/PLL_ADV
|
||||
instance_name/pll_base_inst/PLL_ADV
|
||||
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0
|
||||
BUFGMUX_X3Y13.O Tgi0o 0.209 instance_name/clkout1_buf
|
||||
instance_name/clkout1_buf
|
||||
ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK
|
||||
------------------------------------------------- ---------------------------
|
||||
Total -5.070ns (-7.149ns logic, 2.079ns route)
|
||||
|
||||
Maximum Data Path at Slow Process Corner: OUTt to OUTt
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
ILOGIC_X0Y5.Q4 Tickq 1.778 OUTt_OBUF
|
||||
OUTt
|
||||
M3.O net (fanout=1) e 2.308 OUTt_OBUF
|
||||
M3.PAD Tioop 1.982 OUTt
|
||||
OUTt_OBUF
|
||||
OUTt
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 6.068ns (3.760ns logic, 2.308ns route)
|
||||
(62.0% logic, 38.0% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Fastest Paths: COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN";
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point OUTt (M3.PAD), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Delay (fastest paths): 0.213ns (clock arrival + clock path + data path - uncertainty)
|
||||
Source: OUTt (FF)
|
||||
Destination: OUTt (PAD)
|
||||
Source Clock: FSBCLK rising at 0.000ns
|
||||
Data Path Delay: 3.663ns (Levels of Logic = 1)
|
||||
Clock Path Delay: -3.036ns (Levels of Logic = 4)
|
||||
Clock Uncertainty: 0.414ns
|
||||
|
||||
Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.050ns
|
||||
Discrete Jitter (DJ): 0.287ns
|
||||
Phase Error (PE): 0.267ns
|
||||
|
||||
Minimum Clock Path at Fast Process Corner: CLKIN to OUTt
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
J4.I Tiopi 0.321 CLKIN
|
||||
CLKIN
|
||||
instance_name/clkin1_buf
|
||||
ProtoComp0.IMUX.3
|
||||
BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1
|
||||
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
||||
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
||||
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
||||
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.617 instance_name/pll_base_inst/PLL_ADV
|
||||
instance_name/pll_base_inst/PLL_ADV
|
||||
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0
|
||||
BUFGMUX_X3Y13.O Tgi0o 0.059 instance_name/clkout1_buf
|
||||
instance_name/clkout1_buf
|
||||
ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK
|
||||
------------------------------------------------- ---------------------------
|
||||
Total -3.036ns (-5.115ns logic, 2.079ns route)
|
||||
|
||||
Minimum Data Path at Fast Process Corner: OUTt to OUTt
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
ILOGIC_X0Y5.Q4 Tickq 0.656 OUTt_OBUF
|
||||
OUTt
|
||||
M3.O net (fanout=1) e 2.308 OUTt_OBUF
|
||||
M3.PAD Tioop 0.699 OUTt
|
||||
OUTt_OBUF
|
||||
OUTt
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 3.663ns (1.355ns logic, 2.308ns route)
|
||||
(37.0% logic, 63.0% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Derived Constraint Report
|
||||
Derived Constraints for instance_name/clkin1
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
| | Period | Actual Period | Timing Errors | Paths Analyzed |
|
||||
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|
||||
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|instance_name/clkin1 | 20.000ns| 5.000ns| 5.332ns| 0| 0| 0| 0|
|
||||
| instance_name/clkfbout | 20.000ns| 2.666ns| N/A| 0| 0| 0| 0|
|
||||
| instance_name/clkout0 | 10.000ns| 2.666ns| N/A| 0| 0| 0| 0|
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|
||||
All constraints were met.
|
||||
|
||||
|
||||
Data Sheet report:
|
||||
@ -40,114 +554,67 @@ Setup/Hold to clock CLKIN
|
||||
|Max Setup to| Process |Max Hold to | Process | | Clock |
|
||||
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
|
||||
------------+------------+------------+------------+------------+------------------+--------+
|
||||
FSB_A<0> | 13.023(R)| SLOW | -7.585(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<1> | 12.884(R)| SLOW | -7.431(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<2> | 12.631(R)| SLOW | -7.394(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<3> | 12.641(R)| SLOW | -7.409(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<4> | 12.880(R)| SLOW | -7.561(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<5> | 12.741(R)| SLOW | -7.407(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<6> | 12.296(R)| SLOW | -7.155(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<7> | 12.306(R)| SLOW | -7.170(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<8> | 12.539(R)| SLOW | -7.316(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<9> | 12.400(R)| SLOW | -7.162(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<10> | 11.961(R)| SLOW | -6.916(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<11> | 12.140(R)| SLOW | -7.100(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<12> | 11.370(R)| SLOW | -6.243(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<13> | 11.798(R)| SLOW | -6.633(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<14> | 11.760(R)| SLOW | -6.788(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<15> | 11.233(R)| SLOW | -6.266(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<16> | 11.974(R)| SLOW | -6.920(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<17> | 11.982(R)| SLOW | -6.936(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<18> | 11.664(R)| SLOW | -6.788(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<19> | 11.544(R)| SLOW | -6.696(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<20> | 11.618(R)| SLOW | -6.683(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<21> | 11.622(R)| SLOW | -6.672(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<22> | 11.438(R)| SLOW | -6.681(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<23> | 11.192(R)| SLOW | -6.440(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<24> | 11.518(R)| SLOW | -6.679(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<25> | 11.768(R)| SLOW | -6.914(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<26> | 11.702(R)| SLOW | -7.041(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<27> | 11.630(R)| SLOW | -6.974(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<28> | 11.573(R)| SLOW | -6.971(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<29> | 11.565(R)| SLOW | -6.929(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<30> | 11.495(R)| SLOW | -7.056(R)| FAST |FSBCLK | 0.000|
|
||||
FSB_A<31> | 11.352(R)| SLOW | -6.975(R)| FAST |FSBCLK | 0.000|
|
||||
CPU_nAS | 9.880(R)| SLOW | -5.650(R)| FAST |FSBCLK | 0.000|
|
||||
INt | 8.814(R)| SLOW | -4.307(R)| FAST |FSBCLK | 0.000|
|
||||
------------+------------+------------+------------+------------+------------------+--------+
|
||||
|
||||
Clock CLKIN to Pad
|
||||
------------+-----------------+------------+-----------------+------------+----------------------------+--------+
|
||||
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
|
||||
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
|
||||
------------+-----------------+------------+-----------------+------------+----------------------------+--------+
|
||||
CLKFB_OUT | -0.063(R)| FAST | -0.086(R)| SLOW |instance_name/clkfb_bufg_out| 0.000|
|
||||
| -0.057(F)| FAST | -0.086(F)| SLOW |instance_name/clkfb_bufg_out| 0.000|
|
||||
CPUCLK | -0.151(R)| FAST | -0.159(R)| SLOW |CPUCLKi | 0.000|
|
||||
CPU_nDSACK | 2.827(R)| FAST | 2.128(R)| SLOW |FSBCLK | 0.000|
|
||||
CPU_nSTERM | 1.831(R)| FAST | 1.400(R)| SLOW |FSBCLK | 0.000|
|
||||
RAM_CLK01 | -0.063(R)| FAST | -0.086(R)| SLOW |FSBCLK | 0.000|
|
||||
| -0.057(F)| FAST | -0.086(F)| SLOW |FSBCLK | 0.000|
|
||||
nFPUCS | 2.114(R)| FAST | 1.715(R)| SLOW |CPUCLKi | 0.000|
|
||||
------------+-----------------+------------+-----------------+------------+----------------------------+--------+
|
||||
------------+-----------------+------------+-----------------+------------+------------------+--------+
|
||||
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
|
||||
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
|
||||
------------+-----------------+------------+-----------------+------------+------------------+--------+
|
||||
OUTt | 1.412(R)| SLOW | 0.213(R)| FAST |FSBCLK | 0.000|
|
||||
------------+-----------------+------------+-----------------+------------+------------------+--------+
|
||||
|
||||
Clock to Setup on destination clock CLKIN
|
||||
---------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
---------------+---------+---------+---------+---------+
|
||||
CLKIN | 2.278| 3.404| 1.399| |
|
||||
---------------+---------+---------+---------+---------+
|
||||
COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";
|
||||
Worst Case Data Window 4.230; Ideal Clock Offset To Actual Clock 3.265;
|
||||
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
||||
| | Process | | Process | Setup | Hold |Source Offset|
|
||||
Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center |
|
||||
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
||||
CPU_nAS | 9.880(R)| SLOW | -5.650(R)| FAST | 0.120| 6.650| -3.265|
|
||||
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
||||
Worst Case Summary| 9.880| - | -5.650| - | 0.120| 6.650| |
|
||||
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
||||
|
||||
Pad to Pad
|
||||
---------------+---------------+---------+
|
||||
Source Pad |Destination Pad| Delay |
|
||||
---------------+---------------+---------+
|
||||
CPU_nAS |nFPUCS | 9.241|
|
||||
FSB_A<0> |CPU_nDSACK | 11.438|
|
||||
FSB_A<1> |CPU_nDSACK | 11.056|
|
||||
FSB_A<2> |CPU_nDSACK | 10.934|
|
||||
FSB_A<3> |CPU_nDSACK | 11.272|
|
||||
FSB_A<4> |CPU_nDSACK | 10.959|
|
||||
FSB_A<5> |CPU_nDSACK | 10.647|
|
||||
FSB_A<6> |CPU_nDSACK | 11.009|
|
||||
FSB_A<7> |CPU_nDSACK | 10.884|
|
||||
FSB_A<8> |CPU_nDSACK | 10.427|
|
||||
FSB_A<9> |CPU_nDSACK | 10.796|
|
||||
FSB_A<10> |CPU_nDSACK | 10.296|
|
||||
FSB_A<11> |CPU_nDSACK | 9.984|
|
||||
FSB_A<12> |CPU_nDSACK | 10.429|
|
||||
FSB_A<13> |CPU_nDSACK | 10.457|
|
||||
FSB_A<13> |nFPUCS | 10.825|
|
||||
FSB_A<14> |CPU_nDSACK | 10.376|
|
||||
FSB_A<14> |nFPUCS | 11.030|
|
||||
FSB_A<15> |CPU_nDSACK | 10.288|
|
||||
FSB_A<15> |nFPUCS | 11.487|
|
||||
FSB_A<16> |CPU_nDSACK | 10.253|
|
||||
FSB_A<16> |nFPUCS | 12.145|
|
||||
FSB_A<17> |CPU_nDSACK | 9.855|
|
||||
FSB_A<17> |nFPUCS | 11.537|
|
||||
FSB_A<18> |CPU_nDSACK | 10.759|
|
||||
FSB_A<18> |nFPUCS | 10.887|
|
||||
FSB_A<19> |CPU_nDSACK | 10.601|
|
||||
FSB_A<19> |nFPUCS | 10.945|
|
||||
FSB_A<20> |CPU_nDSACK | 9.890|
|
||||
FSB_A<21> |CPU_nDSACK | 10.054|
|
||||
FSB_A<22> |CPU_nDSACK | 10.300|
|
||||
FSB_A<23> |CPU_nDSACK | 10.098|
|
||||
FSB_A<24> |CPU_nDSACK | 10.551|
|
||||
FSB_A<25> |CPU_nDSACK | 10.797|
|
||||
FSB_A<26> |CPU_nDSACK | 10.476|
|
||||
FSB_A<27> |CPU_nDSACK | 10.851|
|
||||
FSB_A<28> |CPU_nDSACK | 11.005|
|
||||
FSB_A<29> |CPU_nDSACK | 10.668|
|
||||
FSB_A<30> |CPU_nDSACK | 10.761|
|
||||
FSB_A<31> |CPU_nDSACK | 10.776|
|
||||
FSB_FC<0> |nFPUCS | 11.389|
|
||||
FSB_FC<1> |nFPUCS | 10.227|
|
||||
FSB_FC<2> |nFPUCS | 11.232|
|
||||
---------------+---------------+---------+
|
||||
COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";
|
||||
Worst Case Data Window 4.507; Ideal Clock Offset To Actual Clock 2.061;
|
||||
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
||||
| | Process | | Process | Setup | Hold |Source Offset|
|
||||
Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center |
|
||||
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
||||
INt | 8.814(R)| SLOW | -4.307(R)| FAST | 1.186| 5.307| -2.061|
|
||||
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
||||
Worst Case Summary| 8.814| - | -4.307| - | 1.186| 5.307| |
|
||||
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
||||
|
||||
COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN";
|
||||
Bus Skew: 0.000 ns;
|
||||
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
|
||||
|Max (slowest)| Process |Min (fastest)| Process | |
|
||||
PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)|
|
||||
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
|
||||
OUTt | 1.412| SLOW | 0.213| FAST | 0.000|
|
||||
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
|
||||
|
||||
|
||||
Analysis completed Fri Oct 29 08:28:45 2021
|
||||
Timing summary:
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
|
||||
|
||||
Constraints cover 3 paths, 0 nets, and 12 connections
|
||||
|
||||
Design statistics:
|
||||
Minimum period: 5.000ns{1} (Maximum frequency: 200.000MHz)
|
||||
Minimum input required time before clock: 9.880ns
|
||||
Minimum output required time after clock: 1.412ns
|
||||
|
||||
|
||||
------------------------------------Footnotes-----------------------------------
|
||||
1) The minimum period statistic assumes all single cycle delays.
|
||||
|
||||
Analysis completed Fri Oct 29 10:25:28 2021
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Trace Settings:
|
||||
|
||||
File diff suppressed because one or more lines are too long
345
fpga/WarpLC_preroute_2021-10-29-10-24-20.twx
Normal file
345
fpga/WarpLC_preroute_2021-10-29-10-24-20.twx
Normal file
@ -0,0 +1,345 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE twReport [
|
||||
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
|
||||
twDebug*, twFoot?, twClientInfo?)>
|
||||
<!ATTLIST twReport version CDATA "10,4">
|
||||
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
|
||||
<!ELEMENT twExecVer (#PCDATA)>
|
||||
<!ELEMENT twCopyright (#PCDATA)>
|
||||
<!ELEMENT twCmdLine (#PCDATA)>
|
||||
<!ELEMENT twDesign (#PCDATA)>
|
||||
<!ELEMENT twPCF (#PCDATA)>
|
||||
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
|
||||
<!ELEMENT twDevName (#PCDATA)>
|
||||
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
|
||||
<!ELEMENT twSpeedGrade (#PCDATA)>
|
||||
<!ELEMENT twSpeedVer (#PCDATA)>
|
||||
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
|
||||
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
|
||||
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
|
||||
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
|
||||
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
|
||||
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twItemLimit (#PCDATA)>
|
||||
<!ELEMENT twUnconst EMPTY>
|
||||
<!ELEMENT twUnconstLimit (#PCDATA)>
|
||||
<!ELEMENT twEnvVar EMPTY>
|
||||
<!ATTLIST twEnvVar name CDATA #REQUIRED>
|
||||
<!ATTLIST twEnvVar description CDATA #REQUIRED>
|
||||
<!ELEMENT twWarn (#PCDATA)>
|
||||
<!ELEMENT twInfo (#PCDATA)>
|
||||
<!ELEMENT twDebug (#PCDATA)>
|
||||
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
|
||||
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
|
||||
<!ELEMENT twProc (#PCDATA)>
|
||||
<!ELEMENT twTemp (#PCDATA)>
|
||||
<!ELEMENT twVolt (#PCDATA)>
|
||||
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
|
||||
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
|
||||
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twCycles (twSigConn+)>
|
||||
<!ATTLIST twCycles twNum CDATA #REQUIRED>
|
||||
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
|
||||
<!ELEMENT twSig (#PCDATA)>
|
||||
<!ELEMENT twDriver (#PCDATA)>
|
||||
<!ELEMENT twLoad (#PCDATA)>
|
||||
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
|
||||
<!ATTLIST twConst twConstType (NET |
|
||||
NETDELAY |
|
||||
NETSKEW |
|
||||
PATH |
|
||||
DEFPERIOD |
|
||||
UNCONSTPATH |
|
||||
DEFPATH |
|
||||
PATH2SETUP |
|
||||
UNCONSTPATH2SETUP |
|
||||
PATHCLASS |
|
||||
PATHDELAY |
|
||||
PERIOD |
|
||||
FREQUENCY |
|
||||
PATHBLOCK |
|
||||
OFFSET |
|
||||
OFFSETIN |
|
||||
OFFSETINCLOCK |
|
||||
UNCONSTOFFSETINCLOCK |
|
||||
OFFSETINDELAY |
|
||||
OFFSETINMOD |
|
||||
OFFSETOUT |
|
||||
OFFSETOUTCLOCK |
|
||||
UNCONSTOFFSETOUTCLOCK |
|
||||
OFFSETOUTDELAY |
|
||||
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
|
||||
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
|
||||
twEndPtCnt?,
|
||||
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
|
||||
<!ELEMENT twConstName (#PCDATA)>
|
||||
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
|
||||
<!ATTLIST twConstHead uID CDATA #IMPLIED>
|
||||
<!ELEMENT twItemCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCntEndPt (#PCDATA)>
|
||||
<!ELEMENT twErrCntSetup (#PCDATA)>
|
||||
<!ELEMENT twErrCntHold (#PCDATA)>
|
||||
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twEndPtCnt (#PCDATA)>
|
||||
<!ELEMENT twPathErrCnt (#PCDATA)>
|
||||
<!ELEMENT twMinPer (#PCDATA) >
|
||||
<!ELEMENT twFootnote EMPTY>
|
||||
<!ATTLIST twFootnote number CDATA #REQUIRED>
|
||||
<!ELEMENT twMaxDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFreq (#PCDATA)>
|
||||
<!ELEMENT twMinOff (#PCDATA)>
|
||||
<!ELEMENT twMaxOff (#PCDATA)>
|
||||
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
|
||||
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
|
||||
<!ELEMENT twTIGName (#PCDATA)>
|
||||
<!ELEMENT twInstantiated (#PCDATA)>
|
||||
<!ELEMENT twBlocked (#PCDATA)>
|
||||
<!ELEMENT twRacePathRpt (twRacePath+)>
|
||||
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
|
||||
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
|
||||
twSimpleMinPath CDATA #IMPLIED>
|
||||
<!ELEMENT twTotDel (#PCDATA)>
|
||||
<!ELEMENT twSrc (#PCDATA)>
|
||||
<!ATTLIST twSrc BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDest (#PCDATA)>
|
||||
<!ATTLIST twDest BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDel (#PCDATA)>
|
||||
<!ELEMENT twSUTime (#PCDATA)>
|
||||
<!ELEMENT twTotPathDel (#PCDATA)>
|
||||
<!ELEMENT twClkSkew (#PCDATA)>
|
||||
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
|
||||
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
|
||||
<!ELEMENT twSlack (#PCDATA)>
|
||||
<!ELEMENT twDelConst (#PCDATA)>
|
||||
<!ELEMENT tw2Phase EMPTY>
|
||||
<!ELEMENT twClkUncert (#PCDATA)>
|
||||
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
|
||||
fDCMJit CDATA #IMPLIED
|
||||
fPhaseErr CDATA #IMPLIED
|
||||
sEqu CDATA #IMPLIED>
|
||||
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
|
||||
<!ELEMENT twPathRptBanner (#PCDATA)>
|
||||
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twOff (#PCDATA)>
|
||||
<!ELEMENT twGuaranteed EMPTY>
|
||||
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
|
||||
<!ELEMENT twClkDel (#PCDATA)>
|
||||
<!ELEMENT twClkSrc (#PCDATA)>
|
||||
<!ELEMENT twClkDest (#PCDATA)>
|
||||
<!ELEMENT twGuarInSetup (#PCDATA)>
|
||||
<!ELEMENT twOffSrc (#PCDATA)>
|
||||
<!ELEMENT twOffDest (#PCDATA)>
|
||||
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ELEMENT twDataDel (#PCDATA)>
|
||||
<!ELEMENT twDataSrc (#PCDATA)>
|
||||
<!ELEMENT twDataDest (#PCDATA)>
|
||||
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
|
||||
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twLogLvls (#PCDATA)>
|
||||
<!ELEMENT twSrcSite (#PCDATA)>
|
||||
<!ELEMENT twSrcClk (#PCDATA)>
|
||||
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
|
||||
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twDelInfo (#PCDATA)>
|
||||
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twSite (#PCDATA)>
|
||||
<!ELEMENT twDelType (#PCDATA)>
|
||||
<!ELEMENT twFanCnt (#PCDATA)>
|
||||
<!ELEMENT twComp (#PCDATA)>
|
||||
<!ELEMENT twNet (#PCDATA)>
|
||||
<!ELEMENT twBEL (#PCDATA)>
|
||||
<!ELEMENT twLogDel (#PCDATA)>
|
||||
<!ELEMENT twRouteDel (#PCDATA)>
|
||||
<!ELEMENT twDestClk (#PCDATA)>
|
||||
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPctLog (#PCDATA)>
|
||||
<!ELEMENT twPctRoute (#PCDATA)>
|
||||
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
|
||||
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
|
||||
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
|
||||
<!ELEMENT twTimeConst (#PCDATA)>
|
||||
<!ELEMENT twAbsSlack (#PCDATA)>
|
||||
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
|
||||
<!ELEMENT twSkew (#PCDATA)>
|
||||
<!ELEMENT twDetNet (twNetDel*)>
|
||||
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
|
||||
<!ELEMENT twNetDelInfo (#PCDATA)>
|
||||
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twDetSkewNet (twNetSkew*)>
|
||||
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
|
||||
<!ELEMENT twClkSkewLimit EMPTY>
|
||||
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
|
||||
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollupTable (twConstRollup*)>
|
||||
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollup EMPTY>
|
||||
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
|
||||
<!ELEMENT twConstList (twConstListItem)*>
|
||||
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
|
||||
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
|
||||
<!ELEMENT twNotMet EMPTY>
|
||||
<!ELEMENT twReqVal (#PCDATA)>
|
||||
<!ELEMENT twActVal (#PCDATA)>
|
||||
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
|
||||
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
|
||||
<!ELEMENT twConstStats (twConstName)>
|
||||
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
|
||||
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
|
||||
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
|
||||
<!ELEMENT twConstData EMPTY>
|
||||
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
|
||||
best CDATA #IMPLIED requested CDATA #IMPLIED
|
||||
errors CDATA #IMPLIED
|
||||
score CDATA #IMPLIED>
|
||||
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
|
||||
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
|
||||
<!ELEMENT twTimeGrpName (#PCDATA)>
|
||||
<!ELEMENT twCompList (twCompName+)>
|
||||
<!ELEMENT twCompName (#PCDATA)>
|
||||
<!ELEMENT twSigList (twSigName+)>
|
||||
<!ELEMENT twSigName (#PCDATA)>
|
||||
<!ELEMENT twBELList (twBELName+)>
|
||||
<!ELEMENT twBELName (#PCDATA)>
|
||||
<!ELEMENT twBlockList (twBlockName+)>
|
||||
<!ELEMENT twBlockName (#PCDATA)>
|
||||
<!ELEMENT twMacList (twMacName+)>
|
||||
<!ELEMENT twMacName (#PCDATA)>
|
||||
<!ELEMENT twPinList (twPinName+)>
|
||||
<!ELEMENT twPinName (#PCDATA)>
|
||||
<!ELEMENT twUnmetConstCnt (#PCDATA)>
|
||||
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
|
||||
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
|
||||
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
|
||||
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
|
||||
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
|
||||
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
|
||||
<!ELEMENT twSU2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twH2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
|
||||
<!ELEMENT twClk2Pad (twDest, twTime)>
|
||||
<!ELEMENT twTime (#PCDATA)>
|
||||
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
|
||||
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2Out EMPTY>
|
||||
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
|
||||
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
|
||||
<!ELEMENT twRiseRise (#PCDATA)>
|
||||
<!ELEMENT twFallRise (#PCDATA)>
|
||||
<!ELEMENT twRiseFall (#PCDATA)>
|
||||
<!ELEMENT twFallFall (#PCDATA)>
|
||||
<!ELEMENT twPad2PadList (twPad2Pad+)>
|
||||
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
|
||||
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
|
||||
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
|
||||
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
|
||||
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
|
||||
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffOutTblRow EMPTY>
|
||||
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
|
||||
<!ELEMENT twNonDedClk (#PCDATA)>
|
||||
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
|
||||
<!ELEMENT twScore (#PCDATA)>
|
||||
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
|
||||
<!ELEMENT twPathCnt (#PCDATA)>
|
||||
<!ELEMENT twNetCnt (#PCDATA)>
|
||||
<!ELEMENT twConnCnt (#PCDATA)>
|
||||
<!ELEMENT twPct (#PCDATA)>
|
||||
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
|
||||
<!ELEMENT twMaxCombDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFromToDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetSkew (#PCDATA)>
|
||||
<!ELEMENT twMaxInAfterClk (#PCDATA)>
|
||||
<!ELEMENT twMinInBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMinOutAfterClk (#PCDATA)>
|
||||
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
|
||||
<!ELEMENT twTimestamp (#PCDATA)>
|
||||
<!ELEMENT twFootnoteExplanation EMPTY>
|
||||
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
|
||||
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
|
||||
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
|
||||
<!ELEMENT twClientName (#PCDATA)>
|
||||
<!ELEMENT twAttrList (twAttrListItem)*>
|
||||
<!ELEMENT twAttrListItem (twName, twValue*)>
|
||||
<!ELEMENT twName (#PCDATA)>
|
||||
<!ELEMENT twValue (#PCDATA)>
|
||||
]>
|
||||
<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (nt)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
|
||||
3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr
|
||||
WarpLC.pcf -ucf PLL.ucf
|
||||
|
||||
</twCmdLine><twDesign>WarpLC_map.ncd</twDesign><twDesignPath>WarpLC_map.ncd</twDesignPath><twPCF>WarpLC.pcf</twPCF><twPcfPath>WarpLC.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="ftg256"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="NET FSBCLK PERIOD = 10ns HIGH;" ScopeName="">NET "FSBCLK" PERIOD = 10 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.866</twMinPer></twConstHead><twPinLimitRpt anchorID="6"><twPinLimitBanner>Component Switching Limit Checks: NET "FSBCLK" PERIOD = 10 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="7" type="MINPERIOD" name="Tickper" slack="8.134" period="10.000" constraintValue="10.000" deviceLimit="1.866" freqLimit="535.906" physResource="OUTt_OBUF/CLK0" logResource="OUTt/CLK0" locationPin="ILOGIC_X0Y6.CLK0" clockNet="FSBCLK"/></twPinLimitRpt></twConst><twConst anchorID="8" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="NET CLKIN PERIOD = 20ns HIGH;" ScopeName="">NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>5.000</twMinPer></twConstHead><twPinLimitRpt anchorID="9"><twPinLimitBanner>Component Switching Limit Checks: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="10" type="MINLOWPULSE" name="Tdcmpw_CLKIN_50_100" slack="15.000" period="20.000" constraintValue="10.000" deviceLimit="2.500" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN1" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/><twPinLimit anchorID="11" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_50_100" slack="15.000" period="20.000" constraintValue="10.000" deviceLimit="2.500" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN1" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/><twPinLimit anchorID="12" type="MINPERIOD" name="Tpllper_CLKIN(Finmax)" slack="17.780" period="20.000" constraintValue="20.000" deviceLimit="2.220" freqLimit="450.450" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN1" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/></twPinLimitRpt></twConst><twConst anchorID="13" twConstType="PERIOD" ><twConstHead uID="4"><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS </twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.666</twMinPer></twConstHead><twPinLimitRpt anchorID="14"><twPinLimitBanner>Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkfbout" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
duty cycle corrected to 20 nS HIGH 10 nS
|
||||
</twPinLimitBanner><twPinLimit anchorID="15" type="MINPERIOD" name="Tbcper_I" slack="17.334" period="20.000" constraintValue="20.000" deviceLimit="2.666" freqLimit="375.094" physResource="instance_name/clkfbout_bufg/I0" logResource="instance_name/clkfbout_bufg/I0" locationPin="BUFGMUX_X2Y3.I0" clockNet="instance_name/clkfbout"/><twPinLimit anchorID="16" type="MINPERIOD" name="Tockper" slack="17.751" period="20.000" constraintValue="20.000" deviceLimit="2.249" freqLimit="444.642" physResource="CLKFB_OUT_OBUF/CLK0" logResource="instance_name/clkfbout_oddr/CK0" locationPin="OLOGIC_X0Y5.CLK0" clockNet="instance_name/clkfb_bufg_out"/><twPinLimit anchorID="17" type="MINPERIOD" name="Tpllper_CLKFB" slack="17.780" period="20.000" constraintValue="20.000" deviceLimit="2.220" freqLimit="450.450" physResource="instance_name/pll_base_inst/PLL_ADV/CLKFBOUT" logResource="instance_name/pll_base_inst/PLL_ADV/CLKFBOUT" locationPin="PLL_ADV_X0Y1.CLKFBOUT" clockNet="instance_name/clkfbout"/></twPinLimitRpt></twConst><twConst anchorID="18" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS </twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.666</twMinPer></twConstHead><twPinLimitRpt anchorID="19"><twPinLimitBanner>Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout0" derived from
|
||||
NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
|
||||
divided by 2.00 to 10 nS
|
||||
</twPinLimitBanner><twPinLimit anchorID="20" type="MINPERIOD" name="Tbcper_I" slack="7.334" period="10.000" constraintValue="10.000" deviceLimit="2.666" freqLimit="375.094" physResource="instance_name/clkout1_buf/I0" logResource="instance_name/clkout1_buf/I0" locationPin="BUFGMUX_X3Y13.I0" clockNet="instance_name/clkout0"/><twPinLimit anchorID="21" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="8.948" period="10.000" constraintValue="10.000" deviceLimit="1.052" freqLimit="950.570" physResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" logResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" locationPin="PLL_ADV_X0Y1.CLKOUT0" clockNet="instance_name/clkout0"/><twPinLimit anchorID="22" type="MAXPERIOD" name="Tpllper_CLKOUT(Foutmin)" slack="310.000" period="10.000" constraintValue="10.000" deviceLimit="320.000" freqLimit="3.125" physResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" logResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" locationPin="PLL_ADV_X0Y1.CLKOUT0" clockNet="instance_name/clkout0"/></twPinLimitRpt></twConst><twConstRollupTable uID="2" anchorID="23"><twConstRollup name="instance_name/clkin1" fullName="NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="5.000" actualRollup="5.332" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="instance_name/clkfbout" fullName="PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS " type="child" depth="1" requirement="20.000" prefType="period" actual="2.666" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="instance_name/clkout0" fullName="PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS " type="child" depth="1" requirement="10.000" prefType="period" actual="2.666" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="24">0</twUnmetConstCnt><twDataSheet anchorID="25" twNameLen="15"><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="26"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>0</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>0</twConnCnt></twConstCov><twStats anchorID="27"><twMinPer>5.000</twMinPer><twFootnote number="1" /><twMaxFreq>200.000</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Fri Oct 29 10:24:20 2021 </twTimestamp></twFoot><twClientInfo anchorID="28"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
|
||||
|
||||
Peak Memory Usage: 167 MB
|
||||
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
|
||||
@ -2,7 +2,7 @@
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>WarpLC Project Status (10/29/2021 - 10:03:11)</B></TD></TR>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>WarpLC Project Status (10/29/2021 - 17:59:59)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>WarpLC.xise</TD>
|
||||
@ -25,7 +25,7 @@ No Errors</TD>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/*.xmsgs?&DataKey=Warning'>527 Warnings (2 new)</A></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/*.xmsgs?&DataKey=Warning'>7 Warnings (0 new)</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
@ -60,13 +60,13 @@ System Settings</A>
|
||||
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
|
||||
<TD ALIGN=RIGHT>56</TD>
|
||||
<TD ALIGN=RIGHT>34</TD>
|
||||
<TD ALIGN=RIGHT>11,440</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD>
|
||||
<TD ALIGN=RIGHT>56</TD>
|
||||
<TD ALIGN=RIGHT>34</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
@ -90,31 +90,31 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
|
||||
<TD ALIGN=RIGHT>59</TD>
|
||||
<TD ALIGN=RIGHT>17</TD>
|
||||
<TD ALIGN=RIGHT>5,720</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
|
||||
<TD ALIGN=RIGHT>56</TD>
|
||||
<TD ALIGN=RIGHT>13</TD>
|
||||
<TD ALIGN=RIGHT>5,720</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
|
||||
<TD ALIGN=RIGHT>24</TD>
|
||||
<TD ALIGN=RIGHT>11</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
|
||||
<TD ALIGN=RIGHT>29</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
|
||||
<TD ALIGN=RIGHT>3</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
@ -132,19 +132,19 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD>
|
||||
<TD ALIGN=RIGHT>3</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
@ -156,57 +156,57 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
|
||||
<TD ALIGN=RIGHT>25</TD>
|
||||
<TD ALIGN=RIGHT>11</TD>
|
||||
<TD ALIGN=RIGHT>1,430</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
|
||||
<TD ALIGN=RIGHT>56</TD>
|
||||
<TD ALIGN=RIGHT>12</TD>
|
||||
<TD ALIGN=RIGHT>2,860</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
|
||||
<TD ALIGN=RIGHT>76</TD>
|
||||
<TD ALIGN=RIGHT>41</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD>
|
||||
<TD ALIGN=RIGHT>22</TD>
|
||||
<TD ALIGN=RIGHT>76</TD>
|
||||
<TD ALIGN=RIGHT>28%</TD>
|
||||
<TD ALIGN=RIGHT>11</TD>
|
||||
<TD ALIGN=RIGHT>41</TD>
|
||||
<TD ALIGN=RIGHT>26%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD>
|
||||
<TD ALIGN=RIGHT>17</TD>
|
||||
<TD ALIGN=RIGHT>76</TD>
|
||||
<TD ALIGN=RIGHT>22%</TD>
|
||||
<TD ALIGN=RIGHT>24</TD>
|
||||
<TD ALIGN=RIGHT>41</TD>
|
||||
<TD ALIGN=RIGHT>58%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD>
|
||||
<TD ALIGN=RIGHT>37</TD>
|
||||
<TD ALIGN=RIGHT>76</TD>
|
||||
<TD ALIGN=RIGHT>48%</TD>
|
||||
<TD ALIGN=RIGHT>6</TD>
|
||||
<TD ALIGN=RIGHT>41</TD>
|
||||
<TD ALIGN=RIGHT>14%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD>
|
||||
<TD ALIGN=RIGHT>16</TD>
|
||||
<TD ALIGN=RIGHT>6</TD>
|
||||
<TD ALIGN=RIGHT>11,440</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
|
||||
<TD ALIGN=RIGHT>49</TD>
|
||||
<TD ALIGN=RIGHT>43</TD>
|
||||
<TD ALIGN=RIGHT>186</TD>
|
||||
<TD ALIGN=RIGHT>26%</TD>
|
||||
<TD ALIGN=RIGHT>23%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Flip Flops</TD>
|
||||
@ -215,12 +215,6 @@ System Settings</A>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Latches</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>32</TD>
|
||||
@ -270,13 +264,13 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
|
||||
<TD ALIGN=RIGHT>3</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>16</TD>
|
||||
<TD ALIGN=RIGHT>18%</TD>
|
||||
<TD ALIGN=RIGHT>12%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD>
|
||||
<TD ALIGN=RIGHT>3</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
@ -294,21 +288,9 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>200</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ILOGIC2s</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ISERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD ALIGN=RIGHT>200</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
|
||||
@ -408,7 +390,7 @@ System Settings</A>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
|
||||
<TD ALIGN=RIGHT>2.16</TD>
|
||||
<TD ALIGN=RIGHT>1.41</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
@ -445,20 +427,20 @@ System Settings</A>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:02:50 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>272 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:02:55 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>254 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:03:01 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/map.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (1 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:03:06 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Oct 29 17:59:39 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>7 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Oct 29 17:59:43 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Oct 29 17:59:48 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/map.xmsgs?&DataKey=Info'>6 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Oct 29 17:59:53 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:03:09 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri Oct 29 17:59:57 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri Oct 29 08:28:45 2021</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri Oct 29 10:25:28 2021</TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 10/29/2021 - 10:03:11</center>
|
||||
<br><center><b>Date Generated:</b> 10/29/2021 - 17:59:59</center>
|
||||
</BODY></HTML>
|
||||
@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Fri Oct 29 10:02:47 2021">
|
||||
<application stringID="Xst" timeStamp="Fri Oct 29 17:59:37 2021">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@ -106,30 +106,28 @@
|
||||
<item dataType="int" stringID="XST_NUM_BUFG" value="1"/>
|
||||
<item dataType="int" stringID="XST_NUM_BUFIO2FB" value="1"/>
|
||||
<item dataType="int" stringID="XST_NUM_IBUFG" value="1"/>
|
||||
<item dataType="int" stringID="XST_NUM_ODDR2" value="2"/>
|
||||
<item dataType="int" stringID="XST_NUM_ODDR2" value="5"/>
|
||||
</section>
|
||||
<section stringID="XST_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="10">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="8"/>
|
||||
<item dataType="int" stringID="XST_30BIT_REGISTER" value="1"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="3">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="2"/>
|
||||
<item dataType="int" stringID="XST_32BIT_REGISTER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="2">
|
||||
<item dataType="int" stringID="XST_30BIT_COMPARATOR_EQUAL" value="1"/>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="1">
|
||||
<item dataType="int" stringID="XST_32BIT_COMPARATOR_EQUAL" value="1"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="59">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="59"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="34">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="34"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="2">
|
||||
<item dataType="int" stringID="XST_30BIT_COMPARATOR_EQUAL" value="1"/>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="1">
|
||||
<item dataType="int" stringID="XST_32BIT_COMPARATOR_EQUAL" value="1"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_FINAL_REGISTER_REPORT">
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="59">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="59"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="34">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="34"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_REPORT">
|
||||
@ -142,56 +140,50 @@
|
||||
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="WarpLC.ngc"/>
|
||||
</section>
|
||||
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="141">
|
||||
<item dataType="int" stringID="XST_BELS" value="29">
|
||||
<item dataType="int" stringID="XST_GND" value="1"/>
|
||||
<item dataType="int" stringID="XST_INV" value="6"/>
|
||||
<item dataType="int" stringID="XST_LUT1" value="29"/>
|
||||
<item dataType="int" stringID="XST_LUT2" value="3"/>
|
||||
<item dataType="int" stringID="XST_LUT3" value="2"/>
|
||||
<item dataType="int" stringID="XST_INV" value="3"/>
|
||||
<item dataType="int" stringID="XST_LUT3" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT4" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT6" value="20"/>
|
||||
<item dataType="int" stringID="XST_MUXCY" value="48"/>
|
||||
<item dataType="int" stringID="XST_LUT6" value="10"/>
|
||||
<item dataType="int" stringID="XST_MUXCY" value="12"/>
|
||||
<item dataType="int" stringID="XST_VCC" value="1"/>
|
||||
<item dataType="int" stringID="XST_XORCY" value="30"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="62">
|
||||
<item dataType="int" stringID="XST_FD" value="7"/>
|
||||
<item dataType="int" stringID="XST_FD1" value="1"/>
|
||||
<item dataType="int" stringID="XST_FDE" value="51"/>
|
||||
<item dataType="int" stringID="XST_ODDR2" value="2"/>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="39">
|
||||
<item dataType="int" stringID="XST_FD" value="34"/>
|
||||
<item dataType="int" stringID="XST_ODDR2" value="5"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="3">
|
||||
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="3"/>
|
||||
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="2">
|
||||
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="2"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="49">
|
||||
<item dataType="int" stringID="XST_IBUF" value="38"/>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="43">
|
||||
<item dataType="int" stringID="XST_IBUF" value="35"/>
|
||||
<item dataType="int" stringID="XST_IBUFG" value="2"/>
|
||||
<item dataType="int" stringID="XST_OBUF" value="9"/>
|
||||
<item dataType="int" stringID="XST_OBUF" value="6"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_OTHERS" value="2"></item>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
|
||||
<item stringID="XST_SELECTED_DEVICE" value="6slx9ftg256-2"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="61"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="61"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="61"/>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="114"/>
|
||||
<item AVAILABLE="114" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="53"/>
|
||||
<item AVAILABLE="114" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="53"/>
|
||||
<item AVAILABLE="114" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="8"/>
|
||||
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="5"/>
|
||||
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="170"/>
|
||||
<item AVAILABLE="186" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="49"/>
|
||||
<item dataType="int" label="IOB Flip Flops/Latches" stringID="XST_IOB_FLIP_FLOPSLATCHES" value="1"/>
|
||||
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="3"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="39"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="15"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="15"/>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="52"/>
|
||||
<item AVAILABLE="52" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="13"/>
|
||||
<item AVAILABLE="52" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="37"/>
|
||||
<item AVAILABLE="52" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="2"/>
|
||||
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="1"/>
|
||||
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="43"/>
|
||||
<item AVAILABLE="186" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="43"/>
|
||||
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="2"/>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
<section stringID="XST_ERRORS_STATISTICS">
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="272"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="7"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="2"/>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
@ -1,2 +1,2 @@
|
||||
C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.ngc 1635516170
|
||||
C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.ngc 1635544779
|
||||
OK
|
||||
|
||||
@ -5,25 +5,10 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">FSB_A<0></arg> has no load.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">120</arg> more times for the following (max. 5 shown):
|
||||
<arg fmt="%s" index="3">FSB_SIZ<1>,
|
||||
FSB_SIZ<0>,
|
||||
IOB_nDSACK<1>,
|
||||
IOB_nDSACK<0>,
|
||||
CPU_nCIOUT</arg>
|
||||
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="MapLib" num="159" delta="new" >Net Timing constraints on signal <arg fmt="%s" index="1">CLKIN</arg> are pushed forward through input buffer.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="MapLib" num="53" delta="new" >The offset specification "<arg fmt="%s" index="1">OFFSET=IN 10000 pS VALID 11000 pS BEFORE FSBCLK</arg>" has been discarded because the referenced clock pad net (<arg fmt="%s" index="2">FSBCLK</arg>) was optimized away.
|
||||
<msg type="info" file="MapLib" num="159" delta="old" >Net Timing constraints on signal <arg fmt="%s" index="1">CLKIN</arg> are pushed forward through input buffer.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
|
||||
|
||||
@ -5,769 +5,7 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<9>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<9></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<9>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<9></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<10>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<10></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<10>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<10></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<11>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<11></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<11>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<11></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<12>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<12></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<12>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<12></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<13>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<13></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<13>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<13></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<14>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<14></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<14>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<14></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<15>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<15></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<15>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<15></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<16>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<16></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<16>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<16></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<17>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<17></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<17>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<17></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<18>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<18></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<18>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<18></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<19>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<19></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<19>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<19></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<20>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<20></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<20>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<20></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<21>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<21></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<21>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<21></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<22>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<22></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<22>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<22></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<23>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<23></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<23>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<23></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<24>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<24></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<24>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<24></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<25>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<25></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<25>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<25></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<26>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<26></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<26>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<26></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<27>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<27></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<27>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<27></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<28>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<28></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<28>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<28></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<29>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<29></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<29>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<29></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<30>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<30></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<30>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<30></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<31>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<31></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<31>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<31></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_nBERR" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_nBERR</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOBCLK" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOBCLK</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "nRES" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/nRES</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nCBREQ" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nCBREQ</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nDS" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nDS</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nECS" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nECS</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nCIOUT" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nCIOUT</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_nDSACK<0>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_nDSACK<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_nDSACK<1>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_nDSACK<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_SIZ<0>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_SIZ<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_SIZ<1>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_SIZ<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_A<0>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_A<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_CLK23" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_CLK23</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_CKE" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_CKE</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_nWE" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_nWE</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_nCAS" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_nCAS</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_nRAS" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_nRAS</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_nCS" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_nCS</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nCIIN" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nCIIN</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nCBACK" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nCBACK</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_DDIR" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_DDIR</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nDOE" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nDOE</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "CPU_nDSACKOE" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/CPU_nDSACKOE</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_nRMC" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_nRMC</arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<0>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<1>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<2>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<2></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<3>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<3></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<4>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<4></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<5>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<5></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<6>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<6></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<7>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<7></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<8>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<8></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<9>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<9></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<10>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<10></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<11>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<11></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<12>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<12></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<13>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<13></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<14>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<14></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<15>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<15></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<16>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<16></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<17>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<17></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<18>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<18></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<19>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<19></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<20>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<20></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<21>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<21></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<22>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<22></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<23>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<23></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<24>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<24></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<25>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<25></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<26>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<26></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<27>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<27></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<28>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<28></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<29>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<29></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<30>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<30></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "IOB_D<31>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/IOB_D<31></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_DQM<0>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_DQM<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_DQM<1>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_DQM<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_DQM<2>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_DQM<2></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_DQM<3>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_DQM<3></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<0>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<1>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<2>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<2></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<3>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<3></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<4>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<4></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<5>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<5></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<6>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<6></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<7>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<7></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<8>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<8></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<9>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<9></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<10>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<10></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<11>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<11></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_A<12>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_A<12></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_BA<0>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_BA<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "RAM_BA<1>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/RAM_BA<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<0>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<0>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<0></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<1>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<1>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<1></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<2>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<2></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<2>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<2></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<3>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<3></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<3>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<3></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<4>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<4></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<4>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<4></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<5>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<5></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<5>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<5></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<6>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<6></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<6>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<6></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<7>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<7></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<7>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<7></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<8>" IOBDELAY = NONE></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<8></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="119" delta="old" >Constraint <arg fmt="%s" index="1"><NET "FSB_D<8>" SLEW = FAST></arg>: This constraint cannot be distributed from the design objects matching '<arg fmt="%s" index="2">NET: UniqueName: /WarpLC/EXPANDED/FSB_D<8></arg>' because those design objects do not contain or drive any instances of the correct type.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="130" delta="old" >Constraint <arg fmt="%s" index="1"><NET FSBCLK FEEDBACK = 160ps NET CLKFB_IN;> [PLL.ucf(2)]</arg>: <arg fmt="%s" index="2">NET "FSBCLK"</arg> is not connected to an input or output pad.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="85" delta="old" >Constraint <arg fmt="%s" index="1"><NET FSBCLK FEEDBACK = 160ps NET CLKFB_IN;> [PLL.ucf(2)]</arg>: This constraint will be ignored because <arg fmt="%s" index="2">NET "FSBCLK"</arg> could not be found.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="130" delta="old" >Constraint <arg fmt="%s" index="1"><NET CPUCLKi FEEDBACK = 160ps NET CLKFB_IN;> [PLL.ucf(3)]</arg>: <arg fmt="%s" index="2">NET "CPUCLKi"</arg> is not connected to an input or output pad.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="85" delta="old" >Constraint <arg fmt="%s" index="1"><NET CPUCLKi FEEDBACK = 160ps NET CLKFB_IN;> [PLL.ucf(3)]</arg>: This constraint will be ignored because <arg fmt="%s" index="2">NET "CPUCLKi"</arg> could not be found.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="ConstraintSystem" num="168" delta="new" >Constraint <arg fmt="%s" index="1"><NET CPU_nAS OFFSET = IN 10ns VALID 11ns BEFORE FSBCLK;> [PLL.ucf(6)]</arg>: This constraint will be ignored because <arg fmt="%s" index="2">NET "FSBCLK"</arg> could not be found or was not connected to a PAD.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ConstraintSystem" num="0" >The Period constraint <NET CLKIN PERIOD = 20ns HIGH;> [PLL.ucf(5)], is specified using the Net Period method which is not recommended. Please use the Timespec PERIOD method.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_A<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<31></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<30></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<29></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<28></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<27></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<26></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<25></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<24></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<23></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<22></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<21></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<20></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<19></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<18></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<17></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<16></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<15></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<14></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<13></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<12></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<11></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<10></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<9></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<8></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<7></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<6></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<5></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<4></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<3></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<2></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_D<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_BA<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_BA<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<12></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<11></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<10></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<9></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<8></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<7></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<6></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<5></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<4></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<3></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<2></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_A<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_DQM<3></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_DQM<2></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_DQM<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_DQM<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_A<3></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_A<2></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_A<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_A<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_SIZ<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_SIZ<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<31></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<30></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<29></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<28></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<27></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<26></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<25></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<24></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<23></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<22></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<21></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<20></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<19></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<18></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<17></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<16></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<15></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<14></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<13></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<12></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<11></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<10></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<9></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<8></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<7></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<6></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<5></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<4></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<3></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<2></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<1></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_D<0></arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">FSB_nRMC</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_nAOE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_nDSACKOE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_nDOE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_DDIR</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_nCBACK</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_nCIIN</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">CPU_nHALT</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_nCS</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_nRAS</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_nCAS</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_nWE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_CKE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">RAM_CLK23</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_nAOE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_ADoutLE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_nAS</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_nDS</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_nDOE</arg>' has no driver
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">IOB_DDIR</arg>' has no driver
|
||||
<msg type="info" file="ConstraintSystem" num="0" >The Period constraint <NET CLKIN PERIOD = 30ns HIGH;> [PLL.ucf(3)], is specified using the Net Period method which is not recommended. Please use the Timespec PERIOD method.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
@ -5,827 +5,32 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 133: Assignment to <arg fmt="%s" index="1">clkout2_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 128: Assignment to <arg fmt="%s" index="1">clkout1_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 134: Assignment to <arg fmt="%s" index="1">clkout3_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 129: Assignment to <arg fmt="%s" index="1">clkout2_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 135: Assignment to <arg fmt="%s" index="1">clkout4_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 130: Assignment to <arg fmt="%s" index="1">clkout3_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 136: Assignment to <arg fmt="%s" index="1">clkout5_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 131: Assignment to <arg fmt="%s" index="1">clkout4_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 137: Assignment to <arg fmt="%s" index="1">locked_unused</arg> ignored, since the identifier is never used
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 132: Assignment to <arg fmt="%s" index="1">clkout5_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 352: Result of <arg fmt="%d" index="1">31</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">30</arg>-bit target.
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 133: Assignment to <arg fmt="%s" index="1">locked_unused</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">FSB_A<0:0></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 84: Assignment to <arg fmt="%s" index="1">CPUCLKr</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">FSB_SIZ</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">IOB_nDSACK</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CPU_nCIOUT</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CPU_nECS</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CPU_nDS</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CPU_nCBREQ</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">nRES</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">IOBCLK</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">IOB_nBERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">LHALT</arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
||||
<msg type="info" file="Xst" num="3210" delta="old" >"<arg fmt="%s" index="1">C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v</arg>" line <arg fmt="%s" index="2">79</arg>: Output port <<arg fmt="%s" index="3">CPUCLKr</arg>> of the instance <<arg fmt="%s" index="4">CLKGEN_inst</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="1901" delta="old" >Instance <arg fmt="%s" index="1">pll_base_inst</arg> in unit <arg fmt="%s" index="2">pll_base_inst</arg> of type <arg fmt="%s" index="3">PLL_BASE</arg> has been replaced by <arg fmt="%s" index="4">PLL_ADV</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Flip flop associated with net</arg> <arg fmt="%s" index="2">RAM_CLK01_OBUF</arg> not found, property <arg fmt="%s" index="3">IOB</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_FC<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_FC<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_FC<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<31></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<30></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<29></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<28></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<27></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<26></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<25></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<24></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<23></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<22></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<21></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<20></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<19></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<18></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<17></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<16></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<15></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<14></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<13></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<12></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<11></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<10></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<9></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<8></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<7></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<6></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<5></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<4></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_A<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_RnW</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<31></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<31></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<30></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<30></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<29></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<29></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<28></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<28></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<27></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<27></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<26></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<26></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<25></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<25></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<24></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<24></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<23></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<23></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<22></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<22></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<21></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<21></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<20></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<20></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<19></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<19></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<18></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<18></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<17></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<17></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<16></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<16></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<15></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<15></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<14></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<14></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<13></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<13></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<12></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<12></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<11></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<11></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<10></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<10></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<9></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<9></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<8></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<8></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<7></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<7></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<6></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<6></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<5></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<5></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<4></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<4></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<3></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<2></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_D<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_BA<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_BA<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_BA<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_BA<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<12></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<12></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<11></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<11></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<10></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<10></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<9></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<9></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<8></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<8></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<7></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<7></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<6></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<6></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<5></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<5></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<4></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<4></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<3></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<2></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_A<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<3></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<2></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_DQM<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<3></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<2></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_A<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_SIZ<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_SIZ<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_SIZ<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_SIZ<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<31></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<31></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<30></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<30></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<29></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<29></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<28></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<28></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<27></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<27></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<26></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<26></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<25></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<25></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<24></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<24></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<23></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<23></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<22></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<22></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<21></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<21></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<20></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<20></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<19></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<19></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<18></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<18></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<17></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<17></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<16></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<16></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<15></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<15></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<14></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<14></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<13></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<13></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<12></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<12></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<11></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<11></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<10></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<10></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<9></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<9></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<8></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<8></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<7></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<7></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<6></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<6></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<5></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<5></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<4></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<4></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<3></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<3></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<2></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<2></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<1></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<1></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<0></arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_D<0></arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_nRMC</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">FSB_nRMC</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nAOE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nAOE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nDSACKOE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nDSACKOE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nDOE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nDOE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_DDIR</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_DDIR</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nCBACK</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nCBACK</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nCIIN</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nCIIN</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nHALT</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">CPU_nHALT</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nCS</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nCS</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nRAS</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nRAS</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nCAS</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nCAS</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nWE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_nWE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_CKE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_CKE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_CLK23</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">RAM_CLK23</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nAOE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nAOE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_ADoutLE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_ADoutLE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nAS</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nAS</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nDS</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nDS</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nDOE</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_nDOE</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_DDIR</arg> not found, property <arg fmt="%s" index="3">IOSTANDARD</arg> not attached.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="615" delta="old" ><arg fmt="%s" index="1">Instance associated with port</arg> <arg fmt="%s" index="2">IOB_DDIR</arg> not found, property <arg fmt="%s" index="3">DRIVE</arg> not attached.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
||||
@ -14,10 +14,6 @@ LINE Normal 608 80 576 80
|
||||
PIN 608 80 RIGHT 36
|
||||
PINATTR PinName clk_out1
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 176 576 176
|
||||
PIN 608 176 RIGHT 36
|
||||
PINATTR PinName clk_out2
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 752 576 752
|
||||
PIN 608 752 RIGHT 36
|
||||
PINATTR PinName clkfb_out
|
||||
|
||||
@ -31,19 +31,19 @@
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1194492726557041007" xil_pn:start_ts="1635516166">
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1194492726557041007" xil_pn:start_ts="1635544541">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6061207241259343081" xil_pn:start_ts="1635516166">
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6061207241259343081" xil_pn:start_ts="1635544541">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635516166">
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635544541">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635516166" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1097761553319033393" xil_pn:start_ts="1635516166">
|
||||
<transform xil_pn:end_ts="1635544541" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1097761553319033393" xil_pn:start_ts="1635544541">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
|
||||
@ -51,7 +51,7 @@
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 303.03ps;
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 250.0ps;
|
||||
|
||||
|
||||
# Constraints for external feedback.
|
||||
|
||||
@ -1,11 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<symbol version="7" name="CLK">
|
||||
<symboltype>BLOCK</symboltype>
|
||||
<timestamp>2021-10-29T12:25:33</timestamp>
|
||||
<timestamp>2021-10-29T21:49:45</timestamp>
|
||||
<pin polarity="Input" x="0" y="80" name="clk_in1" />
|
||||
<pin polarity="Input" x="0" y="304" name="clkfb_in" />
|
||||
<pin polarity="Output" x="608" y="80" name="clk_out1" />
|
||||
<pin polarity="Output" x="608" y="176" name="clk_out2" />
|
||||
<pin polarity="Output" x="608" y="752" name="clkfb_out" />
|
||||
<graph>
|
||||
<text style="fontsize:40;fontname:Arial" x="32" y="32">CLK</text>
|
||||
@ -16,8 +15,6 @@
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="304" type="pin clkfb_in" />
|
||||
<line x2="576" y1="80" y2="80" x1="608" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="80" type="pin clk_out1" />
|
||||
<line x2="576" y1="176" y2="176" x1="608" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="176" type="pin clk_out2" />
|
||||
<line x2="576" y1="752" y2="752" x1="608" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="752" type="pin clkfb_out" />
|
||||
</graph>
|
||||
|
||||
@ -51,7 +51,7 @@
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 303.03ps;
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 250.0ps;
|
||||
|
||||
|
||||
# Constraints for external feedback.
|
||||
|
||||
@ -55,24 +55,22 @@
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____66.667______0.000______50.0______306.616____267.927
|
||||
// CLK_OUT2____66.667______0.000______50.0______306.616____267.927
|
||||
// CLK_OUT1____66.667______0.000______50.0______300.590____267.927
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________33.333___________0.010101
|
||||
// __primary_________33.3333___________0.00833333333333
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "CLK,clk_wiz_v3_6,{component_name=CLK,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO_OFFCHIP,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=30.0,clkin2_period=30.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
|
||||
(* CORE_GENERATION_INFO = "CLK,clk_wiz_v3_6,{component_name=CLK,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO_OFFCHIP,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=30.0,clkin2_period=30.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
|
||||
module CLK
|
||||
(// Clock in ports
|
||||
input CLKIN,
|
||||
input CLKFB_IN,
|
||||
// Clock out ports
|
||||
output FSBCLK,
|
||||
output CPUCLK,
|
||||
output CLKFB_OUT
|
||||
);
|
||||
|
||||
@ -105,6 +103,7 @@ module CLK
|
||||
wire locked_unused;
|
||||
wire clkfbout;
|
||||
wire clkfbout_buf;
|
||||
wire clkout1_unused;
|
||||
wire clkout2_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout4_unused;
|
||||
@ -120,16 +119,13 @@ module CLK
|
||||
.CLKOUT0_DIVIDE (6),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_DIVIDE (6),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKIN_PERIOD (30.0),
|
||||
.REF_JITTER (0.010))
|
||||
.REF_JITTER (0.008))
|
||||
pll_base_inst
|
||||
// Output clocks
|
||||
(.CLKFBOUT (clkfbout),
|
||||
.CLKOUT0 (clkout0),
|
||||
.CLKOUT1 (clkout1),
|
||||
.CLKOUT1 (clkout1_unused),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
@ -170,10 +166,6 @@ module CLK
|
||||
.I (clkout0));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (CPUCLK),
|
||||
.I (clkout1));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@ -54,13 +54,12 @@
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____66.667______0.000______50.0______306.616____267.927
|
||||
// CLK_OUT2____66.667______0.000______50.0______306.616____267.927
|
||||
// CLK_OUT1____66.667______0.000______50.0______300.590____267.927
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________33.333___________0.010101
|
||||
// __primary_________33.3333___________0.00833333333333
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
@ -74,6 +73,5 @@
|
||||
.CLKFB_IN(CLKFB_IN), // IN
|
||||
// Clock out ports
|
||||
.FSBCLK(FSBCLK), // OUT
|
||||
.CPUCLK(CPUCLK), // OUT
|
||||
.CLKFB_OUT(CLKFB_OUT)); // OUT
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.7
|
||||
# Date: Fri Oct 29 12:25:16 2021
|
||||
# Date: Fri Oct 29 21:49:29 2021
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
@ -43,13 +43,13 @@ CSET calc_done=DONE
|
||||
CSET clk_in_sel_port=CLK_IN_SEL
|
||||
CSET clk_out1_port=FSBCLK
|
||||
CSET clk_out1_use_fine_ps_gui=false
|
||||
CSET clk_out2_port=CPUCLK
|
||||
CSET clk_out2_port=RAMCLK
|
||||
CSET clk_out2_use_fine_ps_gui=false
|
||||
CSET clk_out3_port=CPUCLK
|
||||
CSET clk_out3_use_fine_ps_gui=false
|
||||
CSET clk_out4_port=FPUCLK
|
||||
CSET clk_out4_port=C80M
|
||||
CSET clk_out4_use_fine_ps_gui=false
|
||||
CSET clk_out5_port=CLK_OUT5
|
||||
CSET clk_out5_port=C50M
|
||||
CSET clk_out5_use_fine_ps_gui=false
|
||||
CSET clk_out6_port=CLK_OUT6
|
||||
CSET clk_out6_use_fine_ps_gui=false
|
||||
@ -64,9 +64,9 @@ CSET clkfb_out_n_port=CLKFB_OUT_N
|
||||
CSET clkfb_out_p_port=CLKFB_OUT_P
|
||||
CSET clkfb_out_port=CLKFB_OUT
|
||||
CSET clkfb_stopped_port=CLKFB_STOPPED
|
||||
CSET clkin1_jitter_ps=303.03
|
||||
CSET clkin1_ui_jitter=303.030
|
||||
CSET clkin2_jitter_ps=33.000033
|
||||
CSET clkin1_jitter_ps=250.0
|
||||
CSET clkin1_ui_jitter=250.000
|
||||
CSET clkin2_jitter_ps=40.0
|
||||
CSET clkin2_ui_jitter=100.000
|
||||
CSET clkout1_drives=BUFG
|
||||
CSET clkout1_requested_duty_cycle=50.0
|
||||
@ -74,48 +74,48 @@ CSET clkout1_requested_out_freq=66.667
|
||||
CSET clkout1_requested_phase=0.000
|
||||
CSET clkout2_drives=BUFG
|
||||
CSET clkout2_requested_duty_cycle=50.0
|
||||
CSET clkout2_requested_out_freq=66.667
|
||||
CSET clkout2_requested_out_freq=33.3333
|
||||
CSET clkout2_requested_phase=0
|
||||
CSET clkout2_used=true
|
||||
CSET clkout2_used=false
|
||||
CSET clkout3_drives=BUFG
|
||||
CSET clkout3_requested_duty_cycle=50.0
|
||||
CSET clkout3_requested_out_freq=33.333
|
||||
CSET clkout3_requested_phase=0
|
||||
CSET clkout3_requested_out_freq=33.3333
|
||||
CSET clkout3_requested_phase=-72
|
||||
CSET clkout3_used=false
|
||||
CSET clkout4_drives=BUFG
|
||||
CSET clkout4_requested_duty_cycle=50.0
|
||||
CSET clkout4_requested_out_freq=33.333
|
||||
CSET clkout4_requested_out_freq=33.3333
|
||||
CSET clkout4_requested_phase=0
|
||||
CSET clkout4_used=false
|
||||
CSET clkout5_drives=BUFG
|
||||
CSET clkout5_requested_duty_cycle=50.0
|
||||
CSET clkout5_requested_out_freq=40
|
||||
CSET clkout5_requested_out_freq=33.3333
|
||||
CSET clkout5_requested_phase=0.000
|
||||
CSET clkout5_used=false
|
||||
CSET clkout6_drives=BUFG
|
||||
CSET clkout6_requested_duty_cycle=50.0
|
||||
CSET clkout6_requested_out_freq=33.000
|
||||
CSET clkout6_requested_out_freq=33.3333
|
||||
CSET clkout6_requested_phase=0.000
|
||||
CSET clkout6_used=false
|
||||
CSET clkout7_drives=BUFG
|
||||
CSET clkout7_requested_duty_cycle=50.0
|
||||
CSET clkout7_requested_out_freq=33.000
|
||||
CSET clkout7_requested_out_freq=33.3333
|
||||
CSET clkout7_requested_phase=0.000
|
||||
CSET clkout7_used=false
|
||||
CSET clock_mgr_type=MANUAL
|
||||
CSET component_name=CLK
|
||||
CSET daddr_port=DADDR
|
||||
CSET dclk_port=DCLK
|
||||
CSET dcm_clk_feedback=NONE
|
||||
CSET dcm_clk_out1_port=CLKFX
|
||||
CSET dcm_clk_out2_port=CLKFX
|
||||
CSET dcm_clk_feedback=1X
|
||||
CSET dcm_clk_out1_port=CLK0
|
||||
CSET dcm_clk_out2_port=CLK2X
|
||||
CSET dcm_clk_out3_port=CLKFX
|
||||
CSET dcm_clk_out4_port=CLKFX
|
||||
CSET dcm_clk_out5_port=CLKFX
|
||||
CSET dcm_clk_out6_port=CLK0
|
||||
CSET dcm_clkdv_divide=2.0
|
||||
CSET dcm_clkfx_divide=2
|
||||
CSET dcm_clkfx_multiply=2
|
||||
CSET dcm_clkfx_divide=1
|
||||
CSET dcm_clkfx_multiply=4
|
||||
CSET dcm_clkgen_clk_out1_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out2_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out3_port=CLKFX180
|
||||
@ -128,7 +128,7 @@ CSET dcm_clkgen_notes=None
|
||||
CSET dcm_clkgen_spread_spectrum=NONE
|
||||
CSET dcm_clkgen_startup_wait=false
|
||||
CSET dcm_clkin_divide_by_2=false
|
||||
CSET dcm_clkin_period=30.303
|
||||
CSET dcm_clkin_period=30.000
|
||||
CSET dcm_clkout_phase_shift=NONE
|
||||
CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
|
||||
CSET dcm_notes=None
|
||||
@ -189,7 +189,7 @@ CSET mmcm_notes=None
|
||||
CSET mmcm_ref_jitter1=0.010
|
||||
CSET mmcm_ref_jitter2=0.010
|
||||
CSET mmcm_startup_wait=false
|
||||
CSET num_out_clks=2
|
||||
CSET num_out_clks=1
|
||||
CSET override_dcm=false
|
||||
CSET override_dcm_clkgen=false
|
||||
CSET override_mmcm=false
|
||||
@ -203,16 +203,16 @@ CSET pll_clkin_period=30.0
|
||||
CSET pll_clkout0_divide=6
|
||||
CSET pll_clkout0_duty_cycle=0.500
|
||||
CSET pll_clkout0_phase=0.000
|
||||
CSET pll_clkout1_divide=6
|
||||
CSET pll_clkout1_divide=10
|
||||
CSET pll_clkout1_duty_cycle=0.500
|
||||
CSET pll_clkout1_phase=0.000
|
||||
CSET pll_clkout2_divide=12
|
||||
CSET pll_clkout2_divide=10
|
||||
CSET pll_clkout2_duty_cycle=0.500
|
||||
CSET pll_clkout2_phase=0.000
|
||||
CSET pll_clkout3_divide=12
|
||||
CSET pll_clkout2_phase=-72.000
|
||||
CSET pll_clkout3_divide=10
|
||||
CSET pll_clkout3_duty_cycle=0.500
|
||||
CSET pll_clkout3_phase=0.000
|
||||
CSET pll_clkout4_divide=10
|
||||
CSET pll_clkout4_divide=16
|
||||
CSET pll_clkout4_duty_cycle=0.500
|
||||
CSET pll_clkout4_phase=0.000
|
||||
CSET pll_clkout5_divide=1
|
||||
@ -221,10 +221,10 @@ CSET pll_clkout5_phase=0.000
|
||||
CSET pll_compensation=EXTERNAL
|
||||
CSET pll_divclk_divide=1
|
||||
CSET pll_notes=None
|
||||
CSET pll_ref_jitter=0.010
|
||||
CSET pll_ref_jitter=0.008
|
||||
CSET power_down_port=POWER_DOWN
|
||||
CSET prim_in_freq=33.333
|
||||
CSET prim_in_jitter=0.010101
|
||||
CSET prim_in_freq=33.3333
|
||||
CSET prim_in_jitter=0.00833333333333
|
||||
CSET prim_source=Single_ended_clock_capable_pin
|
||||
CSET primary_port=CLKIN
|
||||
CSET primitive=MMCM
|
||||
@ -236,7 +236,7 @@ CSET psincdec_port=PSINCDEC
|
||||
CSET relative_inclk=REL_PRIMARY
|
||||
CSET reset_port=RESET
|
||||
CSET secondary_in_freq=100.000
|
||||
CSET secondary_in_jitter=0.0033000033
|
||||
CSET secondary_in_jitter=0.004
|
||||
CSET secondary_port=CLK_IN2
|
||||
CSET secondary_source=Single_ended_clock_capable_pin
|
||||
CSET ss_mod_freq=250
|
||||
@ -266,4 +266,4 @@ CSET use_status=false
|
||||
MISC pkg_timestamp=2012-05-10T12:44:55Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 6c4dba5b
|
||||
# CRC: 51d6f701
|
||||
|
||||
@ -52,7 +52,7 @@
|
||||
#----------------------------------------------------------------
|
||||
create_clock -name CLK_IN1 -period 30.0 [get_ports CLK_IN1]
|
||||
set_propagated_clock CLK_IN1
|
||||
set_input_jitter CLK_IN1 0.30302999999999997
|
||||
set_input_jitter CLK_IN1 0.25
|
||||
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
|
||||
@ -379,8 +379,8 @@
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-10-29T08:25:35" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="CB437BF50B554A6C887C126004DC024B" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-10-29T17:49:47" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="197B7C5C9E5D48F4B518B820AA5AF1D8" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
@ -51,7 +51,7 @@
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 303.03ps;
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 250.0ps;
|
||||
|
||||
|
||||
# Constraints for external feedback.
|
||||
|
||||
@ -65,9 +65,9 @@ module CLK_exdes
|
||||
input CLKFB_IN,
|
||||
// Reset that only drives logic in example design
|
||||
input COUNTER_RESET,
|
||||
output [2:1] CLK_OUT,
|
||||
output [1:1] CLK_OUT,
|
||||
// High bits of counters driven by clocks
|
||||
output [2:1] COUNT,
|
||||
output COUNT,
|
||||
output CLKFB_OUT
|
||||
);
|
||||
|
||||
@ -75,22 +75,21 @@ module CLK_exdes
|
||||
//-------------------------------
|
||||
// Counter width
|
||||
localparam C_W = 16;
|
||||
localparam NUM_C = 2;
|
||||
genvar count_gen;
|
||||
// Create reset for the counters
|
||||
wire reset_int = COUNTER_RESET;
|
||||
|
||||
reg [NUM_C:1] rst_sync;
|
||||
reg [NUM_C:1] rst_sync_int;
|
||||
reg [NUM_C:1] rst_sync_int1;
|
||||
reg [NUM_C:1] rst_sync_int2;
|
||||
reg rst_sync;
|
||||
reg rst_sync_int;
|
||||
reg rst_sync_int1;
|
||||
reg rst_sync_int2;
|
||||
|
||||
|
||||
// Declare the clocks and counters
|
||||
wire [NUM_C:1] clk_int;
|
||||
wire [NUM_C:1] clk_n;
|
||||
wire [NUM_C:1] clk;
|
||||
reg [C_W-1:0] counter [NUM_C:1];
|
||||
|
||||
// Declare the clocks and counter
|
||||
wire clk_int;
|
||||
wire clk_n;
|
||||
wire clk;
|
||||
reg [C_W-1:0] counter;
|
||||
|
||||
// Instantiation of the clocking network
|
||||
//--------------------------------------
|
||||
@ -99,74 +98,56 @@ module CLK_exdes
|
||||
.CLKIN (CLK_IN1),
|
||||
.CLKFB_IN (CLKFB_IN),
|
||||
// Clock out ports
|
||||
.FSBCLK (clk_int[1]),
|
||||
.CPUCLK (clk_int[2]),
|
||||
.FSBCLK (clk_int),
|
||||
.CLKFB_OUT (CLKFB_OUT));
|
||||
|
||||
genvar clk_out_pins;
|
||||
|
||||
generate
|
||||
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
|
||||
begin: gen_outclk_oddr
|
||||
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
|
||||
assign clk_n = ~clk;
|
||||
|
||||
ODDR2 clkout_oddr
|
||||
(.Q (CLK_OUT[clk_out_pins]),
|
||||
.C0 (clk[clk_out_pins]),
|
||||
.C1 (clk_n[clk_out_pins]),
|
||||
(.Q (CLK_OUT[1]),
|
||||
.C0 (clk),
|
||||
.C1 (clk_n),
|
||||
.CE (1'b1),
|
||||
.D0 (1'b1),
|
||||
.D1 (1'b0),
|
||||
.R (1'b0),
|
||||
.S (1'b0));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Connect the output clocks to the design
|
||||
//-----------------------------------------
|
||||
assign clk[1] = clk_int[1];
|
||||
assign clk[2] = clk_int[2];
|
||||
assign clk = clk_int;
|
||||
|
||||
|
||||
// Reset synchronizer
|
||||
//-----------------------------------
|
||||
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
|
||||
always @(posedge reset_int or posedge clk[count_gen]) begin
|
||||
always @(posedge reset_int or posedge clk) begin
|
||||
if (reset_int) begin
|
||||
rst_sync[count_gen] <= 1'b1;
|
||||
rst_sync_int[count_gen]<= 1'b1;
|
||||
rst_sync_int1[count_gen]<= 1'b1;
|
||||
rst_sync_int2[count_gen]<= 1'b1;
|
||||
rst_sync <= 1'b1;
|
||||
rst_sync_int <= 1'b1;
|
||||
rst_sync_int1 <= 1'b1;
|
||||
rst_sync_int2 <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
rst_sync[count_gen] <= 1'b0;
|
||||
rst_sync_int[count_gen] <= rst_sync[count_gen];
|
||||
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
|
||||
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
|
||||
rst_sync <= 1'b0;
|
||||
rst_sync_int <= rst_sync;
|
||||
rst_sync_int1 <= rst_sync_int;
|
||||
rst_sync_int2 <= rst_sync_int1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// Output clock sampling
|
||||
//-----------------------------------
|
||||
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
|
||||
|
||||
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
|
||||
if (rst_sync_int2[count_gen]) begin
|
||||
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
|
||||
end else begin
|
||||
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
|
||||
end
|
||||
always @(posedge clk or posedge rst_sync_int2) begin
|
||||
if (rst_sync_int2) begin
|
||||
counter <= #TCQ { C_W { 1'b 0 } };
|
||||
end else begin
|
||||
counter <= #TCQ counter + 1'b 1;
|
||||
end
|
||||
// alias the high bit of each counter to the corresponding
|
||||
// bit in the output bus
|
||||
assign COUNT[count_gen] = counter[count_gen][C_W-1];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// alias the high bit to the output
|
||||
assign COUNT = counter[C_W-1];
|
||||
|
||||
|
||||
|
||||
|
||||
@ -52,7 +52,7 @@
|
||||
#----------------------------------------------------------------
|
||||
create_clock -name CLK_IN1 -period 30.0 [get_ports CLK_IN1]
|
||||
set_propagated_clock CLK_IN1
|
||||
set_input_jitter CLK_IN1 0.30302999999999997
|
||||
set_input_jitter CLK_IN1 0.25
|
||||
|
||||
# FALSE PATH constraint added on COUNTER_RESET
|
||||
set_false_path -from [get_ports "COUNTER_RESET"]
|
||||
|
||||
@ -78,13 +78,13 @@ module CLK_tb ();
|
||||
// Declare the input clock signals
|
||||
reg CLK_IN1 = 1;
|
||||
|
||||
// The high bits of the sampling counters
|
||||
wire [2:1] COUNT;
|
||||
// The high bit of the sampling counter
|
||||
wire COUNT;
|
||||
// Connect the feedback
|
||||
wire CLKFB_OUT;
|
||||
wire CLKFB_IN = CLKFB_OUT;
|
||||
reg COUNTER_RESET = 0;
|
||||
wire [2:1] CLK_OUT;
|
||||
wire [1:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
|
||||
|
||||
@ -51,7 +51,7 @@ add wave -noupdate -format Literal -radix ascii /CLK_tb/test_phase
|
||||
add wave -noupdate -divider {Input clocks}
|
||||
add wave -noupdate -format Logic /CLK_tb/CLK_IN1
|
||||
add wave -noupdate -divider {Output clocks}
|
||||
add wave -noupdate -format Literal -expand /CLK_tb/dut/clk
|
||||
add wave -noupdate -format Logic /CLK_tb/dut/clk
|
||||
add wave -noupdate -divider Counters
|
||||
add wave -noupdate -format Literal -radix hexadecimal /CLK_tb/COUNT
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /CLK_tb/dut/counter
|
||||
add wave -noupdate -format Literal -radix hexadecimal /CLK_tb/dut/counter
|
||||
|
||||
@ -89,16 +89,16 @@ group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{CLK_tb.dut.clk[1]} \
|
||||
{CLK_tb.dut.clk[2]}
|
||||
{CLK_tb.dut.clk} \
|
||||
|
||||
group using {Counters}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{CLK_tb.dut.counter[1]} \
|
||||
{CLK_tb.dut.counter[2]}
|
||||
{CLK_tb.dut.counter} \
|
||||
|
||||
|
||||
set id [waveform add -signals [list {nc::CLK_tb.COUNT} ]]
|
||||
|
||||
|
||||
@ -77,13 +77,13 @@ module CLK_tb ();
|
||||
// Declare the input clock signals
|
||||
reg CLK_IN1 = 1;
|
||||
|
||||
// The high bits of the sampling counters
|
||||
wire [2:1] COUNT;
|
||||
// The high bit of the sampling counter
|
||||
wire COUNT;
|
||||
// Connect the feedback
|
||||
wire CLKFB_OUT;
|
||||
wire CLKFB_IN = CLKFB_OUT;
|
||||
reg COUNTER_RESET = 0;
|
||||
wire [2:1] CLK_OUT;
|
||||
wire [1:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
reg [13:0] timeout_counter = 14'b00000000000000;
|
||||
|
||||
505
fpga/ipcore_dir/tmp/customization_gui.0.0754907550642.out
Normal file
505
fpga/ipcore_dir/tmp/customization_gui.0.0754907550642.out
Normal file
@ -0,0 +1,505 @@
|
||||
SET_FLAG DEBUG FALSE
|
||||
SET_FLAG MODE BATCH
|
||||
SET_FLAG STANDALONE_MODE FALSE
|
||||
SET_PREFERENCE devicefamily spartan6
|
||||
SET_PREFERENCE device xc6slx9
|
||||
SET_PREFERENCE speedgrade -2
|
||||
SET_PREFERENCE package ftg256
|
||||
SET_PREFERENCE verilogsim true
|
||||
SET_PREFERENCE vhdlsim false
|
||||
SET_PREFERENCE simulationfiles Behavioral
|
||||
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
|
||||
SET_PREFERENCE outputdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/
|
||||
SET_PREFERENCE workingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/
|
||||
SET_PREFERENCE subworkingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/
|
||||
SET_PREFERENCE transientdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/_dbg/
|
||||
SET_PREFERENCE designentry Verilog
|
||||
SET_PREFERENCE flowvendor Other
|
||||
SET_PREFERENCE addpads false
|
||||
SET_PREFERENCE projectname coregen
|
||||
SET_PREFERENCE formalverification false
|
||||
SET_PREFERENCE asysymbol false
|
||||
SET_PREFERENCE implementationfiletype Ngc
|
||||
SET_PREFERENCE foundationsym false
|
||||
SET_PREFERENCE createndf false
|
||||
SET_PREFERENCE removerpms false
|
||||
SET_PARAMETER Component_Name CLK
|
||||
SET_PARAMETER Use_Freq_Synth true
|
||||
SET_PARAMETER Use_Phase_Alignment true
|
||||
SET_PARAMETER Use_Min_Power false
|
||||
SET_PARAMETER Use_Dyn_Phase_Shift false
|
||||
SET_PARAMETER Use_Dyn_Reconfig false
|
||||
SET_PARAMETER Jitter_Sel No_Jitter
|
||||
SET_PARAMETER Use_Spread_Spectrum false
|
||||
SET_PARAMETER Use_Spread_Spectrum_1 false
|
||||
SET_PARAMETER Prim_In_Freq 33.3333
|
||||
SET_PARAMETER In_Freq_Units Units_MHz
|
||||
SET_PARAMETER In_Jitter_Units Units_UI
|
||||
SET_PARAMETER Relative_Inclk REL_PRIMARY
|
||||
SET_PARAMETER Secondary_In_Freq 100.000
|
||||
SET_PARAMETER Jitter_Options PS
|
||||
SET_PARAMETER Clkin1_UI_Jitter 250.000
|
||||
SET_PARAMETER Clkin2_UI_Jitter 100.000
|
||||
SET_PARAMETER Prim_In_Jitter 0.00833333333333
|
||||
SET_PARAMETER Secondary_In_Jitter 0.004
|
||||
SET_PARAMETER Clkin1_Jitter_Ps 250.0
|
||||
SET_PARAMETER Clkin2_Jitter_Ps 40.0
|
||||
SET_PARAMETER Clkout2_Used false
|
||||
SET_PARAMETER Clkout3_Used false
|
||||
SET_PARAMETER Clkout4_Used false
|
||||
SET_PARAMETER Clkout5_Used false
|
||||
SET_PARAMETER Clkout6_Used false
|
||||
SET_PARAMETER Clkout7_Used false
|
||||
SET_PARAMETER Num_Out_Clks 1
|
||||
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER primary_port CLKIN
|
||||
SET_PARAMETER CLK_OUT1_port FSBCLK
|
||||
SET_PARAMETER CLK_OUT2_port RAMCLK
|
||||
SET_PARAMETER CLK_OUT3_port CPUCLK
|
||||
SET_PARAMETER CLK_OUT4_port C80M
|
||||
SET_PARAMETER CLK_OUT5_port C50M
|
||||
SET_PARAMETER CLK_OUT6_port CLK_OUT6
|
||||
SET_PARAMETER CLK_OUT7_port CLK_OUT7
|
||||
SET_PARAMETER DADDR_port DADDR
|
||||
SET_PARAMETER DCLK_port DCLK
|
||||
SET_PARAMETER DRDY_port DRDY
|
||||
SET_PARAMETER DWE_port DWE
|
||||
SET_PARAMETER DIN_port DIN
|
||||
SET_PARAMETER DOUT_port DOUT
|
||||
SET_PARAMETER DEN_port DEN
|
||||
SET_PARAMETER PSCLK_port PSCLK
|
||||
SET_PARAMETER PSEN_port PSEN
|
||||
SET_PARAMETER PSINCDEC_port PSINCDEC
|
||||
SET_PARAMETER PSDONE_port PSDONE
|
||||
SET_PARAMETER Clkout1_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout1_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout2_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout2_Requested_Phase 0
|
||||
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout3_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout3_Requested_Phase -72
|
||||
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout4_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout4_Requested_Phase 0
|
||||
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout5_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout5_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout6_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout6_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout7_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout7_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Use_Max_I_Jitter false
|
||||
SET_PARAMETER Use_Min_O_Jitter false
|
||||
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Use_Inclk_Switchover false
|
||||
SET_PARAMETER secondary_port CLK_IN2
|
||||
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Clkout1_Drives BUFG
|
||||
SET_PARAMETER Clkout2_Drives BUFG
|
||||
SET_PARAMETER Clkout3_Drives BUFG
|
||||
SET_PARAMETER Clkout4_Drives BUFG
|
||||
SET_PARAMETER Clkout5_Drives BUFG
|
||||
SET_PARAMETER Clkout6_Drives BUFG
|
||||
SET_PARAMETER Clkout7_Drives BUFG
|
||||
SET_PARAMETER Feedback_Source FDBK_AUTO_OFFCHIP
|
||||
SET_PARAMETER Clkfb_In_Signaling SINGLE
|
||||
SET_PARAMETER CLKFB_IN_port CLKFB_IN
|
||||
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
|
||||
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
|
||||
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
|
||||
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
|
||||
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
|
||||
SET_PARAMETER Platform nt
|
||||
SET_PARAMETER Summary_Strings empty
|
||||
SET_PARAMETER Use_Locked false
|
||||
SET_PARAMETER calc_done DONE
|
||||
SET_PARAMETER Use_Reset false
|
||||
SET_PARAMETER Use_Power_Down false
|
||||
SET_PARAMETER Use_Status false
|
||||
SET_PARAMETER Use_Freeze false
|
||||
SET_PARAMETER Use_Clk_Valid false
|
||||
SET_PARAMETER Use_Inclk_Stopped false
|
||||
SET_PARAMETER Use_Clkfb_Stopped false
|
||||
SET_PARAMETER RESET_port RESET
|
||||
SET_PARAMETER LOCKED_port LOCKED
|
||||
SET_PARAMETER Power_Down_port POWER_DOWN
|
||||
SET_PARAMETER CLK_VALID_port CLK_VALID
|
||||
SET_PARAMETER STATUS_port STATUS
|
||||
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
|
||||
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
|
||||
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
|
||||
SET_PARAMETER Override_Mmcm false
|
||||
SET_PARAMETER Mmcm_Notes None
|
||||
SET_PARAMETER Mmcm_Divclk_Divide 1
|
||||
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkin1_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkin2_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Cascade false
|
||||
SET_PARAMETER Mmcm_Clock_Hold false
|
||||
SET_PARAMETER Mmcm_Compensation ZHOLD
|
||||
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
|
||||
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
|
||||
SET_PARAMETER Mmcm_Startup_Wait false
|
||||
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout1_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout2_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout3_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout4_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout5_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout6_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
|
||||
SET_PARAMETER Override_Dcm false
|
||||
SET_PARAMETER Dcm_Notes None
|
||||
SET_PARAMETER Dcm_Clkdv_Divide 2.0
|
||||
SET_PARAMETER Dcm_Clkfx_Divide 1
|
||||
SET_PARAMETER Dcm_Clkfx_Multiply 4
|
||||
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
|
||||
SET_PARAMETER Dcm_Clkin_Period 30.000
|
||||
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
|
||||
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
|
||||
SET_PARAMETER Dcm_Phase_Shift 0
|
||||
SET_PARAMETER Dcm_Clk_Feedback 1X
|
||||
SET_PARAMETER Dcm_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clk_Out1_Port CLK0
|
||||
SET_PARAMETER Dcm_Clk_Out2_Port CLK2X
|
||||
SET_PARAMETER Dcm_Clk_Out3_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out4_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out5_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
|
||||
SET_PARAMETER Override_Dcm_Clkgen false
|
||||
SET_PARAMETER Dcm_Clkgen_Notes None
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
|
||||
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clkgen_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX180
|
||||
SET_PARAMETER Override_Pll false
|
||||
SET_PARAMETER Pll_Notes None
|
||||
SET_PARAMETER Pll_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Pll_Clkfbout_Mult 12
|
||||
SET_PARAMETER Pll_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
|
||||
SET_PARAMETER Pll_Divclk_Divide 1
|
||||
SET_PARAMETER Pll_Clkin_Period 30.0
|
||||
SET_PARAMETER Pll_Compensation EXTERNAL
|
||||
SET_PARAMETER Pll_Ref_Jitter 0.008
|
||||
SET_PARAMETER Pll_Clkout0_Divide 6
|
||||
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout1_Divide 10
|
||||
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout2_Divide 10
|
||||
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout2_Phase -72.000
|
||||
SET_PARAMETER Pll_Clkout3_Divide 10
|
||||
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout4_Divide 16
|
||||
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout5_Divide 1
|
||||
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout5_Phase 0.000
|
||||
SET_PARAMETER dcm_pll_cascade NONE
|
||||
SET_PARAMETER clock_mgr_type MANUAL
|
||||
SET_PARAMETER primtype_sel PLL_BASE
|
||||
SET_PARAMETER primitive MMCM
|
||||
SET_PARAMETER SS_Mode CENTER_HIGH
|
||||
SET_PARAMETER SS_Mod_Freq 250
|
||||
SET_SIM_PARAMETER c_clkout2_used 0
|
||||
SET_SIM_PARAMETER c_clkout3_used 0
|
||||
SET_SIM_PARAMETER c_clkout4_used 0
|
||||
SET_SIM_PARAMETER c_clkout5_used 0
|
||||
SET_SIM_PARAMETER c_clkout6_used 0
|
||||
SET_SIM_PARAMETER c_clkout7_used 0
|
||||
SET_SIM_PARAMETER c_use_clkout1_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout2_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout3_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout4_bar 0
|
||||
SET_SIM_PARAMETER c_component_name CLK
|
||||
SET_SIM_PARAMETER c_platform nt
|
||||
SET_SIM_PARAMETER c_use_freq_synth 1
|
||||
SET_SIM_PARAMETER c_use_phase_alignment 1
|
||||
SET_SIM_PARAMETER c_prim_in_jitter 0.00833333333333
|
||||
SET_SIM_PARAMETER c_secondary_in_jitter 0.004
|
||||
SET_SIM_PARAMETER c_jitter_sel No_Jitter
|
||||
SET_SIM_PARAMETER c_use_min_power 0
|
||||
SET_SIM_PARAMETER c_use_min_o_jitter 0
|
||||
SET_SIM_PARAMETER c_use_max_i_jitter 0
|
||||
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
|
||||
SET_SIM_PARAMETER c_use_inclk_switchover 0
|
||||
SET_SIM_PARAMETER c_use_dyn_reconfig 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
|
||||
SET_SIM_PARAMETER c_primtype_sel PLL_BASE
|
||||
SET_SIM_PARAMETER c_use_clk_valid 0
|
||||
SET_SIM_PARAMETER c_prim_in_freq 33.3333
|
||||
SET_SIM_PARAMETER c_in_freq_units Units_MHz
|
||||
SET_SIM_PARAMETER c_secondary_in_freq 100.000
|
||||
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO_OFFCHIP
|
||||
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
|
||||
SET_SIM_PARAMETER c_use_reset 0
|
||||
SET_SIM_PARAMETER c_use_locked 0
|
||||
SET_SIM_PARAMETER c_use_inclk_stopped 0
|
||||
SET_SIM_PARAMETER c_use_clkfb_stopped 0
|
||||
SET_SIM_PARAMETER c_use_power_down 0
|
||||
SET_SIM_PARAMETER c_use_status 0
|
||||
SET_SIM_PARAMETER c_use_freeze 0
|
||||
SET_SIM_PARAMETER c_num_out_clks 1
|
||||
SET_SIM_PARAMETER c_clkout1_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout2_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout3_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout4_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout5_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout6_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout7_drives BUFG
|
||||
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
SET_SIM_PARAMETER c_inclk_sum_row1 __primary_________33.3333___________0.00833333333333
|
||||
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____66.667______0.000______50.0______300.590____267.927
|
||||
SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
|
||||
SET_SIM_PARAMETER c_clkout1_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout3_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout4_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout5_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout6_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout7_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_phase -72
|
||||
SET_SIM_PARAMETER c_clkout4_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout1_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout3_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout4_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout5_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout6_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout7_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout3_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout4_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout5_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout6_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout7_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_mmcm_notes None
|
||||
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
|
||||
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_pll_notes None
|
||||
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_mult 12
|
||||
SET_SIM_PARAMETER c_pll_clkin_period 30.0
|
||||
SET_SIM_PARAMETER c_pll_compensation EXTERNAL
|
||||
SET_SIM_PARAMETER c_pll_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_pll_ref_jitter 0.008
|
||||
SET_SIM_PARAMETER c_pll_clkout0_divide 6
|
||||
SET_SIM_PARAMETER c_pll_clkout1_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout2_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout3_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout4_divide 16
|
||||
SET_SIM_PARAMETER c_pll_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout2_phase -72.000
|
||||
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_dcm_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_divide 1
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_multiply 4
|
||||
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkin_period 30.0
|
||||
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback 1X
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback_port CLKOUT1
|
||||
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
|
||||
SET_SIM_PARAMETER c_dcm_phase_shift 0
|
||||
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out1_port CLK0
|
||||
SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 30.0
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
|
||||
SET_SIM_PARAMETER c_clock_mgr_type MANUAL
|
||||
SET_SIM_PARAMETER c_override_mmcm 0
|
||||
SET_SIM_PARAMETER c_override_pll 0
|
||||
SET_SIM_PARAMETER c_override_dcm 0
|
||||
SET_SIM_PARAMETER c_override_dcm_clkgen 0
|
||||
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
|
||||
SET_SIM_PARAMETER c_primary_port CLKIN
|
||||
SET_SIM_PARAMETER c_secondary_port CLK_IN2
|
||||
SET_SIM_PARAMETER c_clk_out1_port FSBCLK
|
||||
SET_SIM_PARAMETER c_clk_out2_port RAMCLK
|
||||
SET_SIM_PARAMETER c_clk_out3_port CPUCLK
|
||||
SET_SIM_PARAMETER c_clk_out4_port C80M
|
||||
SET_SIM_PARAMETER c_clk_out5_port C50M
|
||||
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
|
||||
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
|
||||
SET_SIM_PARAMETER c_reset_port RESET
|
||||
SET_SIM_PARAMETER c_locked_port LOCKED
|
||||
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
|
||||
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
|
||||
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
|
||||
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
|
||||
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
|
||||
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
|
||||
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
|
||||
SET_SIM_PARAMETER c_daddr_port DADDR
|
||||
SET_SIM_PARAMETER c_dclk_port DCLK
|
||||
SET_SIM_PARAMETER c_drdy_port DRDY
|
||||
SET_SIM_PARAMETER c_dwe_port DWE
|
||||
SET_SIM_PARAMETER c_din_port DIN
|
||||
SET_SIM_PARAMETER c_dout_port DOUT
|
||||
SET_SIM_PARAMETER c_den_port DEN
|
||||
SET_SIM_PARAMETER c_psclk_port PSCLK
|
||||
SET_SIM_PARAMETER c_psen_port PSEN
|
||||
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
|
||||
SET_SIM_PARAMETER c_psdone_port PSDONE
|
||||
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
|
||||
SET_SIM_PARAMETER c_status_port STATUS
|
||||
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
|
||||
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
|
||||
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
|
||||
SET_SIM_PARAMETER c_clkin1_jitter_ps 250.0
|
||||
SET_SIM_PARAMETER c_clkin2_jitter_ps 40.0
|
||||
SET_SIM_PARAMETER c_primitive MMCM
|
||||
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
|
||||
SET_SIM_PARAMETER c_ss_mod_period 4000
|
||||
SET_CORE_NAME Clocking Wizard
|
||||
SET_CORE_VERSION 3.6
|
||||
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
|
||||
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
|
||||
SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
|
||||
SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
|
||||
SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
|
||||
505
fpga/ipcore_dir/tmp/customization_gui.0.114951344726.out
Normal file
505
fpga/ipcore_dir/tmp/customization_gui.0.114951344726.out
Normal file
@ -0,0 +1,505 @@
|
||||
SET_FLAG DEBUG FALSE
|
||||
SET_FLAG MODE BATCH
|
||||
SET_FLAG STANDALONE_MODE FALSE
|
||||
SET_PREFERENCE devicefamily spartan6
|
||||
SET_PREFERENCE device xc6slx9
|
||||
SET_PREFERENCE speedgrade -2
|
||||
SET_PREFERENCE package ftg256
|
||||
SET_PREFERENCE verilogsim true
|
||||
SET_PREFERENCE vhdlsim false
|
||||
SET_PREFERENCE simulationfiles Behavioral
|
||||
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
|
||||
SET_PREFERENCE outputdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/
|
||||
SET_PREFERENCE workingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/
|
||||
SET_PREFERENCE subworkingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/
|
||||
SET_PREFERENCE transientdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/_dbg/
|
||||
SET_PREFERENCE designentry Verilog
|
||||
SET_PREFERENCE flowvendor Other
|
||||
SET_PREFERENCE addpads false
|
||||
SET_PREFERENCE projectname coregen
|
||||
SET_PREFERENCE formalverification false
|
||||
SET_PREFERENCE asysymbol false
|
||||
SET_PREFERENCE implementationfiletype Ngc
|
||||
SET_PREFERENCE foundationsym false
|
||||
SET_PREFERENCE createndf false
|
||||
SET_PREFERENCE removerpms false
|
||||
SET_PARAMETER Component_Name CLK
|
||||
SET_PARAMETER Use_Freq_Synth true
|
||||
SET_PARAMETER Use_Phase_Alignment true
|
||||
SET_PARAMETER Use_Min_Power false
|
||||
SET_PARAMETER Use_Dyn_Phase_Shift false
|
||||
SET_PARAMETER Use_Dyn_Reconfig false
|
||||
SET_PARAMETER Jitter_Sel No_Jitter
|
||||
SET_PARAMETER Use_Spread_Spectrum false
|
||||
SET_PARAMETER Use_Spread_Spectrum_1 false
|
||||
SET_PARAMETER Prim_In_Freq 40
|
||||
SET_PARAMETER In_Freq_Units Units_MHz
|
||||
SET_PARAMETER In_Jitter_Units Units_UI
|
||||
SET_PARAMETER Relative_Inclk REL_PRIMARY
|
||||
SET_PARAMETER Secondary_In_Freq 100.000
|
||||
SET_PARAMETER Jitter_Options PS
|
||||
SET_PARAMETER Clkin1_UI_Jitter 250.000
|
||||
SET_PARAMETER Clkin2_UI_Jitter 100.000
|
||||
SET_PARAMETER Prim_In_Jitter 0.01
|
||||
SET_PARAMETER Secondary_In_Jitter 0.004
|
||||
SET_PARAMETER Clkin1_Jitter_Ps 250.0
|
||||
SET_PARAMETER Clkin2_Jitter_Ps 40.0
|
||||
SET_PARAMETER Clkout2_Used true
|
||||
SET_PARAMETER Clkout3_Used true
|
||||
SET_PARAMETER Clkout4_Used true
|
||||
SET_PARAMETER Clkout5_Used true
|
||||
SET_PARAMETER Clkout6_Used false
|
||||
SET_PARAMETER Clkout7_Used false
|
||||
SET_PARAMETER Num_Out_Clks 5
|
||||
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER primary_port CLKIN
|
||||
SET_PARAMETER CLK_OUT1_port FSBCLK
|
||||
SET_PARAMETER CLK_OUT2_port RAMCLK
|
||||
SET_PARAMETER CLK_OUT3_port CPUCLK
|
||||
SET_PARAMETER CLK_OUT4_port C80M
|
||||
SET_PARAMETER CLK_OUT5_port C50M
|
||||
SET_PARAMETER CLK_OUT6_port CLK_OUT6
|
||||
SET_PARAMETER CLK_OUT7_port CLK_OUT7
|
||||
SET_PARAMETER DADDR_port DADDR
|
||||
SET_PARAMETER DCLK_port DCLK
|
||||
SET_PARAMETER DRDY_port DRDY
|
||||
SET_PARAMETER DWE_port DWE
|
||||
SET_PARAMETER DIN_port DIN
|
||||
SET_PARAMETER DOUT_port DOUT
|
||||
SET_PARAMETER DEN_port DEN
|
||||
SET_PARAMETER PSCLK_port PSCLK
|
||||
SET_PARAMETER PSEN_port PSEN
|
||||
SET_PARAMETER PSINCDEC_port PSINCDEC
|
||||
SET_PARAMETER PSDONE_port PSDONE
|
||||
SET_PARAMETER Clkout1_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout1_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout2_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout2_Requested_Phase 0
|
||||
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout3_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout3_Requested_Phase 0
|
||||
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout4_Requested_Out_Freq 80
|
||||
SET_PARAMETER Clkout4_Requested_Phase 0
|
||||
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout5_Requested_Out_Freq 50
|
||||
SET_PARAMETER Clkout5_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout6_Requested_Out_Freq 33.000
|
||||
SET_PARAMETER Clkout6_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout7_Requested_Out_Freq 33.000
|
||||
SET_PARAMETER Clkout7_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Use_Max_I_Jitter false
|
||||
SET_PARAMETER Use_Min_O_Jitter false
|
||||
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Use_Inclk_Switchover false
|
||||
SET_PARAMETER secondary_port CLK_IN2
|
||||
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Clkout1_Drives BUFG
|
||||
SET_PARAMETER Clkout2_Drives BUFG
|
||||
SET_PARAMETER Clkout3_Drives BUFG
|
||||
SET_PARAMETER Clkout4_Drives BUFG
|
||||
SET_PARAMETER Clkout5_Drives BUFG
|
||||
SET_PARAMETER Clkout6_Drives BUFG
|
||||
SET_PARAMETER Clkout7_Drives BUFG
|
||||
SET_PARAMETER Feedback_Source FDBK_AUTO_OFFCHIP
|
||||
SET_PARAMETER Clkfb_In_Signaling SINGLE
|
||||
SET_PARAMETER CLKFB_IN_port CLKFB_IN
|
||||
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
|
||||
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
|
||||
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
|
||||
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
|
||||
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
|
||||
SET_PARAMETER Platform nt
|
||||
SET_PARAMETER Summary_Strings empty
|
||||
SET_PARAMETER Use_Locked false
|
||||
SET_PARAMETER calc_done DONE
|
||||
SET_PARAMETER Use_Reset false
|
||||
SET_PARAMETER Use_Power_Down false
|
||||
SET_PARAMETER Use_Status false
|
||||
SET_PARAMETER Use_Freeze false
|
||||
SET_PARAMETER Use_Clk_Valid false
|
||||
SET_PARAMETER Use_Inclk_Stopped false
|
||||
SET_PARAMETER Use_Clkfb_Stopped false
|
||||
SET_PARAMETER RESET_port RESET
|
||||
SET_PARAMETER LOCKED_port LOCKED
|
||||
SET_PARAMETER Power_Down_port POWER_DOWN
|
||||
SET_PARAMETER CLK_VALID_port CLK_VALID
|
||||
SET_PARAMETER STATUS_port STATUS
|
||||
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
|
||||
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
|
||||
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
|
||||
SET_PARAMETER Override_Mmcm false
|
||||
SET_PARAMETER Mmcm_Notes None
|
||||
SET_PARAMETER Mmcm_Divclk_Divide 1
|
||||
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkin1_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkin2_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Cascade false
|
||||
SET_PARAMETER Mmcm_Clock_Hold false
|
||||
SET_PARAMETER Mmcm_Compensation ZHOLD
|
||||
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
|
||||
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
|
||||
SET_PARAMETER Mmcm_Startup_Wait false
|
||||
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout1_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout2_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout3_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout4_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout5_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout6_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
|
||||
SET_PARAMETER Override_Dcm false
|
||||
SET_PARAMETER Dcm_Notes None
|
||||
SET_PARAMETER Dcm_Clkdv_Divide 2.0
|
||||
SET_PARAMETER Dcm_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
|
||||
SET_PARAMETER Dcm_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
|
||||
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
|
||||
SET_PARAMETER Dcm_Phase_Shift 0
|
||||
SET_PARAMETER Dcm_Clk_Feedback NONE
|
||||
SET_PARAMETER Dcm_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out3_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out4_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out5_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
|
||||
SET_PARAMETER Override_Dcm_Clkgen false
|
||||
SET_PARAMETER Dcm_Clkgen_Notes None
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
|
||||
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clkgen_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX180
|
||||
SET_PARAMETER Override_Pll false
|
||||
SET_PARAMETER Pll_Notes None
|
||||
SET_PARAMETER Pll_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Pll_Clkfbout_Mult 10
|
||||
SET_PARAMETER Pll_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
|
||||
SET_PARAMETER Pll_Divclk_Divide 1
|
||||
SET_PARAMETER Pll_Clkin_Period 25.0
|
||||
SET_PARAMETER Pll_Compensation EXTERNAL
|
||||
SET_PARAMETER Pll_Ref_Jitter 0.010
|
||||
SET_PARAMETER Pll_Clkout0_Divide 6
|
||||
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout1_Divide 6
|
||||
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout2_Divide 6
|
||||
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout2_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout3_Divide 5
|
||||
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout4_Divide 8
|
||||
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout5_Divide 1
|
||||
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout5_Phase 0.000
|
||||
SET_PARAMETER dcm_pll_cascade NONE
|
||||
SET_PARAMETER clock_mgr_type MANUAL
|
||||
SET_PARAMETER primtype_sel PLL_BASE
|
||||
SET_PARAMETER primitive MMCM
|
||||
SET_PARAMETER SS_Mode CENTER_HIGH
|
||||
SET_PARAMETER SS_Mod_Freq 250
|
||||
SET_SIM_PARAMETER c_clkout2_used 1
|
||||
SET_SIM_PARAMETER c_clkout3_used 1
|
||||
SET_SIM_PARAMETER c_clkout4_used 1
|
||||
SET_SIM_PARAMETER c_clkout5_used 1
|
||||
SET_SIM_PARAMETER c_clkout6_used 0
|
||||
SET_SIM_PARAMETER c_clkout7_used 0
|
||||
SET_SIM_PARAMETER c_use_clkout1_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout2_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout3_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout4_bar 0
|
||||
SET_SIM_PARAMETER c_component_name CLK
|
||||
SET_SIM_PARAMETER c_platform nt
|
||||
SET_SIM_PARAMETER c_use_freq_synth 1
|
||||
SET_SIM_PARAMETER c_use_phase_alignment 1
|
||||
SET_SIM_PARAMETER c_prim_in_jitter 0.01
|
||||
SET_SIM_PARAMETER c_secondary_in_jitter 0.004
|
||||
SET_SIM_PARAMETER c_jitter_sel No_Jitter
|
||||
SET_SIM_PARAMETER c_use_min_power 0
|
||||
SET_SIM_PARAMETER c_use_min_o_jitter 0
|
||||
SET_SIM_PARAMETER c_use_max_i_jitter 0
|
||||
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
|
||||
SET_SIM_PARAMETER c_use_inclk_switchover 0
|
||||
SET_SIM_PARAMETER c_use_dyn_reconfig 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
|
||||
SET_SIM_PARAMETER c_primtype_sel PLL_BASE
|
||||
SET_SIM_PARAMETER c_use_clk_valid 0
|
||||
SET_SIM_PARAMETER c_prim_in_freq 40
|
||||
SET_SIM_PARAMETER c_in_freq_units Units_MHz
|
||||
SET_SIM_PARAMETER c_secondary_in_freq 100.000
|
||||
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO_OFFCHIP
|
||||
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
|
||||
SET_SIM_PARAMETER c_use_reset 0
|
||||
SET_SIM_PARAMETER c_use_locked 0
|
||||
SET_SIM_PARAMETER c_use_inclk_stopped 0
|
||||
SET_SIM_PARAMETER c_use_clkfb_stopped 0
|
||||
SET_SIM_PARAMETER c_use_power_down 0
|
||||
SET_SIM_PARAMETER c_use_status 0
|
||||
SET_SIM_PARAMETER c_use_freeze 0
|
||||
SET_SIM_PARAMETER c_num_out_clks 5
|
||||
SET_SIM_PARAMETER c_clkout1_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout2_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout3_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout4_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout5_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout6_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout7_drives BUFG
|
||||
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
SET_SIM_PARAMETER c_inclk_sum_row1 __primary______________40_____________0.01
|
||||
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____66.667______0.000______50.0______279.382____259.584
|
||||
SET_SIM_PARAMETER c_outclk_sum_row2 CLK_OUT2____66.667______0.000______50.0______279.382____259.584
|
||||
SET_SIM_PARAMETER c_outclk_sum_row3 CLK_OUT3____66.667______0.000______50.0______279.382____259.584
|
||||
SET_SIM_PARAMETER c_outclk_sum_row4 CLK_OUT4____80.000______0.000______50.0______268.445____259.584
|
||||
SET_SIM_PARAMETER c_outclk_sum_row5 CLK_OUT5____50.000______0.000______50.0______297.425____259.584
|
||||
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
|
||||
SET_SIM_PARAMETER c_clkout1_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout3_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout4_requested_out_freq 80
|
||||
SET_SIM_PARAMETER c_clkout5_requested_out_freq 50
|
||||
SET_SIM_PARAMETER c_clkout6_requested_out_freq 33.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_out_freq 33.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout4_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout1_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout3_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout4_out_freq 80.000
|
||||
SET_SIM_PARAMETER c_clkout5_out_freq 50.000
|
||||
SET_SIM_PARAMETER c_clkout6_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout7_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout6_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout7_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout3_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout4_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout5_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_mmcm_notes None
|
||||
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
|
||||
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_pll_notes None
|
||||
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_mult 10
|
||||
SET_SIM_PARAMETER c_pll_clkin_period 25.0
|
||||
SET_SIM_PARAMETER c_pll_compensation EXTERNAL
|
||||
SET_SIM_PARAMETER c_pll_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_pll_ref_jitter 0.010
|
||||
SET_SIM_PARAMETER c_pll_clkout0_divide 6
|
||||
SET_SIM_PARAMETER c_pll_clkout1_divide 6
|
||||
SET_SIM_PARAMETER c_pll_clkout2_divide 6
|
||||
SET_SIM_PARAMETER c_pll_clkout3_divide 5
|
||||
SET_SIM_PARAMETER c_pll_clkout4_divide 8
|
||||
SET_SIM_PARAMETER c_pll_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_dcm_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkin_period 25.0
|
||||
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback_port CLKOUT1
|
||||
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
|
||||
SET_SIM_PARAMETER c_dcm_phase_shift 0
|
||||
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out2_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out3_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out4_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out5_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out6_port CLK0
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 25.0
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port CLKFX180
|
||||
SET_SIM_PARAMETER c_clock_mgr_type MANUAL
|
||||
SET_SIM_PARAMETER c_override_mmcm 0
|
||||
SET_SIM_PARAMETER c_override_pll 0
|
||||
SET_SIM_PARAMETER c_override_dcm 0
|
||||
SET_SIM_PARAMETER c_override_dcm_clkgen 0
|
||||
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
|
||||
SET_SIM_PARAMETER c_primary_port CLKIN
|
||||
SET_SIM_PARAMETER c_secondary_port CLK_IN2
|
||||
SET_SIM_PARAMETER c_clk_out1_port FSBCLK
|
||||
SET_SIM_PARAMETER c_clk_out2_port RAMCLK
|
||||
SET_SIM_PARAMETER c_clk_out3_port CPUCLK
|
||||
SET_SIM_PARAMETER c_clk_out4_port C80M
|
||||
SET_SIM_PARAMETER c_clk_out5_port C50M
|
||||
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
|
||||
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
|
||||
SET_SIM_PARAMETER c_reset_port RESET
|
||||
SET_SIM_PARAMETER c_locked_port LOCKED
|
||||
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
|
||||
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
|
||||
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
|
||||
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
|
||||
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
|
||||
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
|
||||
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
|
||||
SET_SIM_PARAMETER c_daddr_port DADDR
|
||||
SET_SIM_PARAMETER c_dclk_port DCLK
|
||||
SET_SIM_PARAMETER c_drdy_port DRDY
|
||||
SET_SIM_PARAMETER c_dwe_port DWE
|
||||
SET_SIM_PARAMETER c_din_port DIN
|
||||
SET_SIM_PARAMETER c_dout_port DOUT
|
||||
SET_SIM_PARAMETER c_den_port DEN
|
||||
SET_SIM_PARAMETER c_psclk_port PSCLK
|
||||
SET_SIM_PARAMETER c_psen_port PSEN
|
||||
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
|
||||
SET_SIM_PARAMETER c_psdone_port PSDONE
|
||||
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
|
||||
SET_SIM_PARAMETER c_status_port STATUS
|
||||
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
|
||||
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
|
||||
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
|
||||
SET_SIM_PARAMETER c_clkin1_jitter_ps 250.0
|
||||
SET_SIM_PARAMETER c_clkin2_jitter_ps 40.0
|
||||
SET_SIM_PARAMETER c_primitive MMCM
|
||||
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
|
||||
SET_SIM_PARAMETER c_ss_mod_period 4000
|
||||
SET_CORE_NAME Clocking Wizard
|
||||
SET_CORE_VERSION 3.6
|
||||
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
|
||||
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
|
||||
SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
|
||||
SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
|
||||
SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
|
||||
505
fpga/ipcore_dir/tmp/customization_gui.0.505732142602.out
Normal file
505
fpga/ipcore_dir/tmp/customization_gui.0.505732142602.out
Normal file
@ -0,0 +1,505 @@
|
||||
SET_FLAG DEBUG FALSE
|
||||
SET_FLAG MODE BATCH
|
||||
SET_FLAG STANDALONE_MODE FALSE
|
||||
SET_PREFERENCE devicefamily spartan6
|
||||
SET_PREFERENCE device xc6slx9
|
||||
SET_PREFERENCE speedgrade -2
|
||||
SET_PREFERENCE package ftg256
|
||||
SET_PREFERENCE verilogsim true
|
||||
SET_PREFERENCE vhdlsim false
|
||||
SET_PREFERENCE simulationfiles Behavioral
|
||||
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
|
||||
SET_PREFERENCE outputdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/
|
||||
SET_PREFERENCE workingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/
|
||||
SET_PREFERENCE subworkingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/
|
||||
SET_PREFERENCE transientdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/_dbg/
|
||||
SET_PREFERENCE designentry Verilog
|
||||
SET_PREFERENCE flowvendor Other
|
||||
SET_PREFERENCE addpads false
|
||||
SET_PREFERENCE projectname coregen
|
||||
SET_PREFERENCE formalverification false
|
||||
SET_PREFERENCE asysymbol false
|
||||
SET_PREFERENCE implementationfiletype Ngc
|
||||
SET_PREFERENCE foundationsym false
|
||||
SET_PREFERENCE createndf false
|
||||
SET_PREFERENCE removerpms false
|
||||
SET_PARAMETER Component_Name CLK
|
||||
SET_PARAMETER Use_Freq_Synth true
|
||||
SET_PARAMETER Use_Phase_Alignment true
|
||||
SET_PARAMETER Use_Min_Power false
|
||||
SET_PARAMETER Use_Dyn_Phase_Shift false
|
||||
SET_PARAMETER Use_Dyn_Reconfig false
|
||||
SET_PARAMETER Jitter_Sel No_Jitter
|
||||
SET_PARAMETER Use_Spread_Spectrum false
|
||||
SET_PARAMETER Use_Spread_Spectrum_1 false
|
||||
SET_PARAMETER Prim_In_Freq 33.3333
|
||||
SET_PARAMETER In_Freq_Units Units_MHz
|
||||
SET_PARAMETER In_Jitter_Units Units_UI
|
||||
SET_PARAMETER Relative_Inclk REL_PRIMARY
|
||||
SET_PARAMETER Secondary_In_Freq 100.000
|
||||
SET_PARAMETER Jitter_Options PS
|
||||
SET_PARAMETER Clkin1_UI_Jitter 250.000
|
||||
SET_PARAMETER Clkin2_UI_Jitter 100.000
|
||||
SET_PARAMETER Prim_In_Jitter 0.00833333333333
|
||||
SET_PARAMETER Secondary_In_Jitter 0.004
|
||||
SET_PARAMETER Clkin1_Jitter_Ps 250.0
|
||||
SET_PARAMETER Clkin2_Jitter_Ps 40.0
|
||||
SET_PARAMETER Clkout2_Used false
|
||||
SET_PARAMETER Clkout3_Used false
|
||||
SET_PARAMETER Clkout4_Used false
|
||||
SET_PARAMETER Clkout5_Used false
|
||||
SET_PARAMETER Clkout6_Used false
|
||||
SET_PARAMETER Clkout7_Used false
|
||||
SET_PARAMETER Num_Out_Clks 1
|
||||
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER primary_port CLKIN
|
||||
SET_PARAMETER CLK_OUT1_port FSBCLK
|
||||
SET_PARAMETER CLK_OUT2_port RAMCLK
|
||||
SET_PARAMETER CLK_OUT3_port CPUCLK
|
||||
SET_PARAMETER CLK_OUT4_port C80M
|
||||
SET_PARAMETER CLK_OUT5_port C50M
|
||||
SET_PARAMETER CLK_OUT6_port CLK_OUT6
|
||||
SET_PARAMETER CLK_OUT7_port CLK_OUT7
|
||||
SET_PARAMETER DADDR_port DADDR
|
||||
SET_PARAMETER DCLK_port DCLK
|
||||
SET_PARAMETER DRDY_port DRDY
|
||||
SET_PARAMETER DWE_port DWE
|
||||
SET_PARAMETER DIN_port DIN
|
||||
SET_PARAMETER DOUT_port DOUT
|
||||
SET_PARAMETER DEN_port DEN
|
||||
SET_PARAMETER PSCLK_port PSCLK
|
||||
SET_PARAMETER PSEN_port PSEN
|
||||
SET_PARAMETER PSINCDEC_port PSINCDEC
|
||||
SET_PARAMETER PSDONE_port PSDONE
|
||||
SET_PARAMETER Clkout1_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout1_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout2_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout2_Requested_Phase 0
|
||||
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout3_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout3_Requested_Phase -72
|
||||
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout4_Requested_Out_Freq 80
|
||||
SET_PARAMETER Clkout4_Requested_Phase 0
|
||||
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout5_Requested_Out_Freq 50
|
||||
SET_PARAMETER Clkout5_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout6_Requested_Out_Freq 33.000
|
||||
SET_PARAMETER Clkout6_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout7_Requested_Out_Freq 33.000
|
||||
SET_PARAMETER Clkout7_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Use_Max_I_Jitter false
|
||||
SET_PARAMETER Use_Min_O_Jitter false
|
||||
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Use_Inclk_Switchover false
|
||||
SET_PARAMETER secondary_port CLK_IN2
|
||||
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Clkout1_Drives BUFG
|
||||
SET_PARAMETER Clkout2_Drives BUFG
|
||||
SET_PARAMETER Clkout3_Drives BUFG
|
||||
SET_PARAMETER Clkout4_Drives BUFG
|
||||
SET_PARAMETER Clkout5_Drives BUFG
|
||||
SET_PARAMETER Clkout6_Drives BUFG
|
||||
SET_PARAMETER Clkout7_Drives BUFG
|
||||
SET_PARAMETER Feedback_Source FDBK_AUTO_OFFCHIP
|
||||
SET_PARAMETER Clkfb_In_Signaling SINGLE
|
||||
SET_PARAMETER CLKFB_IN_port CLKFB_IN
|
||||
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
|
||||
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
|
||||
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
|
||||
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
|
||||
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
|
||||
SET_PARAMETER Platform nt
|
||||
SET_PARAMETER Summary_Strings empty
|
||||
SET_PARAMETER Use_Locked false
|
||||
SET_PARAMETER calc_done DONE
|
||||
SET_PARAMETER Use_Reset false
|
||||
SET_PARAMETER Use_Power_Down false
|
||||
SET_PARAMETER Use_Status false
|
||||
SET_PARAMETER Use_Freeze false
|
||||
SET_PARAMETER Use_Clk_Valid false
|
||||
SET_PARAMETER Use_Inclk_Stopped false
|
||||
SET_PARAMETER Use_Clkfb_Stopped false
|
||||
SET_PARAMETER RESET_port RESET
|
||||
SET_PARAMETER LOCKED_port LOCKED
|
||||
SET_PARAMETER Power_Down_port POWER_DOWN
|
||||
SET_PARAMETER CLK_VALID_port CLK_VALID
|
||||
SET_PARAMETER STATUS_port STATUS
|
||||
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
|
||||
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
|
||||
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
|
||||
SET_PARAMETER Override_Mmcm false
|
||||
SET_PARAMETER Mmcm_Notes None
|
||||
SET_PARAMETER Mmcm_Divclk_Divide 1
|
||||
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkin1_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkin2_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Cascade false
|
||||
SET_PARAMETER Mmcm_Clock_Hold false
|
||||
SET_PARAMETER Mmcm_Compensation ZHOLD
|
||||
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
|
||||
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
|
||||
SET_PARAMETER Mmcm_Startup_Wait false
|
||||
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout1_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout2_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout3_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout4_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout5_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout6_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
|
||||
SET_PARAMETER Override_Dcm false
|
||||
SET_PARAMETER Dcm_Notes None
|
||||
SET_PARAMETER Dcm_Clkdv_Divide 2.0
|
||||
SET_PARAMETER Dcm_Clkfx_Divide 1
|
||||
SET_PARAMETER Dcm_Clkfx_Multiply 4
|
||||
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
|
||||
SET_PARAMETER Dcm_Clkin_Period 30.000
|
||||
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
|
||||
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
|
||||
SET_PARAMETER Dcm_Phase_Shift 0
|
||||
SET_PARAMETER Dcm_Clk_Feedback 1X
|
||||
SET_PARAMETER Dcm_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clk_Out1_Port CLK2X
|
||||
SET_PARAMETER Dcm_Clk_Out2_Port CLK2X
|
||||
SET_PARAMETER Dcm_Clk_Out3_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out4_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out5_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
|
||||
SET_PARAMETER Override_Dcm_Clkgen false
|
||||
SET_PARAMETER Dcm_Clkgen_Notes None
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
|
||||
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clkgen_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX180
|
||||
SET_PARAMETER Override_Pll false
|
||||
SET_PARAMETER Pll_Notes None
|
||||
SET_PARAMETER Pll_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Pll_Clkfbout_Mult 20
|
||||
SET_PARAMETER Pll_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
|
||||
SET_PARAMETER Pll_Divclk_Divide 1
|
||||
SET_PARAMETER Pll_Clkin_Period 30.000
|
||||
SET_PARAMETER Pll_Compensation EXTERNAL
|
||||
SET_PARAMETER Pll_Ref_Jitter 0.008
|
||||
SET_PARAMETER Pll_Clkout0_Divide 10
|
||||
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout1_Divide 10
|
||||
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout2_Divide 10
|
||||
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout2_Phase -72.000
|
||||
SET_PARAMETER Pll_Clkout3_Divide 10
|
||||
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout4_Divide 16
|
||||
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout5_Divide 1
|
||||
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout5_Phase 0.000
|
||||
SET_PARAMETER dcm_pll_cascade NONE
|
||||
SET_PARAMETER clock_mgr_type AUTO
|
||||
SET_PARAMETER primtype_sel PLL_BASE
|
||||
SET_PARAMETER primitive MMCM
|
||||
SET_PARAMETER SS_Mode CENTER_HIGH
|
||||
SET_PARAMETER SS_Mod_Freq 250
|
||||
SET_SIM_PARAMETER c_clkout2_used 0
|
||||
SET_SIM_PARAMETER c_clkout3_used 0
|
||||
SET_SIM_PARAMETER c_clkout4_used 0
|
||||
SET_SIM_PARAMETER c_clkout5_used 0
|
||||
SET_SIM_PARAMETER c_clkout6_used 0
|
||||
SET_SIM_PARAMETER c_clkout7_used 0
|
||||
SET_SIM_PARAMETER c_use_clkout1_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout2_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout3_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout4_bar 0
|
||||
SET_SIM_PARAMETER c_component_name CLK
|
||||
SET_SIM_PARAMETER c_platform nt
|
||||
SET_SIM_PARAMETER c_use_freq_synth 1
|
||||
SET_SIM_PARAMETER c_use_phase_alignment 1
|
||||
SET_SIM_PARAMETER c_prim_in_jitter 0.00833333333333
|
||||
SET_SIM_PARAMETER c_secondary_in_jitter 0.004
|
||||
SET_SIM_PARAMETER c_jitter_sel No_Jitter
|
||||
SET_SIM_PARAMETER c_use_min_power 0
|
||||
SET_SIM_PARAMETER c_use_min_o_jitter 0
|
||||
SET_SIM_PARAMETER c_use_max_i_jitter 0
|
||||
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
|
||||
SET_SIM_PARAMETER c_use_inclk_switchover 0
|
||||
SET_SIM_PARAMETER c_use_dyn_reconfig 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
|
||||
SET_SIM_PARAMETER c_primtype_sel DCM_SP
|
||||
SET_SIM_PARAMETER c_use_clk_valid 0
|
||||
SET_SIM_PARAMETER c_prim_in_freq 33.3333
|
||||
SET_SIM_PARAMETER c_in_freq_units Units_MHz
|
||||
SET_SIM_PARAMETER c_secondary_in_freq 100.000
|
||||
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO_OFFCHIP
|
||||
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
|
||||
SET_SIM_PARAMETER c_use_reset 0
|
||||
SET_SIM_PARAMETER c_use_locked 0
|
||||
SET_SIM_PARAMETER c_use_inclk_stopped 0
|
||||
SET_SIM_PARAMETER c_use_clkfb_stopped 0
|
||||
SET_SIM_PARAMETER c_use_power_down 0
|
||||
SET_SIM_PARAMETER c_use_status 0
|
||||
SET_SIM_PARAMETER c_use_freeze 0
|
||||
SET_SIM_PARAMETER c_num_out_clks 1
|
||||
SET_SIM_PARAMETER c_clkout1_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout2_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout3_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout4_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout5_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout6_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout7_drives BUFG
|
||||
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
SET_SIM_PARAMETER c_inclk_sum_row1 __primary_________33.3333___________0.00833333333333
|
||||
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____66.667______0.000______50.0______500.000____150.000
|
||||
SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
|
||||
SET_SIM_PARAMETER c_clkout1_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout3_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout4_requested_out_freq 80
|
||||
SET_SIM_PARAMETER c_clkout5_requested_out_freq 50
|
||||
SET_SIM_PARAMETER c_clkout6_requested_out_freq 33.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_out_freq 33.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_phase -72
|
||||
SET_SIM_PARAMETER c_clkout4_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout1_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout3_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout4_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout5_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout6_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout7_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout3_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout4_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout5_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout6_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout7_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_mmcm_notes None
|
||||
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
|
||||
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_pll_notes None
|
||||
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_mult 20
|
||||
SET_SIM_PARAMETER c_pll_clkin_period 30.000
|
||||
SET_SIM_PARAMETER c_pll_compensation EXTERNAL
|
||||
SET_SIM_PARAMETER c_pll_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_pll_ref_jitter 0.008
|
||||
SET_SIM_PARAMETER c_pll_clkout0_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout1_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout2_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout3_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout4_divide 16
|
||||
SET_SIM_PARAMETER c_pll_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout2_phase -72.000
|
||||
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_dcm_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_divide 1
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_multiply 4
|
||||
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkin_period 30.0
|
||||
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback 1X
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback_port CLK0
|
||||
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
|
||||
SET_SIM_PARAMETER c_dcm_phase_shift 0
|
||||
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out1_port CLK2X
|
||||
SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 30.0
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
|
||||
SET_SIM_PARAMETER c_clock_mgr_type AUTO
|
||||
SET_SIM_PARAMETER c_override_mmcm 0
|
||||
SET_SIM_PARAMETER c_override_pll 0
|
||||
SET_SIM_PARAMETER c_override_dcm 0
|
||||
SET_SIM_PARAMETER c_override_dcm_clkgen 0
|
||||
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
|
||||
SET_SIM_PARAMETER c_primary_port CLKIN
|
||||
SET_SIM_PARAMETER c_secondary_port CLK_IN2
|
||||
SET_SIM_PARAMETER c_clk_out1_port FSBCLK
|
||||
SET_SIM_PARAMETER c_clk_out2_port RAMCLK
|
||||
SET_SIM_PARAMETER c_clk_out3_port CPUCLK
|
||||
SET_SIM_PARAMETER c_clk_out4_port C80M
|
||||
SET_SIM_PARAMETER c_clk_out5_port C50M
|
||||
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
|
||||
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
|
||||
SET_SIM_PARAMETER c_reset_port RESET
|
||||
SET_SIM_PARAMETER c_locked_port LOCKED
|
||||
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
|
||||
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
|
||||
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
|
||||
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
|
||||
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
|
||||
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
|
||||
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
|
||||
SET_SIM_PARAMETER c_daddr_port DADDR
|
||||
SET_SIM_PARAMETER c_dclk_port DCLK
|
||||
SET_SIM_PARAMETER c_drdy_port DRDY
|
||||
SET_SIM_PARAMETER c_dwe_port DWE
|
||||
SET_SIM_PARAMETER c_din_port DIN
|
||||
SET_SIM_PARAMETER c_dout_port DOUT
|
||||
SET_SIM_PARAMETER c_den_port DEN
|
||||
SET_SIM_PARAMETER c_psclk_port PSCLK
|
||||
SET_SIM_PARAMETER c_psen_port PSEN
|
||||
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
|
||||
SET_SIM_PARAMETER c_psdone_port PSDONE
|
||||
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
|
||||
SET_SIM_PARAMETER c_status_port STATUS
|
||||
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
|
||||
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
|
||||
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
|
||||
SET_SIM_PARAMETER c_clkin1_jitter_ps 250.0
|
||||
SET_SIM_PARAMETER c_clkin2_jitter_ps 40.0
|
||||
SET_SIM_PARAMETER c_primitive MMCM
|
||||
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
|
||||
SET_SIM_PARAMETER c_ss_mod_period 4000
|
||||
SET_CORE_NAME Clocking Wizard
|
||||
SET_CORE_VERSION 3.6
|
||||
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
|
||||
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
|
||||
SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
|
||||
SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
|
||||
SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
|
||||
505
fpga/ipcore_dir/tmp/customization_gui.0.580684475405.out
Normal file
505
fpga/ipcore_dir/tmp/customization_gui.0.580684475405.out
Normal file
@ -0,0 +1,505 @@
|
||||
SET_FLAG DEBUG FALSE
|
||||
SET_FLAG MODE BATCH
|
||||
SET_FLAG STANDALONE_MODE FALSE
|
||||
SET_PREFERENCE devicefamily spartan6
|
||||
SET_PREFERENCE device xc6slx9
|
||||
SET_PREFERENCE speedgrade -2
|
||||
SET_PREFERENCE package ftg256
|
||||
SET_PREFERENCE verilogsim true
|
||||
SET_PREFERENCE vhdlsim false
|
||||
SET_PREFERENCE simulationfiles Behavioral
|
||||
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
|
||||
SET_PREFERENCE outputdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/
|
||||
SET_PREFERENCE workingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/
|
||||
SET_PREFERENCE subworkingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/
|
||||
SET_PREFERENCE transientdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/_dbg/
|
||||
SET_PREFERENCE designentry Verilog
|
||||
SET_PREFERENCE flowvendor Other
|
||||
SET_PREFERENCE addpads false
|
||||
SET_PREFERENCE projectname coregen
|
||||
SET_PREFERENCE formalverification false
|
||||
SET_PREFERENCE asysymbol false
|
||||
SET_PREFERENCE implementationfiletype Ngc
|
||||
SET_PREFERENCE foundationsym false
|
||||
SET_PREFERENCE createndf false
|
||||
SET_PREFERENCE removerpms false
|
||||
SET_PARAMETER Component_Name CLK
|
||||
SET_PARAMETER Use_Freq_Synth true
|
||||
SET_PARAMETER Use_Phase_Alignment true
|
||||
SET_PARAMETER Use_Min_Power false
|
||||
SET_PARAMETER Use_Dyn_Phase_Shift false
|
||||
SET_PARAMETER Use_Dyn_Reconfig false
|
||||
SET_PARAMETER Jitter_Sel No_Jitter
|
||||
SET_PARAMETER Use_Spread_Spectrum false
|
||||
SET_PARAMETER Use_Spread_Spectrum_1 false
|
||||
SET_PARAMETER Prim_In_Freq 33.333
|
||||
SET_PARAMETER In_Freq_Units Units_MHz
|
||||
SET_PARAMETER In_Jitter_Units Units_UI
|
||||
SET_PARAMETER Relative_Inclk REL_PRIMARY
|
||||
SET_PARAMETER Secondary_In_Freq 100.000
|
||||
SET_PARAMETER Jitter_Options PS
|
||||
SET_PARAMETER Clkin1_UI_Jitter 303.030
|
||||
SET_PARAMETER Clkin2_UI_Jitter 100.000
|
||||
SET_PARAMETER Prim_In_Jitter 0.010101
|
||||
SET_PARAMETER Secondary_In_Jitter 0.0033000033
|
||||
SET_PARAMETER Clkin1_Jitter_Ps 303.03
|
||||
SET_PARAMETER Clkin2_Jitter_Ps 33.000033
|
||||
SET_PARAMETER Clkout2_Used false
|
||||
SET_PARAMETER Clkout3_Used false
|
||||
SET_PARAMETER Clkout4_Used false
|
||||
SET_PARAMETER Clkout5_Used false
|
||||
SET_PARAMETER Clkout6_Used false
|
||||
SET_PARAMETER Clkout7_Used false
|
||||
SET_PARAMETER Num_Out_Clks 1
|
||||
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER primary_port CLKIN
|
||||
SET_PARAMETER CLK_OUT1_port FSBCLK
|
||||
SET_PARAMETER CLK_OUT2_port CPUCLK
|
||||
SET_PARAMETER CLK_OUT3_port CPUCLK
|
||||
SET_PARAMETER CLK_OUT4_port FPUCLK
|
||||
SET_PARAMETER CLK_OUT5_port CLK_OUT5
|
||||
SET_PARAMETER CLK_OUT6_port CLK_OUT6
|
||||
SET_PARAMETER CLK_OUT7_port CLK_OUT7
|
||||
SET_PARAMETER DADDR_port DADDR
|
||||
SET_PARAMETER DCLK_port DCLK
|
||||
SET_PARAMETER DRDY_port DRDY
|
||||
SET_PARAMETER DWE_port DWE
|
||||
SET_PARAMETER DIN_port DIN
|
||||
SET_PARAMETER DOUT_port DOUT
|
||||
SET_PARAMETER DEN_port DEN
|
||||
SET_PARAMETER PSCLK_port PSCLK
|
||||
SET_PARAMETER PSEN_port PSEN
|
||||
SET_PARAMETER PSINCDEC_port PSINCDEC
|
||||
SET_PARAMETER PSDONE_port PSDONE
|
||||
SET_PARAMETER Clkout1_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout1_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout2_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout2_Requested_Phase 0
|
||||
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout3_Requested_Out_Freq 33.333
|
||||
SET_PARAMETER Clkout3_Requested_Phase 0
|
||||
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout4_Requested_Out_Freq 33.333
|
||||
SET_PARAMETER Clkout4_Requested_Phase 0
|
||||
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout5_Requested_Out_Freq 40
|
||||
SET_PARAMETER Clkout5_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout6_Requested_Out_Freq 33.000
|
||||
SET_PARAMETER Clkout6_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout7_Requested_Out_Freq 33.000
|
||||
SET_PARAMETER Clkout7_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Use_Max_I_Jitter false
|
||||
SET_PARAMETER Use_Min_O_Jitter false
|
||||
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Use_Inclk_Switchover false
|
||||
SET_PARAMETER secondary_port CLK_IN2
|
||||
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Clkout1_Drives BUFG
|
||||
SET_PARAMETER Clkout2_Drives BUFG
|
||||
SET_PARAMETER Clkout3_Drives BUFG
|
||||
SET_PARAMETER Clkout4_Drives BUFG
|
||||
SET_PARAMETER Clkout5_Drives BUFG
|
||||
SET_PARAMETER Clkout6_Drives BUFG
|
||||
SET_PARAMETER Clkout7_Drives BUFG
|
||||
SET_PARAMETER Feedback_Source FDBK_AUTO_OFFCHIP
|
||||
SET_PARAMETER Clkfb_In_Signaling SINGLE
|
||||
SET_PARAMETER CLKFB_IN_port CLKFB_IN
|
||||
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
|
||||
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
|
||||
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
|
||||
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
|
||||
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
|
||||
SET_PARAMETER Platform nt
|
||||
SET_PARAMETER Summary_Strings empty
|
||||
SET_PARAMETER Use_Locked false
|
||||
SET_PARAMETER calc_done DONE
|
||||
SET_PARAMETER Use_Reset false
|
||||
SET_PARAMETER Use_Power_Down false
|
||||
SET_PARAMETER Use_Status false
|
||||
SET_PARAMETER Use_Freeze false
|
||||
SET_PARAMETER Use_Clk_Valid false
|
||||
SET_PARAMETER Use_Inclk_Stopped false
|
||||
SET_PARAMETER Use_Clkfb_Stopped false
|
||||
SET_PARAMETER RESET_port RESET
|
||||
SET_PARAMETER LOCKED_port LOCKED
|
||||
SET_PARAMETER Power_Down_port POWER_DOWN
|
||||
SET_PARAMETER CLK_VALID_port CLK_VALID
|
||||
SET_PARAMETER STATUS_port STATUS
|
||||
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
|
||||
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
|
||||
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
|
||||
SET_PARAMETER Override_Mmcm false
|
||||
SET_PARAMETER Mmcm_Notes None
|
||||
SET_PARAMETER Mmcm_Divclk_Divide 1
|
||||
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkin1_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkin2_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Cascade false
|
||||
SET_PARAMETER Mmcm_Clock_Hold false
|
||||
SET_PARAMETER Mmcm_Compensation ZHOLD
|
||||
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
|
||||
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
|
||||
SET_PARAMETER Mmcm_Startup_Wait false
|
||||
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout1_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout2_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout3_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout4_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout5_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout6_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
|
||||
SET_PARAMETER Override_Dcm false
|
||||
SET_PARAMETER Dcm_Notes None
|
||||
SET_PARAMETER Dcm_Clkdv_Divide 2.0
|
||||
SET_PARAMETER Dcm_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
|
||||
SET_PARAMETER Dcm_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
|
||||
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
|
||||
SET_PARAMETER Dcm_Phase_Shift 0
|
||||
SET_PARAMETER Dcm_Clk_Feedback NONE
|
||||
SET_PARAMETER Dcm_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out3_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out4_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out5_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
|
||||
SET_PARAMETER Override_Dcm_Clkgen false
|
||||
SET_PARAMETER Dcm_Clkgen_Notes None
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
|
||||
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clkgen_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX180
|
||||
SET_PARAMETER Override_Pll false
|
||||
SET_PARAMETER Pll_Notes None
|
||||
SET_PARAMETER Pll_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Pll_Clkfbout_Mult 12
|
||||
SET_PARAMETER Pll_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
|
||||
SET_PARAMETER Pll_Divclk_Divide 1
|
||||
SET_PARAMETER Pll_Clkin_Period 30.0
|
||||
SET_PARAMETER Pll_Compensation EXTERNAL
|
||||
SET_PARAMETER Pll_Ref_Jitter 0.010
|
||||
SET_PARAMETER Pll_Clkout0_Divide 6
|
||||
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout1_Divide 6
|
||||
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout2_Divide 12
|
||||
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout2_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout3_Divide 12
|
||||
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout4_Divide 10
|
||||
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout5_Divide 1
|
||||
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout5_Phase 0.000
|
||||
SET_PARAMETER dcm_pll_cascade NONE
|
||||
SET_PARAMETER clock_mgr_type MANUAL
|
||||
SET_PARAMETER primtype_sel PLL_BASE
|
||||
SET_PARAMETER primitive MMCM
|
||||
SET_PARAMETER SS_Mode CENTER_HIGH
|
||||
SET_PARAMETER SS_Mod_Freq 250
|
||||
SET_SIM_PARAMETER c_clkout2_used 0
|
||||
SET_SIM_PARAMETER c_clkout3_used 0
|
||||
SET_SIM_PARAMETER c_clkout4_used 0
|
||||
SET_SIM_PARAMETER c_clkout5_used 0
|
||||
SET_SIM_PARAMETER c_clkout6_used 0
|
||||
SET_SIM_PARAMETER c_clkout7_used 0
|
||||
SET_SIM_PARAMETER c_use_clkout1_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout2_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout3_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout4_bar 0
|
||||
SET_SIM_PARAMETER c_component_name CLK
|
||||
SET_SIM_PARAMETER c_platform nt
|
||||
SET_SIM_PARAMETER c_use_freq_synth 1
|
||||
SET_SIM_PARAMETER c_use_phase_alignment 1
|
||||
SET_SIM_PARAMETER c_prim_in_jitter 0.010101
|
||||
SET_SIM_PARAMETER c_secondary_in_jitter 0.0033000033
|
||||
SET_SIM_PARAMETER c_jitter_sel No_Jitter
|
||||
SET_SIM_PARAMETER c_use_min_power 0
|
||||
SET_SIM_PARAMETER c_use_min_o_jitter 0
|
||||
SET_SIM_PARAMETER c_use_max_i_jitter 0
|
||||
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
|
||||
SET_SIM_PARAMETER c_use_inclk_switchover 0
|
||||
SET_SIM_PARAMETER c_use_dyn_reconfig 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
|
||||
SET_SIM_PARAMETER c_primtype_sel PLL_BASE
|
||||
SET_SIM_PARAMETER c_use_clk_valid 0
|
||||
SET_SIM_PARAMETER c_prim_in_freq 33.333
|
||||
SET_SIM_PARAMETER c_in_freq_units Units_MHz
|
||||
SET_SIM_PARAMETER c_secondary_in_freq 100.000
|
||||
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO_OFFCHIP
|
||||
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
|
||||
SET_SIM_PARAMETER c_use_reset 0
|
||||
SET_SIM_PARAMETER c_use_locked 0
|
||||
SET_SIM_PARAMETER c_use_inclk_stopped 0
|
||||
SET_SIM_PARAMETER c_use_clkfb_stopped 0
|
||||
SET_SIM_PARAMETER c_use_power_down 0
|
||||
SET_SIM_PARAMETER c_use_status 0
|
||||
SET_SIM_PARAMETER c_use_freeze 0
|
||||
SET_SIM_PARAMETER c_num_out_clks 1
|
||||
SET_SIM_PARAMETER c_clkout1_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout2_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout3_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout4_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout5_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout6_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout7_drives BUFG
|
||||
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
SET_SIM_PARAMETER c_inclk_sum_row1 __primary__________33.333___________0.010101
|
||||
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____66.667______0.000______50.0______306.616____267.927
|
||||
SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
|
||||
SET_SIM_PARAMETER c_clkout1_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout3_requested_out_freq 33.333
|
||||
SET_SIM_PARAMETER c_clkout4_requested_out_freq 33.333
|
||||
SET_SIM_PARAMETER c_clkout5_requested_out_freq 40
|
||||
SET_SIM_PARAMETER c_clkout6_requested_out_freq 33.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_out_freq 33.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout4_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout1_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout3_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout4_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout5_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout6_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout7_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout3_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout4_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout5_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout6_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout7_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_mmcm_notes None
|
||||
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
|
||||
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_pll_notes None
|
||||
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_mult 12
|
||||
SET_SIM_PARAMETER c_pll_clkin_period 30.0
|
||||
SET_SIM_PARAMETER c_pll_compensation EXTERNAL
|
||||
SET_SIM_PARAMETER c_pll_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_pll_ref_jitter 0.010
|
||||
SET_SIM_PARAMETER c_pll_clkout0_divide 6
|
||||
SET_SIM_PARAMETER c_pll_clkout1_divide 6
|
||||
SET_SIM_PARAMETER c_pll_clkout2_divide 12
|
||||
SET_SIM_PARAMETER c_pll_clkout3_divide 12
|
||||
SET_SIM_PARAMETER c_pll_clkout4_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_dcm_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkin_period 30.0
|
||||
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback_port CLKOUT1
|
||||
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
|
||||
SET_SIM_PARAMETER c_dcm_phase_shift 0
|
||||
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 30.0
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
|
||||
SET_SIM_PARAMETER c_clock_mgr_type MANUAL
|
||||
SET_SIM_PARAMETER c_override_mmcm 0
|
||||
SET_SIM_PARAMETER c_override_pll 0
|
||||
SET_SIM_PARAMETER c_override_dcm 0
|
||||
SET_SIM_PARAMETER c_override_dcm_clkgen 0
|
||||
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
|
||||
SET_SIM_PARAMETER c_primary_port CLKIN
|
||||
SET_SIM_PARAMETER c_secondary_port CLK_IN2
|
||||
SET_SIM_PARAMETER c_clk_out1_port FSBCLK
|
||||
SET_SIM_PARAMETER c_clk_out2_port CPUCLK
|
||||
SET_SIM_PARAMETER c_clk_out3_port CPUCLK
|
||||
SET_SIM_PARAMETER c_clk_out4_port FPUCLK
|
||||
SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
|
||||
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
|
||||
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
|
||||
SET_SIM_PARAMETER c_reset_port RESET
|
||||
SET_SIM_PARAMETER c_locked_port LOCKED
|
||||
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
|
||||
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
|
||||
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
|
||||
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
|
||||
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
|
||||
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
|
||||
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
|
||||
SET_SIM_PARAMETER c_daddr_port DADDR
|
||||
SET_SIM_PARAMETER c_dclk_port DCLK
|
||||
SET_SIM_PARAMETER c_drdy_port DRDY
|
||||
SET_SIM_PARAMETER c_dwe_port DWE
|
||||
SET_SIM_PARAMETER c_din_port DIN
|
||||
SET_SIM_PARAMETER c_dout_port DOUT
|
||||
SET_SIM_PARAMETER c_den_port DEN
|
||||
SET_SIM_PARAMETER c_psclk_port PSCLK
|
||||
SET_SIM_PARAMETER c_psen_port PSEN
|
||||
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
|
||||
SET_SIM_PARAMETER c_psdone_port PSDONE
|
||||
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
|
||||
SET_SIM_PARAMETER c_status_port STATUS
|
||||
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
|
||||
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
|
||||
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
|
||||
SET_SIM_PARAMETER c_clkin1_jitter_ps 303.03
|
||||
SET_SIM_PARAMETER c_clkin2_jitter_ps 33.000033
|
||||
SET_SIM_PARAMETER c_primitive MMCM
|
||||
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
|
||||
SET_SIM_PARAMETER c_ss_mod_period 4000
|
||||
SET_CORE_NAME Clocking Wizard
|
||||
SET_CORE_VERSION 3.6
|
||||
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
|
||||
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
|
||||
SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
|
||||
SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
|
||||
SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
|
||||
505
fpga/ipcore_dir/tmp/customization_gui.0.65758347635.out
Normal file
505
fpga/ipcore_dir/tmp/customization_gui.0.65758347635.out
Normal file
@ -0,0 +1,505 @@
|
||||
SET_FLAG DEBUG FALSE
|
||||
SET_FLAG MODE BATCH
|
||||
SET_FLAG STANDALONE_MODE FALSE
|
||||
SET_PREFERENCE devicefamily spartan6
|
||||
SET_PREFERENCE device xc6slx9
|
||||
SET_PREFERENCE speedgrade -2
|
||||
SET_PREFERENCE package ftg256
|
||||
SET_PREFERENCE verilogsim true
|
||||
SET_PREFERENCE vhdlsim false
|
||||
SET_PREFERENCE simulationfiles Behavioral
|
||||
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
|
||||
SET_PREFERENCE outputdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/
|
||||
SET_PREFERENCE workingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/
|
||||
SET_PREFERENCE subworkingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/
|
||||
SET_PREFERENCE transientdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/_dbg/
|
||||
SET_PREFERENCE designentry Verilog
|
||||
SET_PREFERENCE flowvendor Other
|
||||
SET_PREFERENCE addpads false
|
||||
SET_PREFERENCE projectname coregen
|
||||
SET_PREFERENCE formalverification false
|
||||
SET_PREFERENCE asysymbol false
|
||||
SET_PREFERENCE implementationfiletype Ngc
|
||||
SET_PREFERENCE foundationsym false
|
||||
SET_PREFERENCE createndf false
|
||||
SET_PREFERENCE removerpms false
|
||||
SET_PARAMETER Component_Name CLK
|
||||
SET_PARAMETER Use_Freq_Synth true
|
||||
SET_PARAMETER Use_Phase_Alignment true
|
||||
SET_PARAMETER Use_Min_Power false
|
||||
SET_PARAMETER Use_Dyn_Phase_Shift false
|
||||
SET_PARAMETER Use_Dyn_Reconfig false
|
||||
SET_PARAMETER Jitter_Sel No_Jitter
|
||||
SET_PARAMETER Use_Spread_Spectrum false
|
||||
SET_PARAMETER Use_Spread_Spectrum_1 false
|
||||
SET_PARAMETER Prim_In_Freq 33.3333
|
||||
SET_PARAMETER In_Freq_Units Units_MHz
|
||||
SET_PARAMETER In_Jitter_Units Units_UI
|
||||
SET_PARAMETER Relative_Inclk REL_PRIMARY
|
||||
SET_PARAMETER Secondary_In_Freq 100.000
|
||||
SET_PARAMETER Jitter_Options PS
|
||||
SET_PARAMETER Clkin1_UI_Jitter 250.000
|
||||
SET_PARAMETER Clkin2_UI_Jitter 100.000
|
||||
SET_PARAMETER Prim_In_Jitter 0.00833333333333
|
||||
SET_PARAMETER Secondary_In_Jitter 0.004
|
||||
SET_PARAMETER Clkin1_Jitter_Ps 250.0
|
||||
SET_PARAMETER Clkin2_Jitter_Ps 40.0
|
||||
SET_PARAMETER Clkout2_Used true
|
||||
SET_PARAMETER Clkout3_Used true
|
||||
SET_PARAMETER Clkout4_Used false
|
||||
SET_PARAMETER Clkout5_Used false
|
||||
SET_PARAMETER Clkout6_Used false
|
||||
SET_PARAMETER Clkout7_Used false
|
||||
SET_PARAMETER Num_Out_Clks 3
|
||||
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER primary_port CLKIN
|
||||
SET_PARAMETER CLK_OUT1_port FSBCLK
|
||||
SET_PARAMETER CLK_OUT2_port RAMCLK
|
||||
SET_PARAMETER CLK_OUT3_port CPUCLK
|
||||
SET_PARAMETER CLK_OUT4_port C80M
|
||||
SET_PARAMETER CLK_OUT5_port C50M
|
||||
SET_PARAMETER CLK_OUT6_port CLK_OUT6
|
||||
SET_PARAMETER CLK_OUT7_port CLK_OUT7
|
||||
SET_PARAMETER DADDR_port DADDR
|
||||
SET_PARAMETER DCLK_port DCLK
|
||||
SET_PARAMETER DRDY_port DRDY
|
||||
SET_PARAMETER DWE_port DWE
|
||||
SET_PARAMETER DIN_port DIN
|
||||
SET_PARAMETER DOUT_port DOUT
|
||||
SET_PARAMETER DEN_port DEN
|
||||
SET_PARAMETER PSCLK_port PSCLK
|
||||
SET_PARAMETER PSEN_port PSEN
|
||||
SET_PARAMETER PSINCDEC_port PSINCDEC
|
||||
SET_PARAMETER PSDONE_port PSDONE
|
||||
SET_PARAMETER Clkout1_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout1_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout2_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout2_Requested_Phase 0
|
||||
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout3_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout3_Requested_Phase -72
|
||||
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout4_Requested_Out_Freq 80
|
||||
SET_PARAMETER Clkout4_Requested_Phase 0
|
||||
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout5_Requested_Out_Freq 50
|
||||
SET_PARAMETER Clkout5_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout6_Requested_Out_Freq 33.000
|
||||
SET_PARAMETER Clkout6_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout7_Requested_Out_Freq 33.000
|
||||
SET_PARAMETER Clkout7_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Use_Max_I_Jitter false
|
||||
SET_PARAMETER Use_Min_O_Jitter false
|
||||
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Use_Inclk_Switchover false
|
||||
SET_PARAMETER secondary_port CLK_IN2
|
||||
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Clkout1_Drives BUFG
|
||||
SET_PARAMETER Clkout2_Drives BUFG
|
||||
SET_PARAMETER Clkout3_Drives BUFG
|
||||
SET_PARAMETER Clkout4_Drives BUFG
|
||||
SET_PARAMETER Clkout5_Drives BUFG
|
||||
SET_PARAMETER Clkout6_Drives BUFG
|
||||
SET_PARAMETER Clkout7_Drives BUFG
|
||||
SET_PARAMETER Feedback_Source FDBK_AUTO_OFFCHIP
|
||||
SET_PARAMETER Clkfb_In_Signaling SINGLE
|
||||
SET_PARAMETER CLKFB_IN_port CLKFB_IN
|
||||
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
|
||||
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
|
||||
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
|
||||
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
|
||||
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
|
||||
SET_PARAMETER Platform nt
|
||||
SET_PARAMETER Summary_Strings empty
|
||||
SET_PARAMETER Use_Locked false
|
||||
SET_PARAMETER calc_done DONE
|
||||
SET_PARAMETER Use_Reset false
|
||||
SET_PARAMETER Use_Power_Down false
|
||||
SET_PARAMETER Use_Status false
|
||||
SET_PARAMETER Use_Freeze false
|
||||
SET_PARAMETER Use_Clk_Valid false
|
||||
SET_PARAMETER Use_Inclk_Stopped false
|
||||
SET_PARAMETER Use_Clkfb_Stopped false
|
||||
SET_PARAMETER RESET_port RESET
|
||||
SET_PARAMETER LOCKED_port LOCKED
|
||||
SET_PARAMETER Power_Down_port POWER_DOWN
|
||||
SET_PARAMETER CLK_VALID_port CLK_VALID
|
||||
SET_PARAMETER STATUS_port STATUS
|
||||
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
|
||||
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
|
||||
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
|
||||
SET_PARAMETER Override_Mmcm false
|
||||
SET_PARAMETER Mmcm_Notes None
|
||||
SET_PARAMETER Mmcm_Divclk_Divide 1
|
||||
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkin1_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkin2_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Cascade false
|
||||
SET_PARAMETER Mmcm_Clock_Hold false
|
||||
SET_PARAMETER Mmcm_Compensation ZHOLD
|
||||
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
|
||||
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
|
||||
SET_PARAMETER Mmcm_Startup_Wait false
|
||||
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout1_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout2_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout3_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout4_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout5_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout6_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
|
||||
SET_PARAMETER Override_Dcm false
|
||||
SET_PARAMETER Dcm_Notes None
|
||||
SET_PARAMETER Dcm_Clkdv_Divide 2.0
|
||||
SET_PARAMETER Dcm_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
|
||||
SET_PARAMETER Dcm_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
|
||||
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
|
||||
SET_PARAMETER Dcm_Phase_Shift 0
|
||||
SET_PARAMETER Dcm_Clk_Feedback NONE
|
||||
SET_PARAMETER Dcm_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out3_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out4_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out5_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
|
||||
SET_PARAMETER Override_Dcm_Clkgen false
|
||||
SET_PARAMETER Dcm_Clkgen_Notes None
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
|
||||
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clkgen_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX180
|
||||
SET_PARAMETER Override_Pll false
|
||||
SET_PARAMETER Pll_Notes None
|
||||
SET_PARAMETER Pll_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Pll_Clkfbout_Mult 20
|
||||
SET_PARAMETER Pll_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
|
||||
SET_PARAMETER Pll_Divclk_Divide 1
|
||||
SET_PARAMETER Pll_Clkin_Period 30.000
|
||||
SET_PARAMETER Pll_Compensation EXTERNAL
|
||||
SET_PARAMETER Pll_Ref_Jitter 0.008
|
||||
SET_PARAMETER Pll_Clkout0_Divide 10
|
||||
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout1_Divide 10
|
||||
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout2_Divide 10
|
||||
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout2_Phase -72.000
|
||||
SET_PARAMETER Pll_Clkout3_Divide 10
|
||||
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout4_Divide 16
|
||||
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout5_Divide 1
|
||||
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout5_Phase 0.000
|
||||
SET_PARAMETER dcm_pll_cascade NONE
|
||||
SET_PARAMETER clock_mgr_type MANUAL
|
||||
SET_PARAMETER primtype_sel PLL_BASE
|
||||
SET_PARAMETER primitive MMCM
|
||||
SET_PARAMETER SS_Mode CENTER_HIGH
|
||||
SET_PARAMETER SS_Mod_Freq 250
|
||||
SET_SIM_PARAMETER c_clkout2_used 1
|
||||
SET_SIM_PARAMETER c_clkout3_used 1
|
||||
SET_SIM_PARAMETER c_clkout4_used 0
|
||||
SET_SIM_PARAMETER c_clkout5_used 0
|
||||
SET_SIM_PARAMETER c_clkout6_used 0
|
||||
SET_SIM_PARAMETER c_clkout7_used 0
|
||||
SET_SIM_PARAMETER c_use_clkout1_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout2_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout3_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout4_bar 0
|
||||
SET_SIM_PARAMETER c_component_name CLK
|
||||
SET_SIM_PARAMETER c_platform nt
|
||||
SET_SIM_PARAMETER c_use_freq_synth 1
|
||||
SET_SIM_PARAMETER c_use_phase_alignment 1
|
||||
SET_SIM_PARAMETER c_prim_in_jitter 0.00833333333333
|
||||
SET_SIM_PARAMETER c_secondary_in_jitter 0.004
|
||||
SET_SIM_PARAMETER c_jitter_sel No_Jitter
|
||||
SET_SIM_PARAMETER c_use_min_power 0
|
||||
SET_SIM_PARAMETER c_use_min_o_jitter 0
|
||||
SET_SIM_PARAMETER c_use_max_i_jitter 0
|
||||
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
|
||||
SET_SIM_PARAMETER c_use_inclk_switchover 0
|
||||
SET_SIM_PARAMETER c_use_dyn_reconfig 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
|
||||
SET_SIM_PARAMETER c_primtype_sel PLL_BASE
|
||||
SET_SIM_PARAMETER c_use_clk_valid 0
|
||||
SET_SIM_PARAMETER c_prim_in_freq 33.3333
|
||||
SET_SIM_PARAMETER c_in_freq_units Units_MHz
|
||||
SET_SIM_PARAMETER c_secondary_in_freq 100.000
|
||||
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO_OFFCHIP
|
||||
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
|
||||
SET_SIM_PARAMETER c_use_reset 0
|
||||
SET_SIM_PARAMETER c_use_locked 0
|
||||
SET_SIM_PARAMETER c_use_inclk_stopped 0
|
||||
SET_SIM_PARAMETER c_use_clkfb_stopped 0
|
||||
SET_SIM_PARAMETER c_use_power_down 0
|
||||
SET_SIM_PARAMETER c_use_status 0
|
||||
SET_SIM_PARAMETER c_use_freeze 0
|
||||
SET_SIM_PARAMETER c_num_out_clks 3
|
||||
SET_SIM_PARAMETER c_clkout1_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout2_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout3_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout4_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout5_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout6_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout7_drives BUFG
|
||||
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
SET_SIM_PARAMETER c_inclk_sum_row1 __primary_________33.3333___________0.00833333333333
|
||||
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____66.667______0.000______50.0______284.597____217.556
|
||||
SET_SIM_PARAMETER c_outclk_sum_row2 CLK_OUT2____66.667______0.000______50.0______284.597____217.556
|
||||
SET_SIM_PARAMETER c_outclk_sum_row3 CLK_OUT3____66.667____-72.000______50.0______284.597____217.556
|
||||
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
|
||||
SET_SIM_PARAMETER c_clkout1_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout3_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout4_requested_out_freq 80
|
||||
SET_SIM_PARAMETER c_clkout5_requested_out_freq 50
|
||||
SET_SIM_PARAMETER c_clkout6_requested_out_freq 33.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_out_freq 33.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_phase -72
|
||||
SET_SIM_PARAMETER c_clkout4_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout1_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout3_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout4_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout5_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout6_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout7_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout3_phase -72.000
|
||||
SET_SIM_PARAMETER c_clkout4_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout5_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout6_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout7_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout3_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_mmcm_notes None
|
||||
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
|
||||
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_pll_notes None
|
||||
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_mult 20
|
||||
SET_SIM_PARAMETER c_pll_clkin_period 30.000
|
||||
SET_SIM_PARAMETER c_pll_compensation EXTERNAL
|
||||
SET_SIM_PARAMETER c_pll_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_pll_ref_jitter 0.008
|
||||
SET_SIM_PARAMETER c_pll_clkout0_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout1_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout2_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout3_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout4_divide 16
|
||||
SET_SIM_PARAMETER c_pll_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout2_phase -72.000
|
||||
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_dcm_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkin_period 30.0
|
||||
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback_port CLKOUT1
|
||||
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
|
||||
SET_SIM_PARAMETER c_dcm_phase_shift 0
|
||||
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out2_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out3_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 30.0
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port CLKFX180
|
||||
SET_SIM_PARAMETER c_clock_mgr_type MANUAL
|
||||
SET_SIM_PARAMETER c_override_mmcm 0
|
||||
SET_SIM_PARAMETER c_override_pll 0
|
||||
SET_SIM_PARAMETER c_override_dcm 0
|
||||
SET_SIM_PARAMETER c_override_dcm_clkgen 0
|
||||
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
|
||||
SET_SIM_PARAMETER c_primary_port CLKIN
|
||||
SET_SIM_PARAMETER c_secondary_port CLK_IN2
|
||||
SET_SIM_PARAMETER c_clk_out1_port FSBCLK
|
||||
SET_SIM_PARAMETER c_clk_out2_port RAMCLK
|
||||
SET_SIM_PARAMETER c_clk_out3_port CPUCLK
|
||||
SET_SIM_PARAMETER c_clk_out4_port C80M
|
||||
SET_SIM_PARAMETER c_clk_out5_port C50M
|
||||
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
|
||||
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
|
||||
SET_SIM_PARAMETER c_reset_port RESET
|
||||
SET_SIM_PARAMETER c_locked_port LOCKED
|
||||
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
|
||||
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
|
||||
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
|
||||
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
|
||||
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
|
||||
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
|
||||
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
|
||||
SET_SIM_PARAMETER c_daddr_port DADDR
|
||||
SET_SIM_PARAMETER c_dclk_port DCLK
|
||||
SET_SIM_PARAMETER c_drdy_port DRDY
|
||||
SET_SIM_PARAMETER c_dwe_port DWE
|
||||
SET_SIM_PARAMETER c_din_port DIN
|
||||
SET_SIM_PARAMETER c_dout_port DOUT
|
||||
SET_SIM_PARAMETER c_den_port DEN
|
||||
SET_SIM_PARAMETER c_psclk_port PSCLK
|
||||
SET_SIM_PARAMETER c_psen_port PSEN
|
||||
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
|
||||
SET_SIM_PARAMETER c_psdone_port PSDONE
|
||||
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
|
||||
SET_SIM_PARAMETER c_status_port STATUS
|
||||
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
|
||||
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
|
||||
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
|
||||
SET_SIM_PARAMETER c_clkin1_jitter_ps 250.0
|
||||
SET_SIM_PARAMETER c_clkin2_jitter_ps 40.0
|
||||
SET_SIM_PARAMETER c_primitive MMCM
|
||||
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
|
||||
SET_SIM_PARAMETER c_ss_mod_period 4000
|
||||
SET_CORE_NAME Clocking Wizard
|
||||
SET_CORE_VERSION 3.6
|
||||
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
|
||||
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
|
||||
SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
|
||||
SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
|
||||
SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
|
||||
505
fpga/ipcore_dir/tmp/customization_gui.0.857701522232.out
Normal file
505
fpga/ipcore_dir/tmp/customization_gui.0.857701522232.out
Normal file
@ -0,0 +1,505 @@
|
||||
SET_FLAG DEBUG FALSE
|
||||
SET_FLAG MODE BATCH
|
||||
SET_FLAG STANDALONE_MODE FALSE
|
||||
SET_PREFERENCE devicefamily spartan6
|
||||
SET_PREFERENCE device xc6slx9
|
||||
SET_PREFERENCE speedgrade -2
|
||||
SET_PREFERENCE package ftg256
|
||||
SET_PREFERENCE verilogsim true
|
||||
SET_PREFERENCE vhdlsim false
|
||||
SET_PREFERENCE simulationfiles Behavioral
|
||||
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
|
||||
SET_PREFERENCE outputdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/
|
||||
SET_PREFERENCE workingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/
|
||||
SET_PREFERENCE subworkingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/
|
||||
SET_PREFERENCE transientdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/_dbg/
|
||||
SET_PREFERENCE designentry Verilog
|
||||
SET_PREFERENCE flowvendor Other
|
||||
SET_PREFERENCE addpads false
|
||||
SET_PREFERENCE projectname coregen
|
||||
SET_PREFERENCE formalverification false
|
||||
SET_PREFERENCE asysymbol false
|
||||
SET_PREFERENCE implementationfiletype Ngc
|
||||
SET_PREFERENCE foundationsym false
|
||||
SET_PREFERENCE createndf false
|
||||
SET_PREFERENCE removerpms false
|
||||
SET_PARAMETER Component_Name CLK
|
||||
SET_PARAMETER Use_Freq_Synth true
|
||||
SET_PARAMETER Use_Phase_Alignment true
|
||||
SET_PARAMETER Use_Min_Power false
|
||||
SET_PARAMETER Use_Dyn_Phase_Shift false
|
||||
SET_PARAMETER Use_Dyn_Reconfig false
|
||||
SET_PARAMETER Jitter_Sel No_Jitter
|
||||
SET_PARAMETER Use_Spread_Spectrum false
|
||||
SET_PARAMETER Use_Spread_Spectrum_1 false
|
||||
SET_PARAMETER Prim_In_Freq 40
|
||||
SET_PARAMETER In_Freq_Units Units_MHz
|
||||
SET_PARAMETER In_Jitter_Units Units_UI
|
||||
SET_PARAMETER Relative_Inclk REL_PRIMARY
|
||||
SET_PARAMETER Secondary_In_Freq 100.000
|
||||
SET_PARAMETER Jitter_Options PS
|
||||
SET_PARAMETER Clkin1_UI_Jitter 250.000
|
||||
SET_PARAMETER Clkin2_UI_Jitter 100.000
|
||||
SET_PARAMETER Prim_In_Jitter 0.01
|
||||
SET_PARAMETER Secondary_In_Jitter 0.004
|
||||
SET_PARAMETER Clkin1_Jitter_Ps 250.0
|
||||
SET_PARAMETER Clkin2_Jitter_Ps 40.0
|
||||
SET_PARAMETER Clkout2_Used true
|
||||
SET_PARAMETER Clkout3_Used true
|
||||
SET_PARAMETER Clkout4_Used true
|
||||
SET_PARAMETER Clkout5_Used true
|
||||
SET_PARAMETER Clkout6_Used false
|
||||
SET_PARAMETER Clkout7_Used false
|
||||
SET_PARAMETER Num_Out_Clks 5
|
||||
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER primary_port CLKIN
|
||||
SET_PARAMETER CLK_OUT1_port FSBCLK
|
||||
SET_PARAMETER CLK_OUT2_port RAMCLK
|
||||
SET_PARAMETER CLK_OUT3_port CPUCLK
|
||||
SET_PARAMETER CLK_OUT4_port C80M
|
||||
SET_PARAMETER CLK_OUT5_port C50M
|
||||
SET_PARAMETER CLK_OUT6_port CLK_OUT6
|
||||
SET_PARAMETER CLK_OUT7_port CLK_OUT7
|
||||
SET_PARAMETER DADDR_port DADDR
|
||||
SET_PARAMETER DCLK_port DCLK
|
||||
SET_PARAMETER DRDY_port DRDY
|
||||
SET_PARAMETER DWE_port DWE
|
||||
SET_PARAMETER DIN_port DIN
|
||||
SET_PARAMETER DOUT_port DOUT
|
||||
SET_PARAMETER DEN_port DEN
|
||||
SET_PARAMETER PSCLK_port PSCLK
|
||||
SET_PARAMETER PSEN_port PSEN
|
||||
SET_PARAMETER PSINCDEC_port PSINCDEC
|
||||
SET_PARAMETER PSDONE_port PSDONE
|
||||
SET_PARAMETER Clkout1_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout1_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout2_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout2_Requested_Phase 0
|
||||
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout3_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout3_Requested_Phase -72
|
||||
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout4_Requested_Out_Freq 80
|
||||
SET_PARAMETER Clkout4_Requested_Phase 0
|
||||
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout5_Requested_Out_Freq 50
|
||||
SET_PARAMETER Clkout5_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout6_Requested_Out_Freq 33.000
|
||||
SET_PARAMETER Clkout6_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout7_Requested_Out_Freq 33.000
|
||||
SET_PARAMETER Clkout7_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Use_Max_I_Jitter false
|
||||
SET_PARAMETER Use_Min_O_Jitter false
|
||||
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Use_Inclk_Switchover false
|
||||
SET_PARAMETER secondary_port CLK_IN2
|
||||
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Clkout1_Drives BUFG
|
||||
SET_PARAMETER Clkout2_Drives BUFG
|
||||
SET_PARAMETER Clkout3_Drives BUFG
|
||||
SET_PARAMETER Clkout4_Drives BUFG
|
||||
SET_PARAMETER Clkout5_Drives BUFG
|
||||
SET_PARAMETER Clkout6_Drives BUFG
|
||||
SET_PARAMETER Clkout7_Drives BUFG
|
||||
SET_PARAMETER Feedback_Source FDBK_AUTO_OFFCHIP
|
||||
SET_PARAMETER Clkfb_In_Signaling SINGLE
|
||||
SET_PARAMETER CLKFB_IN_port CLKFB_IN
|
||||
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
|
||||
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
|
||||
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
|
||||
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
|
||||
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
|
||||
SET_PARAMETER Platform nt
|
||||
SET_PARAMETER Summary_Strings empty
|
||||
SET_PARAMETER Use_Locked false
|
||||
SET_PARAMETER calc_done DONE
|
||||
SET_PARAMETER Use_Reset false
|
||||
SET_PARAMETER Use_Power_Down false
|
||||
SET_PARAMETER Use_Status false
|
||||
SET_PARAMETER Use_Freeze false
|
||||
SET_PARAMETER Use_Clk_Valid false
|
||||
SET_PARAMETER Use_Inclk_Stopped false
|
||||
SET_PARAMETER Use_Clkfb_Stopped false
|
||||
SET_PARAMETER RESET_port RESET
|
||||
SET_PARAMETER LOCKED_port LOCKED
|
||||
SET_PARAMETER Power_Down_port POWER_DOWN
|
||||
SET_PARAMETER CLK_VALID_port CLK_VALID
|
||||
SET_PARAMETER STATUS_port STATUS
|
||||
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
|
||||
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
|
||||
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
|
||||
SET_PARAMETER Override_Mmcm false
|
||||
SET_PARAMETER Mmcm_Notes None
|
||||
SET_PARAMETER Mmcm_Divclk_Divide 1
|
||||
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkin1_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkin2_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Cascade false
|
||||
SET_PARAMETER Mmcm_Clock_Hold false
|
||||
SET_PARAMETER Mmcm_Compensation ZHOLD
|
||||
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
|
||||
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
|
||||
SET_PARAMETER Mmcm_Startup_Wait false
|
||||
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout1_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout2_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout3_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout4_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout5_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout6_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
|
||||
SET_PARAMETER Override_Dcm false
|
||||
SET_PARAMETER Dcm_Notes None
|
||||
SET_PARAMETER Dcm_Clkdv_Divide 2.0
|
||||
SET_PARAMETER Dcm_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
|
||||
SET_PARAMETER Dcm_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
|
||||
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
|
||||
SET_PARAMETER Dcm_Phase_Shift 0
|
||||
SET_PARAMETER Dcm_Clk_Feedback NONE
|
||||
SET_PARAMETER Dcm_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out3_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out4_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out5_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
|
||||
SET_PARAMETER Override_Dcm_Clkgen false
|
||||
SET_PARAMETER Dcm_Clkgen_Notes None
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
|
||||
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clkgen_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX180
|
||||
SET_PARAMETER Override_Pll false
|
||||
SET_PARAMETER Pll_Notes None
|
||||
SET_PARAMETER Pll_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Pll_Clkfbout_Mult 20
|
||||
SET_PARAMETER Pll_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
|
||||
SET_PARAMETER Pll_Divclk_Divide 1
|
||||
SET_PARAMETER Pll_Clkin_Period 25.000
|
||||
SET_PARAMETER Pll_Compensation EXTERNAL
|
||||
SET_PARAMETER Pll_Ref_Jitter 0.010
|
||||
SET_PARAMETER Pll_Clkout0_Divide 12
|
||||
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout1_Divide 12
|
||||
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout2_Divide 12
|
||||
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout2_Phase -71.250
|
||||
SET_PARAMETER Pll_Clkout3_Divide 10
|
||||
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout4_Divide 16
|
||||
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout5_Divide 1
|
||||
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout5_Phase 0.000
|
||||
SET_PARAMETER dcm_pll_cascade NONE
|
||||
SET_PARAMETER clock_mgr_type MANUAL
|
||||
SET_PARAMETER primtype_sel PLL_BASE
|
||||
SET_PARAMETER primitive MMCM
|
||||
SET_PARAMETER SS_Mode CENTER_HIGH
|
||||
SET_PARAMETER SS_Mod_Freq 250
|
||||
SET_SIM_PARAMETER c_clkout2_used 1
|
||||
SET_SIM_PARAMETER c_clkout3_used 1
|
||||
SET_SIM_PARAMETER c_clkout4_used 1
|
||||
SET_SIM_PARAMETER c_clkout5_used 1
|
||||
SET_SIM_PARAMETER c_clkout6_used 0
|
||||
SET_SIM_PARAMETER c_clkout7_used 0
|
||||
SET_SIM_PARAMETER c_use_clkout1_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout2_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout3_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout4_bar 0
|
||||
SET_SIM_PARAMETER c_component_name CLK
|
||||
SET_SIM_PARAMETER c_platform nt
|
||||
SET_SIM_PARAMETER c_use_freq_synth 1
|
||||
SET_SIM_PARAMETER c_use_phase_alignment 1
|
||||
SET_SIM_PARAMETER c_prim_in_jitter 0.01
|
||||
SET_SIM_PARAMETER c_secondary_in_jitter 0.004
|
||||
SET_SIM_PARAMETER c_jitter_sel No_Jitter
|
||||
SET_SIM_PARAMETER c_use_min_power 0
|
||||
SET_SIM_PARAMETER c_use_min_o_jitter 0
|
||||
SET_SIM_PARAMETER c_use_max_i_jitter 0
|
||||
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
|
||||
SET_SIM_PARAMETER c_use_inclk_switchover 0
|
||||
SET_SIM_PARAMETER c_use_dyn_reconfig 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
|
||||
SET_SIM_PARAMETER c_primtype_sel PLL_BASE
|
||||
SET_SIM_PARAMETER c_use_clk_valid 0
|
||||
SET_SIM_PARAMETER c_prim_in_freq 40
|
||||
SET_SIM_PARAMETER c_in_freq_units Units_MHz
|
||||
SET_SIM_PARAMETER c_secondary_in_freq 100.000
|
||||
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO_OFFCHIP
|
||||
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
|
||||
SET_SIM_PARAMETER c_use_reset 0
|
||||
SET_SIM_PARAMETER c_use_locked 0
|
||||
SET_SIM_PARAMETER c_use_inclk_stopped 0
|
||||
SET_SIM_PARAMETER c_use_clkfb_stopped 0
|
||||
SET_SIM_PARAMETER c_use_power_down 0
|
||||
SET_SIM_PARAMETER c_use_status 0
|
||||
SET_SIM_PARAMETER c_use_freeze 0
|
||||
SET_SIM_PARAMETER c_num_out_clks 5
|
||||
SET_SIM_PARAMETER c_clkout1_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout2_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout3_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout4_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout5_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout6_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout7_drives BUFG
|
||||
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
SET_SIM_PARAMETER c_inclk_sum_row1 __primary______________40_____________0.01
|
||||
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____66.667______0.000______50.0______255.979____194.528
|
||||
SET_SIM_PARAMETER c_outclk_sum_row2 CLK_OUT2____66.667______0.000______50.0______255.979____194.528
|
||||
SET_SIM_PARAMETER c_outclk_sum_row3 CLK_OUT3____66.667____-71.250______50.0______255.979____194.528
|
||||
SET_SIM_PARAMETER c_outclk_sum_row4 CLK_OUT4____80.000______0.000______50.0______244.226____194.528
|
||||
SET_SIM_PARAMETER c_outclk_sum_row5 CLK_OUT5____50.000______0.000______50.0______277.107____194.528
|
||||
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
|
||||
SET_SIM_PARAMETER c_clkout1_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout3_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout4_requested_out_freq 80
|
||||
SET_SIM_PARAMETER c_clkout5_requested_out_freq 50
|
||||
SET_SIM_PARAMETER c_clkout6_requested_out_freq 33.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_out_freq 33.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_phase -72
|
||||
SET_SIM_PARAMETER c_clkout4_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout1_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout3_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout4_out_freq 80.000
|
||||
SET_SIM_PARAMETER c_clkout5_out_freq 50.000
|
||||
SET_SIM_PARAMETER c_clkout6_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout7_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout3_phase -71.250
|
||||
SET_SIM_PARAMETER c_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout6_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout7_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout3_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout4_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout5_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_mmcm_notes None
|
||||
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
|
||||
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_pll_notes None
|
||||
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_mult 20
|
||||
SET_SIM_PARAMETER c_pll_clkin_period 25.000
|
||||
SET_SIM_PARAMETER c_pll_compensation EXTERNAL
|
||||
SET_SIM_PARAMETER c_pll_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_pll_ref_jitter 0.010
|
||||
SET_SIM_PARAMETER c_pll_clkout0_divide 12
|
||||
SET_SIM_PARAMETER c_pll_clkout1_divide 12
|
||||
SET_SIM_PARAMETER c_pll_clkout2_divide 12
|
||||
SET_SIM_PARAMETER c_pll_clkout3_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout4_divide 16
|
||||
SET_SIM_PARAMETER c_pll_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout2_phase -71.250
|
||||
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_dcm_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkin_period 25.0
|
||||
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback_port CLKOUT1
|
||||
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
|
||||
SET_SIM_PARAMETER c_dcm_phase_shift 0
|
||||
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out2_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out3_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out4_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out5_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out6_port CLK0
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 25.0
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port CLKFX180
|
||||
SET_SIM_PARAMETER c_clock_mgr_type MANUAL
|
||||
SET_SIM_PARAMETER c_override_mmcm 0
|
||||
SET_SIM_PARAMETER c_override_pll 0
|
||||
SET_SIM_PARAMETER c_override_dcm 0
|
||||
SET_SIM_PARAMETER c_override_dcm_clkgen 0
|
||||
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
|
||||
SET_SIM_PARAMETER c_primary_port CLKIN
|
||||
SET_SIM_PARAMETER c_secondary_port CLK_IN2
|
||||
SET_SIM_PARAMETER c_clk_out1_port FSBCLK
|
||||
SET_SIM_PARAMETER c_clk_out2_port RAMCLK
|
||||
SET_SIM_PARAMETER c_clk_out3_port CPUCLK
|
||||
SET_SIM_PARAMETER c_clk_out4_port C80M
|
||||
SET_SIM_PARAMETER c_clk_out5_port C50M
|
||||
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
|
||||
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
|
||||
SET_SIM_PARAMETER c_reset_port RESET
|
||||
SET_SIM_PARAMETER c_locked_port LOCKED
|
||||
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
|
||||
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
|
||||
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
|
||||
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
|
||||
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
|
||||
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
|
||||
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
|
||||
SET_SIM_PARAMETER c_daddr_port DADDR
|
||||
SET_SIM_PARAMETER c_dclk_port DCLK
|
||||
SET_SIM_PARAMETER c_drdy_port DRDY
|
||||
SET_SIM_PARAMETER c_dwe_port DWE
|
||||
SET_SIM_PARAMETER c_din_port DIN
|
||||
SET_SIM_PARAMETER c_dout_port DOUT
|
||||
SET_SIM_PARAMETER c_den_port DEN
|
||||
SET_SIM_PARAMETER c_psclk_port PSCLK
|
||||
SET_SIM_PARAMETER c_psen_port PSEN
|
||||
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
|
||||
SET_SIM_PARAMETER c_psdone_port PSDONE
|
||||
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
|
||||
SET_SIM_PARAMETER c_status_port STATUS
|
||||
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
|
||||
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
|
||||
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
|
||||
SET_SIM_PARAMETER c_clkin1_jitter_ps 250.0
|
||||
SET_SIM_PARAMETER c_clkin2_jitter_ps 40.0
|
||||
SET_SIM_PARAMETER c_primitive MMCM
|
||||
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
|
||||
SET_SIM_PARAMETER c_ss_mod_period 4000
|
||||
SET_CORE_NAME Clocking Wizard
|
||||
SET_CORE_VERSION 3.6
|
||||
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
|
||||
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
|
||||
SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
|
||||
SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
|
||||
SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
|
||||
505
fpga/ipcore_dir/tmp/customization_gui.0.863760402828.out
Normal file
505
fpga/ipcore_dir/tmp/customization_gui.0.863760402828.out
Normal file
@ -0,0 +1,505 @@
|
||||
SET_FLAG DEBUG FALSE
|
||||
SET_FLAG MODE BATCH
|
||||
SET_FLAG STANDALONE_MODE FALSE
|
||||
SET_PREFERENCE devicefamily spartan6
|
||||
SET_PREFERENCE device xc6slx9
|
||||
SET_PREFERENCE speedgrade -2
|
||||
SET_PREFERENCE package ftg256
|
||||
SET_PREFERENCE verilogsim true
|
||||
SET_PREFERENCE vhdlsim false
|
||||
SET_PREFERENCE simulationfiles Behavioral
|
||||
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
|
||||
SET_PREFERENCE outputdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/
|
||||
SET_PREFERENCE workingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/
|
||||
SET_PREFERENCE subworkingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/
|
||||
SET_PREFERENCE transientdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/_dbg/
|
||||
SET_PREFERENCE designentry Verilog
|
||||
SET_PREFERENCE flowvendor Other
|
||||
SET_PREFERENCE addpads false
|
||||
SET_PREFERENCE projectname coregen
|
||||
SET_PREFERENCE formalverification false
|
||||
SET_PREFERENCE asysymbol false
|
||||
SET_PREFERENCE implementationfiletype Ngc
|
||||
SET_PREFERENCE foundationsym false
|
||||
SET_PREFERENCE createndf false
|
||||
SET_PREFERENCE removerpms false
|
||||
SET_PARAMETER Component_Name CLK
|
||||
SET_PARAMETER Use_Freq_Synth true
|
||||
SET_PARAMETER Use_Phase_Alignment true
|
||||
SET_PARAMETER Use_Min_Power false
|
||||
SET_PARAMETER Use_Dyn_Phase_Shift false
|
||||
SET_PARAMETER Use_Dyn_Reconfig false
|
||||
SET_PARAMETER Jitter_Sel No_Jitter
|
||||
SET_PARAMETER Use_Spread_Spectrum false
|
||||
SET_PARAMETER Use_Spread_Spectrum_1 false
|
||||
SET_PARAMETER Prim_In_Freq 33.3333
|
||||
SET_PARAMETER In_Freq_Units Units_MHz
|
||||
SET_PARAMETER In_Jitter_Units Units_UI
|
||||
SET_PARAMETER Relative_Inclk REL_PRIMARY
|
||||
SET_PARAMETER Secondary_In_Freq 100.000
|
||||
SET_PARAMETER Jitter_Options PS
|
||||
SET_PARAMETER Clkin1_UI_Jitter 250.000
|
||||
SET_PARAMETER Clkin2_UI_Jitter 100.000
|
||||
SET_PARAMETER Prim_In_Jitter 0.00833333333333
|
||||
SET_PARAMETER Secondary_In_Jitter 0.004
|
||||
SET_PARAMETER Clkin1_Jitter_Ps 250.0
|
||||
SET_PARAMETER Clkin2_Jitter_Ps 40.0
|
||||
SET_PARAMETER Clkout2_Used false
|
||||
SET_PARAMETER Clkout3_Used false
|
||||
SET_PARAMETER Clkout4_Used false
|
||||
SET_PARAMETER Clkout5_Used false
|
||||
SET_PARAMETER Clkout6_Used false
|
||||
SET_PARAMETER Clkout7_Used false
|
||||
SET_PARAMETER Num_Out_Clks 1
|
||||
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER primary_port CLKIN
|
||||
SET_PARAMETER CLK_OUT1_port FSBCLK
|
||||
SET_PARAMETER CLK_OUT2_port RAMCLK
|
||||
SET_PARAMETER CLK_OUT3_port CPUCLK
|
||||
SET_PARAMETER CLK_OUT4_port C80M
|
||||
SET_PARAMETER CLK_OUT5_port C50M
|
||||
SET_PARAMETER CLK_OUT6_port CLK_OUT6
|
||||
SET_PARAMETER CLK_OUT7_port CLK_OUT7
|
||||
SET_PARAMETER DADDR_port DADDR
|
||||
SET_PARAMETER DCLK_port DCLK
|
||||
SET_PARAMETER DRDY_port DRDY
|
||||
SET_PARAMETER DWE_port DWE
|
||||
SET_PARAMETER DIN_port DIN
|
||||
SET_PARAMETER DOUT_port DOUT
|
||||
SET_PARAMETER DEN_port DEN
|
||||
SET_PARAMETER PSCLK_port PSCLK
|
||||
SET_PARAMETER PSEN_port PSEN
|
||||
SET_PARAMETER PSINCDEC_port PSINCDEC
|
||||
SET_PARAMETER PSDONE_port PSDONE
|
||||
SET_PARAMETER Clkout1_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout1_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout2_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout2_Requested_Phase 0
|
||||
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout3_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout3_Requested_Phase -72
|
||||
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout4_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout4_Requested_Phase 0
|
||||
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout5_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout5_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout6_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout6_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout7_Requested_Out_Freq 33.3333
|
||||
SET_PARAMETER Clkout7_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Use_Max_I_Jitter false
|
||||
SET_PARAMETER Use_Min_O_Jitter false
|
||||
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Use_Inclk_Switchover false
|
||||
SET_PARAMETER secondary_port CLK_IN2
|
||||
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Clkout1_Drives BUFG
|
||||
SET_PARAMETER Clkout2_Drives BUFG
|
||||
SET_PARAMETER Clkout3_Drives BUFG
|
||||
SET_PARAMETER Clkout4_Drives BUFG
|
||||
SET_PARAMETER Clkout5_Drives BUFG
|
||||
SET_PARAMETER Clkout6_Drives BUFG
|
||||
SET_PARAMETER Clkout7_Drives BUFG
|
||||
SET_PARAMETER Feedback_Source FDBK_AUTO_OFFCHIP
|
||||
SET_PARAMETER Clkfb_In_Signaling SINGLE
|
||||
SET_PARAMETER CLKFB_IN_port CLKFB_IN
|
||||
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
|
||||
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
|
||||
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
|
||||
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
|
||||
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
|
||||
SET_PARAMETER Platform nt
|
||||
SET_PARAMETER Summary_Strings empty
|
||||
SET_PARAMETER Use_Locked false
|
||||
SET_PARAMETER calc_done DONE
|
||||
SET_PARAMETER Use_Reset false
|
||||
SET_PARAMETER Use_Power_Down false
|
||||
SET_PARAMETER Use_Status false
|
||||
SET_PARAMETER Use_Freeze false
|
||||
SET_PARAMETER Use_Clk_Valid false
|
||||
SET_PARAMETER Use_Inclk_Stopped false
|
||||
SET_PARAMETER Use_Clkfb_Stopped false
|
||||
SET_PARAMETER RESET_port RESET
|
||||
SET_PARAMETER LOCKED_port LOCKED
|
||||
SET_PARAMETER Power_Down_port POWER_DOWN
|
||||
SET_PARAMETER CLK_VALID_port CLK_VALID
|
||||
SET_PARAMETER STATUS_port STATUS
|
||||
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
|
||||
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
|
||||
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
|
||||
SET_PARAMETER Override_Mmcm false
|
||||
SET_PARAMETER Mmcm_Notes None
|
||||
SET_PARAMETER Mmcm_Divclk_Divide 1
|
||||
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkin1_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkin2_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Cascade false
|
||||
SET_PARAMETER Mmcm_Clock_Hold false
|
||||
SET_PARAMETER Mmcm_Compensation ZHOLD
|
||||
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
|
||||
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
|
||||
SET_PARAMETER Mmcm_Startup_Wait false
|
||||
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout1_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout2_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout3_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout4_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout5_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout6_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
|
||||
SET_PARAMETER Override_Dcm false
|
||||
SET_PARAMETER Dcm_Notes None
|
||||
SET_PARAMETER Dcm_Clkdv_Divide 2.0
|
||||
SET_PARAMETER Dcm_Clkfx_Divide 1
|
||||
SET_PARAMETER Dcm_Clkfx_Multiply 4
|
||||
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
|
||||
SET_PARAMETER Dcm_Clkin_Period 30.000
|
||||
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
|
||||
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
|
||||
SET_PARAMETER Dcm_Phase_Shift 0
|
||||
SET_PARAMETER Dcm_Clk_Feedback 1X
|
||||
SET_PARAMETER Dcm_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clk_Out1_Port CLK0
|
||||
SET_PARAMETER Dcm_Clk_Out2_Port CLK2X
|
||||
SET_PARAMETER Dcm_Clk_Out3_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out4_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out5_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
|
||||
SET_PARAMETER Override_Dcm_Clkgen false
|
||||
SET_PARAMETER Dcm_Clkgen_Notes None
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
|
||||
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clkgen_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX180
|
||||
SET_PARAMETER Override_Pll false
|
||||
SET_PARAMETER Pll_Notes None
|
||||
SET_PARAMETER Pll_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Pll_Clkfbout_Mult 20
|
||||
SET_PARAMETER Pll_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
|
||||
SET_PARAMETER Pll_Divclk_Divide 1
|
||||
SET_PARAMETER Pll_Clkin_Period 30.000
|
||||
SET_PARAMETER Pll_Compensation EXTERNAL
|
||||
SET_PARAMETER Pll_Ref_Jitter 0.008
|
||||
SET_PARAMETER Pll_Clkout0_Divide 10
|
||||
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout1_Divide 10
|
||||
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout2_Divide 10
|
||||
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout2_Phase -72.000
|
||||
SET_PARAMETER Pll_Clkout3_Divide 10
|
||||
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout4_Divide 16
|
||||
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout5_Divide 1
|
||||
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout5_Phase 0.000
|
||||
SET_PARAMETER dcm_pll_cascade NONE
|
||||
SET_PARAMETER clock_mgr_type AUTO
|
||||
SET_PARAMETER primtype_sel PLL_BASE
|
||||
SET_PARAMETER primitive MMCM
|
||||
SET_PARAMETER SS_Mode CENTER_HIGH
|
||||
SET_PARAMETER SS_Mod_Freq 250
|
||||
SET_SIM_PARAMETER c_clkout2_used 0
|
||||
SET_SIM_PARAMETER c_clkout3_used 0
|
||||
SET_SIM_PARAMETER c_clkout4_used 0
|
||||
SET_SIM_PARAMETER c_clkout5_used 0
|
||||
SET_SIM_PARAMETER c_clkout6_used 0
|
||||
SET_SIM_PARAMETER c_clkout7_used 0
|
||||
SET_SIM_PARAMETER c_use_clkout1_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout2_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout3_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout4_bar 0
|
||||
SET_SIM_PARAMETER c_component_name CLK
|
||||
SET_SIM_PARAMETER c_platform nt
|
||||
SET_SIM_PARAMETER c_use_freq_synth 1
|
||||
SET_SIM_PARAMETER c_use_phase_alignment 1
|
||||
SET_SIM_PARAMETER c_prim_in_jitter 0.00833333333333
|
||||
SET_SIM_PARAMETER c_secondary_in_jitter 0.004
|
||||
SET_SIM_PARAMETER c_jitter_sel No_Jitter
|
||||
SET_SIM_PARAMETER c_use_min_power 0
|
||||
SET_SIM_PARAMETER c_use_min_o_jitter 0
|
||||
SET_SIM_PARAMETER c_use_max_i_jitter 0
|
||||
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
|
||||
SET_SIM_PARAMETER c_use_inclk_switchover 0
|
||||
SET_SIM_PARAMETER c_use_dyn_reconfig 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
|
||||
SET_SIM_PARAMETER c_primtype_sel DCM_SP
|
||||
SET_SIM_PARAMETER c_use_clk_valid 0
|
||||
SET_SIM_PARAMETER c_prim_in_freq 33.3333
|
||||
SET_SIM_PARAMETER c_in_freq_units Units_MHz
|
||||
SET_SIM_PARAMETER c_secondary_in_freq 100.000
|
||||
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO_OFFCHIP
|
||||
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
|
||||
SET_SIM_PARAMETER c_use_reset 0
|
||||
SET_SIM_PARAMETER c_use_locked 0
|
||||
SET_SIM_PARAMETER c_use_inclk_stopped 0
|
||||
SET_SIM_PARAMETER c_use_clkfb_stopped 0
|
||||
SET_SIM_PARAMETER c_use_power_down 0
|
||||
SET_SIM_PARAMETER c_use_status 0
|
||||
SET_SIM_PARAMETER c_use_freeze 0
|
||||
SET_SIM_PARAMETER c_num_out_clks 1
|
||||
SET_SIM_PARAMETER c_clkout1_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout2_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout3_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout4_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout5_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout6_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout7_drives BUFG
|
||||
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
SET_SIM_PARAMETER c_inclk_sum_row1 __primary_________33.3333___________0.00833333333333
|
||||
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____33.333______0.000______50.0______200.000____150.000
|
||||
SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
|
||||
SET_SIM_PARAMETER c_clkout1_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout2_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout3_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout4_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout5_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout6_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout7_requested_out_freq 33.3333
|
||||
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_phase -72
|
||||
SET_SIM_PARAMETER c_clkout4_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout1_out_freq 33.333
|
||||
SET_SIM_PARAMETER c_clkout2_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout3_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout4_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout5_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout6_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout7_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout3_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout4_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout5_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout6_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout7_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_mmcm_notes None
|
||||
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
|
||||
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_pll_notes None
|
||||
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_mult 20
|
||||
SET_SIM_PARAMETER c_pll_clkin_period 30.000
|
||||
SET_SIM_PARAMETER c_pll_compensation EXTERNAL
|
||||
SET_SIM_PARAMETER c_pll_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_pll_ref_jitter 0.008
|
||||
SET_SIM_PARAMETER c_pll_clkout0_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout1_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout2_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout3_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout4_divide 16
|
||||
SET_SIM_PARAMETER c_pll_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout2_phase -72.000
|
||||
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_dcm_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_divide 1
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_multiply 4
|
||||
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkin_period 30.0
|
||||
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback 1X
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback_port CLK0
|
||||
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
|
||||
SET_SIM_PARAMETER c_dcm_phase_shift 0
|
||||
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out1_port CLK0
|
||||
SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 30.0
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
|
||||
SET_SIM_PARAMETER c_clock_mgr_type AUTO
|
||||
SET_SIM_PARAMETER c_override_mmcm 0
|
||||
SET_SIM_PARAMETER c_override_pll 0
|
||||
SET_SIM_PARAMETER c_override_dcm 0
|
||||
SET_SIM_PARAMETER c_override_dcm_clkgen 0
|
||||
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
|
||||
SET_SIM_PARAMETER c_primary_port CLKIN
|
||||
SET_SIM_PARAMETER c_secondary_port CLK_IN2
|
||||
SET_SIM_PARAMETER c_clk_out1_port FSBCLK
|
||||
SET_SIM_PARAMETER c_clk_out2_port RAMCLK
|
||||
SET_SIM_PARAMETER c_clk_out3_port CPUCLK
|
||||
SET_SIM_PARAMETER c_clk_out4_port C80M
|
||||
SET_SIM_PARAMETER c_clk_out5_port C50M
|
||||
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
|
||||
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
|
||||
SET_SIM_PARAMETER c_reset_port RESET
|
||||
SET_SIM_PARAMETER c_locked_port LOCKED
|
||||
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
|
||||
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
|
||||
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
|
||||
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
|
||||
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
|
||||
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
|
||||
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
|
||||
SET_SIM_PARAMETER c_daddr_port DADDR
|
||||
SET_SIM_PARAMETER c_dclk_port DCLK
|
||||
SET_SIM_PARAMETER c_drdy_port DRDY
|
||||
SET_SIM_PARAMETER c_dwe_port DWE
|
||||
SET_SIM_PARAMETER c_din_port DIN
|
||||
SET_SIM_PARAMETER c_dout_port DOUT
|
||||
SET_SIM_PARAMETER c_den_port DEN
|
||||
SET_SIM_PARAMETER c_psclk_port PSCLK
|
||||
SET_SIM_PARAMETER c_psen_port PSEN
|
||||
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
|
||||
SET_SIM_PARAMETER c_psdone_port PSDONE
|
||||
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
|
||||
SET_SIM_PARAMETER c_status_port STATUS
|
||||
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
|
||||
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
|
||||
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
|
||||
SET_SIM_PARAMETER c_clkin1_jitter_ps 250.0
|
||||
SET_SIM_PARAMETER c_clkin2_jitter_ps 40.0
|
||||
SET_SIM_PARAMETER c_primitive MMCM
|
||||
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
|
||||
SET_SIM_PARAMETER c_ss_mod_period 4000
|
||||
SET_CORE_NAME Clocking Wizard
|
||||
SET_CORE_VERSION 3.6
|
||||
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
|
||||
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
|
||||
SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
|
||||
SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
|
||||
SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
|
||||
505
fpga/ipcore_dir/tmp/customization_gui.0.943263247117.out
Normal file
505
fpga/ipcore_dir/tmp/customization_gui.0.943263247117.out
Normal file
@ -0,0 +1,505 @@
|
||||
SET_FLAG DEBUG FALSE
|
||||
SET_FLAG MODE BATCH
|
||||
SET_FLAG STANDALONE_MODE FALSE
|
||||
SET_PREFERENCE devicefamily spartan6
|
||||
SET_PREFERENCE device xc6slx9
|
||||
SET_PREFERENCE speedgrade -2
|
||||
SET_PREFERENCE package ftg256
|
||||
SET_PREFERENCE verilogsim true
|
||||
SET_PREFERENCE vhdlsim false
|
||||
SET_PREFERENCE simulationfiles Behavioral
|
||||
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
|
||||
SET_PREFERENCE outputdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/
|
||||
SET_PREFERENCE workingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/
|
||||
SET_PREFERENCE subworkingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/
|
||||
SET_PREFERENCE transientdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/_dbg/
|
||||
SET_PREFERENCE designentry Verilog
|
||||
SET_PREFERENCE flowvendor Other
|
||||
SET_PREFERENCE addpads false
|
||||
SET_PREFERENCE projectname coregen
|
||||
SET_PREFERENCE formalverification false
|
||||
SET_PREFERENCE asysymbol false
|
||||
SET_PREFERENCE implementationfiletype Ngc
|
||||
SET_PREFERENCE foundationsym false
|
||||
SET_PREFERENCE createndf false
|
||||
SET_PREFERENCE removerpms false
|
||||
SET_PARAMETER Component_Name CLK
|
||||
SET_PARAMETER Use_Freq_Synth true
|
||||
SET_PARAMETER Use_Phase_Alignment true
|
||||
SET_PARAMETER Use_Min_Power false
|
||||
SET_PARAMETER Use_Dyn_Phase_Shift false
|
||||
SET_PARAMETER Use_Dyn_Reconfig false
|
||||
SET_PARAMETER Jitter_Sel No_Jitter
|
||||
SET_PARAMETER Use_Spread_Spectrum false
|
||||
SET_PARAMETER Use_Spread_Spectrum_1 false
|
||||
SET_PARAMETER Prim_In_Freq 40
|
||||
SET_PARAMETER In_Freq_Units Units_MHz
|
||||
SET_PARAMETER In_Jitter_Units Units_UI
|
||||
SET_PARAMETER Relative_Inclk REL_PRIMARY
|
||||
SET_PARAMETER Secondary_In_Freq 100.000
|
||||
SET_PARAMETER Jitter_Options PS
|
||||
SET_PARAMETER Clkin1_UI_Jitter 250.000
|
||||
SET_PARAMETER Clkin2_UI_Jitter 100.000
|
||||
SET_PARAMETER Prim_In_Jitter 0.01
|
||||
SET_PARAMETER Secondary_In_Jitter 0.004
|
||||
SET_PARAMETER Clkin1_Jitter_Ps 250.0
|
||||
SET_PARAMETER Clkin2_Jitter_Ps 40.0
|
||||
SET_PARAMETER Clkout2_Used true
|
||||
SET_PARAMETER Clkout3_Used true
|
||||
SET_PARAMETER Clkout4_Used false
|
||||
SET_PARAMETER Clkout5_Used false
|
||||
SET_PARAMETER Clkout6_Used false
|
||||
SET_PARAMETER Clkout7_Used false
|
||||
SET_PARAMETER Num_Out_Clks 3
|
||||
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
|
||||
SET_PARAMETER primary_port CLKIN
|
||||
SET_PARAMETER CLK_OUT1_port FSBCLK
|
||||
SET_PARAMETER CLK_OUT2_port RAMCLK
|
||||
SET_PARAMETER CLK_OUT3_port CPUCLK
|
||||
SET_PARAMETER CLK_OUT4_port C80M
|
||||
SET_PARAMETER CLK_OUT5_port C50M
|
||||
SET_PARAMETER CLK_OUT6_port CLK_OUT6
|
||||
SET_PARAMETER CLK_OUT7_port CLK_OUT7
|
||||
SET_PARAMETER DADDR_port DADDR
|
||||
SET_PARAMETER DCLK_port DCLK
|
||||
SET_PARAMETER DRDY_port DRDY
|
||||
SET_PARAMETER DWE_port DWE
|
||||
SET_PARAMETER DIN_port DIN
|
||||
SET_PARAMETER DOUT_port DOUT
|
||||
SET_PARAMETER DEN_port DEN
|
||||
SET_PARAMETER PSCLK_port PSCLK
|
||||
SET_PARAMETER PSEN_port PSEN
|
||||
SET_PARAMETER PSINCDEC_port PSINCDEC
|
||||
SET_PARAMETER PSDONE_port PSDONE
|
||||
SET_PARAMETER Clkout1_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout1_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout2_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout2_Requested_Phase 0
|
||||
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout3_Requested_Out_Freq 66.667
|
||||
SET_PARAMETER Clkout3_Requested_Phase -72
|
||||
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout4_Requested_Out_Freq 80
|
||||
SET_PARAMETER Clkout4_Requested_Phase 0
|
||||
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout5_Requested_Out_Freq 50
|
||||
SET_PARAMETER Clkout5_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout6_Requested_Out_Freq 33.000
|
||||
SET_PARAMETER Clkout6_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Clkout7_Requested_Out_Freq 33.000
|
||||
SET_PARAMETER Clkout7_Requested_Phase 0.000
|
||||
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.0
|
||||
SET_PARAMETER Use_Max_I_Jitter false
|
||||
SET_PARAMETER Use_Min_O_Jitter false
|
||||
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Use_Inclk_Switchover false
|
||||
SET_PARAMETER secondary_port CLK_IN2
|
||||
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
|
||||
SET_PARAMETER Clkout1_Drives BUFG
|
||||
SET_PARAMETER Clkout2_Drives BUFG
|
||||
SET_PARAMETER Clkout3_Drives BUFG
|
||||
SET_PARAMETER Clkout4_Drives BUFG
|
||||
SET_PARAMETER Clkout5_Drives BUFG
|
||||
SET_PARAMETER Clkout6_Drives BUFG
|
||||
SET_PARAMETER Clkout7_Drives BUFG
|
||||
SET_PARAMETER Feedback_Source FDBK_AUTO_OFFCHIP
|
||||
SET_PARAMETER Clkfb_In_Signaling SINGLE
|
||||
SET_PARAMETER CLKFB_IN_port CLKFB_IN
|
||||
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
|
||||
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
|
||||
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
|
||||
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
|
||||
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
|
||||
SET_PARAMETER Platform nt
|
||||
SET_PARAMETER Summary_Strings empty
|
||||
SET_PARAMETER Use_Locked false
|
||||
SET_PARAMETER calc_done DONE
|
||||
SET_PARAMETER Use_Reset false
|
||||
SET_PARAMETER Use_Power_Down false
|
||||
SET_PARAMETER Use_Status false
|
||||
SET_PARAMETER Use_Freeze false
|
||||
SET_PARAMETER Use_Clk_Valid false
|
||||
SET_PARAMETER Use_Inclk_Stopped false
|
||||
SET_PARAMETER Use_Clkfb_Stopped false
|
||||
SET_PARAMETER RESET_port RESET
|
||||
SET_PARAMETER LOCKED_port LOCKED
|
||||
SET_PARAMETER Power_Down_port POWER_DOWN
|
||||
SET_PARAMETER CLK_VALID_port CLK_VALID
|
||||
SET_PARAMETER STATUS_port STATUS
|
||||
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
|
||||
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
|
||||
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
|
||||
SET_PARAMETER Override_Mmcm false
|
||||
SET_PARAMETER Mmcm_Notes None
|
||||
SET_PARAMETER Mmcm_Divclk_Divide 1
|
||||
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkin1_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkin2_Period 10.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Cascade false
|
||||
SET_PARAMETER Mmcm_Clock_Hold false
|
||||
SET_PARAMETER Mmcm_Compensation ZHOLD
|
||||
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
|
||||
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
|
||||
SET_PARAMETER Mmcm_Startup_Wait false
|
||||
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout1_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout2_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout3_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout4_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout5_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
|
||||
SET_PARAMETER Mmcm_Clkout6_Divide 1
|
||||
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
|
||||
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
|
||||
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
|
||||
SET_PARAMETER Override_Dcm false
|
||||
SET_PARAMETER Dcm_Notes None
|
||||
SET_PARAMETER Dcm_Clkdv_Divide 2.0
|
||||
SET_PARAMETER Dcm_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
|
||||
SET_PARAMETER Dcm_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
|
||||
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
|
||||
SET_PARAMETER Dcm_Phase_Shift 0
|
||||
SET_PARAMETER Dcm_Clk_Feedback NONE
|
||||
SET_PARAMETER Dcm_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out3_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out4_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out5_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
|
||||
SET_PARAMETER Override_Dcm_Clkgen false
|
||||
SET_PARAMETER Dcm_Clkgen_Notes None
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
|
||||
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
|
||||
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
|
||||
SET_PARAMETER Dcm_Clkgen_Clkin_Period 30.303
|
||||
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
|
||||
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX180
|
||||
SET_PARAMETER Override_Pll false
|
||||
SET_PARAMETER Pll_Notes None
|
||||
SET_PARAMETER Pll_Bandwidth OPTIMIZED
|
||||
SET_PARAMETER Pll_Clkfbout_Mult 20
|
||||
SET_PARAMETER Pll_Clkfbout_Phase 0.000
|
||||
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
|
||||
SET_PARAMETER Pll_Divclk_Divide 1
|
||||
SET_PARAMETER Pll_Clkin_Period 25.000
|
||||
SET_PARAMETER Pll_Compensation EXTERNAL
|
||||
SET_PARAMETER Pll_Ref_Jitter 0.010
|
||||
SET_PARAMETER Pll_Clkout0_Divide 12
|
||||
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout0_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout1_Divide 12
|
||||
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout1_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout2_Divide 12
|
||||
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout2_Phase -71.250
|
||||
SET_PARAMETER Pll_Clkout3_Divide 10
|
||||
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout3_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout4_Divide 16
|
||||
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout4_Phase 0.000
|
||||
SET_PARAMETER Pll_Clkout5_Divide 1
|
||||
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
|
||||
SET_PARAMETER Pll_Clkout5_Phase 0.000
|
||||
SET_PARAMETER dcm_pll_cascade NONE
|
||||
SET_PARAMETER clock_mgr_type MANUAL
|
||||
SET_PARAMETER primtype_sel PLL_BASE
|
||||
SET_PARAMETER primitive MMCM
|
||||
SET_PARAMETER SS_Mode CENTER_HIGH
|
||||
SET_PARAMETER SS_Mod_Freq 250
|
||||
SET_SIM_PARAMETER c_clkout2_used 1
|
||||
SET_SIM_PARAMETER c_clkout3_used 1
|
||||
SET_SIM_PARAMETER c_clkout4_used 0
|
||||
SET_SIM_PARAMETER c_clkout5_used 0
|
||||
SET_SIM_PARAMETER c_clkout6_used 0
|
||||
SET_SIM_PARAMETER c_clkout7_used 0
|
||||
SET_SIM_PARAMETER c_use_clkout1_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout2_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout3_bar 0
|
||||
SET_SIM_PARAMETER c_use_clkout4_bar 0
|
||||
SET_SIM_PARAMETER c_component_name CLK
|
||||
SET_SIM_PARAMETER c_platform nt
|
||||
SET_SIM_PARAMETER c_use_freq_synth 1
|
||||
SET_SIM_PARAMETER c_use_phase_alignment 1
|
||||
SET_SIM_PARAMETER c_prim_in_jitter 0.01
|
||||
SET_SIM_PARAMETER c_secondary_in_jitter 0.004
|
||||
SET_SIM_PARAMETER c_jitter_sel No_Jitter
|
||||
SET_SIM_PARAMETER c_use_min_power 0
|
||||
SET_SIM_PARAMETER c_use_min_o_jitter 0
|
||||
SET_SIM_PARAMETER c_use_max_i_jitter 0
|
||||
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
|
||||
SET_SIM_PARAMETER c_use_inclk_switchover 0
|
||||
SET_SIM_PARAMETER c_use_dyn_reconfig 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum 0
|
||||
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
|
||||
SET_SIM_PARAMETER c_primtype_sel PLL_BASE
|
||||
SET_SIM_PARAMETER c_use_clk_valid 0
|
||||
SET_SIM_PARAMETER c_prim_in_freq 40
|
||||
SET_SIM_PARAMETER c_in_freq_units Units_MHz
|
||||
SET_SIM_PARAMETER c_secondary_in_freq 100.000
|
||||
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO_OFFCHIP
|
||||
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
|
||||
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
|
||||
SET_SIM_PARAMETER c_use_reset 0
|
||||
SET_SIM_PARAMETER c_use_locked 0
|
||||
SET_SIM_PARAMETER c_use_inclk_stopped 0
|
||||
SET_SIM_PARAMETER c_use_clkfb_stopped 0
|
||||
SET_SIM_PARAMETER c_use_power_down 0
|
||||
SET_SIM_PARAMETER c_use_status 0
|
||||
SET_SIM_PARAMETER c_use_freeze 0
|
||||
SET_SIM_PARAMETER c_num_out_clks 3
|
||||
SET_SIM_PARAMETER c_clkout1_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout2_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout3_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout4_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout5_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout6_drives BUFG
|
||||
SET_SIM_PARAMETER c_clkout7_drives BUFG
|
||||
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
SET_SIM_PARAMETER c_inclk_sum_row1 __primary______________40_____________0.01
|
||||
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____66.667______0.000______50.0______255.979____194.528
|
||||
SET_SIM_PARAMETER c_outclk_sum_row2 CLK_OUT2____66.667______0.000______50.0______255.979____194.528
|
||||
SET_SIM_PARAMETER c_outclk_sum_row3 CLK_OUT3____66.667____-71.250______50.0______255.979____194.528
|
||||
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
|
||||
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
|
||||
SET_SIM_PARAMETER c_clkout1_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout3_requested_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout4_requested_out_freq 80
|
||||
SET_SIM_PARAMETER c_clkout5_requested_out_freq 50
|
||||
SET_SIM_PARAMETER c_clkout6_requested_out_freq 33.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_out_freq 33.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_phase -72
|
||||
SET_SIM_PARAMETER c_clkout4_requested_phase 0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout1_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout2_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout3_out_freq 66.667
|
||||
SET_SIM_PARAMETER c_clkout4_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout5_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout6_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout7_out_freq N/A
|
||||
SET_SIM_PARAMETER c_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_clkout3_phase -71.250
|
||||
SET_SIM_PARAMETER c_clkout4_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout5_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout6_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout7_phase N/A
|
||||
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout2_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout3_duty_cycle 50.0
|
||||
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
|
||||
SET_SIM_PARAMETER c_mmcm_notes None
|
||||
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
|
||||
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
|
||||
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
|
||||
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
|
||||
SET_SIM_PARAMETER c_pll_notes None
|
||||
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_mult 20
|
||||
SET_SIM_PARAMETER c_pll_clkin_period 25.000
|
||||
SET_SIM_PARAMETER c_pll_compensation EXTERNAL
|
||||
SET_SIM_PARAMETER c_pll_divclk_divide 1
|
||||
SET_SIM_PARAMETER c_pll_ref_jitter 0.010
|
||||
SET_SIM_PARAMETER c_pll_clkout0_divide 12
|
||||
SET_SIM_PARAMETER c_pll_clkout1_divide 12
|
||||
SET_SIM_PARAMETER c_pll_clkout2_divide 12
|
||||
SET_SIM_PARAMETER c_pll_clkout3_divide 10
|
||||
SET_SIM_PARAMETER c_pll_clkout4_divide 16
|
||||
SET_SIM_PARAMETER c_pll_clkout5_divide 1
|
||||
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
|
||||
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout2_phase -71.250
|
||||
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
|
||||
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
|
||||
SET_SIM_PARAMETER c_dcm_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkin_period 25.0
|
||||
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_feedback_port CLKOUT1
|
||||
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
|
||||
SET_SIM_PARAMETER c_dcm_phase_shift 0
|
||||
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out2_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out3_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_notes None
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 2
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 25.0
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port CLKFX
|
||||
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port CLKFX180
|
||||
SET_SIM_PARAMETER c_clock_mgr_type MANUAL
|
||||
SET_SIM_PARAMETER c_override_mmcm 0
|
||||
SET_SIM_PARAMETER c_override_pll 0
|
||||
SET_SIM_PARAMETER c_override_dcm 0
|
||||
SET_SIM_PARAMETER c_override_dcm_clkgen 0
|
||||
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
|
||||
SET_SIM_PARAMETER c_primary_port CLKIN
|
||||
SET_SIM_PARAMETER c_secondary_port CLK_IN2
|
||||
SET_SIM_PARAMETER c_clk_out1_port FSBCLK
|
||||
SET_SIM_PARAMETER c_clk_out2_port RAMCLK
|
||||
SET_SIM_PARAMETER c_clk_out3_port CPUCLK
|
||||
SET_SIM_PARAMETER c_clk_out4_port C80M
|
||||
SET_SIM_PARAMETER c_clk_out5_port C50M
|
||||
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
|
||||
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
|
||||
SET_SIM_PARAMETER c_reset_port RESET
|
||||
SET_SIM_PARAMETER c_locked_port LOCKED
|
||||
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
|
||||
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
|
||||
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
|
||||
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
|
||||
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
|
||||
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
|
||||
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
|
||||
SET_SIM_PARAMETER c_daddr_port DADDR
|
||||
SET_SIM_PARAMETER c_dclk_port DCLK
|
||||
SET_SIM_PARAMETER c_drdy_port DRDY
|
||||
SET_SIM_PARAMETER c_dwe_port DWE
|
||||
SET_SIM_PARAMETER c_din_port DIN
|
||||
SET_SIM_PARAMETER c_dout_port DOUT
|
||||
SET_SIM_PARAMETER c_den_port DEN
|
||||
SET_SIM_PARAMETER c_psclk_port PSCLK
|
||||
SET_SIM_PARAMETER c_psen_port PSEN
|
||||
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
|
||||
SET_SIM_PARAMETER c_psdone_port PSDONE
|
||||
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
|
||||
SET_SIM_PARAMETER c_status_port STATUS
|
||||
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
|
||||
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
|
||||
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
|
||||
SET_SIM_PARAMETER c_clkin1_jitter_ps 250.0
|
||||
SET_SIM_PARAMETER c_clkin2_jitter_ps 40.0
|
||||
SET_SIM_PARAMETER c_primitive MMCM
|
||||
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
|
||||
SET_SIM_PARAMETER c_ss_mod_period 4000
|
||||
SET_CORE_NAME Clocking Wizard
|
||||
SET_CORE_VERSION 3.6
|
||||
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
|
||||
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
|
||||
SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
|
||||
SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
|
||||
SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
|
||||
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
|
||||
125
fpga/iseconfig/WarpLC.projectmgr
Normal file
125
fpga/iseconfig/WarpLC.projectmgr
Normal file
@ -0,0 +1,125 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!--This is an ISE project configuration file.-->
|
||||
<!--It holds project specific layout data for the projectmgr plugin.-->
|
||||
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
|
||||
<Project version="2" owner="projectmgr" name="WarpLC" >
|
||||
<!--This is an ISE project configuration file.-->
|
||||
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>2</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>WarpLC (C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.v)</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000014a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000014a0000000100000003000000000000000100000003</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
|
||||
<CurrentItem>WarpLC (C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.v)</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>Configure Target Device</ClosedNode>
|
||||
<ClosedNode>Design Utilities</ClosedNode>
|
||||
<ClosedNode>Implement Design</ClosedNode>
|
||||
<ClosedNode>Synthesize - XST</ClosedNode>
|
||||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView guiview="File" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems/>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000126000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004200000001000000000000002400000001000000000000006600000001000000000000005a0000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>WarpLC.v</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView guiview="Library" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>work</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems/>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000000fb000000010001000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>work</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>Configure Target Device</ClosedNode>
|
||||
<ClosedNode>Design Utilities</ClosedNode>
|
||||
<ClosedNode>Implement Design</ClosedNode>
|
||||
<ClosedNode>Synthesize - XST</ClosedNode>
|
||||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>Design Utilities</ClosedNode>
|
||||
<ClosedNode>Implement Design/Place & Route/Back-annotate Pin Locations</ClosedNode>
|
||||
<ClosedNode>Implement Design/Place & Route/Generate IBIS Model</ClosedNode>
|
||||
<ClosedNode>Implement Design/Translate</ClosedNode>
|
||||
<ClosedNode>Synthesize - XST</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>Analyze Post-Place & Route Static Timing</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >14</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000ea000000010000000100000000000000000000000064ffffffff000000810000000000000001000000ea0000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>Analyze Post-Place & Route Static Timing</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_XCO" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
|
||||
<CurrentView>Implementation</CurrentView>
|
||||
</Project>
|
||||
@ -1,9 +1,9 @@
|
||||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2021-10-29T07:38:32</DateModified>
|
||||
<DateModified>2021-10-29T17:40:54</DateModified>
|
||||
<ModuleName>WarpLC</ModuleName>
|
||||
<SummaryTimeStamp>2021-10-29T07:36:49</SummaryTimeStamp>
|
||||
<SummaryTimeStamp>2021-10-29T17:39:15</SummaryTimeStamp>
|
||||
<SavedFilePath>C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/iseconfig/WarpLC.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>C:/Users/zanek/Documents/GitHub/Warp-LC/fpga</ImplementationReportsDirectory>
|
||||
<DateInitialized>2021-10-29T06:26:45</DateInitialized>
|
||||
|
||||
@ -1,32 +1,32 @@
|
||||
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
|
||||
<xtag-section name="ParStatistics">
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>129</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>261</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>261</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>93</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>84</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>135</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>135</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>122</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>2.1 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>2.4 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>2.4 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>2.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>2.5 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>2.7 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>2.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>2.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>2.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>2.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>2.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>2.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>13.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>17.3</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>7.8</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>5.1</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>2.9 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>2.9 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>2.9 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>2.9 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>2.9 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>2.9 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>5.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>10.5</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>0.7</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>9.1</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0269</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0090</xtag-par-property-value></TD></TR>
|
||||
</xtag-section>
|
||||
</TABLE>
|
||||
|
||||
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Loading…
x
Reference in New Issue
Block a user