226 lines
8.5 KiB
Plaintext
226 lines
8.5 KiB
Plaintext
Release 14.7 - xst P.20131013 (nt)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Reading design: STERMINATOR.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "STERMINATOR.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "STERMINATOR"
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Output Format : NGC
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Target Device : XC9500XL CPLDs
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---- Source Options
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Top Module Name : STERMINATOR
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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Mux Extraction : Yes
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Resource Sharing : YES
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---- Target Options
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Add IO Buffers : YES
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MACRO Preserve : YES
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XOR Preserve : YES
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : Yes
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Verilog 2001 : YES
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---- Other Options
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Clock Enable : YES
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wysiwyg : NO
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../STERMINATOR.v" in library work
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Module <STERMINATOR> compiled
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No errors in compilation
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Analysis of file <"STERMINATOR.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module <STERMINATOR> in library <work>.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module <STERMINATOR>.
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Module <STERMINATOR> is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit <STERMINATOR>.
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Related source file is "../STERMINATOR.v".
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WARNING:Xst:647 - Input <A<27:26>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <nWE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Found 1-bit register for signal <NA>.
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Found 2-bit register for signal <NB>.
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Found 9-bit register for signal <NC>.
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Found 9-bit adder for signal <NC$add0000> created at line 51.
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Found 13-bit register for signal <NR>.
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Found 2-bit comparator equal for signal <NSEL$cmp_eq0000> created at line 59.
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Found 13-bit comparator equal for signal <NSEL$cmp_eq0001> created at line 59.
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Found 9-bit comparator equal for signal <NSEL$cmp_eq0002> created at line 59.
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Summary:
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inferred 1 D-type flip-flop(s).
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inferred 1 Adder/Subtractor(s).
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inferred 3 Comparator(s).
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Unit <STERMINATOR> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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9-bit adder : 1
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# Registers : 4
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1-bit register : 1
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13-bit register : 1
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2-bit register : 1
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9-bit register : 1
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# Comparators : 3
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13-bit comparator equal : 1
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2-bit comparator equal : 1
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9-bit comparator equal : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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9-bit adder : 1
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# Registers : 1
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Flip-Flops : 1
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# Comparators : 3
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13-bit comparator equal : 1
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2-bit comparator equal : 1
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9-bit comparator equal : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit <STERMINATOR> ...
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : STERMINATOR.ngr
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Top Level Output File Name : STERMINATOR
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : Yes
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Target Technology : XC9500XL CPLDs
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Macro Preserve : YES
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XOR Preserve : YES
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Clock Enable : YES
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wysiwyg : NO
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Design Statistics
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# IOs : 42
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Cell Usage :
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# BELS : 102
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# AND2 : 14
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# AND3 : 5
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# AND4 : 2
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# AND5 : 1
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# AND8 : 2
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# GND : 1
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# INV : 41
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# OR2 : 4
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# XOR2 : 32
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# FlipFlops/Latches : 25
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# FD : 1
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# FDCE : 24
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# IO Buffers : 39
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# IBUF : 37
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# OBUF : 2
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=========================================================================
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Total REAL time to Xst completion: 2.00 secs
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Total CPU time to Xst completion: 2.08 secs
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-->
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Total memory usage is 225560 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 2 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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