mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2025-02-19 18:31:12 +00:00
355 lines
52 KiB
XML
355 lines
52 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE twReport [
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<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
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twDebug*, twFoot?, twClientInfo?)>
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<!ATTLIST twReport version CDATA "10,4">
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<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
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<!ELEMENT twExecVer (#PCDATA)>
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<!ELEMENT twCopyright (#PCDATA)>
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<!ELEMENT twCmdLine (#PCDATA)>
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<!ELEMENT twDesign (#PCDATA)>
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<!ELEMENT twPCF (#PCDATA)>
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<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
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<!ELEMENT twDevName (#PCDATA)>
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<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
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<!ELEMENT twSpeedGrade (#PCDATA)>
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<!ELEMENT twSpeedVer (#PCDATA)>
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<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
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<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
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<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
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<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
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<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
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<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
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<!ELEMENT twItemLimit (#PCDATA)>
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<!ELEMENT twUnconst EMPTY>
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<!ELEMENT twUnconstLimit (#PCDATA)>
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<!ELEMENT twEnvVar EMPTY>
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<!ATTLIST twEnvVar name CDATA #REQUIRED>
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<!ATTLIST twEnvVar description CDATA #REQUIRED>
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<!ELEMENT twWarn (#PCDATA)>
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<!ELEMENT twInfo (#PCDATA)>
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<!ELEMENT twDebug (#PCDATA)>
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<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
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<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
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<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
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<!ELEMENT twProc (#PCDATA)>
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<!ELEMENT twTemp (#PCDATA)>
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<!ELEMENT twVolt (#PCDATA)>
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<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
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<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
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<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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<!ELEMENT twCycles (twSigConn+)>
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<!ATTLIST twCycles twNum CDATA #REQUIRED>
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<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
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<!ELEMENT twSig (#PCDATA)>
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<!ELEMENT twDriver (#PCDATA)>
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<!ELEMENT twLoad (#PCDATA)>
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<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
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<!ATTLIST twConst twConstType (NET |
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NETDELAY |
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NETSKEW |
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PATH |
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DEFPERIOD |
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UNCONSTPATH |
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DEFPATH |
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PATH2SETUP |
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UNCONSTPATH2SETUP |
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PATHCLASS |
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PATHDELAY |
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PERIOD |
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FREQUENCY |
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PATHBLOCK |
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OFFSET |
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OFFSETIN |
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OFFSETINCLOCK |
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UNCONSTOFFSETINCLOCK |
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OFFSETINDELAY |
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OFFSETINMOD |
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OFFSETOUT |
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OFFSETOUTCLOCK |
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UNCONSTOFFSETOUTCLOCK |
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OFFSETOUTDELAY |
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OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
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<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
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twEndPtCnt?,
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twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
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<!ELEMENT twConstName (#PCDATA)>
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<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
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<!ATTLIST twConstHead uID CDATA #IMPLIED>
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<!ELEMENT twItemCnt (#PCDATA)>
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<!ELEMENT twErrCnt (#PCDATA)>
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<!ELEMENT twErrCntEndPt (#PCDATA)>
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<!ELEMENT twErrCntSetup (#PCDATA)>
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<!ELEMENT twErrCntHold (#PCDATA)>
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<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
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<!ELEMENT twEndPtCnt (#PCDATA)>
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<!ELEMENT twPathErrCnt (#PCDATA)>
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<!ELEMENT twMinPer (#PCDATA) >
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<!ELEMENT twFootnote EMPTY>
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<!ATTLIST twFootnote number CDATA #REQUIRED>
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<!ELEMENT twMaxDel (#PCDATA)>
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<!ELEMENT twMaxFreq (#PCDATA)>
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<!ELEMENT twMinOff (#PCDATA)>
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<!ELEMENT twMaxOff (#PCDATA)>
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<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
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<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
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<!ELEMENT twTIGName (#PCDATA)>
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<!ELEMENT twInstantiated (#PCDATA)>
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<!ELEMENT twBlocked (#PCDATA)>
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<!ELEMENT twRacePathRpt (twRacePath+)>
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<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
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<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
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<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
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twSimpleMinPath CDATA #IMPLIED>
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<!ELEMENT twTotDel (#PCDATA)>
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<!ELEMENT twSrc (#PCDATA)>
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<!ATTLIST twSrc BELType CDATA #IMPLIED>
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<!ELEMENT twDest (#PCDATA)>
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<!ATTLIST twDest BELType CDATA #IMPLIED>
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<!ELEMENT twDel (#PCDATA)>
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<!ELEMENT twSUTime (#PCDATA)>
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<!ELEMENT twTotPathDel (#PCDATA)>
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<!ELEMENT twClkSkew (#PCDATA)>
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<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
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<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
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<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
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<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
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<!ELEMENT twSlack (#PCDATA)>
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<!ELEMENT twDelConst (#PCDATA)>
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<!ELEMENT tw2Phase EMPTY>
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<!ELEMENT twClkUncert (#PCDATA)>
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<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
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fDCMJit CDATA #IMPLIED
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fPhaseErr CDATA #IMPLIED
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sEqu CDATA #IMPLIED>
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<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
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<!ELEMENT twPathRptBanner (#PCDATA)>
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<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
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<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
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<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
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<!ELEMENT twOff (#PCDATA)>
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<!ELEMENT twGuaranteed EMPTY>
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<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
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<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
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<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
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<!ELEMENT twClkDel (#PCDATA)>
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<!ELEMENT twClkSrc (#PCDATA)>
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<!ELEMENT twClkDest (#PCDATA)>
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<!ELEMENT twGuarInSetup (#PCDATA)>
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<!ELEMENT twOffSrc (#PCDATA)>
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<!ELEMENT twOffDest (#PCDATA)>
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<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
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<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
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<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
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<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
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<!ELEMENT twDataDel (#PCDATA)>
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<!ELEMENT twDataSrc (#PCDATA)>
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<!ELEMENT twDataDest (#PCDATA)>
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<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
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<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twLogLvls (#PCDATA)>
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<!ELEMENT twSrcSite (#PCDATA)>
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<!ELEMENT twSrcClk (#PCDATA)>
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<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
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<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
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<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
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<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
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<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
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<!ELEMENT twDelInfo (#PCDATA)>
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<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
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<!ELEMENT twSite (#PCDATA)>
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<!ELEMENT twDelType (#PCDATA)>
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<!ELEMENT twFanCnt (#PCDATA)>
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<!ELEMENT twComp (#PCDATA)>
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<!ELEMENT twNet (#PCDATA)>
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<!ELEMENT twBEL (#PCDATA)>
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<!ELEMENT twLogDel (#PCDATA)>
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<!ELEMENT twRouteDel (#PCDATA)>
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<!ELEMENT twDestClk (#PCDATA)>
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<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
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<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
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<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
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<!ELEMENT twPctLog (#PCDATA)>
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<!ELEMENT twPctRoute (#PCDATA)>
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<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
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<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
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<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
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<!ELEMENT twTimeConst (#PCDATA)>
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<!ELEMENT twAbsSlack (#PCDATA)>
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<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
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<!ELEMENT twSkew (#PCDATA)>
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<!ELEMENT twDetNet (twNetDel*)>
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<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
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<!ELEMENT twNetDelInfo (#PCDATA)>
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<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
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<!ELEMENT twDetSkewNet (twNetSkew*)>
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<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
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<!ELEMENT twClkSkewLimit EMPTY>
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<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
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arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
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<!ELEMENT twConstRollupTable (twConstRollup*)>
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<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
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<!ELEMENT twConstRollup EMPTY>
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<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
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<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
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<!ELEMENT twConstList (twConstListItem)*>
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<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
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<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
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<!ELEMENT twNotMet EMPTY>
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<!ELEMENT twReqVal (#PCDATA)>
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<!ELEMENT twActVal (#PCDATA)>
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<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
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<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
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<!ELEMENT twConstStats (twConstName)>
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<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
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<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
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<!ATTLIST twConstStats twActual CDATA #IMPLIED>
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<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
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<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
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<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
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<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
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<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
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<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
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<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
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<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
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<!ELEMENT twConstData EMPTY>
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<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
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best CDATA #IMPLIED requested CDATA #IMPLIED
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errors CDATA #IMPLIED
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score CDATA #IMPLIED>
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<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
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<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
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<!ELEMENT twTimeGrpName (#PCDATA)>
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<!ELEMENT twCompList (twCompName+)>
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<!ELEMENT twCompName (#PCDATA)>
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<!ELEMENT twSigList (twSigName+)>
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<!ELEMENT twSigName (#PCDATA)>
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<!ELEMENT twBELList (twBELName+)>
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<!ELEMENT twBELName (#PCDATA)>
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<!ELEMENT twBlockList (twBlockName+)>
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<!ELEMENT twBlockName (#PCDATA)>
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<!ELEMENT twMacList (twMacName+)>
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<!ELEMENT twMacName (#PCDATA)>
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<!ELEMENT twPinList (twPinName+)>
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<!ELEMENT twPinName (#PCDATA)>
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<!ELEMENT twUnmetConstCnt (#PCDATA)>
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<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
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<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
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<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
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<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
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<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
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<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
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<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
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<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
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<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
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<!ELEMENT twSU2ClkTime (#PCDATA)>
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<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twH2ClkTime (#PCDATA)>
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<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
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<!ELEMENT twClk2Pad (twDest, twTime)>
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<!ELEMENT twTime (#PCDATA)>
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<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
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<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
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<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
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<!ELEMENT twClk2Out EMPTY>
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<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
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<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
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<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
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<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
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<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
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<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
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<!ELEMENT twRiseRise (#PCDATA)>
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<!ELEMENT twFallRise (#PCDATA)>
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<!ELEMENT twRiseFall (#PCDATA)>
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<!ELEMENT twFallFall (#PCDATA)>
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<!ELEMENT twPad2PadList (twPad2Pad+)>
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<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
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<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
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<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
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<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
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<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
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<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
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<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
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<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
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<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
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<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
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<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
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<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
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<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
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<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
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<!ELEMENT twOffOutTblRow EMPTY>
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<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
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<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
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<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
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<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
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<!ELEMENT twNonDedClk (#PCDATA)>
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<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
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<!ELEMENT twScore (#PCDATA)>
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<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
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<!ELEMENT twPathCnt (#PCDATA)>
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<!ELEMENT twNetCnt (#PCDATA)>
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<!ELEMENT twConnCnt (#PCDATA)>
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<!ELEMENT twPct (#PCDATA)>
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<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
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<!ELEMENT twMaxCombDel (#PCDATA)>
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<!ELEMENT twMaxFromToDel (#PCDATA)>
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<!ELEMENT twMaxNetDel (#PCDATA)>
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<!ELEMENT twMaxNetSkew (#PCDATA)>
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<!ELEMENT twMaxInAfterClk (#PCDATA)>
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<!ELEMENT twMinInBeforeClk (#PCDATA)>
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<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (nt)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
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3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr
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WarpLC.pcf -ucf PLL.ucf
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</twCmdLine><twDesign>WarpLC_map.ncd</twDesign><twDesignPath>WarpLC_map.ncd</twDesignPath><twPCF>WarpLC.pcf</twPCF><twPcfPath>WarpLC.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="ftg256"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3284 - This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="6" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="NET FSBCLK PERIOD = 10ns HIGH;" ScopeName="">NET "FSBCLK" PERIOD = 10 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.866</twMinPer></twConstHead><twPinLimitRpt anchorID="7"><twPinLimitBanner>Component Switching Limit Checks: NET "FSBCLK" PERIOD = 10 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="8" type="MINPERIOD" name="Tickper" slack="8.134" period="10.000" constraintValue="10.000" deviceLimit="1.866" freqLimit="535.906" physResource="OUTt_OBUF/CLK0" logResource="OUTt/CLK0" locationPin="ILOGIC_X0Y5.CLK0" clockNet="FSBCLK"/></twPinLimitRpt></twConst><twConst anchorID="9" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="NET CLKIN PERIOD = 20ns HIGH;" ScopeName="">NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>5.000</twMinPer></twConstHead><twPinLimitRpt anchorID="10"><twPinLimitBanner>Component Switching Limit Checks: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="11" type="MINLOWPULSE" name="Tdcmpw_CLKIN_50_100" slack="15.000" period="20.000" constraintValue="10.000" deviceLimit="2.500" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN1" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/><twPinLimit anchorID="12" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_50_100" slack="15.000" period="20.000" constraintValue="10.000" deviceLimit="2.500" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN1" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/><twPinLimit anchorID="13" type="MINPERIOD" name="Tpllper_CLKIN(Finmax)" slack="17.780" period="20.000" constraintValue="20.000" deviceLimit="2.220" freqLimit="450.450" physResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" logResource="instance_name/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y1.CLKIN1" clockNet="instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK"/></twPinLimitRpt></twConst><twConst anchorID="14" twConstType="PERIOD" ><twConstHead uID="7"><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS </twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.666</twMinPer></twConstHead><twPinLimitRpt anchorID="15"><twPinLimitBanner>Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkfbout" derived from
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NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
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duty cycle corrected to 20 nS HIGH 10 nS
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</twPinLimitBanner><twPinLimit anchorID="16" type="MINPERIOD" name="Tbcper_I" slack="17.334" period="20.000" constraintValue="20.000" deviceLimit="2.666" freqLimit="375.094" physResource="instance_name/clkfbout_bufg/I0" logResource="instance_name/clkfbout_bufg/I0" locationPin="BUFGMUX_X2Y3.I0" clockNet="instance_name/clkfbout"/><twPinLimit anchorID="17" type="MINPERIOD" name="Tockper" slack="17.751" period="20.000" constraintValue="20.000" deviceLimit="2.249" freqLimit="444.642" physResource="CLKFB_OUT_OBUF/CLK0" logResource="instance_name/clkfbout_oddr/CK0" locationPin="OLOGIC_X0Y7.CLK0" clockNet="instance_name/clkfb_bufg_out"/><twPinLimit anchorID="18" type="MINPERIOD" name="Tpllper_CLKFB" slack="17.780" period="20.000" constraintValue="20.000" deviceLimit="2.220" freqLimit="450.450" physResource="instance_name/pll_base_inst/PLL_ADV/CLKFBOUT" logResource="instance_name/pll_base_inst/PLL_ADV/CLKFBOUT" locationPin="PLL_ADV_X0Y1.CLKFBOUT" clockNet="instance_name/clkfbout"/></twPinLimitRpt></twConst><twConst anchorID="19" twConstType="PERIOD" ><twConstHead uID="6"><twConstName UCFConstName="" ScopeName="">PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS </twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.666</twMinPer></twConstHead><twPinLimitRpt anchorID="20"><twPinLimitBanner>Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout0" derived from
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NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;
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divided by 2.00 to 10 nS
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</twPinLimitBanner><twPinLimit anchorID="21" type="MINPERIOD" name="Tbcper_I" slack="7.334" period="10.000" constraintValue="10.000" deviceLimit="2.666" freqLimit="375.094" physResource="instance_name/clkout1_buf/I0" logResource="instance_name/clkout1_buf/I0" locationPin="BUFGMUX_X3Y13.I0" clockNet="instance_name/clkout0"/><twPinLimit anchorID="22" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="8.948" period="10.000" constraintValue="10.000" deviceLimit="1.052" freqLimit="950.570" physResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" logResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" locationPin="PLL_ADV_X0Y1.CLKOUT0" clockNet="instance_name/clkout0"/><twPinLimit anchorID="23" type="MAXPERIOD" name="Tpllper_CLKOUT(Foutmin)" slack="310.000" period="10.000" constraintValue="10.000" deviceLimit="320.000" freqLimit="3.125" physResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" logResource="instance_name/pll_base_inst/PLL_ADV/CLKOUT0" locationPin="PLL_ADV_X0Y1.CLKOUT0" clockNet="instance_name/clkout0"/></twPinLimitRpt></twConst><twConst anchorID="24" twConstType="OFFSETINDELAY" ><twConstHead uID="3"><twConstName UCFConstName="NET CPU_nAS OFFSET = IN 10ns VALID 11ns BEFORE CLKIN;" ScopeName="">COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";</twConstName><twItemCnt>1</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinOff>9.880</twMinOff></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point OUTt (ILOGIC_X0Y5.SR), 1 path
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</twPathRptBanner><twPathRpt anchorID="25"><twConstOffIn anchorID="26" twDataPathType="twDataPathMaxDelay"><twSlack>0.120</twSlack><twSrc BELType="PAD">CPU_nAS</twSrc><twDest BELType="FF">OUTt</twDest><twClkDel>-4.891</twClkDel><twClkSrc>CLKIN</twClkSrc><twClkDest>OUTt_OBUF</twClkDest><twOff>10.000</twOff><twOffSrc>CPU_nAS</twOffSrc><twOffDest>CLKIN</twOffDest><twClkUncert fSysJit="0.050" fDCMJit="0.287" fPhaseErr="0.267" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.414</twClkUncert><twDataPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='PAD'>CPU_nAS</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>1</twLogLvls><twSrcSite>N4.PAD</twSrcSite><twPathDel><twSite>N4.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twFalling">1.557</twDelInfo><twComp>CPU_nAS</twComp><twBEL>CPU_nAS</twBEL><twBEL>CPU_nAS_IBUF</twBEL><twBEL>ProtoComp0.IMUX.1</twBEL></twPathDel><twPathDel><twSite>ILOGIC_X0Y5.SR</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling" twAcc="twEst">2.043</twDelInfo><twComp>CPU_nAS_IBUF</twComp></twPathDel><twPathDel><twSite>ILOGIC_X0Y5.CLK0</twSite><twDelType>Tisrck</twDelType><twDelInfo twEdge="twFalling">0.975</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>OUTt</twBEL></twPathDel><twLogDel>2.532</twLogDel><twRouteDel>2.043</twRouteDel><twTotDel>4.575</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twDestClk><twPctLog>55.3</twPctLog><twPctRoute>44.7</twPctRoute></twDataPath><twClkPath maxSiteLen="20" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='PAD'>CLKIN</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>4</twLogLvls><twSrcSite>J4.PAD</twSrcSite><twPathDel><twSite>J4.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.902</twDelInfo><twComp>CLKIN</twComp><twBEL>CLKIN</twBEL><twBEL>instance_name/clkin1_buf</twBEL><twBEL>ProtoComp0.IMUX.3</twBEL></twPathDel><twPathDel><twSite>BUFIO2_X0Y23.I</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>instance_name/clkin1</twComp></twPathDel><twPathDel><twSite>BUFIO2_X0Y23.DIVCLK</twSite><twDelType>Tbufcko_DIVCLK</twDelType><twDelInfo twEdge="twRising">0.179</twDelInfo><twComp>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0</twComp><twBEL>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0</twBEL></twPathDel><twPathDel><twSite>PLL_ADV_X0Y1.CLKIN1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK</twComp></twPathDel><twPathDel><twSite>PLL_ADV_X0Y1.CLKOUT0</twSite><twDelType>Tpllcko_CLK</twDelType><twDelInfo twEdge="twRising">-8.248</twDelInfo><twComp>instance_name/pll_base_inst/PLL_ADV</twComp><twBEL>instance_name/pll_base_inst/PLL_ADV</twBEL></twPathDel><twPathDel><twSite>BUFGMUX_X3Y13.I0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.505</twDelInfo><twComp>instance_name/clkout0</twComp></twPathDel><twPathDel><twSite>BUFGMUX_X3Y13.O</twSite><twDelType>Tgi0o</twDelType><twDelInfo twEdge="twRising">0.197</twDelInfo><twComp>instance_name/clkout1_buf</twComp><twBEL>instance_name/clkout1_buf</twBEL></twPathDel><twPathDel><twSite>ILOGIC_X0Y5.CLK0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.574</twDelInfo><twComp>FSBCLK</twComp></twPathDel><twLogDel>-6.970</twLogDel><twRouteDel>2.079</twRouteDel><twTotDel>-4.891</twTotDel></twClkPath></twConstOffIn></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";
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</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point OUTt (ILOGIC_X0Y5.SR), 1 path
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</twPathRptBanner><twPathRpt anchorID="27"><twConstOffIn anchorID="28" twDataPathType="twDataPathMinDelay"><twSlack>6.650</twSlack><twSrc BELType="PAD">CPU_nAS</twSrc><twDest BELType="FF">OUTt</twDest><twClkDel>-3.099</twClkDel><twClkSrc>CLKIN</twClkSrc><twClkDest>OUTt_OBUF</twClkDest><twOff>1.000</twOff><twOffSrc>CPU_nAS</twOffSrc><twOffDest>CLKIN</twOffDest><twClkUncert fSysJit="0.050" fDCMJit="0.287" fPhaseErr="0.267" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.414</twClkUncert><twDataPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='PAD'>CPU_nAS</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>1</twLogLvls><twSrcSite>N4.PAD</twSrcSite><twPathDel><twSite>N4.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.763</twDelInfo><twComp>CPU_nAS</twComp><twBEL>CPU_nAS</twBEL><twBEL>CPU_nAS_IBUF</twBEL><twBEL>ProtoComp0.IMUX.1</twBEL></twPathDel><twPathDel><twSite>ILOGIC_X0Y5.SR</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.043</twDelInfo><twComp>CPU_nAS_IBUF</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>ILOGIC_X0Y5.CLK0</twSite><twDelType>Ticksr</twDelType><twDelInfo twEdge="twRising">0.159</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>OUTt</twBEL></twPathDel><twLogDel>0.922</twLogDel><twRouteDel>2.043</twRouteDel><twTotDel>2.965</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twDestClk><twPctLog>31.1</twPctLog><twPctRoute>68.9</twPctRoute></twDataPath><twClkPath maxSiteLen="20" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='PAD'>CLKIN</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>4</twLogLvls><twSrcSite>J4.PAD</twSrcSite><twPathDel><twSite>J4.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.367</twDelInfo><twComp>CLKIN</twComp><twBEL>CLKIN</twBEL><twBEL>instance_name/clkin1_buf</twBEL><twBEL>ProtoComp0.IMUX.3</twBEL></twPathDel><twPathDel><twSite>BUFIO2_X0Y23.I</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>instance_name/clkin1</twComp></twPathDel><twPathDel><twSite>BUFIO2_X0Y23.DIVCLK</twSite><twDelType>Tbufcko_DIVCLK</twDelType><twDelInfo twEdge="twRising">0.130</twDelInfo><twComp>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0</twComp><twBEL>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0</twBEL></twPathDel><twPathDel><twSite>PLL_ADV_X0Y1.CLKIN1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK</twComp></twPathDel><twPathDel><twSite>PLL_ADV_X0Y1.CLKOUT0</twSite><twDelType>Tpllcko_CLK</twDelType><twDelInfo twEdge="twRising">-5.738</twDelInfo><twComp>instance_name/pll_base_inst/PLL_ADV</twComp><twBEL>instance_name/pll_base_inst/PLL_ADV</twBEL></twPathDel><twPathDel><twSite>BUFGMUX_X3Y13.I0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.505</twDelInfo><twComp>instance_name/clkout0</twComp></twPathDel><twPathDel><twSite>BUFGMUX_X3Y13.O</twSite><twDelType>Tgi0o</twDelType><twDelInfo twEdge="twRising">0.063</twDelInfo><twComp>instance_name/clkout1_buf</twComp><twBEL>instance_name/clkout1_buf</twBEL></twPathDel><twPathDel><twSite>ILOGIC_X0Y5.CLK0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.574</twDelInfo><twComp>FSBCLK</twComp></twPathDel><twLogDel>-5.178</twLogDel><twRouteDel>2.079</twRouteDel><twTotDel>-3.099</twTotDel></twClkPath></twConstOffIn></twPathRpt></twConst><twConst anchorID="29" twConstType="OFFSETINDELAY" ><twConstHead uID="4"><twConstName UCFConstName="NET INt OFFSET = IN 10ns VALID 11ns BEFORE CLKIN;" ScopeName="">COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";</twConstName><twItemCnt>1</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinOff>8.814</twMinOff></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point OUTt (ILOGIC_X0Y5.D), 1 path
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</twPathRptBanner><twPathRpt anchorID="30"><twConstOffIn anchorID="31" twDataPathType="twDataPathMaxDelay"><twSlack>1.186</twSlack><twSrc BELType="PAD">INt</twSrc><twDest BELType="FF">OUTt</twDest><twClkDel>-4.891</twClkDel><twClkSrc>CLKIN</twClkSrc><twClkDest>OUTt_OBUF</twClkDest><twOff>10.000</twOff><twOffSrc>INt</twOffSrc><twOffDest>CLKIN</twOffDest><twClkUncert fSysJit="0.050" fDCMJit="0.287" fPhaseErr="0.267" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.414</twClkUncert><twDataPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='PAD'>INt</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>2</twLogLvls><twSrcSite>M4.PAD</twSrcSite><twPathDel><twSite>M4.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twFalling">1.557</twDelInfo><twComp>INt</twComp><twBEL>INt</twBEL><twBEL>INt_IBUF</twBEL><twBEL>ProtoComp0.IMUX.2</twBEL></twPathDel><twPathDel><twSite>ILOGIC_X0Y5.D</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling" twAcc="twEst">0.229</twDelInfo><twComp>CPU_nAS_INt_AND_1_o_norst</twComp></twPathDel><twPathDel><twSite>ILOGIC_X0Y5.CLK0</twSite><twDelType>Tidock</twDelType><twDelInfo twEdge="twFalling">1.723</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>ProtoComp3.D2OFFBYP_SRC</twBEL><twBEL>OUTt</twBEL></twPathDel><twLogDel>3.280</twLogDel><twRouteDel>0.229</twRouteDel><twTotDel>3.509</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twDestClk><twPctLog>93.5</twPctLog><twPctRoute>6.5</twPctRoute></twDataPath><twClkPath maxSiteLen="20" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='PAD'>CLKIN</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>4</twLogLvls><twSrcSite>J4.PAD</twSrcSite><twPathDel><twSite>J4.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.902</twDelInfo><twComp>CLKIN</twComp><twBEL>CLKIN</twBEL><twBEL>instance_name/clkin1_buf</twBEL><twBEL>ProtoComp0.IMUX.3</twBEL></twPathDel><twPathDel><twSite>BUFIO2_X0Y23.I</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>instance_name/clkin1</twComp></twPathDel><twPathDel><twSite>BUFIO2_X0Y23.DIVCLK</twSite><twDelType>Tbufcko_DIVCLK</twDelType><twDelInfo twEdge="twRising">0.179</twDelInfo><twComp>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0</twComp><twBEL>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0</twBEL></twPathDel><twPathDel><twSite>PLL_ADV_X0Y1.CLKIN1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK</twComp></twPathDel><twPathDel><twSite>PLL_ADV_X0Y1.CLKOUT0</twSite><twDelType>Tpllcko_CLK</twDelType><twDelInfo twEdge="twRising">-8.248</twDelInfo><twComp>instance_name/pll_base_inst/PLL_ADV</twComp><twBEL>instance_name/pll_base_inst/PLL_ADV</twBEL></twPathDel><twPathDel><twSite>BUFGMUX_X3Y13.I0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.505</twDelInfo><twComp>instance_name/clkout0</twComp></twPathDel><twPathDel><twSite>BUFGMUX_X3Y13.O</twSite><twDelType>Tgi0o</twDelType><twDelInfo twEdge="twRising">0.197</twDelInfo><twComp>instance_name/clkout1_buf</twComp><twBEL>instance_name/clkout1_buf</twBEL></twPathDel><twPathDel><twSite>ILOGIC_X0Y5.CLK0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.574</twDelInfo><twComp>FSBCLK</twComp></twPathDel><twLogDel>-6.970</twLogDel><twRouteDel>2.079</twRouteDel><twTotDel>-4.891</twTotDel></twClkPath></twConstOffIn></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";
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</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point OUTt (ILOGIC_X0Y5.D), 1 path
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</twPathRptBanner><twPathRpt anchorID="32"><twConstOffIn anchorID="33" twDataPathType="twDataPathMinDelay"><twSlack>5.307</twSlack><twSrc BELType="PAD">INt</twSrc><twDest BELType="FF">OUTt</twDest><twClkDel>-3.099</twClkDel><twClkSrc>CLKIN</twClkSrc><twClkDest>OUTt_OBUF</twClkDest><twOff>1.000</twOff><twOffSrc>INt</twOffSrc><twOffDest>CLKIN</twOffDest><twClkUncert fSysJit="0.050" fDCMJit="0.287" fPhaseErr="0.267" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.414</twClkUncert><twDataPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='PAD'>INt</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>2</twLogLvls><twSrcSite>M4.PAD</twSrcSite><twPathDel><twSite>M4.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.763</twDelInfo><twComp>INt</twComp><twBEL>INt</twBEL><twBEL>INt_IBUF</twBEL><twBEL>ProtoComp0.IMUX.2</twBEL></twPathDel><twPathDel><twSite>ILOGIC_X0Y5.D</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.229</twDelInfo><twComp>CPU_nAS_INt_AND_1_o_norst</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>ILOGIC_X0Y5.CLK0</twSite><twDelType>Tiockd</twDelType><twDelInfo twEdge="twRising">0.630</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>ProtoComp3.D2OFFBYP_SRC</twBEL><twBEL>OUTt</twBEL></twPathDel><twLogDel>1.393</twLogDel><twRouteDel>0.229</twRouteDel><twTotDel>1.622</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twDestClk><twPctLog>85.9</twPctLog><twPctRoute>14.1</twPctRoute></twDataPath><twClkPath maxSiteLen="20" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='PAD'>CLKIN</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>4</twLogLvls><twSrcSite>J4.PAD</twSrcSite><twPathDel><twSite>J4.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.367</twDelInfo><twComp>CLKIN</twComp><twBEL>CLKIN</twBEL><twBEL>instance_name/clkin1_buf</twBEL><twBEL>ProtoComp0.IMUX.3</twBEL></twPathDel><twPathDel><twSite>BUFIO2_X0Y23.I</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>instance_name/clkin1</twComp></twPathDel><twPathDel><twSite>BUFIO2_X0Y23.DIVCLK</twSite><twDelType>Tbufcko_DIVCLK</twDelType><twDelInfo twEdge="twRising">0.130</twDelInfo><twComp>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0</twComp><twBEL>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0</twBEL></twPathDel><twPathDel><twSite>PLL_ADV_X0Y1.CLKIN1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK</twComp></twPathDel><twPathDel><twSite>PLL_ADV_X0Y1.CLKOUT0</twSite><twDelType>Tpllcko_CLK</twDelType><twDelInfo twEdge="twRising">-5.738</twDelInfo><twComp>instance_name/pll_base_inst/PLL_ADV</twComp><twBEL>instance_name/pll_base_inst/PLL_ADV</twBEL></twPathDel><twPathDel><twSite>BUFGMUX_X3Y13.I0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.505</twDelInfo><twComp>instance_name/clkout0</twComp></twPathDel><twPathDel><twSite>BUFGMUX_X3Y13.O</twSite><twDelType>Tgi0o</twDelType><twDelInfo twEdge="twRising">0.063</twDelInfo><twComp>instance_name/clkout1_buf</twComp><twBEL>instance_name/clkout1_buf</twBEL></twPathDel><twPathDel><twSite>ILOGIC_X0Y5.CLK0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.574</twDelInfo><twComp>FSBCLK</twComp></twPathDel><twLogDel>-5.178</twLogDel><twRouteDel>2.079</twRouteDel><twTotDel>-3.099</twTotDel></twClkPath></twConstOffIn></twPathRpt></twConst><twConst anchorID="34" twConstType="OFFSETOUTDELAY" ><twConstHead uID="5"><twConstName UCFConstName="NET OUTt OFFSET = OUT 4ns AFTER CLKIN;" ScopeName="">COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN";</twConstName><twItemCnt>1</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinOff>1.412</twMinOff></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point OUTt (M3.PAD), 1 path
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</twPathRptBanner><twPathRpt anchorID="35"><twConstOffOut anchorID="36" twDataPathType="twDataPathMaxDelay"><twSlack>2.588</twSlack><twSrc BELType="FF">OUTt</twSrc><twDest BELType="PAD">OUTt</twDest><twClkDel>-5.070</twClkDel><twClkSrc>CLKIN</twClkSrc><twClkDest>OUTt_OBUF</twClkDest><twDataDel>6.068</twDataDel><twDataSrc>OUTt_OBUF</twDataSrc><twDataDest>OUTt</twDataDest><twOff>4.000</twOff><twOffSrc>CLKIN</twOffSrc><twOffDest>OUTt</twOffDest><twClkUncert fSysJit="0.050" fDCMJit="0.287" fPhaseErr="0.267" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.414</twClkUncert><twClkPath maxSiteLen="20" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='PAD'>CLKIN</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>4</twLogLvls><twSrcSite>J4.PAD</twSrcSite><twPathDel><twSite>J4.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">1.037</twDelInfo><twComp>CLKIN</twComp><twBEL>CLKIN</twBEL><twBEL>instance_name/clkin1_buf</twBEL><twBEL>ProtoComp0.IMUX.3</twBEL></twPathDel><twPathDel><twSite>BUFIO2_X0Y23.I</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>instance_name/clkin1</twComp></twPathDel><twPathDel><twSite>BUFIO2_X0Y23.DIVCLK</twSite><twDelType>Tbufcko_DIVCLK</twDelType><twDelInfo twEdge="twRising">0.190</twDelInfo><twComp>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0</twComp><twBEL>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0</twBEL></twPathDel><twPathDel><twSite>PLL_ADV_X0Y1.CLKIN1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK</twComp></twPathDel><twPathDel><twSite>PLL_ADV_X0Y1.CLKOUT0</twSite><twDelType>Tpllcko_CLK</twDelType><twDelInfo twEdge="twRising">-8.585</twDelInfo><twComp>instance_name/pll_base_inst/PLL_ADV</twComp><twBEL>instance_name/pll_base_inst/PLL_ADV</twBEL></twPathDel><twPathDel><twSite>BUFGMUX_X3Y13.I0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.505</twDelInfo><twComp>instance_name/clkout0</twComp></twPathDel><twPathDel><twSite>BUFGMUX_X3Y13.O</twSite><twDelType>Tgi0o</twDelType><twDelInfo twEdge="twRising">0.209</twDelInfo><twComp>instance_name/clkout1_buf</twComp><twBEL>instance_name/clkout1_buf</twBEL></twPathDel><twPathDel><twSite>ILOGIC_X0Y5.CLK0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.574</twDelInfo><twComp>FSBCLK</twComp></twPathDel><twLogDel>-7.149</twLogDel><twRouteDel>2.079</twRouteDel><twTotDel>-5.070</twTotDel></twClkPath><twDataPath maxSiteLen="14" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>OUTt</twSrc><twDest BELType='PAD'>OUTt</twDest><twLogLvls>1</twLogLvls><twSrcSite>ILOGIC_X0Y5.CLK0</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twSrcClk><twPathDel><twSite>ILOGIC_X0Y5.Q4</twSite><twDelType>Tickq</twDelType><twDelInfo twEdge="twRising">1.778</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>OUTt</twBEL></twPathDel><twPathDel><twSite>M3.O</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.308</twDelInfo><twComp>OUTt_OBUF</twComp></twPathDel><twPathDel><twSite>M3.PAD</twSite><twDelType>Tioop</twDelType><twDelInfo twEdge="twRising">1.982</twDelInfo><twComp>OUTt</twComp><twBEL>OUTt_OBUF</twBEL><twBEL>OUTt</twBEL></twPathDel><twLogDel>3.760</twLogDel><twRouteDel>2.308</twRouteDel><twTotDel>6.068</twTotDel><twPctLog>62.0</twPctLog><twPctRoute>38.0</twPctRoute></twDataPath></twConstOffOut></twPathRpt><twPathRptBanner sType="PathClass">Fastest Paths: COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN";
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</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point OUTt (M3.PAD), 1 path
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</twPathRptBanner><twPathRpt anchorID="37"><twConstOffOut anchorID="38" twDataPathType="twDataPathMinDelay"><twSlack>0.213</twSlack><twSrc BELType="FF">OUTt</twSrc><twDest BELType="PAD">OUTt</twDest><twClkDel>-3.036</twClkDel><twClkSrc>CLKIN</twClkSrc><twClkDest>OUTt_OBUF</twClkDest><twDataDel>3.663</twDataDel><twDataSrc>OUTt_OBUF</twDataSrc><twDataDest>OUTt</twDataDest><twOff>4.000</twOff><twOffSrc>CLKIN</twOffSrc><twOffDest>OUTt</twOffDest><twClkUncert fSysJit="0.050" fDCMJit="0.287" fPhaseErr="0.267" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.414</twClkUncert><twClkPath maxSiteLen="20" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='PAD'>CLKIN</twSrc><twDest BELType='FF'>OUTt</twDest><twLogLvls>4</twLogLvls><twSrcSite>J4.PAD</twSrcSite><twPathDel><twSite>J4.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.321</twDelInfo><twComp>CLKIN</twComp><twBEL>CLKIN</twBEL><twBEL>instance_name/clkin1_buf</twBEL><twBEL>ProtoComp0.IMUX.3</twBEL></twPathDel><twPathDel><twSite>BUFIO2_X0Y23.I</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>instance_name/clkin1</twComp></twPathDel><twPathDel><twSite>BUFIO2_X0Y23.DIVCLK</twSite><twDelType>Tbufcko_DIVCLK</twDelType><twDelInfo twEdge="twRising">0.122</twDelInfo><twComp>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0</twComp><twBEL>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0</twBEL></twPathDel><twPathDel><twSite>PLL_ADV_X0Y1.CLKIN1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK</twComp></twPathDel><twPathDel><twSite>PLL_ADV_X0Y1.CLKOUT0</twSite><twDelType>Tpllcko_CLK</twDelType><twDelInfo twEdge="twRising">-5.617</twDelInfo><twComp>instance_name/pll_base_inst/PLL_ADV</twComp><twBEL>instance_name/pll_base_inst/PLL_ADV</twBEL></twPathDel><twPathDel><twSite>BUFGMUX_X3Y13.I0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.505</twDelInfo><twComp>instance_name/clkout0</twComp></twPathDel><twPathDel><twSite>BUFGMUX_X3Y13.O</twSite><twDelType>Tgi0o</twDelType><twDelInfo twEdge="twRising">0.059</twDelInfo><twComp>instance_name/clkout1_buf</twComp><twBEL>instance_name/clkout1_buf</twBEL></twPathDel><twPathDel><twSite>ILOGIC_X0Y5.CLK0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.574</twDelInfo><twComp>FSBCLK</twComp></twPathDel><twLogDel>-5.115</twLogDel><twRouteDel>2.079</twRouteDel><twTotDel>-3.036</twTotDel></twClkPath><twDataPath maxSiteLen="14" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>OUTt</twSrc><twDest BELType='PAD'>OUTt</twDest><twLogLvls>1</twLogLvls><twSrcSite>ILOGIC_X0Y5.CLK0</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">FSBCLK</twSrcClk><twPathDel><twSite>ILOGIC_X0Y5.Q4</twSite><twDelType>Tickq</twDelType><twDelInfo twEdge="twRising">0.656</twDelInfo><twComp>OUTt_OBUF</twComp><twBEL>OUTt</twBEL></twPathDel><twPathDel><twSite>M3.O</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.308</twDelInfo><twComp>OUTt_OBUF</twComp></twPathDel><twPathDel><twSite>M3.PAD</twSite><twDelType>Tioop</twDelType><twDelInfo twEdge="twRising">0.699</twDelInfo><twComp>OUTt</twComp><twBEL>OUTt_OBUF</twBEL><twBEL>OUTt</twBEL></twPathDel><twLogDel>1.355</twLogDel><twRouteDel>2.308</twRouteDel><twTotDel>3.663</twTotDel><twPctLog>37.0</twPctLog><twPctRoute>63.0</twPctRoute></twDataPath></twConstOffOut></twPathRpt></twConst><twConstRollupTable uID="2" anchorID="39"><twConstRollup name="instance_name/clkin1" fullName="NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="5.000" actualRollup="5.332" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="instance_name/clkfbout" fullName="PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS " type="child" depth="1" requirement="20.000" prefType="period" actual="2.666" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="instance_name/clkout0" fullName="PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS " type="child" depth="1" requirement="10.000" prefType="period" actual="2.666" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="40">0</twUnmetConstCnt><twDataSheet anchorID="41" twNameLen="15"><twSUH2ClkList anchorID="42" twDestWidth="7" twPhaseWidth="6"><twDest>CLKIN</twDest><twSUH2Clk ><twSrc>CPU_nAS</twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">9.880</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-5.650</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>INt</twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">8.814</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.307</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2OutList anchorID="43" twDestWidth="4" twPhaseWidth="6"><twSrc>CLKIN</twSrc><twClk2Out twOutPad = "OUTt" twMinTime = "0.213" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "1.412" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twOffsetTables><twOffsetInTable anchorID="44" twDestWidth="7" twWorstWindow="4.230" twWorstSetup="9.880" twWorstHold="-5.650" twWorstSetupSlack="0.120" twWorstHoldSlack="6.650" ><twConstName>COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";</twConstName><twOffInTblRow ><twSrc>CPU_nAS</twSrc><twSUHSlackTime twSetupSlack = "0.120" twHoldSlack = "6.650" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">9.880</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-5.650</twH2ClkTime></twSUHSlackTime></twOffInTblRow></twOffsetInTable><twOffsetInTable anchorID="45" twDestWidth="3" twWorstWindow="4.507" twWorstSetup="8.814" twWorstHold="-4.307" twWorstSetupSlack="1.186" twWorstHoldSlack="5.307" ><twConstName>COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";</twConstName><twOffInTblRow ><twSrc>INt</twSrc><twSUHSlackTime twSetupSlack = "1.186" twHoldSlack = "5.307" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">8.814</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.307</twH2ClkTime></twSUHSlackTime></twOffInTblRow></twOffsetInTable><twOffsetOutTable anchorID="46" twDestWidth="4" twMinSlack="2.588" twMaxSlack="2.588" twRelSkew="0.000" ><twConstName>COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN";</twConstName><twOffOutTblRow twOutPad = "OUTt" twSlack = "1.412" twMaxDelayCrnr="f" twMinDelay = "0.213" twMinDelayCrnr="t" twRelSkew = "0.000" ></twOffOutTblRow></twOffsetOutTable></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="47"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>3</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>12</twConnCnt></twConstCov><twStats anchorID="48"><twMinPer>5.000</twMinPer><twFootnote number="1" /><twMaxFreq>200.000</twMaxFreq><twMinInBeforeClk>9.880</twMinInBeforeClk><twMinOutAfterClk>1.412</twMinOutAfterClk></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Fri Oct 29 10:25:28 2021 </twTimestamp></twFoot><twClientInfo anchorID="49"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
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Peak Memory Usage: 167 MB
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</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
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