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https://github.com/garrettsworkshop/Warp-LC.git
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246 lines
12 KiB
Plaintext
246 lines
12 KiB
Plaintext
Release 14.7 par P.20131013 (nt)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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ZANEPC:: Fri Oct 29 10:03:03 2021
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par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
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Constraints file: WarpLC.pcf.
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Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
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"WarpLC" is an NCD, version 3.2, device xc6slx9, package ftg256, speed -2
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vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
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INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
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INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
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'C:\ispLEVER_Classic2_0\license\license.dat;C:\lscc\diamond\3.12\license\license.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'.
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INFO:Security:54 - 'xc6slx9' is a WebPack part.
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INFO:Security:66 - Your license for 'ISE' is for evaluation use only.
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WARNING:Security:43 - No license file was found in the standard Xilinx license directory.
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WARNING:Security:44 - Since no license file was found,
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please run the Xilinx License Configuration Manager
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(xlcm or "Manage Xilinx Licenses")
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to assist in obtaining a license.
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WARNING:Security:40 - Your license for 'ISE' expires in 4 days.
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----------------------------------------------------------------------
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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Device speed data version: "PRODUCTION 1.23 2013-10-13".
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Device Utilization Summary:
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Slice Logic Utilization:
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Number of Slice Registers: 56 out of 11,440 1%
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Number used as Flip Flops: 56
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 59 out of 5,720 1%
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Number used as logic: 56 out of 5,720 1%
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Number using O6 output only: 24
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Number using O5 output only: 29
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Number using O5 and O6: 3
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Number used as ROM: 0
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Number used as Memory: 0 out of 1,440 0%
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Number used exclusively as route-thrus: 3
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Number with same-slice register load: 2
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Number with same-slice carry load: 1
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Number with other load: 0
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Slice Logic Distribution:
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Number of occupied Slices: 25 out of 1,430 1%
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Number of MUXCYs used: 56 out of 2,860 1%
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Number of LUT Flip Flop pairs used: 76
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Number with an unused Flip Flop: 22 out of 76 28%
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Number with an unused LUT: 17 out of 76 22%
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Number of fully used LUT-FF pairs: 37 out of 76 48%
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Number of slice register sites lost
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to control set restrictions: 0 out of 11,440 0%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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Number of bonded IOBs: 49 out of 186 26%
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IOB Flip Flops: 5
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IOB Latches: 1
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Specific Feature Utilization:
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Number of RAMB16BWERs: 0 out of 32 0%
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Number of RAMB8BWERs: 0 out of 64 0%
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Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
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Number used as BUFIO2s: 1
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Number used as BUFIO2_2CLKs: 0
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Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
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Number used as BUFIO2FBs: 1
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Number used as BUFIO2FB_2CLKs: 0
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Number of BUFG/BUFGMUXs: 3 out of 16 18%
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Number used as BUFGs: 3
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Number used as BUFGMUX: 0
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Number of DCM/DCM_CLKGENs: 0 out of 4 0%
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Number of ILOGIC2/ISERDES2s: 1 out of 200 1%
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Number used as ILOGIC2s: 1
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Number used as ISERDES2s: 0
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Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
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Number of OLOGIC2/OSERDES2s: 5 out of 200 2%
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Number used as OLOGIC2s: 5
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Number used as OSERDES2s: 0
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHs: 0 out of 128 0%
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Number of BUFPLLs: 0 out of 8 0%
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Number of BUFPLL_MCBs: 0 out of 4 0%
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Number of DSP48A1s: 0 out of 16 0%
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Number of ICAPs: 0 out of 1 0%
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Number of MCBs: 0 out of 2 0%
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Number of PCILOGICSEs: 0 out of 2 0%
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Number of PLL_ADVs: 1 out of 2 50%
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Number of PMVs: 0 out of 1 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of SUSPEND_SYNCs: 0 out of 1 0%
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Overall effort level (-ol): High
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Router effort level (-rl): High
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Starting initial Timing Analysis. REAL time: 2 secs
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Finished initial Timing Analysis. REAL time: 2 secs
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Starting Router
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Phase 1 : 315 unrouted; REAL time: 2 secs
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Phase 2 : 228 unrouted; REAL time: 2 secs
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Phase 3 : 98 unrouted; REAL time: 2 secs
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Phase 4 : 98 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
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Updating file: WarpLC.ncd with current fully routed design.
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Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
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Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
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Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
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Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
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Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
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Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs
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Total REAL time to Router completion: 2 secs
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Total CPU time to Router completion: 2 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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|instance_name/clkfb_ | | | | | |
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| bufg_out | BUFGMUX_X2Y3| No | 2 | 0.000 | 2.163 |
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+---------------------+--------------+------+------+------------+-------------+
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| CPUCLKi | BUFGMUX_X3Y13| No | 3 | 0.633 | 2.069 |
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+---------------------+--------------+------+------+------------+-------------+
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| FSBCLK | BUFGMUX_X2Y2| No | 21 | 0.728 | 2.163 |
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+---------------------+--------------+------+------+------------+-------------+
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| LE | Local| | 2 | 0.000 | 0.979 |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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* The fanout is the number of component pins not the individual BEL loads,
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for example SLICE loads not FF loads.
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Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
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Number of Timing Constraints that were not applied: 2
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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PERIOD analysis for net "instance_name/cl | SETUP | 1.459ns| 7.082ns| 0| 0
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kout1" derived from NET "instance_name/c | HOLD | 4.848ns| | 0| 0
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lkin1" PERIOD = 20 ns HIGH 50% | | | | |
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----------------------------------------------------------------------------------------------------------
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PERIOD analysis for net "instance_name/cl | SETUP | 5.303ns| 4.697ns| 0| 0
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kout0" derived from NET "instance_name/c | HOLD | 0.414ns| | 0| 0
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lkin1" PERIOD = 20 ns HIGH 50% | | | | |
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----------------------------------------------------------------------------------------------------------
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NET "instance_name/clkin1" PERIOD = 20 ns | MINLOWPULSE | 15.000ns| 5.000ns| 0| 0
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HIGH 50% | | | | |
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----------------------------------------------------------------------------------------------------------
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PERIOD analysis for net "instance_name/cl | MINPERIOD | 17.334ns| 2.666ns| 0| 0
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kfbout" derived from NET "instance_name/ | | | | |
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clkin1" PERIOD = 20 ns HIGH 50% | | | | |
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----------------------------------------------------------------------------------------------------------
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Derived Constraint Report
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Review Timing Report for more details on the following derived constraints.
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To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
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or "Run Timing Analysis" from Timing Analyzer (timingan).
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Derived Constraints for instance_name/clkin1
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+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
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| | Period | Actual Period | Timing Errors | Paths Analyzed |
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| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
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| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
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+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
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|instance_name/clkin1 | 20.000ns| 5.000ns| 14.164ns| 0| 0| 0| 57|
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| instance_name/clkfbout | 20.000ns| 2.666ns| N/A| 0| 0| 0| 0|
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| instance_name/clkout1 | 10.000ns| 7.082ns| N/A| 0| 0| 3| 0|
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| instance_name/clkout0 | 10.000ns| 4.697ns| N/A| 0| 0| 54| 0|
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+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
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All constraints were met.
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 2 secs
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Total CPU time to PAR completion: 2 secs
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Peak Memory Usage: 256 MB
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Timing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 0
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Number of info messages: 0
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Writing design to file WarpLC.ncd
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PAR done!
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