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550 lines
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HTML
550 lines
16 KiB
HTML
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
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<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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<center><big><big><b>System Settings</b></big></big></center><br>
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<A NAME="Environment Settings"></A>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
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</tr>
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<tr bgcolor='#ffff99'>
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<td><b>Environment Variable</b></td>
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<td><b>xst</b></td>
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<td><b>ngdbuild</b></td>
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<td><b>map</b></td>
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<td><b>par</b></td>
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</tr>
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<tr>
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<td>PATHEXT</td>
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<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
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<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
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<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
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<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
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</tr>
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<tr>
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<td>Path</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
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</tr>
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<tr>
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<td>XILINX</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
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</tr>
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<tr>
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<td>XILINX_DSP</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
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<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
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</tr>
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<tr>
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<td>XILINX_EDK</td>
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<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
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<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
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<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
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<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
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</tr>
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<tr>
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<td>XILINX_PLANAHEAD</td>
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<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
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<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
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<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
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<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
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</tr>
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</TABLE>
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<A NAME="Synthesis Property Settings"></A>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
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</tr>
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<tr bgcolor='#ffff99'>
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<td><b>Switch Name</b></td>
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<td><b>Property Name</b></td>
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<td><b>Value</b></td>
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<td><b>Default Value</b></td>
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</tr>
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<tr>
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<td>-ifn</td>
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<td> </td>
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<td>WarpLC.prj</td>
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<td> </td>
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</tr>
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<tr>
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<td>-ofn</td>
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<td> </td>
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<td>WarpLC</td>
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<td> </td>
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</tr>
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<tr>
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<td>-ofmt</td>
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<td> </td>
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<td>NGC</td>
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<td>NGC</td>
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</tr>
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<tr>
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<td>-p</td>
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<td> </td>
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<td>xc6slx9-2-ftg256</td>
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<td> </td>
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</tr>
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<tr>
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<td>-top</td>
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<td> </td>
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<td>WarpLC</td>
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<td> </td>
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</tr>
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<tr>
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<td>-opt_mode</td>
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<td>Optimization Goal</td>
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<td>Speed</td>
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<td>Speed</td>
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</tr>
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<tr>
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<td>-opt_level</td>
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<td>Optimization Effort</td>
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<td>1</td>
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<td>1</td>
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</tr>
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<tr>
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<td>-power</td>
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<td>Power Reduction</td>
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<td>NO</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-iuc</td>
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<td>Use synthesis Constraints File</td>
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<td>NO</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-keep_hierarchy</td>
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<td>Keep Hierarchy</td>
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<td>No</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-netlist_hierarchy</td>
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<td>Netlist Hierarchy</td>
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<td>As_Optimized</td>
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<td>As_Optimized</td>
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</tr>
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<tr>
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<td>-rtlview</td>
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<td>Generate RTL Schematic</td>
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<td>Yes</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-glob_opt</td>
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<td>Global Optimization Goal</td>
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<td>AllClockNets</td>
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<td>AllClockNets</td>
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</tr>
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<tr>
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<td>-read_cores</td>
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<td>Read Cores</td>
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<td>YES</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-sd</td>
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<td>Cores Search Directories</td>
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<td>{"ipcore_dir" }</td>
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<td> </td>
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</tr>
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<tr>
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<td>-write_timing_constraints</td>
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<td>Write Timing Constraints</td>
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<td>NO</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-cross_clock_analysis</td>
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<td>Cross Clock Analysis</td>
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<td>NO</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-bus_delimiter</td>
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<td>Bus Delimiter</td>
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<td><></td>
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<td><></td>
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</tr>
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<tr>
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<td>-slice_utilization_ratio</td>
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<td>Slice Utilization Ratio</td>
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<td>100</td>
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<td>100</td>
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</tr>
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<tr>
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<td>-bram_utilization_ratio</td>
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<td>BRAM Utilization Ratio</td>
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<td>100</td>
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<td>100</td>
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</tr>
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<tr>
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<td>-dsp_utilization_ratio</td>
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<td>DSP Utilization Ratio</td>
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<td>100</td>
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<td>100</td>
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</tr>
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<tr>
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<td>-reduce_control_sets</td>
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<td> </td>
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<td>Auto</td>
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<td>Auto</td>
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</tr>
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<tr>
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<td>-fsm_extract</td>
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<td> </td>
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<td>YES</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-fsm_encoding</td>
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<td> </td>
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<td>Auto</td>
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<td>Auto</td>
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</tr>
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<tr>
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<td>-safe_implementation</td>
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<td> </td>
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<td>No</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-fsm_style</td>
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<td> </td>
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<td>LUT</td>
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<td>LUT</td>
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</tr>
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<tr>
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<td>-ram_extract</td>
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<td> </td>
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<td>Yes</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-ram_style</td>
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<td> </td>
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<td>Auto</td>
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<td>Auto</td>
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</tr>
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<tr>
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<td>-rom_extract</td>
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<td> </td>
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<td>Yes</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-shreg_extract</td>
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<td> </td>
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<td>YES</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-rom_style</td>
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<td> </td>
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<td>Auto</td>
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<td>Auto</td>
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</tr>
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<tr>
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<td>-auto_bram_packing</td>
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<td> </td>
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<td>NO</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-resource_sharing</td>
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<td> </td>
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<td>YES</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-async_to_sync</td>
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<td> </td>
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<td>NO</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-use_dsp48</td>
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<td> </td>
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<td>Auto</td>
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<td>Auto</td>
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</tr>
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<tr>
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<td>-iobuf</td>
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<td> </td>
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<td>YES</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-max_fanout</td>
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<td> </td>
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<td>100000</td>
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<td>100000</td>
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</tr>
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<tr>
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<td>-bufg</td>
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<td> </td>
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<td>16</td>
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<td>16</td>
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</tr>
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<tr>
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<td>-register_duplication</td>
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<td> </td>
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<td>YES</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-register_balancing</td>
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<td> </td>
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<td>No</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-optimize_primitives</td>
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<td> </td>
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<td>NO</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-use_clock_enable</td>
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<td> </td>
|
|
<td>Auto</td>
|
|
<td>Auto</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-use_sync_set</td>
|
|
<td> </td>
|
|
<td>Auto</td>
|
|
<td>Auto</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-use_sync_reset</td>
|
|
<td> </td>
|
|
<td>Auto</td>
|
|
<td>Auto</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-iob</td>
|
|
<td> </td>
|
|
<td>Auto</td>
|
|
<td>Auto</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-equivalent_register_removal</td>
|
|
<td> </td>
|
|
<td>YES</td>
|
|
<td>Yes</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-slice_utilization_ratio_maxmargin</td>
|
|
<td> </td>
|
|
<td>5</td>
|
|
<td>0</td>
|
|
</tr>
|
|
</TABLE>
|
|
<A NAME="Translation Property Settings"></A>
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
|
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
|
|
</tr>
|
|
<tr bgcolor='#ffff99'>
|
|
<td><b>Switch Name</b></td>
|
|
<td><b>Property Name</b></td>
|
|
<td><b>Value</b></td>
|
|
<td><b>Default Value</b></td>
|
|
</tr>
|
|
<tr>
|
|
<td>-intstyle</td>
|
|
<td> </td>
|
|
<td>ise</td>
|
|
<td>None</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-dd</td>
|
|
<td> </td>
|
|
<td>_ngo</td>
|
|
<td>None</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-p</td>
|
|
<td> </td>
|
|
<td>xc6slx9-ftg256-2</td>
|
|
<td>None</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-sd</td>
|
|
<td>Macro Search Path</td>
|
|
<td>ipcore_dir</td>
|
|
<td>None</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-uc</td>
|
|
<td> </td>
|
|
<td>PLL.ucf</td>
|
|
<td>None</td>
|
|
</tr>
|
|
</TABLE>
|
|
<A NAME="Map Property Settings"></A>
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
|
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
|
|
</tr>
|
|
<tr bgcolor='#ffff99'>
|
|
<td><b>Switch Name</b></td>
|
|
<td><b>Property Name</b></td>
|
|
<td><b>Value</b></td>
|
|
<td><b>Default Value</b></td>
|
|
</tr>
|
|
<tr>
|
|
<td>-ol</td>
|
|
<td>Place & Route Effort Level (Overall)</td>
|
|
<td>high</td>
|
|
<td>high</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-xt</td>
|
|
<td>Extra Cost Tables</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-ir</td>
|
|
<td>Use RLOC Constraints</td>
|
|
<td>OFF</td>
|
|
<td>OFF</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-t</td>
|
|
<td>Starting Placer Cost Table (1-100) Map</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-r</td>
|
|
<td>Register Ordering</td>
|
|
<td>4</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-intstyle</td>
|
|
<td> </td>
|
|
<td>ise</td>
|
|
<td>None</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-lc</td>
|
|
<td>LUT Combining</td>
|
|
<td>off</td>
|
|
<td>off</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-o</td>
|
|
<td> </td>
|
|
<td>WarpLC_map.ncd</td>
|
|
<td>None</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-w</td>
|
|
<td> </td>
|
|
<td>true</td>
|
|
<td>false</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-pr</td>
|
|
<td>Pack I/O Registers/Latches into IOBs</td>
|
|
<td>off</td>
|
|
<td>off</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-p</td>
|
|
<td> </td>
|
|
<td>xc6slx9-ftg256-2</td>
|
|
<td>None</td>
|
|
</tr>
|
|
</TABLE>
|
|
<A NAME="Place and Route Property Settings"></A>
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
|
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
|
|
</tr>
|
|
<tr bgcolor='#ffff99'>
|
|
<td><b>Switch Name</b></td>
|
|
<td><b>Property Name</b></td>
|
|
<td><b>Value</b></td>
|
|
<td><b>Default Value</b></td>
|
|
</tr>
|
|
<tr>
|
|
<td>-intstyle</td>
|
|
<td> </td>
|
|
<td>ise</td>
|
|
<td> </td>
|
|
</tr>
|
|
<tr>
|
|
<td>-mt</td>
|
|
<td>Enable Multi-Threading</td>
|
|
<td>off</td>
|
|
<td>off</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-ol</td>
|
|
<td>Place & Route Effort Level (Overall)</td>
|
|
<td>high</td>
|
|
<td>std</td>
|
|
</tr>
|
|
<tr>
|
|
<td>-w</td>
|
|
<td> </td>
|
|
<td>true</td>
|
|
<td>false</td>
|
|
</tr>
|
|
</TABLE>
|
|
<A NAME="Operating System Information"></A>
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
|
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
|
|
</tr>
|
|
<tr bgcolor='#ffff99'>
|
|
<td><b>Operating System Information</b></td>
|
|
<td><b>xst</b></td>
|
|
<td><b>ngdbuild</b></td>
|
|
<td><b>map</b></td>
|
|
<td><b>par</b></td>
|
|
</tr>
|
|
<tr>
|
|
<td>CPU Architecture/Speed</td>
|
|
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
|
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
|
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
|
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
|
</tr>
|
|
<tr>
|
|
<td>Host</td>
|
|
<td>ZanePC</td>
|
|
<td>ZanePC</td>
|
|
<td>ZanePC</td>
|
|
<td>ZanePC</td>
|
|
</tr>
|
|
<tr>
|
|
<td>OS Name</td>
|
|
<td>Microsoft , 64-bit</td>
|
|
<td>Microsoft , 64-bit</td>
|
|
<td>Microsoft , 64-bit</td>
|
|
<td>Microsoft , 64-bit</td>
|
|
</tr>
|
|
<tr>
|
|
<td>OS Release</td>
|
|
<td>major release (build 9200)</td>
|
|
<td>major release (build 9200)</td>
|
|
<td>major release (build 9200)</td>
|
|
<td>major release (build 9200)</td>
|
|
</tr>
|
|
</TABLE>
|
|
</BODY> </HTML> |