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Warp-LC/fpga/WarpLC_map.map
Zane Kaminski 8c91d823f7 screwing around
2021-10-29 10:04:15 -04:00

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Release 14.7 Map P.20131013 (nt)
Xilinx Map Application Log File for Design 'WarpLC'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
Target Device : xc6slx9
Target Package : ftg256
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Oct 29 10:02:57 2021
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'C:\ispLEVER_Classic2_0\license\license.dat;C:\lscc\diamond\3.12\license\license
.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'.
INFO:Security:54 - 'xc6slx9' is a WebPack part.
INFO:Security:66 - Your license for 'ISE' is for evaluation use only.
WARNING:Security:43 - No license file was found in the standard Xilinx license
directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:40 - Your license for 'ISE' expires in 4 days.
----------------------------------------------------------------------
Mapping design into LUTs...
WARNING:MapLib:53 - The offset specification "OFFSET=IN 10000 pS VALID 11000 pS
BEFORE FSBCLK" has been discarded because the referenced clock pad net
(FSBCLK) was optimized away.
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 2 secs
Total CPU time at the beginning of Placer: 2 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:67ca) REAL time: 2 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:67ca) REAL time: 2 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:67ca) REAL time: 2 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
......
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:2cdc04b) REAL time: 3 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:2cdc04b) REAL time: 3 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:2cdc04b) REAL time: 3 secs
Phase 7.3 Local Placement Optimization
....
Phase 7.3 Local Placement Optimization (Checksum:c5a22b64) REAL time: 3 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:c5a22b64) REAL time: 3 secs
Phase 9.8 Global Placement
..
................
..
Phase 9.8 Global Placement (Checksum:3e86b47) REAL time: 3 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:3e86b47) REAL time: 3 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:8081ee) REAL time: 4 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:8081ee) REAL time: 4 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:8081ee) REAL time: 4 secs
Total REAL time to Placer completion: 4 secs
Total CPU time to Placer completion: 4 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 1
Slice Logic Utilization:
Number of Slice Registers: 56 out of 11,440 1%
Number used as Flip Flops: 56
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 59 out of 5,720 1%
Number used as logic: 56 out of 5,720 1%
Number using O6 output only: 24
Number using O5 output only: 29
Number using O5 and O6: 3
Number used as ROM: 0
Number used as Memory: 0 out of 1,440 0%
Number used exclusively as route-thrus: 3
Number with same-slice register load: 2
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 25 out of 1,430 1%
Number of MUXCYs used: 56 out of 2,860 1%
Number of LUT Flip Flop pairs used: 76
Number with an unused Flip Flop: 22 out of 76 28%
Number with an unused LUT: 17 out of 76 22%
Number of fully used LUT-FF pairs: 37 out of 76 48%
Number of unique control sets: 4
Number of slice register sites lost
to control set restrictions: 16 out of 11,440 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 49 out of 186 26%
IOB Flip Flops: 5
IOB Latches: 1
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 1 out of 200 1%
Number used as ILOGIC2s: 1
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 5 out of 200 2%
Number used as OLOGIC2s: 5
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 16 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 2 50%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 2.16
Peak Memory Usage: 272 MB
Total REAL time to MAP completion: 4 secs
Total CPU time to MAP completion: 4 secs
Mapping completed.
See MAP report file "WarpLC_map.mrp" for details.
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