mirror of
https://github.com/garrettsworkshop/Warp-LC.git
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161 lines
9.1 KiB
Plaintext
161 lines
9.1 KiB
Plaintext
--------------------------------------------------------------------------------
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Release 14.7 Trace (nt)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
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3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr
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WarpLC.pcf -ucf PLL.ucf
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Design file: WarpLC_map.ncd
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Physical constraint file: WarpLC.pcf
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Device,package,speed: xc6slx9,ftg256,C,-2 (PRODUCTION 1.23 2013-10-13)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3284 - This timing report was generated using estimated delay
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information. For accurate numbers, please refer to the post Place and Route
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timing report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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Data Sheet report:
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-----------------
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All values displayed in nanoseconds (ns)
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Setup/Hold to clock CLKIN
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------------+------------+------------+------------+------------+------------------+--------+
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|Max Setup to| Process |Max Hold to | Process | | Clock |
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Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
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------------+------------+------------+------------+------------+------------------+--------+
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FSB_A<0> | 13.023(R)| SLOW | -7.585(R)| FAST |FSBCLK | 0.000|
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FSB_A<1> | 12.884(R)| SLOW | -7.431(R)| FAST |FSBCLK | 0.000|
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FSB_A<2> | 12.631(R)| SLOW | -7.394(R)| FAST |FSBCLK | 0.000|
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FSB_A<3> | 12.641(R)| SLOW | -7.409(R)| FAST |FSBCLK | 0.000|
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FSB_A<4> | 12.880(R)| SLOW | -7.561(R)| FAST |FSBCLK | 0.000|
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FSB_A<5> | 12.741(R)| SLOW | -7.407(R)| FAST |FSBCLK | 0.000|
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FSB_A<6> | 12.296(R)| SLOW | -7.155(R)| FAST |FSBCLK | 0.000|
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FSB_A<7> | 12.306(R)| SLOW | -7.170(R)| FAST |FSBCLK | 0.000|
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FSB_A<8> | 12.539(R)| SLOW | -7.316(R)| FAST |FSBCLK | 0.000|
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FSB_A<9> | 12.400(R)| SLOW | -7.162(R)| FAST |FSBCLK | 0.000|
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FSB_A<10> | 11.961(R)| SLOW | -6.916(R)| FAST |FSBCLK | 0.000|
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FSB_A<11> | 12.140(R)| SLOW | -7.100(R)| FAST |FSBCLK | 0.000|
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FSB_A<12> | 11.370(R)| SLOW | -6.243(R)| FAST |FSBCLK | 0.000|
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FSB_A<13> | 11.798(R)| SLOW | -6.633(R)| FAST |FSBCLK | 0.000|
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FSB_A<14> | 11.760(R)| SLOW | -6.788(R)| FAST |FSBCLK | 0.000|
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FSB_A<15> | 11.233(R)| SLOW | -6.266(R)| FAST |FSBCLK | 0.000|
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FSB_A<16> | 11.974(R)| SLOW | -6.920(R)| FAST |FSBCLK | 0.000|
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FSB_A<17> | 11.982(R)| SLOW | -6.936(R)| FAST |FSBCLK | 0.000|
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FSB_A<18> | 11.664(R)| SLOW | -6.788(R)| FAST |FSBCLK | 0.000|
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FSB_A<19> | 11.544(R)| SLOW | -6.696(R)| FAST |FSBCLK | 0.000|
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FSB_A<20> | 11.618(R)| SLOW | -6.683(R)| FAST |FSBCLK | 0.000|
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FSB_A<21> | 11.622(R)| SLOW | -6.672(R)| FAST |FSBCLK | 0.000|
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FSB_A<22> | 11.438(R)| SLOW | -6.681(R)| FAST |FSBCLK | 0.000|
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FSB_A<23> | 11.192(R)| SLOW | -6.440(R)| FAST |FSBCLK | 0.000|
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FSB_A<24> | 11.518(R)| SLOW | -6.679(R)| FAST |FSBCLK | 0.000|
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FSB_A<25> | 11.768(R)| SLOW | -6.914(R)| FAST |FSBCLK | 0.000|
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FSB_A<26> | 11.702(R)| SLOW | -7.041(R)| FAST |FSBCLK | 0.000|
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FSB_A<27> | 11.630(R)| SLOW | -6.974(R)| FAST |FSBCLK | 0.000|
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FSB_A<28> | 11.573(R)| SLOW | -6.971(R)| FAST |FSBCLK | 0.000|
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FSB_A<29> | 11.565(R)| SLOW | -6.929(R)| FAST |FSBCLK | 0.000|
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FSB_A<30> | 11.495(R)| SLOW | -7.056(R)| FAST |FSBCLK | 0.000|
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FSB_A<31> | 11.352(R)| SLOW | -6.975(R)| FAST |FSBCLK | 0.000|
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------------+------------+------------+------------+------------+------------------+--------+
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Clock CLKIN to Pad
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------------+-----------------+------------+-----------------+------------+----------------------------+--------+
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|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
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Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
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------------+-----------------+------------+-----------------+------------+----------------------------+--------+
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CLKFB_OUT | -0.063(R)| FAST | -0.086(R)| SLOW |instance_name/clkfb_bufg_out| 0.000|
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| -0.057(F)| FAST | -0.086(F)| SLOW |instance_name/clkfb_bufg_out| 0.000|
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CPUCLK | -0.151(R)| FAST | -0.159(R)| SLOW |CPUCLKi | 0.000|
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CPU_nDSACK | 2.827(R)| FAST | 2.128(R)| SLOW |FSBCLK | 0.000|
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CPU_nSTERM | 1.831(R)| FAST | 1.400(R)| SLOW |FSBCLK | 0.000|
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RAM_CLK01 | -0.063(R)| FAST | -0.086(R)| SLOW |FSBCLK | 0.000|
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| -0.057(F)| FAST | -0.086(F)| SLOW |FSBCLK | 0.000|
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nFPUCS | 2.114(R)| FAST | 1.715(R)| SLOW |CPUCLKi | 0.000|
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------------+-----------------+------------+-----------------+------------+----------------------------+--------+
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Clock to Setup on destination clock CLKIN
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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CLKIN | 2.278| 3.404| 1.399| |
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---------------+---------+---------+---------+---------+
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Pad to Pad
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---------------+---------------+---------+
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Source Pad |Destination Pad| Delay |
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---------------+---------------+---------+
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CPU_nAS |nFPUCS | 9.241|
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FSB_A<0> |CPU_nDSACK | 11.438|
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FSB_A<1> |CPU_nDSACK | 11.056|
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FSB_A<2> |CPU_nDSACK | 10.934|
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FSB_A<3> |CPU_nDSACK | 11.272|
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FSB_A<4> |CPU_nDSACK | 10.959|
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FSB_A<5> |CPU_nDSACK | 10.647|
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FSB_A<6> |CPU_nDSACK | 11.009|
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FSB_A<7> |CPU_nDSACK | 10.884|
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FSB_A<8> |CPU_nDSACK | 10.427|
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FSB_A<9> |CPU_nDSACK | 10.796|
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FSB_A<10> |CPU_nDSACK | 10.296|
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FSB_A<11> |CPU_nDSACK | 9.984|
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FSB_A<12> |CPU_nDSACK | 10.429|
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FSB_A<13> |CPU_nDSACK | 10.457|
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FSB_A<13> |nFPUCS | 10.825|
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FSB_A<14> |CPU_nDSACK | 10.376|
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FSB_A<14> |nFPUCS | 11.030|
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FSB_A<15> |CPU_nDSACK | 10.288|
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FSB_A<15> |nFPUCS | 11.487|
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FSB_A<16> |CPU_nDSACK | 10.253|
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FSB_A<16> |nFPUCS | 12.145|
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FSB_A<17> |CPU_nDSACK | 9.855|
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FSB_A<17> |nFPUCS | 11.537|
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FSB_A<18> |CPU_nDSACK | 10.759|
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FSB_A<18> |nFPUCS | 10.887|
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FSB_A<19> |CPU_nDSACK | 10.601|
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FSB_A<19> |nFPUCS | 10.945|
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FSB_A<20> |CPU_nDSACK | 9.890|
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FSB_A<21> |CPU_nDSACK | 10.054|
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FSB_A<22> |CPU_nDSACK | 10.300|
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FSB_A<23> |CPU_nDSACK | 10.098|
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FSB_A<24> |CPU_nDSACK | 10.551|
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FSB_A<25> |CPU_nDSACK | 10.797|
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FSB_A<26> |CPU_nDSACK | 10.476|
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FSB_A<27> |CPU_nDSACK | 10.851|
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FSB_A<28> |CPU_nDSACK | 11.005|
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FSB_A<29> |CPU_nDSACK | 10.668|
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FSB_A<30> |CPU_nDSACK | 10.761|
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FSB_A<31> |CPU_nDSACK | 10.776|
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FSB_FC<0> |nFPUCS | 11.389|
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FSB_FC<1> |nFPUCS | 10.227|
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FSB_FC<2> |nFPUCS | 11.232|
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---------------+---------------+---------+
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Analysis completed Fri Oct 29 08:28:45 2021
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--------------------------------------------------------------------------------
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Trace Settings:
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-------------------------
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Trace Settings
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Peak Memory Usage: 167 MB
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