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Warp-LC/fpga/WarpLC_preroute.twr
Zane Kaminski 32019a34ee More cache stuff
2021-11-02 00:38:46 -04:00

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--------------------------------------------------------------------------------
Release 14.7 Trace (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr
WarpLC.pcf -ucf PLL.ucf
Design file: WarpLC_map.ncd
Physical constraint file: WarpLC.pcf
Device,package,speed: xc6slx9,ftg256,C,-2 (PRODUCTION 1.23 2013-10-13)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock CLKIN
------------+------------+------------+------------+------------+------------------+--------+
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
------------+------------+------------+------------+------------+------------------+--------+
FSB_A<2> | 11.357(R)| SLOW | -7.515(R)| FAST |FSBCLK | 0.000|
FSB_A<3> | 11.438(R)| SLOW | -7.483(R)| FAST |FSBCLK | 0.000|
FSB_A<4> | 11.226(R)| SLOW | -7.369(R)| FAST |FSBCLK | 0.000|
FSB_A<5> | 11.134(R)| SLOW | -7.184(R)| FAST |FSBCLK | 0.000|
FSB_A<6> | 11.218(R)| SLOW | -7.413(R)| FAST |FSBCLK | 0.000|
FSB_A<7> | 11.126(R)| SLOW | -7.249(R)| FAST |FSBCLK | 0.000|
FSB_A<8> | 11.001(R)| SLOW | -7.261(R)| FAST |FSBCLK | 0.000|
------------+------------+------------+------------+------------+------------------+--------+
Clock CLKIN to Pad
------------+-----------------+------------+-----------------+------------+---------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+---------------------+--------+
CLKFB_OUT | -0.063(R)| FAST | -0.086(R)| SLOW |cg/pll/clkfb_bufg_out| 0.000|
| -0.057(F)| FAST | -0.086(F)| SLOW |cg/pll/clkfb_bufg_out| 0.000|
CPUCLK | -0.063(R)| FAST | -0.086(R)| SLOW |FSBCLK | 0.000|
CPU_nSTERM | 3.670(R)| SLOW | 2.355(R)| FAST |FSBCLK | 0.000|
FPUCLK | -0.063(R)| FAST | -0.086(R)| SLOW |FSBCLK | 0.000|
FSB_D<0> | 5.995(R)| SLOW | 3.244(R)| FAST |FSBCLK | 0.000|
FSB_D<1> | 6.126(R)| SLOW | 3.390(R)| SLOW |FSBCLK | 0.000|
FSB_D<2> | 6.440(R)| SLOW | 3.181(R)| FAST |FSBCLK | 0.000|
FSB_D<3> | 6.008(R)| SLOW | 3.333(R)| FAST |FSBCLK | 0.000|
FSB_D<4> | 5.920(R)| SLOW | 3.276(R)| FAST |FSBCLK | 0.000|
FSB_D<5> | 5.841(R)| SLOW | 2.948(R)| FAST |FSBCLK | 0.000|
FSB_D<6> | 5.753(R)| SLOW | 2.891(R)| FAST |FSBCLK | 0.000|
FSB_D<7> | 5.937(R)| SLOW | 2.709(R)| FAST |FSBCLK | 0.000|
FSB_D<8> | 5.259(R)| SLOW | 2.621(R)| FAST |FSBCLK | 0.000|
FSB_D<9> | 5.550(R)| SLOW | 2.945(R)| SLOW |FSBCLK | 0.000|
FSB_D<10> | 5.510(R)| SLOW | 2.838(R)| FAST |FSBCLK | 0.000|
FSB_D<11> | 5.669(R)| SLOW | 3.028(R)| FAST |FSBCLK | 0.000|
FSB_D<12> | 5.696(R)| SLOW | 2.934(R)| FAST |FSBCLK | 0.000|
FSB_D<13> | 5.745(R)| SLOW | 3.334(R)| FAST |FSBCLK | 0.000|
FSB_D<14> | 5.637(R)| SLOW | 3.257(R)| FAST |FSBCLK | 0.000|
FSB_D<15> | 5.498(R)| SLOW | 3.434(R)| FAST |FSBCLK | 0.000|
FSB_D<16> | 5.334(R)| SLOW | 3.301(R)| FAST |FSBCLK | 0.000|
FSB_D<17> | 6.352(R)| SLOW | 3.623(R)| SLOW |FSBCLK | 0.000|
FSB_D<18> | 5.322(R)| SLOW | 3.660(R)| FAST |FSBCLK | 0.000|
FSB_D<19> | 5.202(R)| SLOW | 3.571(R)| FAST |FSBCLK | 0.000|
FSB_D<20> | 5.326(R)| SLOW | 3.648(R)| FAST |FSBCLK | 0.000|
FSB_D<21> | 5.433(R)| SLOW | 3.786(R)| FAST |FSBCLK | 0.000|
FSB_D<22> | 5.420(R)| SLOW | 3.815(R)| FAST |FSBCLK | 0.000|
FSB_D<23> | 5.313(R)| SLOW | 3.623(R)| FAST |FSBCLK | 0.000|
FSB_D<24> | 5.376(R)| SLOW | 3.717(R)| FAST |FSBCLK | 0.000|
FSB_D<25> | 5.790(R)| SLOW | 3.918(R)| FAST |FSBCLK | 0.000|
FSB_D<26> | 5.530(R)| SLOW | 3.871(R)| FAST |FSBCLK | 0.000|
FSB_D<27> | 5.307(R)| SLOW | 3.717(R)| SLOW |FSBCLK | 0.000|
FSB_D<28> | 5.952(R)| SLOW | 3.721(R)| FAST |FSBCLK | 0.000|
FSB_D<29> | 6.358(R)| SLOW | 4.158(R)| FAST |FSBCLK | 0.000|
FSB_D<30> | 6.772(R)| SLOW | 4.471(R)| FAST |FSBCLK | 0.000|
FSB_D<31> | 6.477(R)| SLOW | 4.207(R)| FAST |FSBCLK | 0.000|
RAMCLK0 | -0.063(R)| FAST | -0.086(R)| SLOW |FSBCLK | 0.000|
RAMCLK1 | -0.063(R)| FAST | -0.086(R)| SLOW |FSBCLK | 0.000|
------------+-----------------+------------+-----------------+------------+---------------------+--------+
Clock to Setup on destination clock CLKIN
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLKIN | 5.103| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
FSB_A<2> |CPU_nSTERM | 14.296|
FSB_A<2> |FSB_D<0> | 16.621|
FSB_A<2> |FSB_D<1> | 16.752|
FSB_A<2> |FSB_D<2> | 17.066|
FSB_A<2> |FSB_D<3> | 16.634|
FSB_A<2> |FSB_D<4> | 16.546|
FSB_A<2> |FSB_D<5> | 16.467|
FSB_A<2> |FSB_D<6> | 16.379|
FSB_A<2> |FSB_D<7> | 16.563|
FSB_A<2> |FSB_D<8> | 15.885|
FSB_A<2> |FSB_D<9> | 16.176|
FSB_A<2> |FSB_D<10> | 16.136|
FSB_A<2> |FSB_D<11> | 16.295|
FSB_A<2> |FSB_D<12> | 16.322|
FSB_A<2> |FSB_D<13> | 16.371|
FSB_A<2> |FSB_D<14> | 16.263|
FSB_A<2> |FSB_D<15> | 16.124|
FSB_A<2> |FSB_D<16> | 15.960|
FSB_A<2> |FSB_D<17> | 16.978|
FSB_A<2> |FSB_D<18> | 15.948|
FSB_A<2> |FSB_D<19> | 15.828|
FSB_A<2> |FSB_D<20> | 15.952|
FSB_A<2> |FSB_D<21> | 16.059|
FSB_A<2> |FSB_D<22> | 16.046|
FSB_A<2> |FSB_D<23> | 15.939|
FSB_A<2> |FSB_D<24> | 16.002|
FSB_A<2> |FSB_D<25> | 16.234|
FSB_A<2> |FSB_D<26> | 16.156|
FSB_A<2> |FSB_D<27> | 15.933|
FSB_A<2> |FSB_D<28> | 16.578|
FSB_A<2> |FSB_D<29> | 16.984|
FSB_A<2> |FSB_D<30> | 17.398|
FSB_A<2> |FSB_D<31> | 17.103|
FSB_A<3> |CPU_nSTERM | 14.069|
FSB_A<3> |FSB_D<0> | 16.394|
FSB_A<3> |FSB_D<1> | 16.525|
FSB_A<3> |FSB_D<2> | 16.839|
FSB_A<3> |FSB_D<3> | 16.407|
FSB_A<3> |FSB_D<4> | 16.319|
FSB_A<3> |FSB_D<5> | 16.240|
FSB_A<3> |FSB_D<6> | 16.152|
FSB_A<3> |FSB_D<7> | 16.336|
FSB_A<3> |FSB_D<8> | 15.658|
FSB_A<3> |FSB_D<9> | 15.949|
FSB_A<3> |FSB_D<10> | 15.909|
FSB_A<3> |FSB_D<11> | 16.068|
FSB_A<3> |FSB_D<12> | 16.095|
FSB_A<3> |FSB_D<13> | 16.144|
FSB_A<3> |FSB_D<14> | 16.036|
FSB_A<3> |FSB_D<15> | 15.897|
FSB_A<3> |FSB_D<16> | 15.733|
FSB_A<3> |FSB_D<17> | 16.751|
FSB_A<3> |FSB_D<18> | 15.721|
FSB_A<3> |FSB_D<19> | 15.601|
FSB_A<3> |FSB_D<20> | 15.725|
FSB_A<3> |FSB_D<21> | 15.832|
FSB_A<3> |FSB_D<22> | 15.819|
FSB_A<3> |FSB_D<23> | 15.712|
FSB_A<3> |FSB_D<24> | 15.775|
FSB_A<3> |FSB_D<25> | 16.007|
FSB_A<3> |FSB_D<26> | 15.929|
FSB_A<3> |FSB_D<27> | 15.706|
FSB_A<3> |FSB_D<28> | 16.351|
FSB_A<3> |FSB_D<29> | 16.757|
FSB_A<3> |FSB_D<30> | 17.171|
FSB_A<3> |FSB_D<31> | 16.876|
FSB_A<4> |CPU_nSTERM | 13.511|
FSB_A<4> |FSB_D<0> | 15.836|
FSB_A<4> |FSB_D<1> | 15.967|
FSB_A<4> |FSB_D<2> | 16.281|
FSB_A<4> |FSB_D<3> | 15.849|
FSB_A<4> |FSB_D<4> | 15.761|
FSB_A<4> |FSB_D<5> | 15.682|
FSB_A<4> |FSB_D<6> | 15.594|
FSB_A<4> |FSB_D<7> | 15.778|
FSB_A<4> |FSB_D<8> | 15.100|
FSB_A<4> |FSB_D<9> | 15.391|
FSB_A<4> |FSB_D<10> | 15.351|
FSB_A<4> |FSB_D<11> | 15.510|
FSB_A<4> |FSB_D<12> | 15.537|
FSB_A<4> |FSB_D<13> | 15.586|
FSB_A<4> |FSB_D<14> | 15.478|
FSB_A<4> |FSB_D<15> | 15.339|
FSB_A<4> |FSB_D<16> | 15.175|
FSB_A<4> |FSB_D<17> | 16.193|
FSB_A<4> |FSB_D<18> | 15.163|
FSB_A<4> |FSB_D<19> | 15.043|
FSB_A<4> |FSB_D<20> | 15.167|
FSB_A<4> |FSB_D<21> | 15.274|
FSB_A<4> |FSB_D<22> | 15.261|
FSB_A<4> |FSB_D<23> | 15.154|
FSB_A<4> |FSB_D<24> | 15.217|
FSB_A<4> |FSB_D<25> | 15.449|
FSB_A<4> |FSB_D<26> | 15.371|
FSB_A<4> |FSB_D<27> | 15.148|
FSB_A<4> |FSB_D<28> | 15.793|
FSB_A<4> |FSB_D<29> | 16.199|
FSB_A<4> |FSB_D<30> | 16.613|
FSB_A<4> |FSB_D<31> | 16.318|
FSB_A<5> |CPU_nSTERM | 13.587|
FSB_A<5> |FSB_D<0> | 15.912|
FSB_A<5> |FSB_D<1> | 16.043|
FSB_A<5> |FSB_D<2> | 16.357|
FSB_A<5> |FSB_D<3> | 15.925|
FSB_A<5> |FSB_D<4> | 15.837|
FSB_A<5> |FSB_D<5> | 15.758|
FSB_A<5> |FSB_D<6> | 15.670|
FSB_A<5> |FSB_D<7> | 15.854|
FSB_A<5> |FSB_D<8> | 15.176|
FSB_A<5> |FSB_D<9> | 15.467|
FSB_A<5> |FSB_D<10> | 15.427|
FSB_A<5> |FSB_D<11> | 15.586|
FSB_A<5> |FSB_D<12> | 15.613|
FSB_A<5> |FSB_D<13> | 15.662|
FSB_A<5> |FSB_D<14> | 15.554|
FSB_A<5> |FSB_D<15> | 15.415|
FSB_A<5> |FSB_D<16> | 15.251|
FSB_A<5> |FSB_D<17> | 16.269|
FSB_A<5> |FSB_D<18> | 15.239|
FSB_A<5> |FSB_D<19> | 15.119|
FSB_A<5> |FSB_D<20> | 15.243|
FSB_A<5> |FSB_D<21> | 15.350|
FSB_A<5> |FSB_D<22> | 15.337|
FSB_A<5> |FSB_D<23> | 15.230|
FSB_A<5> |FSB_D<24> | 15.293|
FSB_A<5> |FSB_D<25> | 15.525|
FSB_A<5> |FSB_D<26> | 15.447|
FSB_A<5> |FSB_D<27> | 15.224|
FSB_A<5> |FSB_D<28> | 15.869|
FSB_A<5> |FSB_D<29> | 16.275|
FSB_A<5> |FSB_D<30> | 16.689|
FSB_A<5> |FSB_D<31> | 16.394|
FSB_A<6> |CPU_nSTERM | 13.527|
FSB_A<6> |FSB_D<0> | 15.852|
FSB_A<6> |FSB_D<1> | 15.983|
FSB_A<6> |FSB_D<2> | 16.297|
FSB_A<6> |FSB_D<3> | 15.865|
FSB_A<6> |FSB_D<4> | 15.777|
FSB_A<6> |FSB_D<5> | 15.698|
FSB_A<6> |FSB_D<6> | 15.610|
FSB_A<6> |FSB_D<7> | 15.794|
FSB_A<6> |FSB_D<8> | 15.116|
FSB_A<6> |FSB_D<9> | 15.407|
FSB_A<6> |FSB_D<10> | 15.367|
FSB_A<6> |FSB_D<11> | 15.526|
FSB_A<6> |FSB_D<12> | 15.553|
FSB_A<6> |FSB_D<13> | 15.602|
FSB_A<6> |FSB_D<14> | 15.494|
FSB_A<6> |FSB_D<15> | 15.355|
FSB_A<6> |FSB_D<16> | 15.191|
FSB_A<6> |FSB_D<17> | 16.209|
FSB_A<6> |FSB_D<18> | 15.179|
FSB_A<6> |FSB_D<19> | 15.059|
FSB_A<6> |FSB_D<20> | 15.183|
FSB_A<6> |FSB_D<21> | 15.290|
FSB_A<6> |FSB_D<22> | 15.277|
FSB_A<6> |FSB_D<23> | 15.170|
FSB_A<6> |FSB_D<24> | 15.233|
FSB_A<6> |FSB_D<25> | 15.465|
FSB_A<6> |FSB_D<26> | 15.387|
FSB_A<6> |FSB_D<27> | 15.164|
FSB_A<6> |FSB_D<28> | 15.809|
FSB_A<6> |FSB_D<29> | 16.215|
FSB_A<6> |FSB_D<30> | 16.629|
FSB_A<6> |FSB_D<31> | 16.334|
FSB_A<7> |CPU_nSTERM | 13.423|
FSB_A<7> |FSB_D<0> | 15.748|
FSB_A<7> |FSB_D<1> | 15.879|
FSB_A<7> |FSB_D<2> | 16.193|
FSB_A<7> |FSB_D<3> | 15.761|
FSB_A<7> |FSB_D<4> | 15.673|
FSB_A<7> |FSB_D<5> | 15.594|
FSB_A<7> |FSB_D<6> | 15.506|
FSB_A<7> |FSB_D<7> | 15.690|
FSB_A<7> |FSB_D<8> | 15.012|
FSB_A<7> |FSB_D<9> | 15.303|
FSB_A<7> |FSB_D<10> | 15.263|
FSB_A<7> |FSB_D<11> | 15.422|
FSB_A<7> |FSB_D<12> | 15.449|
FSB_A<7> |FSB_D<13> | 15.498|
FSB_A<7> |FSB_D<14> | 15.390|
FSB_A<7> |FSB_D<15> | 15.251|
FSB_A<7> |FSB_D<16> | 15.087|
FSB_A<7> |FSB_D<17> | 16.105|
FSB_A<7> |FSB_D<18> | 15.075|
FSB_A<7> |FSB_D<19> | 14.955|
FSB_A<7> |FSB_D<20> | 15.079|
FSB_A<7> |FSB_D<21> | 15.186|
FSB_A<7> |FSB_D<22> | 15.173|
FSB_A<7> |FSB_D<23> | 15.066|
FSB_A<7> |FSB_D<24> | 15.129|
FSB_A<7> |FSB_D<25> | 15.361|
FSB_A<7> |FSB_D<26> | 15.283|
FSB_A<7> |FSB_D<27> | 15.060|
FSB_A<7> |FSB_D<28> | 15.705|
FSB_A<7> |FSB_D<29> | 16.111|
FSB_A<7> |FSB_D<30> | 16.525|
FSB_A<7> |FSB_D<31> | 16.230|
FSB_A<8> |CPU_nSTERM | 13.315|
FSB_A<8> |FSB_D<0> | 15.640|
FSB_A<8> |FSB_D<1> | 15.771|
FSB_A<8> |FSB_D<2> | 16.085|
FSB_A<8> |FSB_D<3> | 15.653|
FSB_A<8> |FSB_D<4> | 15.565|
FSB_A<8> |FSB_D<5> | 15.486|
FSB_A<8> |FSB_D<6> | 15.398|
FSB_A<8> |FSB_D<7> | 15.582|
FSB_A<8> |FSB_D<8> | 14.904|
FSB_A<8> |FSB_D<9> | 15.195|
FSB_A<8> |FSB_D<10> | 15.155|
FSB_A<8> |FSB_D<11> | 15.314|
FSB_A<8> |FSB_D<12> | 15.341|
FSB_A<8> |FSB_D<13> | 15.390|
FSB_A<8> |FSB_D<14> | 15.282|
FSB_A<8> |FSB_D<15> | 15.143|
FSB_A<8> |FSB_D<16> | 14.979|
FSB_A<8> |FSB_D<17> | 15.997|
FSB_A<8> |FSB_D<18> | 14.967|
FSB_A<8> |FSB_D<19> | 14.847|
FSB_A<8> |FSB_D<20> | 14.971|
FSB_A<8> |FSB_D<21> | 15.078|
FSB_A<8> |FSB_D<22> | 15.065|
FSB_A<8> |FSB_D<23> | 14.958|
FSB_A<8> |FSB_D<24> | 15.021|
FSB_A<8> |FSB_D<25> | 15.253|
FSB_A<8> |FSB_D<26> | 15.175|
FSB_A<8> |FSB_D<27> | 14.952|
FSB_A<8> |FSB_D<28> | 15.597|
FSB_A<8> |FSB_D<29> | 16.003|
FSB_A<8> |FSB_D<30> | 16.417|
FSB_A<8> |FSB_D<31> | 16.122|
FSB_A<9> |CPU_nSTERM | 10.883|
FSB_A<9> |FSB_D<0> | 13.208|
FSB_A<9> |FSB_D<1> | 13.339|
FSB_A<9> |FSB_D<2> | 13.653|
FSB_A<9> |FSB_D<3> | 13.221|
FSB_A<9> |FSB_D<4> | 13.133|
FSB_A<9> |FSB_D<5> | 13.054|
FSB_A<9> |FSB_D<6> | 12.966|
FSB_A<9> |FSB_D<7> | 13.150|
FSB_A<9> |FSB_D<8> | 12.472|
FSB_A<9> |FSB_D<9> | 12.763|
FSB_A<9> |FSB_D<10> | 12.723|
FSB_A<9> |FSB_D<11> | 12.882|
FSB_A<9> |FSB_D<12> | 12.909|
FSB_A<9> |FSB_D<13> | 12.958|
FSB_A<9> |FSB_D<14> | 12.850|
FSB_A<9> |FSB_D<15> | 12.711|
FSB_A<9> |FSB_D<16> | 12.547|
FSB_A<9> |FSB_D<17> | 13.565|
FSB_A<9> |FSB_D<18> | 12.535|
FSB_A<9> |FSB_D<19> | 12.415|
FSB_A<9> |FSB_D<20> | 12.539|
FSB_A<9> |FSB_D<21> | 12.646|
FSB_A<9> |FSB_D<22> | 12.633|
FSB_A<9> |FSB_D<23> | 12.526|
FSB_A<9> |FSB_D<24> | 12.589|
FSB_A<9> |FSB_D<25> | 12.821|
FSB_A<9> |FSB_D<26> | 12.743|
FSB_A<9> |FSB_D<27> | 12.520|
FSB_A<9> |FSB_D<28> | 13.165|
FSB_A<9> |FSB_D<29> | 13.571|
FSB_A<9> |FSB_D<30> | 13.985|
FSB_A<9> |FSB_D<31> | 13.690|
FSB_A<10> |CPU_nSTERM | 10.887|
FSB_A<10> |FSB_D<0> | 13.212|
FSB_A<10> |FSB_D<1> | 13.343|
FSB_A<10> |FSB_D<2> | 13.657|
FSB_A<10> |FSB_D<3> | 13.225|
FSB_A<10> |FSB_D<4> | 13.137|
FSB_A<10> |FSB_D<5> | 13.058|
FSB_A<10> |FSB_D<6> | 12.970|
FSB_A<10> |FSB_D<7> | 13.154|
FSB_A<10> |FSB_D<8> | 12.476|
FSB_A<10> |FSB_D<9> | 12.767|
FSB_A<10> |FSB_D<10> | 12.727|
FSB_A<10> |FSB_D<11> | 12.886|
FSB_A<10> |FSB_D<12> | 12.913|
FSB_A<10> |FSB_D<13> | 12.962|
FSB_A<10> |FSB_D<14> | 12.854|
FSB_A<10> |FSB_D<15> | 12.715|
FSB_A<10> |FSB_D<16> | 12.551|
FSB_A<10> |FSB_D<17> | 13.569|
FSB_A<10> |FSB_D<18> | 12.539|
FSB_A<10> |FSB_D<19> | 12.419|
FSB_A<10> |FSB_D<20> | 12.543|
FSB_A<10> |FSB_D<21> | 12.650|
FSB_A<10> |FSB_D<22> | 12.637|
FSB_A<10> |FSB_D<23> | 12.530|
FSB_A<10> |FSB_D<24> | 12.593|
FSB_A<10> |FSB_D<25> | 12.825|
FSB_A<10> |FSB_D<26> | 12.747|
FSB_A<10> |FSB_D<27> | 12.524|
FSB_A<10> |FSB_D<28> | 13.169|
FSB_A<10> |FSB_D<29> | 13.575|
FSB_A<10> |FSB_D<30> | 13.989|
FSB_A<10> |FSB_D<31> | 13.694|
FSB_A<11> |CPU_nSTERM | 11.010|
FSB_A<11> |FSB_D<0> | 13.335|
FSB_A<11> |FSB_D<1> | 13.466|
FSB_A<11> |FSB_D<2> | 13.780|
FSB_A<11> |FSB_D<3> | 13.348|
FSB_A<11> |FSB_D<4> | 13.260|
FSB_A<11> |FSB_D<5> | 13.181|
FSB_A<11> |FSB_D<6> | 13.093|
FSB_A<11> |FSB_D<7> | 13.277|
FSB_A<11> |FSB_D<8> | 12.599|
FSB_A<11> |FSB_D<9> | 12.890|
FSB_A<11> |FSB_D<10> | 12.850|
FSB_A<11> |FSB_D<11> | 13.009|
FSB_A<11> |FSB_D<12> | 13.036|
FSB_A<11> |FSB_D<13> | 13.085|
FSB_A<11> |FSB_D<14> | 12.977|
FSB_A<11> |FSB_D<15> | 12.838|
FSB_A<11> |FSB_D<16> | 12.674|
FSB_A<11> |FSB_D<17> | 13.692|
FSB_A<11> |FSB_D<18> | 12.662|
FSB_A<11> |FSB_D<19> | 12.542|
FSB_A<11> |FSB_D<20> | 12.666|
FSB_A<11> |FSB_D<21> | 12.773|
FSB_A<11> |FSB_D<22> | 12.760|
FSB_A<11> |FSB_D<23> | 12.653|
FSB_A<11> |FSB_D<24> | 12.716|
FSB_A<11> |FSB_D<25> | 12.948|
FSB_A<11> |FSB_D<26> | 12.870|
FSB_A<11> |FSB_D<27> | 12.647|
FSB_A<11> |FSB_D<28> | 13.292|
FSB_A<11> |FSB_D<29> | 13.698|
FSB_A<11> |FSB_D<30> | 14.112|
FSB_A<11> |FSB_D<31> | 13.817|
FSB_A<12> |CPU_nSTERM | 10.689|
FSB_A<12> |FSB_D<0> | 13.014|
FSB_A<12> |FSB_D<1> | 13.145|
FSB_A<12> |FSB_D<2> | 13.459|
FSB_A<12> |FSB_D<3> | 13.027|
FSB_A<12> |FSB_D<4> | 12.939|
FSB_A<12> |FSB_D<5> | 12.860|
FSB_A<12> |FSB_D<6> | 12.772|
FSB_A<12> |FSB_D<7> | 12.956|
FSB_A<12> |FSB_D<8> | 12.278|
FSB_A<12> |FSB_D<9> | 12.569|
FSB_A<12> |FSB_D<10> | 12.529|
FSB_A<12> |FSB_D<11> | 12.688|
FSB_A<12> |FSB_D<12> | 12.715|
FSB_A<12> |FSB_D<13> | 12.764|
FSB_A<12> |FSB_D<14> | 12.656|
FSB_A<12> |FSB_D<15> | 12.517|
FSB_A<12> |FSB_D<16> | 12.353|
FSB_A<12> |FSB_D<17> | 13.371|
FSB_A<12> |FSB_D<18> | 12.341|
FSB_A<12> |FSB_D<19> | 12.221|
FSB_A<12> |FSB_D<20> | 12.345|
FSB_A<12> |FSB_D<21> | 12.452|
FSB_A<12> |FSB_D<22> | 12.439|
FSB_A<12> |FSB_D<23> | 12.332|
FSB_A<12> |FSB_D<24> | 12.395|
FSB_A<12> |FSB_D<25> | 12.627|
FSB_A<12> |FSB_D<26> | 12.549|
FSB_A<12> |FSB_D<27> | 12.326|
FSB_A<12> |FSB_D<28> | 12.971|
FSB_A<12> |FSB_D<29> | 13.377|
FSB_A<12> |FSB_D<30> | 13.791|
FSB_A<12> |FSB_D<31> | 13.496|
FSB_A<13> |CPU_nSTERM | 10.623|
FSB_A<13> |FSB_D<0> | 12.948|
FSB_A<13> |FSB_D<1> | 13.079|
FSB_A<13> |FSB_D<2> | 13.393|
FSB_A<13> |FSB_D<3> | 12.961|
FSB_A<13> |FSB_D<4> | 12.873|
FSB_A<13> |FSB_D<5> | 12.794|
FSB_A<13> |FSB_D<6> | 12.706|
FSB_A<13> |FSB_D<7> | 12.890|
FSB_A<13> |FSB_D<8> | 12.212|
FSB_A<13> |FSB_D<9> | 12.503|
FSB_A<13> |FSB_D<10> | 12.463|
FSB_A<13> |FSB_D<11> | 12.622|
FSB_A<13> |FSB_D<12> | 12.649|
FSB_A<13> |FSB_D<13> | 12.698|
FSB_A<13> |FSB_D<14> | 12.590|
FSB_A<13> |FSB_D<15> | 12.451|
FSB_A<13> |FSB_D<16> | 12.287|
FSB_A<13> |FSB_D<17> | 13.305|
FSB_A<13> |FSB_D<18> | 12.275|
FSB_A<13> |FSB_D<19> | 12.155|
FSB_A<13> |FSB_D<20> | 12.279|
FSB_A<13> |FSB_D<21> | 12.386|
FSB_A<13> |FSB_D<22> | 12.373|
FSB_A<13> |FSB_D<23> | 12.266|
FSB_A<13> |FSB_D<24> | 12.329|
FSB_A<13> |FSB_D<25> | 12.561|
FSB_A<13> |FSB_D<26> | 12.483|
FSB_A<13> |FSB_D<27> | 12.260|
FSB_A<13> |FSB_D<28> | 12.905|
FSB_A<13> |FSB_D<29> | 13.311|
FSB_A<13> |FSB_D<30> | 13.725|
FSB_A<13> |FSB_D<31> | 13.430|
FSB_A<14> |CPU_nSTERM | 10.788|
FSB_A<14> |FSB_D<0> | 13.113|
FSB_A<14> |FSB_D<1> | 13.244|
FSB_A<14> |FSB_D<2> | 13.558|
FSB_A<14> |FSB_D<3> | 13.126|
FSB_A<14> |FSB_D<4> | 13.038|
FSB_A<14> |FSB_D<5> | 12.959|
FSB_A<14> |FSB_D<6> | 12.871|
FSB_A<14> |FSB_D<7> | 13.055|
FSB_A<14> |FSB_D<8> | 12.377|
FSB_A<14> |FSB_D<9> | 12.668|
FSB_A<14> |FSB_D<10> | 12.628|
FSB_A<14> |FSB_D<11> | 12.787|
FSB_A<14> |FSB_D<12> | 12.814|
FSB_A<14> |FSB_D<13> | 12.863|
FSB_A<14> |FSB_D<14> | 12.755|
FSB_A<14> |FSB_D<15> | 12.616|
FSB_A<14> |FSB_D<16> | 12.452|
FSB_A<14> |FSB_D<17> | 13.470|
FSB_A<14> |FSB_D<18> | 12.440|
FSB_A<14> |FSB_D<19> | 12.320|
FSB_A<14> |FSB_D<20> | 12.444|
FSB_A<14> |FSB_D<21> | 12.551|
FSB_A<14> |FSB_D<22> | 12.538|
FSB_A<14> |FSB_D<23> | 12.431|
FSB_A<14> |FSB_D<24> | 12.494|
FSB_A<14> |FSB_D<25> | 12.726|
FSB_A<14> |FSB_D<26> | 12.648|
FSB_A<14> |FSB_D<27> | 12.425|
FSB_A<14> |FSB_D<28> | 13.070|
FSB_A<14> |FSB_D<29> | 13.476|
FSB_A<14> |FSB_D<30> | 13.890|
FSB_A<14> |FSB_D<31> | 13.595|
FSB_A<15> |CPU_nSTERM | 10.613|
FSB_A<15> |FSB_D<0> | 12.938|
FSB_A<15> |FSB_D<1> | 13.069|
FSB_A<15> |FSB_D<2> | 13.383|
FSB_A<15> |FSB_D<3> | 12.951|
FSB_A<15> |FSB_D<4> | 12.863|
FSB_A<15> |FSB_D<5> | 12.784|
FSB_A<15> |FSB_D<6> | 12.696|
FSB_A<15> |FSB_D<7> | 12.880|
FSB_A<15> |FSB_D<8> | 12.202|
FSB_A<15> |FSB_D<9> | 12.493|
FSB_A<15> |FSB_D<10> | 12.453|
FSB_A<15> |FSB_D<11> | 12.612|
FSB_A<15> |FSB_D<12> | 12.639|
FSB_A<15> |FSB_D<13> | 12.688|
FSB_A<15> |FSB_D<14> | 12.580|
FSB_A<15> |FSB_D<15> | 12.441|
FSB_A<15> |FSB_D<16> | 12.277|
FSB_A<15> |FSB_D<17> | 13.295|
FSB_A<15> |FSB_D<18> | 12.265|
FSB_A<15> |FSB_D<19> | 12.145|
FSB_A<15> |FSB_D<20> | 12.269|
FSB_A<15> |FSB_D<21> | 12.376|
FSB_A<15> |FSB_D<22> | 12.363|
FSB_A<15> |FSB_D<23> | 12.256|
FSB_A<15> |FSB_D<24> | 12.319|
FSB_A<15> |FSB_D<25> | 12.551|
FSB_A<15> |FSB_D<26> | 12.473|
FSB_A<15> |FSB_D<27> | 12.250|
FSB_A<15> |FSB_D<28> | 12.895|
FSB_A<15> |FSB_D<29> | 13.301|
FSB_A<15> |FSB_D<30> | 13.715|
FSB_A<15> |FSB_D<31> | 13.420|
FSB_A<16> |CPU_nSTERM | 11.423|
FSB_A<16> |FSB_D<0> | 13.748|
FSB_A<16> |FSB_D<1> | 13.879|
FSB_A<16> |FSB_D<2> | 14.193|
FSB_A<16> |FSB_D<3> | 13.761|
FSB_A<16> |FSB_D<4> | 13.673|
FSB_A<16> |FSB_D<5> | 13.594|
FSB_A<16> |FSB_D<6> | 13.506|
FSB_A<16> |FSB_D<7> | 13.690|
FSB_A<16> |FSB_D<8> | 13.012|
FSB_A<16> |FSB_D<9> | 13.303|
FSB_A<16> |FSB_D<10> | 13.263|
FSB_A<16> |FSB_D<11> | 13.422|
FSB_A<16> |FSB_D<12> | 13.449|
FSB_A<16> |FSB_D<13> | 13.498|
FSB_A<16> |FSB_D<14> | 13.390|
FSB_A<16> |FSB_D<15> | 13.251|
FSB_A<16> |FSB_D<16> | 13.087|
FSB_A<16> |FSB_D<17> | 14.105|
FSB_A<16> |FSB_D<18> | 13.075|
FSB_A<16> |FSB_D<19> | 12.955|
FSB_A<16> |FSB_D<20> | 13.079|
FSB_A<16> |FSB_D<21> | 13.186|
FSB_A<16> |FSB_D<22> | 13.173|
FSB_A<16> |FSB_D<23> | 13.066|
FSB_A<16> |FSB_D<24> | 13.129|
FSB_A<16> |FSB_D<25> | 13.361|
FSB_A<16> |FSB_D<26> | 13.283|
FSB_A<16> |FSB_D<27> | 13.060|
FSB_A<16> |FSB_D<28> | 13.705|
FSB_A<16> |FSB_D<29> | 14.111|
FSB_A<16> |FSB_D<30> | 14.525|
FSB_A<16> |FSB_D<31> | 14.230|
FSB_A<17> |CPU_nSTERM | 11.557|
FSB_A<17> |FSB_D<0> | 13.882|
FSB_A<17> |FSB_D<1> | 14.013|
FSB_A<17> |FSB_D<2> | 14.327|
FSB_A<17> |FSB_D<3> | 13.895|
FSB_A<17> |FSB_D<4> | 13.807|
FSB_A<17> |FSB_D<5> | 13.728|
FSB_A<17> |FSB_D<6> | 13.640|
FSB_A<17> |FSB_D<7> | 13.824|
FSB_A<17> |FSB_D<8> | 13.146|
FSB_A<17> |FSB_D<9> | 13.437|
FSB_A<17> |FSB_D<10> | 13.397|
FSB_A<17> |FSB_D<11> | 13.556|
FSB_A<17> |FSB_D<12> | 13.583|
FSB_A<17> |FSB_D<13> | 13.632|
FSB_A<17> |FSB_D<14> | 13.524|
FSB_A<17> |FSB_D<15> | 13.385|
FSB_A<17> |FSB_D<16> | 13.221|
FSB_A<17> |FSB_D<17> | 14.239|
FSB_A<17> |FSB_D<18> | 13.209|
FSB_A<17> |FSB_D<19> | 13.089|
FSB_A<17> |FSB_D<20> | 13.213|
FSB_A<17> |FSB_D<21> | 13.320|
FSB_A<17> |FSB_D<22> | 13.307|
FSB_A<17> |FSB_D<23> | 13.200|
FSB_A<17> |FSB_D<24> | 13.263|
FSB_A<17> |FSB_D<25> | 13.495|
FSB_A<17> |FSB_D<26> | 13.417|
FSB_A<17> |FSB_D<27> | 13.194|
FSB_A<17> |FSB_D<28> | 13.839|
FSB_A<17> |FSB_D<29> | 14.245|
FSB_A<17> |FSB_D<30> | 14.659|
FSB_A<17> |FSB_D<31> | 14.364|
FSB_A<18> |CPU_nSTERM | 11.135|
FSB_A<18> |FSB_D<0> | 13.460|
FSB_A<18> |FSB_D<1> | 13.591|
FSB_A<18> |FSB_D<2> | 13.905|
FSB_A<18> |FSB_D<3> | 13.473|
FSB_A<18> |FSB_D<4> | 13.385|
FSB_A<18> |FSB_D<5> | 13.306|
FSB_A<18> |FSB_D<6> | 13.218|
FSB_A<18> |FSB_D<7> | 13.402|
FSB_A<18> |FSB_D<8> | 12.724|
FSB_A<18> |FSB_D<9> | 13.015|
FSB_A<18> |FSB_D<10> | 12.975|
FSB_A<18> |FSB_D<11> | 13.134|
FSB_A<18> |FSB_D<12> | 13.161|
FSB_A<18> |FSB_D<13> | 13.210|
FSB_A<18> |FSB_D<14> | 13.102|
FSB_A<18> |FSB_D<15> | 12.963|
FSB_A<18> |FSB_D<16> | 12.799|
FSB_A<18> |FSB_D<17> | 13.817|
FSB_A<18> |FSB_D<18> | 12.787|
FSB_A<18> |FSB_D<19> | 12.667|
FSB_A<18> |FSB_D<20> | 12.791|
FSB_A<18> |FSB_D<21> | 12.898|
FSB_A<18> |FSB_D<22> | 12.885|
FSB_A<18> |FSB_D<23> | 12.778|
FSB_A<18> |FSB_D<24> | 12.841|
FSB_A<18> |FSB_D<25> | 13.073|
FSB_A<18> |FSB_D<26> | 12.995|
FSB_A<18> |FSB_D<27> | 12.772|
FSB_A<18> |FSB_D<28> | 13.417|
FSB_A<18> |FSB_D<29> | 13.823|
FSB_A<18> |FSB_D<30> | 14.237|
FSB_A<18> |FSB_D<31> | 13.942|
FSB_A<19> |CPU_nSTERM | 11.426|
FSB_A<19> |FSB_D<0> | 13.751|
FSB_A<19> |FSB_D<1> | 13.882|
FSB_A<19> |FSB_D<2> | 14.196|
FSB_A<19> |FSB_D<3> | 13.764|
FSB_A<19> |FSB_D<4> | 13.676|
FSB_A<19> |FSB_D<5> | 13.597|
FSB_A<19> |FSB_D<6> | 13.509|
FSB_A<19> |FSB_D<7> | 13.693|
FSB_A<19> |FSB_D<8> | 13.015|
FSB_A<19> |FSB_D<9> | 13.306|
FSB_A<19> |FSB_D<10> | 13.266|
FSB_A<19> |FSB_D<11> | 13.425|
FSB_A<19> |FSB_D<12> | 13.452|
FSB_A<19> |FSB_D<13> | 13.501|
FSB_A<19> |FSB_D<14> | 13.393|
FSB_A<19> |FSB_D<15> | 13.254|
FSB_A<19> |FSB_D<16> | 13.090|
FSB_A<19> |FSB_D<17> | 14.108|
FSB_A<19> |FSB_D<18> | 13.078|
FSB_A<19> |FSB_D<19> | 12.958|
FSB_A<19> |FSB_D<20> | 13.082|
FSB_A<19> |FSB_D<21> | 13.189|
FSB_A<19> |FSB_D<22> | 13.176|
FSB_A<19> |FSB_D<23> | 13.069|
FSB_A<19> |FSB_D<24> | 13.132|
FSB_A<19> |FSB_D<25> | 13.364|
FSB_A<19> |FSB_D<26> | 13.286|
FSB_A<19> |FSB_D<27> | 13.063|
FSB_A<19> |FSB_D<28> | 13.708|
FSB_A<19> |FSB_D<29> | 14.114|
FSB_A<19> |FSB_D<30> | 14.528|
FSB_A<19> |FSB_D<31> | 14.233|
FSB_A<20> |CPU_nSTERM | 11.417|
FSB_A<20> |FSB_D<0> | 13.742|
FSB_A<20> |FSB_D<1> | 13.873|
FSB_A<20> |FSB_D<2> | 14.187|
FSB_A<20> |FSB_D<3> | 13.755|
FSB_A<20> |FSB_D<4> | 13.667|
FSB_A<20> |FSB_D<5> | 13.588|
FSB_A<20> |FSB_D<6> | 13.500|
FSB_A<20> |FSB_D<7> | 13.684|
FSB_A<20> |FSB_D<8> | 13.006|
FSB_A<20> |FSB_D<9> | 13.297|
FSB_A<20> |FSB_D<10> | 13.257|
FSB_A<20> |FSB_D<11> | 13.416|
FSB_A<20> |FSB_D<12> | 13.443|
FSB_A<20> |FSB_D<13> | 13.492|
FSB_A<20> |FSB_D<14> | 13.384|
FSB_A<20> |FSB_D<15> | 13.245|
FSB_A<20> |FSB_D<16> | 13.081|
FSB_A<20> |FSB_D<17> | 14.099|
FSB_A<20> |FSB_D<18> | 13.069|
FSB_A<20> |FSB_D<19> | 12.949|
FSB_A<20> |FSB_D<20> | 13.073|
FSB_A<20> |FSB_D<21> | 13.180|
FSB_A<20> |FSB_D<22> | 13.167|
FSB_A<20> |FSB_D<23> | 13.060|
FSB_A<20> |FSB_D<24> | 13.123|
FSB_A<20> |FSB_D<25> | 13.355|
FSB_A<20> |FSB_D<26> | 13.277|
FSB_A<20> |FSB_D<27> | 13.054|
FSB_A<20> |FSB_D<28> | 13.699|
FSB_A<20> |FSB_D<29> | 14.105|
FSB_A<20> |FSB_D<30> | 14.519|
FSB_A<20> |FSB_D<31> | 14.224|
FSB_A<21> |CPU_nSTERM | 10.651|
FSB_A<21> |FSB_D<0> | 12.925|
FSB_A<21> |FSB_D<1> | 13.056|
FSB_A<21> |FSB_D<2> | 13.370|
FSB_A<21> |FSB_D<3> | 12.938|
FSB_A<21> |FSB_D<4> | 12.850|
FSB_A<21> |FSB_D<5> | 12.771|
FSB_A<21> |FSB_D<6> | 12.683|
FSB_A<21> |FSB_D<7> | 12.867|
FSB_A<21> |FSB_D<8> | 12.189|
FSB_A<21> |FSB_D<9> | 12.480|
FSB_A<21> |FSB_D<10> | 12.440|
FSB_A<21> |FSB_D<11> | 12.599|
FSB_A<21> |FSB_D<12> | 12.626|
FSB_A<21> |FSB_D<13> | 12.675|
FSB_A<21> |FSB_D<14> | 12.567|
FSB_A<21> |FSB_D<15> | 12.428|
FSB_A<21> |FSB_D<16> | 12.264|
FSB_A<21> |FSB_D<17> | 13.282|
FSB_A<21> |FSB_D<18> | 12.252|
FSB_A<21> |FSB_D<19> | 12.132|
FSB_A<21> |FSB_D<20> | 12.256|
FSB_A<21> |FSB_D<21> | 12.363|
FSB_A<21> |FSB_D<22> | 12.350|
FSB_A<21> |FSB_D<23> | 12.243|
FSB_A<21> |FSB_D<24> | 12.306|
FSB_A<21> |FSB_D<25> | 12.538|
FSB_A<21> |FSB_D<26> | 12.460|
FSB_A<21> |FSB_D<27> | 12.237|
FSB_A<21> |FSB_D<28> | 12.882|
FSB_A<21> |FSB_D<29> | 13.288|
FSB_A<21> |FSB_D<30> | 13.702|
FSB_A<21> |FSB_D<31> | 13.407|
FSB_A<22> |CPU_nSTERM | 10.645|
FSB_A<22> |FSB_D<0> | 12.919|
FSB_A<22> |FSB_D<1> | 13.050|
FSB_A<22> |FSB_D<2> | 13.364|
FSB_A<22> |FSB_D<3> | 12.932|
FSB_A<22> |FSB_D<4> | 12.844|
FSB_A<22> |FSB_D<5> | 12.765|
FSB_A<22> |FSB_D<6> | 12.677|
FSB_A<22> |FSB_D<7> | 12.861|
FSB_A<22> |FSB_D<8> | 12.183|
FSB_A<22> |FSB_D<9> | 12.474|
FSB_A<22> |FSB_D<10> | 12.434|
FSB_A<22> |FSB_D<11> | 12.593|
FSB_A<22> |FSB_D<12> | 12.620|
FSB_A<22> |FSB_D<13> | 12.669|
FSB_A<22> |FSB_D<14> | 12.561|
FSB_A<22> |FSB_D<15> | 12.422|
FSB_A<22> |FSB_D<16> | 12.258|
FSB_A<22> |FSB_D<17> | 13.276|
FSB_A<22> |FSB_D<18> | 12.246|
FSB_A<22> |FSB_D<19> | 12.126|
FSB_A<22> |FSB_D<20> | 12.250|
FSB_A<22> |FSB_D<21> | 12.357|
FSB_A<22> |FSB_D<22> | 12.344|
FSB_A<22> |FSB_D<23> | 12.237|
FSB_A<22> |FSB_D<24> | 12.300|
FSB_A<22> |FSB_D<25> | 12.532|
FSB_A<22> |FSB_D<26> | 12.454|
FSB_A<22> |FSB_D<27> | 12.231|
FSB_A<22> |FSB_D<28> | 12.876|
FSB_A<22> |FSB_D<29> | 13.282|
FSB_A<22> |FSB_D<30> | 13.696|
FSB_A<22> |FSB_D<31> | 13.401|
FSB_A<23> |CPU_nSTERM | 10.795|
FSB_A<23> |FSB_D<0> | 13.069|
FSB_A<23> |FSB_D<1> | 13.200|
FSB_A<23> |FSB_D<2> | 13.514|
FSB_A<23> |FSB_D<3> | 13.082|
FSB_A<23> |FSB_D<4> | 12.994|
FSB_A<23> |FSB_D<5> | 12.915|
FSB_A<23> |FSB_D<6> | 12.827|
FSB_A<23> |FSB_D<7> | 13.011|
FSB_A<23> |FSB_D<8> | 12.333|
FSB_A<23> |FSB_D<9> | 12.624|
FSB_A<23> |FSB_D<10> | 12.584|
FSB_A<23> |FSB_D<11> | 12.743|
FSB_A<23> |FSB_D<12> | 12.770|
FSB_A<23> |FSB_D<13> | 12.819|
FSB_A<23> |FSB_D<14> | 12.711|
FSB_A<23> |FSB_D<15> | 12.572|
FSB_A<23> |FSB_D<16> | 12.408|
FSB_A<23> |FSB_D<17> | 13.426|
FSB_A<23> |FSB_D<18> | 12.396|
FSB_A<23> |FSB_D<19> | 12.276|
FSB_A<23> |FSB_D<20> | 12.400|
FSB_A<23> |FSB_D<21> | 12.507|
FSB_A<23> |FSB_D<22> | 12.494|
FSB_A<23> |FSB_D<23> | 12.387|
FSB_A<23> |FSB_D<24> | 12.450|
FSB_A<23> |FSB_D<25> | 12.682|
FSB_A<23> |FSB_D<26> | 12.604|
FSB_A<23> |FSB_D<27> | 12.381|
FSB_A<23> |FSB_D<28> | 13.026|
FSB_A<23> |FSB_D<29> | 13.432|
FSB_A<23> |FSB_D<30> | 13.846|
FSB_A<23> |FSB_D<31> | 13.551|
FSB_A<24> |CPU_nSTERM | 10.449|
FSB_A<24> |FSB_D<0> | 12.722|
FSB_A<24> |FSB_D<1> | 12.853|
FSB_A<24> |FSB_D<2> | 13.167|
FSB_A<24> |FSB_D<3> | 12.735|
FSB_A<24> |FSB_D<4> | 12.647|
FSB_A<24> |FSB_D<5> | 12.568|
FSB_A<24> |FSB_D<6> | 12.480|
FSB_A<24> |FSB_D<7> | 12.664|
FSB_A<24> |FSB_D<8> | 11.986|
FSB_A<24> |FSB_D<9> | 12.277|
FSB_A<24> |FSB_D<10> | 12.237|
FSB_A<24> |FSB_D<11> | 12.396|
FSB_A<24> |FSB_D<12> | 12.423|
FSB_A<24> |FSB_D<13> | 12.472|
FSB_A<24> |FSB_D<14> | 12.364|
FSB_A<24> |FSB_D<15> | 12.225|
FSB_A<24> |FSB_D<16> | 12.061|
FSB_A<24> |FSB_D<17> | 13.079|
FSB_A<24> |FSB_D<18> | 12.049|
FSB_A<24> |FSB_D<19> | 11.929|
FSB_A<24> |FSB_D<20> | 12.053|
FSB_A<24> |FSB_D<21> | 12.160|
FSB_A<24> |FSB_D<22> | 12.147|
FSB_A<24> |FSB_D<23> | 12.040|
FSB_A<24> |FSB_D<24> | 12.103|
FSB_A<24> |FSB_D<25> | 12.335|
FSB_A<24> |FSB_D<26> | 12.257|
FSB_A<24> |FSB_D<27> | 12.034|
FSB_A<24> |FSB_D<28> | 12.679|
FSB_A<24> |FSB_D<29> | 13.085|
FSB_A<24> |FSB_D<30> | 13.499|
FSB_A<24> |FSB_D<31> | 13.204|
FSB_A<25> |CPU_nSTERM | 11.667|
FSB_A<25> |FSB_D<0> | 13.940|
FSB_A<25> |FSB_D<1> | 14.071|
FSB_A<25> |FSB_D<2> | 14.385|
FSB_A<25> |FSB_D<3> | 13.953|
FSB_A<25> |FSB_D<4> | 13.865|
FSB_A<25> |FSB_D<5> | 13.786|
FSB_A<25> |FSB_D<6> | 13.698|
FSB_A<25> |FSB_D<7> | 13.882|
FSB_A<25> |FSB_D<8> | 13.204|
FSB_A<25> |FSB_D<9> | 13.495|
FSB_A<25> |FSB_D<10> | 13.455|
FSB_A<25> |FSB_D<11> | 13.614|
FSB_A<25> |FSB_D<12> | 13.641|
FSB_A<25> |FSB_D<13> | 13.690|
FSB_A<25> |FSB_D<14> | 13.582|
FSB_A<25> |FSB_D<15> | 13.443|
FSB_A<25> |FSB_D<16> | 13.279|
FSB_A<25> |FSB_D<17> | 14.297|
FSB_A<25> |FSB_D<18> | 13.267|
FSB_A<25> |FSB_D<19> | 13.147|
FSB_A<25> |FSB_D<20> | 13.271|
FSB_A<25> |FSB_D<21> | 13.378|
FSB_A<25> |FSB_D<22> | 13.365|
FSB_A<25> |FSB_D<23> | 13.258|
FSB_A<25> |FSB_D<24> | 13.321|
FSB_A<25> |FSB_D<25> | 13.553|
FSB_A<25> |FSB_D<26> | 13.475|
FSB_A<25> |FSB_D<27> | 13.252|
FSB_A<25> |FSB_D<28> | 13.897|
FSB_A<25> |FSB_D<29> | 14.303|
FSB_A<25> |FSB_D<30> | 14.717|
FSB_A<25> |FSB_D<31> | 14.422|
FSB_A<28> |CPU_nSTERM | 11.769|
FSB_A<28> |FSB_D<0> | 14.042|
FSB_A<28> |FSB_D<1> | 14.173|
FSB_A<28> |FSB_D<2> | 14.487|
FSB_A<28> |FSB_D<3> | 14.055|
FSB_A<28> |FSB_D<4> | 13.967|
FSB_A<28> |FSB_D<5> | 13.888|
FSB_A<28> |FSB_D<6> | 13.800|
FSB_A<28> |FSB_D<7> | 13.984|
FSB_A<28> |FSB_D<8> | 13.306|
FSB_A<28> |FSB_D<9> | 13.597|
FSB_A<28> |FSB_D<10> | 13.557|
FSB_A<28> |FSB_D<11> | 13.716|
FSB_A<28> |FSB_D<12> | 13.743|
FSB_A<28> |FSB_D<13> | 13.792|
FSB_A<28> |FSB_D<14> | 13.684|
FSB_A<28> |FSB_D<15> | 13.545|
FSB_A<28> |FSB_D<16> | 13.381|
FSB_A<28> |FSB_D<17> | 14.399|
FSB_A<28> |FSB_D<18> | 13.369|
FSB_A<28> |FSB_D<19> | 13.249|
FSB_A<28> |FSB_D<20> | 13.373|
FSB_A<28> |FSB_D<21> | 13.480|
FSB_A<28> |FSB_D<22> | 13.467|
FSB_A<28> |FSB_D<23> | 13.360|
FSB_A<28> |FSB_D<24> | 13.423|
FSB_A<28> |FSB_D<25> | 13.655|
FSB_A<28> |FSB_D<26> | 13.577|
FSB_A<28> |FSB_D<27> | 13.354|
FSB_A<28> |FSB_D<28> | 13.999|
FSB_A<28> |FSB_D<29> | 14.405|
FSB_A<28> |FSB_D<30> | 14.819|
FSB_A<28> |FSB_D<31> | 14.524|
FSB_A<30> |CPU_nSTERM | 11.569|
FSB_A<30> |FSB_D<0> | 13.805|
FSB_A<30> |FSB_D<1> | 13.936|
FSB_A<30> |FSB_D<2> | 14.250|
FSB_A<30> |FSB_D<3> | 13.818|
FSB_A<30> |FSB_D<4> | 13.730|
FSB_A<30> |FSB_D<5> | 13.651|
FSB_A<30> |FSB_D<6> | 13.563|
FSB_A<30> |FSB_D<7> | 13.747|
FSB_A<30> |FSB_D<8> | 13.069|
FSB_A<30> |FSB_D<9> | 13.360|
FSB_A<30> |FSB_D<10> | 13.320|
FSB_A<30> |FSB_D<11> | 13.479|
FSB_A<30> |FSB_D<12> | 13.506|
FSB_A<30> |FSB_D<13> | 13.555|
FSB_A<30> |FSB_D<14> | 13.447|
FSB_A<30> |FSB_D<15> | 13.308|
FSB_A<30> |FSB_D<16> | 13.144|
FSB_A<30> |FSB_D<17> | 14.162|
FSB_A<30> |FSB_D<18> | 13.132|
FSB_A<30> |FSB_D<19> | 13.012|
FSB_A<30> |FSB_D<20> | 13.136|
FSB_A<30> |FSB_D<21> | 13.243|
FSB_A<30> |FSB_D<22> | 13.230|
FSB_A<30> |FSB_D<23> | 13.123|
FSB_A<30> |FSB_D<24> | 13.186|
FSB_A<30> |FSB_D<25> | 13.418|
FSB_A<30> |FSB_D<26> | 13.340|
FSB_A<30> |FSB_D<27> | 13.117|
FSB_A<30> |FSB_D<28> | 13.762|
FSB_A<30> |FSB_D<29> | 14.168|
FSB_A<30> |FSB_D<30> | 14.582|
FSB_A<30> |FSB_D<31> | 14.287|
---------------+---------------+---------+
Analysis completed Tue Nov 02 00:33:37 2021
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 164 MB
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