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<title>CPLD Timing Report (Text)</title><PRE><FONT FACE="Courier New", monotype><p align=left><b>CPLD Timing Report (Text)</b></p><b><center>Mon Mar 28 09:30:32 2022</center></b><br><hr><br> Performance Summary Report<br> --------------------------<br><br>Design: WarpSE<br>Device: XC95144XL-10-TQ100<br>Speed File: Version 3.0<br>Program: Timing Report Generator: version P.20131013<br>Date: Mon Mar 28 09:28:06 2022<br><br>Timing Constraint Summary:<br><br>TS_CLK_IOB=PERIOD:CLK_IOB:142.857nS:HIGH:71.428nS N/A<br>TS_CLK_FSB=PERIOD:CLK_FSB:40.000nS:HIGH:20.000nS Met<br>TS_CLK2X_IOB=PERIOD:CLK2X_IOB:66.666nS:HIGH:33.333nS Met<br><br>Performance Summary:<br><br>Pad to Pad (tPD) : 11.0ns (1 macrocell levels)<br>Pad 'A_FSB<11>' to Pad 'RA<1>' <br><br>Clock net 'CLK_IOB' path delays:<br><br>Setup to Clock at the Pad (tSU) : 6.5ns (0 macrocell levels)<br>Data signal 'E_IOB' to DFF D input Pin at 'iobm/Er.D'<br>Clock pad 'CLK_IOB' (GCK)<br><br> Minimum Clock Period: 9.0ns<br> Maximum Internal Clock Speed: 111.1Mhz<br> (Limited by Clock Pulse Width)<br><br>Clock net 'CLK_FSB' path delays:<br><br>Clock Pad to Output Pad (tCO) : 14.5ns (2 macrocell levels)<br>Clock Pad 'CLK_FSB' to Output Pad 'RA<1>' &nb
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