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Warp-SE/cpld/XC95144XL/MXSE.rpt

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cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Prototype
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Design Name: MXSE Date: 3-27-2022, 10:08AM
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Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
Prototype
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115/144 ( 80%) 458 /720 ( 64%) 258/432 ( 60%) 89 /144 ( 62%) 74 /81 ( 91%)
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** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
Prototype
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FB1 18/18* 21/54 23/90 11/11*
FB2 13/18 9/54 12/90 8/10
FB3 7/18 38/54 81/90 10/10*
FB4 18/18* 41/54 41/90 10/10*
FB5 14/18 42/54 81/90 8/10
FB6 18/18* 34/54 64/90 10/10*
FB7 15/18 36/54 75/90 10/10*
FB8 12/18 37/54 81/90 7/10
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----- ----- ----- -----
Prototype
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115/144 258/432 458/720 74/81
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* - Resource is exhausted
** Global Control Resources **
Signal 'CLK2X_IOB' mapped onto global clock net GCK1.
Signal 'CLK_IOB' mapped onto global clock net GCK2.
Signal 'CLK_FSB' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Prototype
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Input : 36 36 | I/O : 68 73
Output : 35 35 | GCK/IO : 3 3
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Bidirectional : 0 0 | GTS/IO : 3 4
GCK : 3 3 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Prototype
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Total 74 74
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** Power Data **
Prototype
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There are 115 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'MXSE.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK2X_IOB' based upon the LOC
constraint 'P22'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK_FSB' based upon the LOC
constraint 'P27'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK_IOB' based upon the LOC
constraint 'P23'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
Prototype
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WARNING:Cpld:1007 - Removing unused input(s) 'SW<2>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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************************* Summary of Mapped Logic ************************
Prototype
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** 35 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
nDTACK_FSB 23 32 FB3_9 28 I/O O STD FAST RESET
nROMWE 1 2 FB3_17 34 I/O O STD FAST
nAoutOE 3 4 FB4_2 87 I/O O STD FAST SET
nDoutOE 2 3 FB4_5 89 I/O O STD FAST RESET
nDinOE 3 7 FB4_6 90 I/O O STD FAST
nVPA_FSB 1 2 FB4_11 93 I/O O STD FAST
nROMCS 3 6 FB5_2 35 I/O O STD FAST
nCAS 1 1 FB5_5 36 I/O O STD FAST RESET
nOE 1 2 FB5_6 37 I/O O STD FAST
RA<4> 2 3 FB5_9 40 I/O O STD FAST
RA<3> 2 3 FB5_11 41 I/O O STD FAST
RA<5> 2 3 FB5_12 42 I/O O STD FAST
RA<2> 2 3 FB5_14 43 I/O O STD FAST
RA<6> 2 3 FB5_15 46 I/O O STD FAST
nVMA_IOB 3 10 FB6_2 74 I/O O STD FAST RESET
nLDS_IOB 4 6 FB6_9 79 I/O O STD FAST RESET
nUDS_IOB 4 6 FB6_11 80 I/O O STD FAST RESET
nAS_IOB 3 4 FB6_12 81 I/O O STD FAST RESET
nADoutLE1 2 3 FB6_14 82 I/O O STD FAST SET
nADoutLE0 1 2 FB6_15 85 I/O O STD FAST
nDinLE 1 2 FB6_17 86 I/O O STD FAST RESET
RA<1> 2 3 FB7_2 50 I/O O STD FAST
RA<7> 2 3 FB7_5 52 I/O O STD FAST
RA<0> 2 3 FB7_6 53 I/O O STD FAST
RA<8> 7 7 FB7_8 54 I/O O STD FAST
RA<10> 1 1 FB7_9 55 I/O O STD FAST
RA<9> 2 3 FB7_11 56 I/O O STD FAST
CLK25EN 1 1 FB7_12 58 I/O O STD FAST
CLK20EN 1 1 FB7_14 59 I/O O STD FAST
RA<11> 1 1 FB8_2 63 I/O O STD FAST
nRAS 3 8 FB8_5 64 I/O O STD FAST
nRAMLWE 1 5 FB8_6 65 I/O O STD FAST
nRAMUWE 1 5 FB8_8 66 I/O O STD FAST
nBERR_FSB 3 9 FB8_12 70 I/O O STD FAST
nBR_IOB 1 6 FB8_15 72 I/O O STD FAST SET
** 80 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
ram/BACTr 1 2 FB1_1 STD RESET
iobm/RESrr 1 1 FB1_2 STD RESET
iobm/RESrf 1 1 FB1_3 STD RESET
fsb/ASrf 1 1 FB1_4 STD RESET
cnt/RefCnt<2> 1 2 FB1_5 STD RESET
cnt/RefCnt<1> 1 1 FB1_6 STD RESET
RefAck 1 2 FB1_7 STD RESET
RESr2 1 1 FB1_8 STD RESET
RESr1 1 1 FB1_9 STD RESET
RESr0 1 1 FB1_10 STD RESET
IPL2r1 1 1 FB1_11 STD RESET
IPL2r0 1 1 FB1_12 STD RESET
ALE0S 1 2 FB1_13 STD RESET
$OpTx$FX_DC$708 1 2 FB1_14 STD
iobs/IOU1 2 2 FB1_15 STD RESET
iobs/IOL1 2 2 FB1_16 STD RESET
iobm/IOS_FSM_FFd1 2 3 FB1_17 STD RESET
IOU0 3 5 FB1_18 STD RESET
iobs/IOACTr 1 1 FB2_6 STD RESET
iobm/VPArr 1 1 FB2_7 STD RESET
iobm/VPArf 1 1 FB2_8 STD RESET
iobm/IOREQr 1 1 FB2_9 STD RESET
iobm/Er2 1 1 FB2_10 STD RESET
iobm/Er 1 1 FB2_11 STD RESET
iobm/DTACKrr 1 1 FB2_12 STD RESET
iobm/DTACKrf 1 1 FB2_13 STD RESET
iobm/BGr1 1 1 FB2_14 STD RESET
iobm/BGr0 1 1 FB2_15 STD RESET
iobm/BERRrr 1 1 FB2_16 STD RESET
iobm/BERRrf 1 1 FB2_17 STD RESET
cnt/RefCnt<0> 0 0 FB2_18 STD RESET
fsb/Ready1r 8 18 FB3_1 STD RESET
iobs/IORW1 17 20 FB3_3 STD RESET
fsb/Ready2r 9 22 FB3_5 STD RESET
fsb/VPA 22 31 FB3_15 STD RESET
iobs/Clear1 1 3 FB3_18 STD RESET
cnt/RefCnt<6> 1 6 FB4_1 STD RESET
cnt/RefCnt<5> 1 5 FB4_3 STD RESET
cnt/RefCnt<4> 1 4 FB4_4 STD RESET
cnt/RefCnt<3> 1 3 FB4_7 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
iobs/PS_FSM_FFd1 2 3 FB4_8 STD RESET
fsb/BERR1r 2 4 FB4_9 STD RESET
cs/nOverlay1 2 3 FB4_10 STD RESET
cnt/RefDone 2 10 FB4_12 STD RESET
cs/nOverlay0 3 8 FB4_13 STD RESET
cnt/TimeoutBPre 3 11 FB4_14 STD RESET
TimeoutA 3 10 FB4_15 STD RESET
IOL0 3 5 FB4_16 STD RESET
iobs/IOReady 4 8 FB4_17 STD RESET
BERR_IOBS 4 8 FB4_18 STD RESET
ram/RASEL 20 15 FB5_1 STD RESET
cnt/RefCnt<7> 1 7 FB5_3 STD RESET
ram/RAMDIS2 7 15 FB5_4 STD RESET
ram/RAMDIS1 18 15 FB5_8 STD RESET
iobs/Load1 15 19 FB5_13 STD RESET
ram/Once 5 10 FB5_16 STD RESET
iobm/ETACK 1 6 FB6_1 STD RESET
iobm/IOS_FSM_FFd3 3 6 FB6_3 STD RESET
iobm/ES<3> 3 6 FB6_4 STD RESET
iobm/ES<1> 3 4 FB6_5 STD RESET
iobm/ES<0> 3 7 FB6_6 STD RESET
ALE0M 3 5 FB6_7 STD RESET
iobm/ES<4> 4 7 FB6_8 STD RESET
iobm/IOS_FSM_FFd2 5 11 FB6_10 STD RESET
iobm/ES<2> 5 7 FB6_13 STD RESET
IOACT 7 13 FB6_16 STD RESET
IOBERR 9 13 FB6_18 STD RESET
ram/RAMReady 16 15 FB7_1 STD RESET
TimeoutB 3 12 FB7_3 STD RESET
fsb/Ready0r 3 8 FB7_4 STD RESET
ram/RS_FSM_FFd1 5 10 FB7_7 STD RESET
$OpTx$$OpTx$FX_DC$182_INV$783 6 8 FB7_10 STD
ram/RS_FSM_FFd3 11 14 FB7_13 STD RESET
ram/RS_FSM_FFd2 13 14 FB7_17 STD RESET
iobs/PS_FSM_FFd2 15 20 FB8_4 STD RESET
RESDone 1 3 FB8_7 STD RESET
IOREQ 15 20 FB8_9 STD RESET
iobs/Once 18 19 FB8_14 STD RESET
fsb/BERR0r 3 8 FB8_16 STD RESET
IORW0 19 21 FB8_18 STD RESET
** 39 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
A_FSB<13> FB1_2 11 I/O I
A_FSB<14> FB1_3 12 I/O I
A_FSB<15> FB1_5 13 I/O I
A_FSB<16> FB1_6 14 I/O I
A_FSB<17> FB1_8 15 I/O I
A_FSB<18> FB1_9 16 I/O I
A_FSB<19> FB1_11 17 I/O I
A_FSB<20> FB1_12 18 I/O I
A_FSB<21> FB1_14 19 I/O I
A_FSB<22> FB1_15 20 I/O I
CLK2X_IOB FB1_17 22 GCK/I/O GCK
A_FSB<5> FB2_6 2 GTS/I/O I
A_FSB<6> FB2_8 3 GTS/I/O I
A_FSB<7> FB2_9 4 GTS/I/O I
A_FSB<8> FB2_11 6 I/O I
A_FSB<9> FB2_12 7 I/O I
A_FSB<10> FB2_14 8 I/O I
A_FSB<11> FB2_15 9 I/O I
A_FSB<12> FB2_17 10 I/O I
CLK_IOB FB3_2 23 GCK/I/O GCK/I
A_FSB<23> FB3_5 24 I/O I
E_IOB FB3_6 25 I/O I
CLK_FSB FB3_8 27 GCK/I/O GCK
nWE_FSB FB3_11 29 I/O I
nLDS_FSB FB3_12 30 I/O I
nAS_FSB FB3_14 32 I/O I
nUDS_FSB FB3_15 33 I/O I
nRES FB4_8 91 I/O I
nIPL2 FB4_9 92 I/O I
A_FSB<1> FB4_12 94 I/O I
A_FSB<2> FB4_14 95 I/O I
A_FSB<3> FB4_15 96 I/O I
A_FSB<4> FB4_17 97 I/O I
nBERR_IOB FB6_5 76 I/O I
nVPA_IOB FB6_6 77 I/O I
nDTACK_IOB FB6_8 78 I/O I
SW<1> FB7_15 60 I/O I
SW<0> FB7_17 61 I/O I
nBG_IOB FB8_17 73 I/O I
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Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Prototype
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Number of function block inputs used/remaining: 21/33
Number of signals used by logic mapping into function block: 21
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Prototype
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ram/BACTr 1 0 0 4 FB1_1 (b) (b)
iobm/RESrr 1 0 0 4 FB1_2 11 I/O I
iobm/RESrf 1 0 0 4 FB1_3 12 I/O I
fsb/ASrf 1 0 0 4 FB1_4 (b) (b)
cnt/RefCnt<2> 1 0 0 4 FB1_5 13 I/O I
cnt/RefCnt<1> 1 0 0 4 FB1_6 14 I/O I
RefAck 1 0 0 4 FB1_7 (b) (b)
RESr2 1 0 0 4 FB1_8 15 I/O I
RESr1 1 0 0 4 FB1_9 16 I/O I
RESr0 1 0 0 4 FB1_10 (b) (b)
IPL2r1 1 0 0 4 FB1_11 17 I/O I
IPL2r0 1 0 0 4 FB1_12 18 I/O I
ALE0S 1 0 0 4 FB1_13 (b) (b)
$OpTx$FX_DC$708 1 0 0 4 FB1_14 19 I/O I
iobs/IOU1 2 0 0 3 FB1_15 20 I/O I
iobs/IOL1 2 0 0 3 FB1_16 (b) (b)
iobm/IOS_FSM_FFd1 2 0 0 3 FB1_17 22 GCK/I/O GCK
IOU0 3 0 0 2 FB1_18 (b) (b)
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Signals Used by Logic in Function Block
Prototype
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1: IPL2r0 8: iobm/IOS_FSM_FFd2 15: nAS_FSB
2: RESr0 9: iobm/IOS_FSM_FFd3 16: nIPL2
3: RESr1 10: iobs/IOU1 17: nLDS_FSB
4: cnt/RefCnt<0> 11: iobs/Load1 18: nRES
5: cnt/RefCnt<1> 12: iobs/PS_FSM_FFd1 19: nUDS_FSB
6: fsb/ASrf 13: iobs/PS_FSM_FFd2 20: ram/RS_FSM_FFd1
7: iobm/IOS_FSM_FFd1 14: nADoutLE1 21: ram/RS_FSM_FFd2
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Prototype
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ram/BACTr .....X........X......................... 2
iobm/RESrr .................X...................... 1
iobm/RESrf .................X...................... 1
fsb/ASrf ..............X......................... 1
cnt/RefCnt<2> ...XX................................... 2
cnt/RefCnt<1> ...X.................................... 1
RefAck ...................XX................... 2
RESr2 ..X..................................... 1
RESr1 .X...................................... 1
RESr0 .................X...................... 1
IPL2r1 X....................................... 1
IPL2r0 ...............X........................ 1
ALE0S ...........XX........................... 2
$OpTx$FX_DC$708 .....X........X......................... 2
iobs/IOU1 ..........X.......X..................... 2
iobs/IOL1 ..........X.....X....................... 2
iobm/IOS_FSM_FFd1 ......XXX............................... 3
IOU0 .........X.XXX....X..................... 5
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0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Prototype
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Number of function block inputs used/remaining: 9/45
Number of signals used by logic mapping into function block: 9
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 99 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 1 GTS/I/O
Prototype
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iobs/IOACTr 1 0 0 4 FB2_6 2 GTS/I/O I
iobm/VPArr 1 0 0 4 FB2_7 (b) (b)
iobm/VPArf 1 0 0 4 FB2_8 3 GTS/I/O I
iobm/IOREQr 1 0 0 4 FB2_9 4 GTS/I/O I
iobm/Er2 1 0 0 4 FB2_10 (b) (b)
iobm/Er 1 0 0 4 FB2_11 6 I/O I
iobm/DTACKrr 1 0 0 4 FB2_12 7 I/O I
iobm/DTACKrf 1 0 0 4 FB2_13 (b) (b)
iobm/BGr1 1 0 0 4 FB2_14 8 I/O I
iobm/BGr0 1 0 0 4 FB2_15 9 I/O I
iobm/BERRrr 1 0 0 4 FB2_16 (b) (b)
iobm/BERRrf 1 0 0 4 FB2_17 10 I/O I
cnt/RefCnt<0> 0 0 0 5 FB2_18 (b) (b)
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Signals Used by Logic in Function Block
Prototype
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1: E_IOB 4: iobm/BGr0 7: nBG_IOB
2: IOACT 5: iobm/Er 8: nDTACK_IOB
3: IOREQ 6: nBERR_IOB 9: nVPA_IOB
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Prototype
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iobs/IOACTr .X...................................... 1
iobm/VPArr ........X............................... 1
iobm/VPArf ........X............................... 1
iobm/IOREQr ..X..................................... 1
iobm/Er2 ....X................................... 1
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iobm/Er X....................................... 1
Prototype
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iobm/DTACKrr .......X................................ 1
iobm/DTACKrf .......X................................ 1
iobm/BGr1 ...X.................................... 1
iobm/BGr0 ......X................................. 1
iobm/BERRrr .....X.................................. 1
iobm/BERRrf .....X.................................. 1
cnt/RefCnt<0> ........................................ 0
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0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Prototype
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Number of function block inputs used/remaining: 38/16
Number of signals used by logic mapping into function block: 38
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Prototype
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fsb/Ready1r 8 4<- \/1 0 FB3_1 (b) (b)
(unused) 0 0 \/5 0 FB3_2 23 GCK/I/O GCK/I
iobs/IORW1 17 12<- 0 0 FB3_3 (b) (b)
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(unused) 0 0 /\5 0 FB3_4 (b) (b)
Prototype
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fsb/Ready2r 9 5<- /\1 0 FB3_5 24 I/O I
(unused) 0 0 /\5 0 FB3_6 25 I/O I
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(unused) 0 0 \/3 2 FB3_7 (b) (b)
(unused) 0 0 \/5 0 FB3_8 27 GCK/I/O GCK
nDTACK_FSB 23 18<- 0 0 FB3_9 28 I/O O
(unused) 0 0 /\5 0 FB3_10 (b) (b)
(unused) 0 0 /\5 0 FB3_11 29 I/O I
Prototype
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(unused) 0 0 0 5 FB3_12 30 I/O I
(unused) 0 0 \/5 0 FB3_13 (b) (b)
(unused) 0 0 \/5 0 FB3_14 32 I/O I
fsb/VPA 22 17<- 0 0 FB3_15 33 I/O I
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(unused) 0 0 /\5 0 FB3_16 (b) (b)
Prototype
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nROMWE 1 0 /\2 2 FB3_17 34 I/O O
iobs/Clear1 1 0 \/4 0 FB3_18 (b) (b)
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Signals Used by Logic in Function Block
Prototype
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1: $OpTx$$OpTx$FX_DC$182_INV$783 14: A_FSB<21> 27: fsb/Ready2r
2: $OpTx$FX_DC$708 15: A_FSB<22> 28: fsb/VPA
3: A_FSB<10> 16: A_FSB<23> 29: iobs/IORW1
4: A_FSB<11> 17: A_FSB<8> 30: iobs/IOReady
5: A_FSB<12> 18: A_FSB<9> 31: iobs/Once
6: A_FSB<13> 19: BERR_IOBS 32: iobs/PS_FSM_FFd1
7: A_FSB<14> 20: SW<1> 33: iobs/PS_FSM_FFd2
8: A_FSB<15> 21: TimeoutA 34: nADoutLE1
9: A_FSB<16> 22: cs/nOverlay1 35: nAS_FSB
10: A_FSB<17> 23: fsb/ASrf 36: nBR_IOB
11: A_FSB<18> 24: fsb/BERR0r 37: nDTACK_FSB
12: A_FSB<19> 25: fsb/BERR1r 38: nWE_FSB
13: A_FSB<20> 26: fsb/Ready1r
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Prototype
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fsb/Ready1r .....XX.XXXXXXXX...X.XX..X...X...XX..X.. 18
iobs/IORW1 .....XX.XXXXXXXX...X.XX.....X.XXXXX..X.. 20
fsb/Ready2r ..XXXXXXXXXXXXXXXX..XXX...X.......X..X.. 22
nDTACK_FSB X.XXXXXXXXXXXXXXXXXXXXXXXXX..X...XXXXX.. 32
fsb/VPA XXXXXXXXXXXXXXXXXXXXXX.XXXXX.X...X.X.X.. 31
nROMWE ..................................X..X.. 2
iobs/Clear1 ...............................XXX...... 3
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0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Prototype
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Number of function block inputs used/remaining: 41/13
Number of signals used by logic mapping into function block: 41
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Prototype
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cnt/RefCnt<6> 1 0 0 4 FB4_1 (b) (b)
nAoutOE 3 0 0 2 FB4_2 87 I/O O
cnt/RefCnt<5> 1 0 0 4 FB4_3 (b) (b)
cnt/RefCnt<4> 1 0 0 4 FB4_4 (b) (b)
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nDoutOE 2 0 0 3 FB4_5 89 I/O O
Prototype
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nDinOE 3 0 0 2 FB4_6 90 I/O O
cnt/RefCnt<3> 1 0 0 4 FB4_7 (b) (b)
iobs/PS_FSM_FFd1 2 0 0 3 FB4_8 91 I/O I
fsb/BERR1r 2 0 0 3 FB4_9 92 I/O I
cs/nOverlay1 2 0 0 3 FB4_10 (b) (b)
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nVPA_FSB 1 0 0 4 FB4_11 93 I/O O
Prototype
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cnt/RefDone 2 0 0 3 FB4_12 94 I/O I
cs/nOverlay0 3 0 0 2 FB4_13 (b) (b)
cnt/TimeoutBPre 3 0 0 2 FB4_14 95 I/O I
TimeoutA 3 0 0 2 FB4_15 96 I/O I
IOL0 3 0 0 2 FB4_16 (b) (b)
iobs/IOReady 4 0 0 1 FB4_17 97 I/O I
BERR_IOBS 4 0 0 1 FB4_18 (b) (b)
Move directories
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Signals Used by Logic in Function Block
Prototype
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1: A_FSB<20> 15: cnt/RefCnt<4> 29: iobs/IOACTr
2: A_FSB<21> 16: cnt/RefCnt<5> 30: iobs/IOL1
3: A_FSB<22> 17: cnt/RefCnt<6> 31: iobs/IOReady
4: A_FSB<23> 18: cnt/RefCnt<7> 32: iobs/Once
5: BERR_IOBS 19: cnt/RefDone 33: iobs/PS_FSM_FFd1
6: IOBERR 20: cnt/TimeoutBPre 34: iobs/PS_FSM_FFd2
7: IORW0 21: cs/nOverlay0 35: nADoutLE1
8: RefAck 22: fsb/ASrf 36: nAS_FSB
9: SW<1> 23: fsb/BERR1r 37: nAS_IOB
10: TimeoutA 24: fsb/VPA 38: nAoutOE
11: cnt/RefCnt<0> 25: iobm/BGr0 39: nLDS_FSB
12: cnt/RefCnt<1> 26: iobm/BGr1 40: nRES
13: cnt/RefCnt<2> 27: iobm/IOS_FSM_FFd2 41: nWE_FSB
14: cnt/RefCnt<3> 28: iobm/IOS_FSM_FFd3
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
cnt/RefCnt<6> ..........XXXXXX.................................. 6
nAoutOE ........................XX..........XX............ 4
cnt/RefCnt<5> ..........XXXXX................................... 5
cnt/RefCnt<4> ..........XXXX.................................... 4
nDoutOE ......X...................XX...................... 3
nDinOE XXXX....X..........................X....X......... 7
cnt/RefCnt<3> ..........XXX..................................... 3
iobs/PS_FSM_FFd1 ............................X...XX................ 3
fsb/BERR1r ....X................XX............X.............. 4
cs/nOverlay1 ....................XX.............X.............. 3
nVPA_FSB .......................X...........X.............. 2
cnt/RefDone .......X..XXXXXXXXX............................... 10
cs/nOverlay0 XXXX................XX.............X...X.......... 8
cnt/TimeoutBPre ..........XXXXXXXX.X.X.............X.............. 11
TimeoutA .........XXXXXXXX....X.............X.............. 10
IOL0 .............................X..XXX...X........... 5
iobs/IOReady .....X...............X......X.XX.XXX.............. 8
BERR_IOBS ....XX...............X......X..X.XXX.............. 8
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
Move directories
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*********************************** FB5 ***********************************
Prototype
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Number of function block inputs used/remaining: 42/12
Number of signals used by logic mapping into function block: 42
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Prototype
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ram/RASEL 20 15<- 0 0 FB5_1 (b) (b)
nROMCS 3 3<- /\5 0 FB5_2 35 I/O O
cnt/RefCnt<7> 1 0 /\3 1 FB5_3 (b) (b)
ram/RAMDIS2 7 2<- 0 0 FB5_4 (b) (b)
nCAS 1 0 /\2 2 FB5_5 36 I/O O
nOE 1 0 \/3 1 FB5_6 37 I/O O
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(unused) 0 0 \/5 0 FB5_7 (b) (b)
Prototype
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ram/RAMDIS1 18 13<- 0 0 FB5_8 39 I/O (b)
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RA<4> 2 2<- /\5 0 FB5_9 40 I/O O
(unused) 0 0 /\2 3 FB5_10 (b) (b)
RA<3> 2 0 \/2 1 FB5_11 41 I/O O
RA<5> 2 2<- \/5 0 FB5_12 42 I/O O
Prototype
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iobs/Load1 15 10<- 0 0 FB5_13 (b) (b)
RA<2> 2 2<- /\5 0 FB5_14 43 I/O O
RA<6> 2 0 /\2 1 FB5_15 46 I/O O
ram/Once 5 0 0 0 FB5_16 (b) (b)
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(unused) 0 0 \/5 0 FB5_17 49 I/O (b)
Prototype
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(unused) 0 0 \/5 0 FB5_18 (b) (b)
Move directories
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Signals Used by Logic in Function Block
Prototype
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1: A_FSB<12> 15: A_FSB<5> 29: fsb/ASrf
2: A_FSB<13> 16: A_FSB<6> 30: iobs/Once
3: A_FSB<14> 17: A_FSB<7> 31: iobs/PS_FSM_FFd1
4: A_FSB<15> 18: SW<1> 32: iobs/PS_FSM_FFd2
5: A_FSB<16> 19: cnt/RefCnt<0> 33: nADoutLE1
6: A_FSB<17> 20: cnt/RefCnt<1> 34: nAS_FSB
7: A_FSB<18> 21: cnt/RefCnt<2> 35: nWE_FSB
8: A_FSB<19> 22: cnt/RefCnt<3> 36: ram/BACTr
9: A_FSB<20> 23: cnt/RefCnt<4> 37: ram/Once
10: A_FSB<21> 24: cnt/RefCnt<5> 38: ram/RAMDIS2
11: A_FSB<22> 25: cnt/RefCnt<6> 39: ram/RASEL
12: A_FSB<23> 26: cnt/RefCnt<7> 40: ram/RS_FSM_FFd1
13: A_FSB<3> 27: cnt/RefDone 41: ram/RS_FSM_FFd2
14: A_FSB<4> 28: cs/nOverlay1 42: ram/RS_FSM_FFd3
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
ram/RASEL .........XXX...........XXXXXX....X.XX..XXX........ 15
nROMCS ........XXXX.....X.........X...................... 6
cnt/RefCnt<7> ..................XXXXXXX......................... 7
ram/RAMDIS2 .........XXX...........XXXXXX....X..XX.XXX........ 15
nCAS ......................................X........... 1
nOE .................................XX............... 2
ram/RAMDIS1 .........XXX...........XXXXXX....X.XX..XXX........ 15
RA<4> ..X...........X.......................X........... 3
RA<3> .X...........X........................X........... 3
RA<5> ...X...........X......................X........... 3
iobs/Load1 .XX.XXXXXXXX.....X.........XXXXXXXX............... 19
RA<2> X...........X.........................X........... 3
RA<6> ....X...........X.....................X........... 3
ram/Once .........XXX...............XX....X..X..XXX........ 10
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
Move directories
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*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 34/20
Number of signals used by logic mapping into function block: 34
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Prototype
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iobm/ETACK 1 0 /\4 0 FB6_1 (b) (b)
nVMA_IOB 3 0 0 2 FB6_2 74 I/O O
iobm/IOS_FSM_FFd3 3 0 0 2 FB6_3 (b) (b)
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iobm/ES<3> 3 0 0 2 FB6_4 (b) (b)
iobm/ES<1> 3 0 0 2 FB6_5 76 I/O I
iobm/ES<0> 3 0 0 2 FB6_6 77 I/O I
Prototype
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ALE0M 3 0 0 2 FB6_7 (b) (b)
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iobm/ES<4> 4 0 0 1 FB6_8 78 I/O I
nLDS_IOB 4 0 0 1 FB6_9 79 I/O O
Prototype
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iobm/IOS_FSM_FFd2 5 0 0 0 FB6_10 (b) (b)
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nUDS_IOB 4 0 0 1 FB6_11 80 I/O O
Prototype
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nAS_IOB 3 0 0 2 FB6_12 81 I/O O
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iobm/ES<2> 5 0 0 0 FB6_13 (b) (b)
nADoutLE1 2 0 0 3 FB6_14 82 I/O O
nADoutLE0 1 0 \/1 3 FB6_15 85 I/O O
Prototype
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IOACT 7 2<- 0 0 FB6_16 (b) (b)
nDinLE 1 0 /\1 3 FB6_17 86 I/O O
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IOBERR 9 4<- 0 0 FB6_18 (b) (b)
Signals Used by Logic in Function Block
1: ALE0M 13: iobm/ES<0> 24: iobm/IOS_FSM_FFd3
Prototype
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2: ALE0S 14: iobm/ES<1> 25: iobm/RESrf
3: CLK_IOB 15: iobm/ES<2> 26: iobm/RESrr
4: IOACT 16: iobm/ES<3> 27: iobm/VPArf
5: IOBERR 17: iobm/ES<4> 28: iobm/VPArr
6: IOL0 18: iobm/ETACK 29: iobs/Clear1
7: IORW0 19: iobm/Er 30: iobs/Load1
8: IOU0 20: iobm/Er2 31: nADoutLE1
9: iobm/BERRrf 21: iobm/IOREQr 32: nAoutOE
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10: iobm/BERRrr 22: iobm/IOS_FSM_FFd1 33: nBERR_IOB
11: iobm/DTACKrf 23: iobm/IOS_FSM_FFd2 34: nVMA_IOB
12: iobm/DTACKrr
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
iobm/ETACK ............XXXXX................X...... 6
Prototype
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nVMA_IOB ...X........XXXXX.........XX...X.X...... 10
iobm/IOS_FSM_FFd3 ..X.................XXXX.......X........ 6
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iobm/ES<3> ............XXXX..XX.................... 6
iobm/ES<1> ............XX....XX.................... 4
iobm/ES<0> ............XXXXX.XX.................... 7
Prototype
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ALE0M ....................XXXX.......X........ 5
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iobm/ES<4> ............XXXXX.XX.................... 7
Prototype
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nLDS_IOB .....XX..............XXX.......X........ 6
iobm/IOS_FSM_FFd2 ..X.....XXXX.....X...XXXXX.............. 11
nUDS_IOB ......XX.............XXX.......X........ 6
nAS_IOB .....................XXX.......X........ 4
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iobm/ES<2> ............XXXXX.XX.................... 7
Prototype
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nADoutLE1 ............................XXX......... 3
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nADoutLE0 XX...................................... 2
Prototype
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IOACT ..X.....XXXX.....X..XXXXXX.....X........ 13
nDinLE .....................XX................. 2
IOBERR ..X.X...XXXX.....X...XXXXX......X....... 13
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0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Prototype
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Number of function block inputs used/remaining: 36/18
Number of signals used by logic mapping into function block: 36
Move directories
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Prototype
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ram/RAMReady 16 11<- 0 0 FB7_1 (b) (b)
RA<1> 2 2<- /\5 0 FB7_2 50 I/O O
TimeoutB 3 0 /\2 0 FB7_3 (b) (b)
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fsb/Ready0r 3 0 0 2 FB7_4 (b) (b)
RA<7> 2 0 0 3 FB7_5 52 I/O O
RA<0> 2 0 0 3 FB7_6 53 I/O O
Prototype
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ram/RS_FSM_FFd1 5 0 0 0 FB7_7 (b) (b)
idk
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RA<8> 7 2<- 0 0 FB7_8 54 I/O O
Prototype
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RA<10> 1 0 /\2 2 FB7_9 55 I/O O
$OpTx$$OpTx$FX_DC$182_INV$783
6 1<- 0 0 FB7_10 (b) (b)
RA<9> 2 0 /\1 2 FB7_11 56 I/O O
CLK25EN 1 0 \/4 0 FB7_12 58 I/O O
ram/RS_FSM_FFd3 11 6<- 0 0 FB7_13 (b) (b)
CLK20EN 1 0 /\2 2 FB7_14 59 I/O O
(unused) 0 0 \/4 1 FB7_15 60 I/O I
(unused) 0 0 \/5 0 FB7_16 (b) (b)
ram/RS_FSM_FFd2 13 9<- \/1 0 FB7_17 61 I/O I
(unused) 0 0 \/5 0 FB7_18 (b) (b)
Move directories
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Signals Used by Logic in Function Block
Prototype
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1: A_FSB<10> 13: A_FSB<9> 25: cnt/TimeoutBPre
2: A_FSB<11> 14: SW<0> 26: cs/nOverlay1
3: A_FSB<17> 15: TimeoutB 27: fsb/ASrf
4: A_FSB<18> 16: cnt/RefCnt<0> 28: fsb/Ready0r
5: A_FSB<19> 17: cnt/RefCnt<1> 29: nAS_FSB
6: A_FSB<1> 18: cnt/RefCnt<2> 30: ram/BACTr
7: A_FSB<20> 19: cnt/RefCnt<3> 31: ram/Once
8: A_FSB<21> 20: cnt/RefCnt<4> 32: ram/RAMReady
9: A_FSB<22> 21: cnt/RefCnt<5> 33: ram/RASEL
10: A_FSB<23> 22: cnt/RefCnt<6> 34: ram/RS_FSM_FFd1
11: A_FSB<2> 23: cnt/RefCnt<7> 35: ram/RS_FSM_FFd2
12: A_FSB<8> 24: cnt/RefDone 36: ram/RS_FSM_FFd3
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Prototype
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ram/RAMReady .......XXX..........XXXX.XX.XXX..XXX.... 15
RA<1> .X........X.....................X....... 3
TimeoutB ..............XXXXXXXXX.X.X.X........... 12
fsb/Ready0r .......XXX...............XXXX..X........ 8
RA<7> ..X........X....................X....... 3
RA<0> X....X..........................X....... 3
ram/RS_FSM_FFd1 .......XXX...............XX.X.X..XXX.... 10
RA<8> ...X...XXX..X............X......X....... 7
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RA<10> .......X................................ 1
Prototype
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$OpTx$$OpTx$FX_DC$182_INV$783
......XXXX....X..........X.X...X........ 8
RA<9> ....X.X.........................X....... 3
CLK25EN .............X.......................... 1
ram/RS_FSM_FFd3 .......XXX..........XXXX.XX.X.X..XXX.... 14
CLK20EN .............X.......................... 1
ram/RS_FSM_FFd2 .......XXX..........XXXX.XX.XX...XXX.... 14
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0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Prototype
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Number of function block inputs used/remaining: 37/17
Number of signals used by logic mapping into function block: 37
Move directories
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Prototype
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(unused) 0 0 /\5 0 FB8_1 (b) (b)
RA<11> 1 0 /\4 0 FB8_2 63 I/O O
(unused) 0 0 \/5 0 FB8_3 (b) (b)
iobs/PS_FSM_FFd2 15 10<- 0 0 FB8_4 (b) (b)
nRAS 3 3<- /\5 0 FB8_5 64 I/O O
nRAMLWE 1 0 /\3 1 FB8_6 65 I/O O
RESDone 1 0 \/1 3 FB8_7 (b) (b)
nRAMUWE 1 1<- \/5 0 FB8_8 66 I/O O
IOREQ 15 10<- 0 0 FB8_9 67 I/O (b)
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(unused) 0 0 /\5 0 FB8_10 (b) (b)
Prototype
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(unused) 0 0 \/2 3 FB8_11 68 I/O (b)
nBERR_FSB 3 2<- \/4 0 FB8_12 70 I/O O
(unused) 0 0 \/5 0 FB8_13 (b) (b)
iobs/Once 18 13<- 0 0 FB8_14 71 I/O (b)
nBR_IOB 1 0 /\4 0 FB8_15 72 I/O O
fsb/BERR0r 3 0 0 2 FB8_16 (b) (b)
(unused) 0 0 \/5 0 FB8_17 73 I/O I
IORW0 19 14<- 0 0 FB8_18 (b) (b)
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Signals Used by Logic in Function Block
Prototype
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1: A_FSB<13> 14: IPL2r1 26: iobs/IOACTr
2: A_FSB<14> 15: RESDone 27: iobs/IORW1
3: A_FSB<16> 16: RESr0 28: iobs/Once
4: A_FSB<17> 17: RESr1 29: iobs/PS_FSM_FFd1
5: A_FSB<18> 18: RESr2 30: iobs/PS_FSM_FFd2
6: A_FSB<19> 19: RefAck 31: nADoutLE1
7: A_FSB<20> 20: SW<1> 32: nAS_FSB
8: A_FSB<21> 21: TimeoutB 33: nLDS_FSB
9: A_FSB<22> 22: cs/nOverlay1 34: nUDS_FSB
10: A_FSB<23> 23: fsb/ASrf 35: nWE_FSB
11: BERR_IOBS 24: fsb/BERR0r 36: ram/RAMDIS1
12: IORW0 25: fsb/BERR1r 37: ram/RAMDIS2
13: IPL2r0
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
RA<11> .....X.................................. 1
Prototype
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iobs/PS_FSM_FFd2 XXXXXXXXXX.........X.XX..X.XXXXX..X..... 20
nRAS .......XXX........X..X.........X...XX... 8
nRAMLWE ...............................XX.XXX... 5
RESDone ...............XXX...................... 3
nRAMUWE ...............................X.XXXX... 5
IOREQ XXXXXXXXXX.........X.XX..X.XXXXX..X..... 20
nBERR_FSB ......XXXXX.........X..XX......X........ 9
iobs/Once XXXXXXXXXX.........X.XX....XXXXX..X..... 19
nBR_IOB ............XXXXXX...................... 6
fsb/BERR0r ......XXXX..........X.XX.......X........ 8
IORW0 XXXXXXXXXX.X.......X.XX...XXXXXX..X..... 21
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0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
Prototype
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$OpTx$$OpTx$FX_DC$182_INV$783 <= ((NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT fsb/Ready0r AND NOT ram/RAMReady)
OR (A_FSB(23) AND TimeoutB)
OR (NOT A_FSB(22) AND TimeoutB)
OR (A_FSB(21) AND TimeoutB)
OR (NOT A_FSB(20) AND TimeoutB)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
NOT fsb/Ready0r AND NOT ram/RAMReady));
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Prototype
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$OpTx$FX_DC$708 <= (nAS_FSB AND NOT fsb/ASrf);
Move directories
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FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,CLK2X_IOB,'0','0');
Prototype
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ALE0M_D <= ((iobm/IOS_FSM_FFd2)
OR (iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd1)
OR (NOT iobm/IOS_FSM_FFd1 AND iobm/IOREQr AND NOT nAoutOE));
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FDCPE_ALE0S: FDCPE port map (ALE0S,ALE0S_D,CLK_FSB,'0','0');
ALE0S_D <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
FTCPE_BERR_IOBS: FTCPE port map (BERR_IOBS,BERR_IOBS_T,CLK_FSB,'0','0');
BERR_IOBS_T <= ((BERR_IOBS AND nAS_FSB AND NOT fsb/ASrf)
OR (iobs/Once AND BERR_IOBS AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/IOACTr AND NOT IOBERR AND nADoutLE1)
OR (iobs/Once AND NOT BERR_IOBS AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND IOBERR AND nADoutLE1)
OR (iobs/Once AND NOT BERR_IOBS AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/IOACTr AND IOBERR AND fsb/ASrf AND nADoutLE1));
Prototype
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CLK20EN <= SW(0);
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Prototype
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CLK25EN <= NOT SW(0);
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FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,CLK2X_IOB,'0','0');
Prototype
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IOACT_D <= ((CLK_IOB AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/DTACKrf AND iobm/DTACKrr)
OR (CLK_IOB AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/RESrf AND iobm/RESrr)
OR (iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd2 AND
NOT iobm/IOREQr)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd2 AND nAoutOE)
OR (CLK_IOB AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/ETACK)
OR (CLK_IOB AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/BERRrf AND iobm/BERRrr));
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FTCPE_IOBERR: FTCPE port map (IOBERR,IOBERR_T,CLK2X_IOB,'0','0');
Prototype
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IOBERR_T <= ((CLK_IOB AND nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND IOBERR AND iobm/RESrf AND
iobm/RESrr)
OR (CLK_IOB AND NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND NOT IOBERR AND iobm/DTACKrf AND
iobm/DTACKrr)
OR (CLK_IOB AND NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND NOT IOBERR AND iobm/BERRrf AND
iobm/BERRrr)
OR (CLK_IOB AND NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND NOT IOBERR AND iobm/RESrf AND
iobm/RESrr)
OR (iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd1 AND
NOT iobm/IOS_FSM_FFd2 AND IOBERR)
OR (CLK_IOB AND nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND IOBERR AND iobm/ETACK)
OR (CLK_IOB AND NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND NOT IOBERR AND iobm/ETACK)
OR (CLK_IOB AND nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND IOBERR AND iobm/DTACKrf AND
iobm/DTACKrr)
OR (CLK_IOB AND nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND IOBERR AND iobm/BERRrf AND
iobm/BERRrr));
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FDCPE_IOL0: FDCPE port map (IOL0,IOL0_D,CLK_FSB,'0','0',IOL0_CE);
IOL0_D <= ((NOT nLDS_FSB AND nADoutLE1)
OR (iobs/IOL1 AND NOT nADoutLE1));
IOL0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
FDCPE_IOREQ: FDCPE port map (IOREQ,IOREQ_D,CLK_FSB,'0','0');
IOREQ_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
Prototype
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OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(20) AND
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NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
Prototype
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OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND
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NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
Prototype
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OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND
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NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18) AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
Prototype
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OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(20) AND SW(1) AND
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NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21) AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
cs/nOverlay1 AND NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (NOT iobs/PS_FSM_FFd2 AND iobs/PS_FSM_FFd1)
OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr)
OR (iobs/Once AND NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
OR (nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT fsb/ASrf AND
Prototype
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nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
NOT iobs/PS_FSM_FFd2 AND nADoutLE1));
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FTCPE_IORW0: FTCPE port map (IORW0,IORW0_T,CLK_FSB,'0','0');
Prototype
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IORW0_T <= ((A_FSB_19_IBUF$BUF0.EXP)
OR (IORW0 AND iobs/IORW1 AND NOT nADoutLE1)
OR (NOT IORW0 AND NOT iobs/IORW1 AND NOT nADoutLE1)
OR (nAS_FSB AND NOT fsb/ASrf AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT IORW0 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18) AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(20) AND SW(1) AND nADoutLE1)
OR (NOT IORW0 AND NOT nWE_FSB AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(20) AND nADoutLE1)
OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21) AND
nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
cs/nOverlay1 AND nADoutLE1));
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FDCPE_IOU0: FDCPE port map (IOU0,IOU0_D,CLK_FSB,'0','0',IOU0_CE);
IOU0_D <= ((NOT nUDS_FSB AND nADoutLE1)
OR (iobs/IOU1 AND NOT nADoutLE1));
IOU0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
Prototype
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FDCPE_IPL2r0: FDCPE port map (IPL2r0,NOT nIPL2,CLK_FSB,'0','0');
FDCPE_IPL2r1: FDCPE port map (IPL2r1,IPL2r0,CLK_FSB,'0','0');
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RA(0) <= ((A_FSB(10) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(1)));
RA(1) <= ((A_FSB(11) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(2)));
Prototype
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RA(2) <= ((A_FSB(12) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(3)));
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RA(3) <= ((A_FSB(13) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(4)));
RA(4) <= ((A_FSB(14) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(5)));
RA(5) <= ((A_FSB(15) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(6)));
RA(6) <= ((A_FSB(16) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(7)));
RA(7) <= ((A_FSB(8) AND ram/RASEL)
OR (A_FSB(17) AND NOT ram/RASEL));
idk
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RA(8) <= ((A_FSB(9) AND NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
ram/RASEL)
OR (A_FSB(9) AND NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND ram/RASEL)
OR (A_FSB(23) AND A_FSB(18))
OR (A_FSB(18) AND NOT ram/RASEL)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(18))
OR (A_FSB(22) AND A_FSB(18) AND cs/nOverlay1)
OR (NOT A_FSB(22) AND A_FSB(18) AND NOT cs/nOverlay1));
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RA(9) <= ((A_FSB(20) AND ram/RASEL)
OR (A_FSB(19) AND NOT ram/RASEL));
RA(10) <= A_FSB(21);
RA(11) <= A_FSB(19);
Prototype
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FDCPE_RESDone: FDCPE port map (RESDone,'1',CLK_FSB,'0','0',RESDone_CE);
RESDone_CE <= (NOT RESr0 AND NOT RESr1 AND RESr2);
FDCPE_RESr0: FDCPE port map (RESr0,NOT nRES,CLK_FSB,'0','0');
FDCPE_RESr1: FDCPE port map (RESr1,RESr0,CLK_FSB,'0','0');
FDCPE_RESr2: FDCPE port map (RESr2,RESr1,CLK_FSB,'0','0');
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FDCPE_RefAck: FDCPE port map (RefAck,RefAck_D,CLK_FSB,'0','0');
RefAck_D <= (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1);
FTCPE_TimeoutA: FTCPE port map (TimeoutA,TimeoutA_T,CLK_FSB,'0','0');
TimeoutA_T <= ((TimeoutA AND nAS_FSB AND NOT fsb/ASrf)
OR (NOT TimeoutA AND NOT nAS_FSB AND NOT cnt/RefCnt(0) AND
NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4))
OR (NOT TimeoutA AND NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND
NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND
NOT cnt/RefCnt(4) AND fsb/ASrf));
FTCPE_TimeoutB: FTCPE port map (TimeoutB,TimeoutB_T,CLK_FSB,'0','0');
TimeoutB_T <= ((TimeoutB AND nAS_FSB AND NOT fsb/ASrf)
OR (NOT TimeoutB AND cnt/TimeoutBPre AND NOT nAS_FSB AND
NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND
NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7))
OR (NOT TimeoutB AND cnt/TimeoutBPre AND NOT cnt/RefCnt(0) AND
NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7) AND fsb/ASrf));
FTCPE_cnt/RefCnt0: FTCPE port map (cnt/RefCnt(0),'1',CLK_FSB,'0','0');
FTCPE_cnt/RefCnt1: FTCPE port map (cnt/RefCnt(1),cnt/RefCnt(0),CLK_FSB,'0','0');
FTCPE_cnt/RefCnt2: FTCPE port map (cnt/RefCnt(2),cnt/RefCnt_T(2),CLK_FSB,'0','0');
cnt/RefCnt_T(2) <= (cnt/RefCnt(0) AND cnt/RefCnt(1));
FTCPE_cnt/RefCnt3: FTCPE port map (cnt/RefCnt(3),cnt/RefCnt_T(3),CLK_FSB,'0','0');
cnt/RefCnt_T(3) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2));
FTCPE_cnt/RefCnt4: FTCPE port map (cnt/RefCnt(4),cnt/RefCnt_T(4),CLK_FSB,'0','0');
cnt/RefCnt_T(4) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2) AND
cnt/RefCnt(3));
FTCPE_cnt/RefCnt5: FTCPE port map (cnt/RefCnt(5),cnt/RefCnt_T(5),CLK_FSB,'0','0');
cnt/RefCnt_T(5) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2) AND
cnt/RefCnt(3) AND cnt/RefCnt(4));
FTCPE_cnt/RefCnt6: FTCPE port map (cnt/RefCnt(6),cnt/RefCnt_T(6),CLK_FSB,'0','0');
cnt/RefCnt_T(6) <= (cnt/RefCnt(0) AND cnt/RefCnt(5) AND cnt/RefCnt(1) AND
cnt/RefCnt(2) AND cnt/RefCnt(3) AND cnt/RefCnt(4));
FTCPE_cnt/RefCnt7: FTCPE port map (cnt/RefCnt(7),cnt/RefCnt_T(7),CLK_FSB,'0','0');
cnt/RefCnt_T(7) <= (cnt/RefCnt(0) AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
cnt/RefCnt(1) AND cnt/RefCnt(2) AND cnt/RefCnt(3) AND cnt/RefCnt(4));
FDCPE_cnt/RefDone: FDCPE port map (cnt/RefDone,cnt/RefDone_D,CLK_FSB,'0','0');
cnt/RefDone_D <= ((NOT cnt/RefDone AND NOT RefAck)
OR (NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND
NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND
NOT cnt/RefCnt(7)));
FTCPE_cnt/TimeoutBPre: FTCPE port map (cnt/TimeoutBPre,cnt/TimeoutBPre_T,CLK_FSB,'0','0');
cnt/TimeoutBPre_T <= ((cnt/TimeoutBPre AND nAS_FSB AND NOT fsb/ASrf)
OR (NOT cnt/TimeoutBPre AND NOT nAS_FSB AND NOT cnt/RefCnt(0) AND
NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7))
OR (NOT cnt/TimeoutBPre AND NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND
NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND
NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7) AND fsb/ASrf));
FTCPE_cs/nOverlay0: FTCPE port map (cs/nOverlay0,cs/nOverlay0_T,CLK_FSB,NOT nRES,'0');
cs/nOverlay0_T <= ((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
NOT cs/nOverlay0 AND NOT nAS_FSB)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
NOT cs/nOverlay0 AND fsb/ASrf));
FDCPE_cs/nOverlay1: FDCPE port map (cs/nOverlay1,cs/nOverlay0,CLK_FSB,'0','0',cs/nOverlay1_CE);
cs/nOverlay1_CE <= (nAS_FSB AND NOT fsb/ASrf);
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT CLK_FSB,'0','0');
FDCPE_fsb/BERR0r: FDCPE port map (fsb/BERR0r,fsb/BERR0r_D,CLK_FSB,'0','0');
fsb/BERR0r_D <= ((NOT TimeoutB AND NOT fsb/BERR0r)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND
NOT fsb/BERR0r));
FDCPE_fsb/BERR1r: FDCPE port map (fsb/BERR1r,fsb/BERR1r_D,CLK_FSB,'0','0');
fsb/BERR1r_D <= ((NOT BERR_IOBS AND NOT fsb/BERR1r)
OR (nAS_FSB AND NOT fsb/ASrf));
FDCPE_fsb/Ready0r: FDCPE port map (fsb/Ready0r,fsb/Ready0r_D,CLK_FSB,'0','0');
fsb/Ready0r_D <= ((nAS_FSB AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
NOT fsb/Ready0r AND NOT ram/RAMReady)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT fsb/Ready0r AND NOT ram/RAMReady));
FDCPE_fsb/Ready1r: FDCPE port map (fsb/Ready1r,fsb/Ready1r_D,CLK_FSB,'0','0');
Prototype
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fsb/Ready1r_D <= ((A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
NOT fsb/Ready1r AND NOT iobs/IOReady)
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
NOT fsb/Ready1r AND NOT iobs/IOReady)
OR (A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
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A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
NOT nADoutLE1)
OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
NOT nADoutLE1)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT fsb/Ready1r AND
NOT iobs/IOReady)
Prototype
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OR (A_FSB(22) AND NOT A_FSB(21) AND NOT fsb/Ready1r AND
NOT iobs/IOReady AND NOT SW(1)));
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FDCPE_fsb/Ready2r: FDCPE port map (fsb/Ready2r,fsb/Ready2r_D,CLK_FSB,'0','0');
fsb/Ready2r_D <= ((nAS_FSB AND NOT fsb/ASrf)
OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(9) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
OR (A_FSB(9) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r));
FDCPE_fsb/VPA: FDCPE port map (fsb/VPA,fsb/VPA_D,CLK_FSB,'0','0');
Prototype
2022-03-28 03:45:53 +00:00
fsb/VPA_D <= ((EXP21_.EXP)
Move directories
2022-02-14 21:38:58 +00:00
OR (A_FSB(23) AND NOT fsb/Ready1r AND fsb/VPA AND
Prototype
2022-03-28 03:45:53 +00:00
NOT iobs/IOReady AND NOT $OpTx$FX_DC$708)
Move directories
2022-02-14 21:38:58 +00:00
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT fsb/Ready1r AND
Prototype
2022-03-28 03:45:53 +00:00
fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$708)
OR (A_FSB(22) AND NOT A_FSB(21) AND NOT fsb/Ready1r AND fsb/VPA AND
NOT iobs/IOReady AND NOT SW(1) AND NOT $OpTx$FX_DC$708)
Move directories
2022-02-14 21:38:58 +00:00
OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
Prototype
2022-03-28 03:45:53 +00:00
NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$708)
Move directories
2022-02-14 21:38:58 +00:00
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
Prototype
2022-03-28 03:45:53 +00:00
NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$708)
OR (nROMWE_OBUF.EXP)
Move directories
2022-02-14 21:38:58 +00:00
OR (A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND
Prototype
2022-03-28 03:45:53 +00:00
NOT nADoutLE1 AND NOT $OpTx$FX_DC$708)
Move directories
2022-02-14 21:38:58 +00:00
OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND
Prototype
2022-03-28 03:45:53 +00:00
NOT nADoutLE1 AND NOT $OpTx$FX_DC$708)
OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r AND
fsb/VPA AND NOT $OpTx$FX_DC$708)
OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r AND
fsb/VPA AND NOT $OpTx$FX_DC$708)
OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r AND
fsb/VPA AND NOT $OpTx$FX_DC$708)
OR (BERR_IOBS AND fsb/VPA AND NOT $OpTx$FX_DC$708)
OR (fsb/BERR0r AND fsb/VPA AND NOT $OpTx$FX_DC$708)
OR (fsb/BERR1r AND fsb/VPA AND NOT $OpTx$FX_DC$708)
OR (fsb/VPA AND NOT nBR_IOB AND NOT $OpTx$FX_DC$708)
OR (fsb/VPA AND NOT $OpTx$FX_DC$708 AND
$OpTx$$OpTx$FX_DC$182_INV$783));
Move directories
2022-02-14 21:38:58 +00:00
FDCPE_iobm/BERRrf: FDCPE port map (iobm/BERRrf,NOT nBERR_IOB,NOT CLK2X_IOB,'0','0');
FDCPE_iobm/BERRrr: FDCPE port map (iobm/BERRrr,NOT nBERR_IOB,CLK2X_IOB,'0','0');
Prototype
2022-03-28 03:45:53 +00:00
FDCPE_iobm/BGr0: FDCPE port map (iobm/BGr0,NOT nBG_IOB,CLK2X_IOB,'0','0');
FDCPE_iobm/BGr1: FDCPE port map (iobm/BGr1,iobm/BGr0,CLK2X_IOB,'0','0');
Move directories
2022-02-14 21:38:58 +00:00
FDCPE_iobm/DTACKrf: FDCPE port map (iobm/DTACKrf,NOT nDTACK_IOB,NOT CLK2X_IOB,'0','0');
FDCPE_iobm/DTACKrr: FDCPE port map (iobm/DTACKrr,NOT nDTACK_IOB,CLK2X_IOB,'0','0');
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),CLK2X_IOB,'0','0');
iobm/ES_T(0) <= ((iobm/ES(0) AND NOT iobm/Er AND iobm/Er2)
OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND NOT iobm/ES(4) AND iobm/Er)
OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND NOT iobm/ES(4) AND NOT iobm/Er2));
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),CLK2X_IOB,'0','0');
iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1))
OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
OR (NOT iobm/Er AND iobm/Er2));
FDCPE_iobm/ES2: FDCPE port map (iobm/ES(2),iobm/ES_D(2),CLK2X_IOB,'0','0');
iobm/ES_D(2) <= ((NOT iobm/ES(0) AND NOT iobm/ES(2))
OR (NOT iobm/ES(1) AND NOT iobm/ES(2))
OR (NOT iobm/Er AND iobm/Er2)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2))
OR (NOT iobm/ES(2) AND NOT iobm/ES(3) AND iobm/ES(4)));
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),CLK2X_IOB,'0','0');
iobm/ES_T(3) <= ((iobm/ES(3) AND NOT iobm/Er AND iobm/Er2)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND iobm/Er)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND NOT iobm/Er2));
FTCPE_iobm/ES4: FTCPE port map (iobm/ES(4),iobm/ES_T(4),CLK2X_IOB,'0','0');
iobm/ES_T(4) <= ((iobm/ES(4) AND NOT iobm/Er AND iobm/Er2)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
iobm/ES(3) AND iobm/Er)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
iobm/ES(3) AND NOT iobm/Er2)
OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND iobm/ES(4)));
FDCPE_iobm/ETACK: FDCPE port map (iobm/ETACK,iobm/ETACK_D,CLK2X_IOB,'0','0');
iobm/ETACK_D <= (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND iobm/ES(4));
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E_IOB,NOT CLK_IOB,'0','0');
FDCPE_iobm/Er2: FDCPE port map (iobm/Er2,iobm/Er,CLK2X_IOB,'0','0');
FDCPE_iobm/IOREQr: FDCPE port map (iobm/IOREQr,IOREQ,NOT CLK2X_IOB,'0','0');
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd1_D,CLK2X_IOB,'0','0');
Prototype
2022-03-28 03:45:53 +00:00
iobm/IOS_FSM_FFd1_D <= ((iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1)
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2));
FTCPE_iobm/IOS_FSM_FFd2: FTCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_T,CLK2X_IOB,'0','0');
iobm/IOS_FSM_FFd2_T <= ((iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd1 AND
NOT iobm/IOS_FSM_FFd2)
OR (CLK_IOB AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/IOS_FSM_FFd2 AND iobm/ETACK)
OR (CLK_IOB AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/IOS_FSM_FFd2 AND iobm/DTACKrf AND iobm/DTACKrr)
OR (CLK_IOB AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/IOS_FSM_FFd2 AND iobm/BERRrf AND iobm/BERRrr)
OR (CLK_IOB AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/IOS_FSM_FFd2 AND iobm/RESrf AND iobm/RESrr));
Move directories
2022-02-14 21:38:58 +00:00
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,CLK2X_IOB,'0','0');
Prototype
2022-03-28 03:45:53 +00:00
iobm/IOS_FSM_FFd3_D <= ((iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2)
OR (iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd1 AND
NOT iobm/IOS_FSM_FFd2)
OR (NOT CLK_IOB AND NOT iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2 AND
iobm/IOREQr AND NOT nAoutOE));
Move directories
2022-02-14 21:38:58 +00:00
FDCPE_iobm/RESrf: FDCPE port map (iobm/RESrf,NOT nRES,NOT CLK2X_IOB,'0','0');
FDCPE_iobm/RESrr: FDCPE port map (iobm/RESrr,NOT nRES,CLK2X_IOB,'0','0');
FDCPE_iobm/VPArf: FDCPE port map (iobm/VPArf,NOT nVPA_IOB,NOT CLK2X_IOB,'0','0');
FDCPE_iobm/VPArr: FDCPE port map (iobm/VPArr,NOT nVPA_IOB,CLK2X_IOB,'0','0');
FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,CLK_FSB,'0','0');
iobs/Clear1_D <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1);
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,CLK_FSB,'0','0');
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,CLK_FSB,'0','0',iobs/Load1);
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,CLK_FSB,'0','0');
iobs/IORW1_T <= ((iobs/Once)
OR (NOT nADoutLE1)
Prototype
2022-03-28 03:45:53 +00:00
OR (fsb/Ready1r.EXP)
Move directories
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OR (nAS_FSB AND NOT fsb/ASrf)
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(20))
Move directories
2022-02-14 21:38:58 +00:00
OR (fsb/Ready2r.EXP)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19))
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18))
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17))
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16))
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(20) AND SW(1))
Move directories
2022-02-14 21:38:58 +00:00
OR (nWE_FSB AND iobs/IORW1)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT nWE_FSB AND NOT iobs/IORW1)
Move directories
2022-02-14 21:38:58 +00:00
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT iobs/IORW1));
FTCPE_iobs/IOReady: FTCPE port map (iobs/IOReady,iobs/IOReady_T,CLK_FSB,'0','0');
iobs/IOReady_T <= ((iobs/IOReady AND nAS_FSB AND NOT fsb/ASrf)
OR (iobs/Once AND iobs/IOReady AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/IOACTr AND IOBERR AND nADoutLE1)
OR (iobs/Once AND NOT iobs/IOReady AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND NOT IOBERR AND nADoutLE1)
OR (iobs/Once AND NOT iobs/IOReady AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/IOACTr AND NOT IOBERR AND fsb/ASrf AND nADoutLE1));
FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,CLK_FSB,'0','0',iobs/Load1);
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,CLK_FSB,'0','0');
iobs/Load1_D <= ((iobs/Once)
OR (NOT nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(20))
Move directories
2022-02-14 21:38:58 +00:00
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19))
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17))
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16))
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18))
OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB)
OR (NOT A_FSB(23) AND NOT A_FSB(20) AND SW(1))
Move directories
2022-02-14 21:38:58 +00:00
OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21))
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
cs/nOverlay1)
OR (nAS_FSB AND NOT fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1));
Move directories
2022-02-14 21:38:58 +00:00
FDCPE_iobs/Once: FDCPE port map (iobs/Once,iobs/Once_D,CLK_FSB,'0','0');
Prototype
2022-03-28 03:45:53 +00:00
iobs/Once_D <= ((nBERR_FSB_OBUF.EXP)
Move directories
2022-02-14 21:38:58 +00:00
OR (A_FSB(23) AND NOT iobs/Once AND iobs/PS_FSM_FFd1)
OR (NOT iobs/Once AND iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Once AND
NOT cs/nOverlay1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(20) AND NOT iobs/Once)
Move directories
2022-02-14 21:38:58 +00:00
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND NOT iobs/Once)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18) AND NOT iobs/Once)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND NOT iobs/Once)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND NOT iobs/Once)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (A_FSB(23) AND NOT iobs/Once AND iobs/PS_FSM_FFd2)
OR (A_FSB(22) AND NOT iobs/Once AND iobs/PS_FSM_FFd2)
Prototype
2022-03-28 03:45:53 +00:00
OR (A_FSB(22) AND NOT iobs/Once AND iobs/PS_FSM_FFd1)
OR (NOT iobs/Once AND iobs/PS_FSM_FFd2 AND NOT nADoutLE1));
Move directories
2022-02-14 21:38:58 +00:00
FDCPE_iobs/PS_FSM_FFd1: FDCPE port map (iobs/PS_FSM_FFd1,iobs/PS_FSM_FFd1_D,CLK_FSB,'0','0');
iobs/PS_FSM_FFd1_D <= ((iobs/PS_FSM_FFd2)
OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr));
FDCPE_iobs/PS_FSM_FFd2: FDCPE port map (iobs/PS_FSM_FFd2,iobs/PS_FSM_FFd2_D,CLK_FSB,'0','0');
iobs/PS_FSM_FFd2_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(20) AND
Move directories
2022-02-14 21:38:58 +00:00
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND
Move directories
2022-02-14 21:38:58 +00:00
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND
Move directories
2022-02-14 21:38:58 +00:00
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18) AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(20) AND SW(1) AND
Move directories
2022-02-14 21:38:58 +00:00
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21) AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
cs/nOverlay1 AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (iobs/PS_FSM_FFd2 AND iobs/PS_FSM_FFd1 AND
iobs/IOACTr)
OR (NOT iobs/PS_FSM_FFd2 AND iobs/PS_FSM_FFd1 AND
NOT iobs/IOACTr)
OR (iobs/Once AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
nADoutLE1)
OR (nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
Prototype
2022-03-28 03:45:53 +00:00
NOT fsb/ASrf AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1));
Move directories
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nADoutLE0 <= (NOT ALE0M AND NOT ALE0S);
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,CLK_FSB,'0','0');
nADoutLE1_D <= ((iobs/Load1)
OR (NOT iobs/Clear1 AND NOT nADoutLE1));
Prototype
2022-03-28 03:45:53 +00:00
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB_I,nAS_IOB,NOT CLK2X_IOB,'0','0');
nAS_IOB <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd2)
OR (iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2));
nAS_IOB <= nAS_IOB_I when nAS_IOB_OE = '1' else 'Z';
nAS_IOB_OE <= NOT nAoutOE;
Move directories
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Prototype
2022-03-28 03:45:53 +00:00
FDCPE_nAoutOE: FDCPE port map (nAoutOE,nAoutOE_D,CLK2X_IOB,'0','0');
nAoutOE_D <= ((NOT iobm/BGr0 AND NOT iobm/BGr1)
OR (NOT iobm/BGr1 AND nAoutOE)
OR (NOT nAS_IOB AND NOT iobm/BGr0 AND NOT nAoutOE));
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nBERR_FSB <= ((nAS_FSB)
OR (NOT BERR_IOBS AND NOT TimeoutB AND NOT fsb/BERR0r AND NOT fsb/BERR1r)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND
NOT BERR_IOBS AND NOT fsb/BERR0r AND NOT fsb/BERR1r));
Prototype
2022-03-28 03:45:53 +00:00
FDCPE_nBR_IOB: FDCPE port map (nBR_IOB,'0',CLK_FSB,'0','0',nBR_IOB_CE);
nBR_IOB_CE <= (RESr0 AND RESr1 AND IPL2r0 AND RESr2 AND NOT RESDone AND
IPL2r1);
Move directories
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FDCPE_nCAS: FDCPE port map (nCAS,NOT ram/RASEL,NOT CLK_FSB,'0','0');
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,CLK_FSB,'0','0');
Prototype
2022-03-28 03:45:53 +00:00
nDTACK_FSB_D <= ((EXP17_.EXP)
OR (nAS_FSB AND NOT fsb/ASrf)
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OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
nDTACK_FSB)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT fsb/Ready1r AND
NOT iobs/IOReady AND nDTACK_FSB)
Prototype
2022-03-28 03:45:53 +00:00
OR (A_FSB(22) AND NOT A_FSB(21) AND NOT fsb/Ready1r AND
NOT iobs/IOReady AND NOT SW(1) AND nDTACK_FSB)
Move directories
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OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
NOT fsb/Ready1r AND NOT iobs/IOReady AND nDTACK_FSB)
Prototype
2022-03-28 03:45:53 +00:00
OR (EXP20_.EXP)
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OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
NOT fsb/Ready1r AND NOT iobs/IOReady AND nDTACK_FSB)
OR (A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
nDTACK_FSB AND NOT nADoutLE1)
OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
nDTACK_FSB AND NOT nADoutLE1)
OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r AND
nDTACK_FSB)
OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r AND
nDTACK_FSB)
OR (BERR_IOBS AND nDTACK_FSB)
OR (fsb/BERR0r AND nDTACK_FSB)
OR (fsb/BERR1r AND nDTACK_FSB)
Prototype
2022-03-28 03:45:53 +00:00
OR (nDTACK_FSB AND NOT nBR_IOB)
OR (nDTACK_FSB AND $OpTx$$OpTx$FX_DC$182_INV$783));
Move directories
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FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT CLK2X_IOB,'0','0');
Prototype
2022-03-28 03:45:53 +00:00
nDinLE_D <= (iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2);
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nDinOE <= ((A_FSB(23) AND nWE_FSB AND NOT nAS_FSB)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND nWE_FSB AND
Prototype
2022-03-28 03:45:53 +00:00
NOT nAS_FSB)
OR (A_FSB(22) AND NOT A_FSB(21) AND nWE_FSB AND NOT nAS_FSB AND
NOT SW(1)));
Move directories
2022-02-14 21:38:58 +00:00
FDCPE_nDoutOE: FDCPE port map (nDoutOE,nDoutOE_D,CLK2X_IOB,'0','0');
nDoutOE_D <= ((NOT IORW0)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd2));
Move directories
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Prototype
2022-03-28 03:45:53 +00:00
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB_I,nLDS_IOB,NOT CLK2X_IOB,'0','0');
nLDS_IOB <= ((IOL0 AND NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2)
OR (IOL0 AND iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2)
OR (NOT IORW0 AND IOL0 AND iobm/IOS_FSM_FFd3 AND
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NOT iobm/IOS_FSM_FFd1));
Prototype
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nLDS_IOB <= nLDS_IOB_I when nLDS_IOB_OE = '1' else 'Z';
nLDS_IOB_OE <= NOT nAoutOE;
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nOE <= NOT ((nWE_FSB AND NOT nAS_FSB));
nRAMLWE <= NOT ((NOT nWE_FSB AND NOT nLDS_FSB AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
NOT ram/RAMDIS1));
nRAMUWE <= NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
NOT ram/RAMDIS1));
nRAS <= NOT (((RefAck)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RAMDIS1)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RAMDIS1)));
Prototype
2022-03-28 03:45:53 +00:00
nROMCS <= NOT (((A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
NOT SW(1))
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
SW(1))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
Move directories
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NOT cs/nOverlay1)));
nROMWE <= NOT ((NOT nWE_FSB AND NOT nAS_FSB));
Prototype
2022-03-28 03:45:53 +00:00
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB_I,nUDS_IOB,NOT CLK2X_IOB,'0','0');
nUDS_IOB <= ((IOU0 AND NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2)
OR (IOU0 AND iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2)
OR (NOT IORW0 AND IOU0 AND iobm/IOS_FSM_FFd3 AND
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NOT iobm/IOS_FSM_FFd1));
Prototype
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nUDS_IOB <= nUDS_IOB_I when nUDS_IOB_OE = '1' else 'Z';
nUDS_IOB_OE <= NOT nAoutOE;
Move directories
2022-02-14 21:38:58 +00:00
Prototype
2022-03-28 03:45:53 +00:00
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB_I,nVMA_IOB_T,CLK2X_IOB,'0','0');
Move directories
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nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND NOT iobm/ES(4))
OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
NOT iobm/ES(3) AND NOT iobm/ES(4) AND IOACT AND iobm/VPArf AND iobm/VPArr));
Prototype
2022-03-28 03:45:53 +00:00
nVMA_IOB <= nVMA_IOB_I when nVMA_IOB_OE = '1' else 'Z';
nVMA_IOB_OE <= NOT nAoutOE;
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nVPA_FSB <= NOT ((fsb/VPA AND NOT nAS_FSB));
FDCPE_ram/BACTr: FDCPE port map (ram/BACTr,ram/BACTr_D,CLK_FSB,'0','0');
ram/BACTr_D <= (nAS_FSB AND NOT fsb/ASrf);
FTCPE_ram/Once: FTCPE port map (ram/Once,ram/Once_T,CLK_FSB,'0','0');
ram/Once_T <= ((ram/Once AND nAS_FSB AND NOT fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT ram/Once AND cs/nOverlay1 AND
Move directories
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NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT ram/Once AND cs/nOverlay1 AND
Move directories
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NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND NOT ram/Once AND
NOT cs/nOverlay1 AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND NOT ram/Once AND
NOT cs/nOverlay1 AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
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NOT ram/RS_FSM_FFd3 AND fsb/ASrf));
FDCPE_ram/RAMDIS1: FDCPE port map (ram/RAMDIS1,ram/RAMDIS1_D,CLK_FSB,'0','0');
Prototype
2022-03-28 03:45:53 +00:00
ram/RAMDIS1_D <= ((nOE_OBUF.EXP)
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OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (A_FSB(22) AND NOT cnt/RefDone AND cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
Prototype
2022-03-28 03:45:53 +00:00
OR (A_FSB(22) AND NOT cnt/RefDone AND cs/nOverlay1 AND
Move directories
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NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(22) AND NOT cnt/RefDone AND NOT cs/nOverlay1 AND
Move directories
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NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(22) AND NOT cnt/RefDone AND NOT cs/nOverlay1 AND
Move directories
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NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
OR (NOT cnt/RefDone AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
OR (NOT cnt/RefDone AND nAS_FSB AND NOT ram/RS_FSM_FFd1 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND NOT fsb/ASrf)
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1)
OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3)
OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
NOT ram/BACTr AND fsb/ASrf));
FTCPE_ram/RAMDIS2: FTCPE port map (ram/RAMDIS2,ram/RAMDIS2_T,CLK_FSB,'0','0');
Prototype
2022-03-28 03:45:53 +00:00
ram/RAMDIS2_T <= ((NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND ram/Once AND
NOT cnt/RefDone AND NOT cs/nOverlay1 AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
Move directories
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NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND ram/Once AND
NOT cnt/RefDone AND NOT cs/nOverlay1 AND NOT ram/RAMDIS2 AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
cnt/RefCnt(7) AND fsb/ASrf)
Move directories
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OR (ram/RAMDIS2 AND nAS_FSB AND NOT fsb/ASrf)
OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND
Prototype
2022-03-28 03:45:53 +00:00
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND
ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND ram/Once AND NOT cnt/RefDone AND
cs/nOverlay1 AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
cnt/RefCnt(7))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND ram/Once AND NOT cnt/RefDone AND
cs/nOverlay1 AND NOT ram/RAMDIS2 AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
fsb/ASrf));
Move directories
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FDCPE_ram/RAMReady: FDCPE port map (ram/RAMReady,ram/RAMReady_D,CLK_FSB,'0','0');
ram/RAMReady_D <= ((ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3)
OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1)
OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
NOT ram/BACTr AND fsb/ASrf)
OR (ram/RS_FSM_FFd2.EXP)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT ram/Once AND cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT ram/Once AND cs/nOverlay1 AND
Move directories
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NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (A_FSB(22) AND NOT cnt/RefDone AND cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(22) AND NOT cnt/RefDone AND NOT cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND NOT ram/Once AND
NOT cs/nOverlay1 AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(22) AND NOT cnt/RefDone AND cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(22) AND NOT cnt/RefDone AND NOT cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(21) AND NOT cnt/RefDone AND NOT cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(21) AND NOT cnt/RefDone AND NOT cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND NOT ram/Once AND
NOT cs/nOverlay1 AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd1));
Move directories
2022-02-14 21:38:58 +00:00
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,CLK_FSB,'0','0');
Prototype
2022-03-28 03:45:53 +00:00
ram/RASEL_D <= ((A_FSB(22) AND NOT cnt/RefDone AND cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(22) AND NOT cnt/RefDone AND NOT cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(22) AND NOT cnt/RefDone AND NOT cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (NOT cnt/RefDone AND nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
NOT fsb/ASrf)
OR (NOT cnt/RefDone AND nAS_FSB AND ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
NOT fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (EXP26_.EXP)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT ram/Once AND cs/nOverlay1 AND
Move directories
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NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT ram/Once AND cs/nOverlay1 AND
Move directories
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NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (A_FSB(22) AND NOT cnt/RefDone AND cs/nOverlay1 AND
Move directories
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NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7)));
FTCPE_ram/RS_FSM_FFd1: FTCPE port map (ram/RS_FSM_FFd1,ram/RS_FSM_FFd1_T,CLK_FSB,'0','0');
ram/RS_FSM_FFd1_T <= ((ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT ram/Once AND cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT ram/Once AND cs/nOverlay1 AND
Move directories
2022-02-14 21:38:58 +00:00
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
Prototype
2022-03-28 03:45:53 +00:00
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND NOT ram/Once AND
NOT cs/nOverlay1 AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND NOT ram/Once AND
NOT cs/nOverlay1 AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
Move directories
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NOT ram/RS_FSM_FFd3 AND fsb/ASrf));
FTCPE_ram/RS_FSM_FFd2: FTCPE port map (ram/RS_FSM_FFd2,ram/RS_FSM_FFd2_T,CLK_FSB,'0','0');
Prototype
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ram/RS_FSM_FFd2_T <= ((EXP28_.EXP)
Move directories
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OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
NOT cnt/RefCnt(5) AND ram/BACTr)
OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
NOT cnt/RefCnt(5) AND NOT fsb/ASrf)
OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
NOT cnt/RefCnt(6) AND NOT fsb/ASrf)
OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
NOT cnt/RefCnt(7) AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3)
OR (cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
NOT cnt/RefCnt(6) AND ram/BACTr)
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND ram/BACTr AND
NOT cnt/RefCnt(7)));
FTCPE_ram/RS_FSM_FFd3: FTCPE port map (ram/RS_FSM_FFd3,ram/RS_FSM_FFd3_T,CLK_FSB,'0','0');
Prototype
2022-03-28 03:45:53 +00:00
ram/RS_FSM_FFd3_T <= ((A_FSB(22) AND NOT A_FSB(21) AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (A_FSB(22) AND cs/nOverlay1 AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND NOT fsb/ASrf)
OR (NOT cnt/RefDone AND NOT nAS_FSB AND ram/RS_FSM_FFd2 AND
ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
cnt/RefCnt(7))
OR (NOT cnt/RefDone AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
fsb/ASrf)
OR (A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
Move directories
2022-02-14 21:38:58 +00:00
OR (ram/Once AND cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(5))
OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(6))
OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
Prototype
2022-03-28 03:45:53 +00:00
NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(7)));
Move directories
2022-02-14 21:38:58 +00:00
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-10-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC95144XL-10-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 51 VCC
2 A_FSB<5> 52 RA<7>
3 A_FSB<6> 53 RA<0>
4 A_FSB<7> 54 RA<8>
5 VCC 55 RA<10>
6 A_FSB<8> 56 RA<9>
7 A_FSB<9> 57 VCC
Prototype
2022-03-28 03:45:53 +00:00
8 A_FSB<10> 58 CLK25EN
9 A_FSB<11> 59 CLK20EN
10 A_FSB<12> 60 SW<1>
11 A_FSB<13> 61 SW<0>
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12 A_FSB<14> 62 GND
13 A_FSB<15> 63 RA<11>
14 A_FSB<16> 64 nRAS
15 A_FSB<17> 65 nRAMLWE
16 A_FSB<18> 66 nRAMUWE
17 A_FSB<19> 67 KPR
18 A_FSB<20> 68 KPR
19 A_FSB<21> 69 GND
20 A_FSB<22> 70 nBERR_FSB
21 GND 71 KPR
Prototype
2022-03-28 03:45:53 +00:00
22 CLK2X_IOB 72 nBR_IOB
23 CLK_IOB 73 nBG_IOB
Move directories
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24 A_FSB<23> 74 nVMA_IOB
25 E_IOB 75 GND
26 VCC 76 nBERR_IOB
27 CLK_FSB 77 nVPA_IOB
28 nDTACK_FSB 78 nDTACK_IOB
29 nWE_FSB 79 nLDS_IOB
30 nLDS_FSB 80 nUDS_IOB
31 GND 81 nAS_IOB
32 nAS_FSB 82 nADoutLE1
33 nUDS_FSB 83 TDO
34 nROMWE 84 GND
35 nROMCS 85 nADoutLE0
36 nCAS 86 nDinLE
37 nOE 87 nAoutOE
38 VCC 88 VCC
39 KPR 89 nDoutOE
40 RA<4> 90 nDinOE
41 RA<3> 91 nRES
Prototype
2022-03-28 03:45:53 +00:00
42 RA<5> 92 nIPL2
Move directories
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43 RA<2> 93 nVPA_FSB
44 GND 94 A_FSB<1>
45 TDI 95 A_FSB<2>
46 RA<6> 96 A_FSB<3>
47 TMS 97 A_FSB<4>
48 TCK 98 VCC
49 KPR 99 KPR
50 RA<1> 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-10-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25