2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
cpldfit: version P.20131013 Xilinx Inc.
|
|
|
|
|
|
Fitter Report
|
2024-10-03 22:46:28 +00:00
|
|
|
|
Design Name: WarpSE Date: 10- 3-2024, 6:42PM
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Device Used: XC95144XL-10-TQ100
|
|
|
|
|
|
Fitting Status: Successful
|
|
|
|
|
|
|
|
|
|
|
|
************************* Mapped Resource Summary **************************
|
|
|
|
|
|
|
|
|
|
|
|
Macrocells Product Terms Function Block Registers Pins
|
|
|
|
|
|
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
|
2024-10-03 22:46:28 +00:00
|
|
|
|
136/144 ( 94%) 439 /720 ( 61%) 282/432 ( 65%) 112/144 ( 78%) 72 /81 ( 89%)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
** Function Block Resources **
|
|
|
|
|
|
|
|
|
|
|
|
Function Mcells FB Inps Pterms IO
|
|
|
|
|
|
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FB1 18/18* 22/54 30/90 11/11*
|
|
|
|
|
|
FB2 18/18* 22/54 22/90 8/10
|
|
|
|
|
|
FB3 18/18* 39/54 51/90 10/10*
|
|
|
|
|
|
FB4 18/18* 53/54 72/90 10/10*
|
|
|
|
|
|
FB5 15/18 45/54 82/90 8/10
|
2024-10-03 22:29:29 +00:00
|
|
|
|
FB6 18/18* 36/54 68/90 10/10*
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FB7 18/18* 27/54 32/90 9/10
|
|
|
|
|
|
FB8 13/18 38/54 82/90 6/10
|
2024-09-29 07:29:49 +00:00
|
|
|
|
----- ----- ----- -----
|
2024-10-03 22:46:28 +00:00
|
|
|
|
136/144 282/432 439/720 72/81
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
* - Resource is exhausted
|
|
|
|
|
|
|
|
|
|
|
|
** Global Control Resources **
|
|
|
|
|
|
|
|
|
|
|
|
Signal 'C16M' mapped onto global clock net GCK1.
|
|
|
|
|
|
Signal 'C8M' mapped onto global clock net GCK2.
|
|
|
|
|
|
Signal 'FCLK' mapped onto global clock net GCK3.
|
|
|
|
|
|
Global output enable net(s) unused.
|
|
|
|
|
|
Global set/reset net(s) unused.
|
|
|
|
|
|
|
|
|
|
|
|
** Pin Resources **
|
|
|
|
|
|
|
|
|
|
|
|
Signal Type Required Mapped | Pin Type Used Total
|
|
|
|
|
|
------------------------------------|------------------------------------
|
|
|
|
|
|
Input : 32 32 | I/O : 66 73
|
2024-10-03 22:29:29 +00:00
|
|
|
|
Output : 36 36 | GCK/IO : 3 3
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Bidirectional : 1 1 | GTS/IO : 3 4
|
2024-10-03 22:29:29 +00:00
|
|
|
|
GCK : 3 3 | GSR/IO : 0 1
|
2024-09-29 07:29:49 +00:00
|
|
|
|
GTS : 0 0 |
|
|
|
|
|
|
GSR : 0 0 |
|
|
|
|
|
|
---- ----
|
2024-10-03 22:29:29 +00:00
|
|
|
|
Total 72 72
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
** Power Data **
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
There are 136 macrocells in high performance mode (MCHP).
|
2024-09-29 07:29:49 +00:00
|
|
|
|
There are 0 macrocells in low power mode (MCLP).
|
|
|
|
|
|
End of Mapped Resource Summary
|
|
|
|
|
|
************************** Errors and Warnings ***************************
|
|
|
|
|
|
|
|
|
|
|
|
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
|
|
|
|
|
|
use the default filename of 'WarpSE.ise'.
|
|
|
|
|
|
INFO:Cpld - Inferring BUFG constraint for signal 'C16M' based upon the LOC
|
|
|
|
|
|
constraint 'P22'. It is recommended that you declare this BUFG explicitedly
|
|
|
|
|
|
in your design. Note that for certain device families the output of a BUFG
|
|
|
|
|
|
constraint can not drive a gated clock, and the BUFG constraint will be
|
|
|
|
|
|
ignored.
|
|
|
|
|
|
INFO:Cpld - Inferring BUFG constraint for signal 'C8M' based upon the LOC
|
|
|
|
|
|
constraint 'P23'. It is recommended that you declare this BUFG explicitedly
|
|
|
|
|
|
in your design. Note that for certain device families the output of a BUFG
|
|
|
|
|
|
constraint can not drive a gated clock, and the BUFG constraint will be
|
|
|
|
|
|
ignored.
|
|
|
|
|
|
INFO:Cpld - Inferring BUFG constraint for signal 'FCLK' based upon the LOC
|
|
|
|
|
|
constraint 'P27'. It is recommended that you declare this BUFG explicitedly
|
|
|
|
|
|
in your design. Note that for certain device families the output of a BUFG
|
|
|
|
|
|
constraint can not drive a gated clock, and the BUFG constraint will be
|
|
|
|
|
|
ignored.
|
|
|
|
|
|
WARNING:Cpld:1007 - Removing unused input(s) 'DBG<0>'. The input(s) are unused
|
|
|
|
|
|
after optimization. Please verify functionality via simulation.
|
|
|
|
|
|
WARNING:Cpld:1007 - Removing unused input(s) 'DBG<1>'. The input(s) are unused
|
|
|
|
|
|
after optimization. Please verify functionality via simulation.
|
|
|
|
|
|
WARNING:Cpld:1007 - Removing unused input(s) 'DBG<2>'. The input(s) are unused
|
|
|
|
|
|
after optimization. Please verify functionality via simulation.
|
|
|
|
|
|
WARNING:Cpld:1007 - Removing unused input(s) 'DBG<3>'. The input(s) are unused
|
|
|
|
|
|
after optimization. Please verify functionality via simulation.
|
|
|
|
|
|
WARNING:Cpld:1007 - Removing unused input(s) 'DBG<4>'. The input(s) are unused
|
|
|
|
|
|
after optimization. Please verify functionality via simulation.
|
|
|
|
|
|
WARNING:Cpld:1007 - Removing unused input(s) 'DBG<5>'. The input(s) are unused
|
|
|
|
|
|
after optimization. Please verify functionality via simulation.
|
|
|
|
|
|
WARNING:Cpld:1007 - Removing unused input(s) 'nBG_IOB'. The input(s) are unused
|
|
|
|
|
|
after optimization. Please verify functionality via simulation.
|
|
|
|
|
|
************************* Summary of Mapped Logic ************************
|
|
|
|
|
|
|
2024-10-03 22:29:29 +00:00
|
|
|
|
** 37 Outputs **
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
|
|
|
|
|
|
Name Pts Inps No. Type Use Mode Rate State
|
2024-10-03 22:46:28 +00:00
|
|
|
|
nDTACK_FSB 14 17 FB3_9 28 I/O O STD FAST RESET
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nROMWE 1 6 FB3_17 34 I/O O STD FAST
|
2024-10-03 22:46:28 +00:00
|
|
|
|
nAoutOE 1 3 FB4_2 87 I/O O STD FAST SET
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nDoutOE 2 5 FB4_5 89 I/O O STD FAST
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nDinOE 3 6 FB4_6 90 I/O O STD FAST
|
|
|
|
|
|
nRES 1 1 FB4_8 91 I/O I/O STD FAST
|
2024-10-03 22:46:28 +00:00
|
|
|
|
nVPA_FSB 3 8 FB4_11 93 I/O O STD FAST RESET
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nROMOE 2 7 FB5_2 35 I/O O STD FAST
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nCAS 15 17 FB5_5 36 I/O O STD FAST RESET
|
|
|
|
|
|
nOE 3 5 FB5_6 37 I/O O STD FAST RESET
|
2024-09-29 07:29:49 +00:00
|
|
|
|
RA<4> 2 3 FB5_9 40 I/O O STD FAST
|
|
|
|
|
|
RA<3> 2 3 FB5_11 41 I/O O STD FAST
|
|
|
|
|
|
RA<5> 2 3 FB5_12 42 I/O O STD FAST
|
|
|
|
|
|
RA<2> 2 3 FB5_14 43 I/O O STD FAST
|
|
|
|
|
|
RA<6> 2 3 FB5_15 46 I/O O STD FAST
|
|
|
|
|
|
nVMA_IOB 3 8 FB6_2 74 I/O O STD FAST RESET
|
|
|
|
|
|
nLDS_IOB 6 10 FB6_9 79 I/O O STD FAST RESET
|
|
|
|
|
|
nUDS_IOB 6 10 FB6_11 80 I/O O STD FAST RESET
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nAS_IOB 4 9 FB6_12 81 I/O O STD FAST RESET
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nADoutLE1 2 3 FB6_14 82 I/O O STD FAST SET
|
|
|
|
|
|
nADoutLE0 1 2 FB6_15 85 I/O O STD FAST
|
|
|
|
|
|
nDinLE 1 2 FB6_17 86 I/O O STD FAST RESET
|
|
|
|
|
|
RA<1> 2 3 FB7_2 50 I/O O STD FAST
|
|
|
|
|
|
RA<7> 2 3 FB7_5 52 I/O O STD FAST
|
|
|
|
|
|
RA<0> 2 3 FB7_6 53 I/O O STD FAST
|
|
|
|
|
|
RA<8> 2 3 FB7_8 54 I/O O STD FAST
|
|
|
|
|
|
RA<10> 2 3 FB7_9 55 I/O O STD FAST
|
|
|
|
|
|
RA<9> 2 3 FB7_11 56 I/O O STD FAST
|
2024-10-03 22:29:29 +00:00
|
|
|
|
MCKE 0 0 FB7_12 58 I/O O STD FAST
|
2024-10-03 22:46:28 +00:00
|
|
|
|
GA<23> 1 1 FB7_15 60 I/O O STD FAST
|
|
|
|
|
|
GA<22> 1 1 FB7_17 61 I/O O STD FAST
|
2024-09-29 07:29:49 +00:00
|
|
|
|
RA<11> 2 3 FB8_2 63 I/O O STD FAST
|
|
|
|
|
|
nRAS 3 7 FB8_5 64 I/O O STD FAST
|
|
|
|
|
|
nRAMLWE 1 3 FB8_6 65 I/O O STD FAST
|
|
|
|
|
|
nRAMUWE 1 3 FB8_8 66 I/O O STD FAST
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nBERR_FSB 3 5 FB8_12 70 I/O O STD FAST RESET
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nBR_IOB 2 4 FB8_15 72 I/O O STD FAST RESET
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
** 99 Buried Nodes **
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signal Total Total Loc Pwr Reg Init
|
|
|
|
|
|
Name Pts Inps Mode State
|
2024-10-01 05:09:25 +00:00
|
|
|
|
ram/RS_FSM_FFd4 1 2 FB1_1 STD RESET
|
|
|
|
|
|
ram/RASrf 1 1 FB1_2 STD RESET
|
2024-10-03 22:46:28 +00:00
|
|
|
|
iobs/Clear1 1 2 FB1_3 STD RESET
|
|
|
|
|
|
cnt/LTimer<0> 1 1 FB1_4 STD RESET
|
|
|
|
|
|
cnt/C8Mr<3> 1 1 FB1_5 STD RESET
|
|
|
|
|
|
cnt/C8Mr<2> 1 1 FB1_6 STD RESET
|
|
|
|
|
|
cnt/C8Mr<1> 1 1 FB1_7 STD RESET
|
|
|
|
|
|
ALE0S 1 1 FB1_8 STD RESET
|
|
|
|
|
|
ram/RS_FSM_FFd5 2 3 FB1_9 STD RESET
|
|
|
|
|
|
iobs/TS_FSM_FFd1 2 3 FB1_10 STD RESET
|
|
|
|
|
|
iobs/IOU1 2 2 FB1_11 STD RESET
|
|
|
|
|
|
iobs/IOL1 2 2 FB1_12 STD RESET
|
|
|
|
|
|
cnt/LTimer<3> 2 4 FB1_13 STD RESET
|
|
|
|
|
|
cnt/LTimer<2> 2 3 FB1_14 STD RESET
|
|
|
|
|
|
cnt/LTimer<1> 2 2 FB1_15 STD RESET
|
|
|
|
|
|
cnt/IS<1> 2 4 FB1_16 STD RESET
|
|
|
|
|
|
cnt/nPOR 3 5 FB1_17 STD RESET
|
|
|
|
|
|
cnt/IS<0> 3 5 FB1_18 STD RESET
|
|
|
|
|
|
ram/RS_FSM_FFd1 1 1 FB2_1 STD RESET
|
|
|
|
|
|
ram/DTACKr 1 1 FB2_2 STD RESET
|
|
|
|
|
|
iobs/IODONEr 1 1 FB2_3 STD RESET
|
|
|
|
|
|
iobs/IOACTr 1 1 FB2_4 STD RESET
|
|
|
|
|
|
iobm/VPAr 1 1 FB2_5 STD RESET
|
|
|
|
|
|
iobm/IOWRREQr 1 1 FB2_6 STD RESET
|
|
|
|
|
|
iobm/IOS_FSM_FFd5 1 1 FB2_7 STD RESET
|
|
|
|
|
|
iobm/IOS_FSM_FFd4 1 1 FB2_8 STD RESET
|
|
|
|
|
|
iobm/IOS_FSM_FFd1 1 1 FB2_9 STD RESET
|
|
|
|
|
|
iobm/IORDREQr 1 1 FB2_10 STD RESET
|
|
|
|
|
|
iobm/Er 1 1 FB2_11 STD RESET
|
|
|
|
|
|
iobm/C8Mr 1 1 FB2_12 STD RESET
|
|
|
|
|
|
fsb/ASrf 1 1 FB2_13 STD RESET
|
|
|
|
|
|
cnt/Er<0> 1 1 FB2_14 STD RESET
|
|
|
|
|
|
cnt/C8Mr<0> 1 1 FB2_15 STD RESET
|
|
|
|
|
|
iobm/IOS_FSM_FFd2 2 4 FB2_16 STD RESET
|
|
|
|
|
|
IOBERR 2 2 FB2_17 STD RESET
|
|
|
|
|
|
iobm/ES<2> 3 5 FB2_18 STD RESET
|
|
|
|
|
|
cnt/Wait<0> 1 3 FB3_1 STD RESET
|
|
|
|
|
|
cnt/LTimerTick 1 13 FB3_2 STD RESET
|
|
|
|
|
|
BACTr 1 2 FB3_3 STD RESET
|
|
|
|
|
|
cnt/LTimer<9> 2 10 FB3_4 STD RESET
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signal Total Total Loc Pwr Reg Init
|
|
|
|
|
|
Name Pts Inps Mode State
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/LTimer<8> 2 9 FB3_5 STD RESET
|
|
|
|
|
|
cnt/LTimer<7> 2 8 FB3_6 STD RESET
|
|
|
|
|
|
cnt/LTimer<6> 2 7 FB3_7 STD RESET
|
|
|
|
|
|
cnt/QS<3> 2 7 FB3_8 STD RESET
|
|
|
|
|
|
cnt/LTimer<11> 2 12 FB3_10 STD RESET
|
|
|
|
|
|
cnt/LTimer<10> 2 11 FB3_11 STD RESET
|
|
|
|
|
|
QoSEN 2 6 FB3_12 STD RESET
|
|
|
|
|
|
cnt/SndQS<1> 3 5 FB3_13 STD RESET
|
|
|
|
|
|
cnt/SndQS<0> 3 5 FB3_14 STD RESET
|
|
|
|
|
|
cnt/QS<0> 3 7 FB3_15 STD RESET
|
|
|
|
|
|
cnt/QS<2> 4 7 FB3_16 STD RESET
|
|
|
|
|
|
cnt/QS<1> 4 7 FB3_18 STD RESET
|
|
|
|
|
|
ram/RASEN 10 12 FB4_1 STD RESET
|
|
|
|
|
|
IORDREQ 9 15 FB4_3 STD RESET
|
|
|
|
|
|
ram/RS_FSM_FFd7 9 11 FB4_4 STD RESET
|
|
|
|
|
|
SndQoSReady 7 10 FB4_7 STD RESET
|
|
|
|
|
|
cnt/QoSCSr 5 7 FB4_9 STD RESET
|
|
|
|
|
|
IONPReady 4 15 FB4_10 STD RESET
|
|
|
|
|
|
cnt/Wait<1> 3 4 FB4_12 STD RESET
|
|
|
|
|
|
cnt/Wait<2> 3 5 FB4_13 STD RESET
|
|
|
|
|
|
cnt/Wait<3> 3 6 FB4_14 STD RESET
|
|
|
|
|
|
ram/RASEL 3 8 FB4_15 STD RESET
|
|
|
|
|
|
nRESout 2 4 FB4_16 STD RESET
|
|
|
|
|
|
ram/RS_FSM_FFd6 2 7 FB4_17 STD RESET
|
|
|
|
|
|
ram/RefDone 2 7 FB4_18 STD RESET
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RS_FSM_FFd8 13 13 FB5_1 STD SET
|
2024-10-03 22:46:28 +00:00
|
|
|
|
ram/RS_FSM_FFd3 1 1 FB5_7 STD RESET
|
|
|
|
|
|
iobs/Load1 4 16 FB5_8 STD RESET
|
|
|
|
|
|
cnt/SndQoSCSr 8 19 FB5_10 STD RESET
|
2024-10-03 22:29:29 +00:00
|
|
|
|
RAMReady 10 14 FB5_13 STD RESET
|
2024-10-03 22:46:28 +00:00
|
|
|
|
iobs/IORW1 4 17 FB5_16 STD RESET
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RASrr 12 13 FB5_18 STD RESET
|
|
|
|
|
|
iobm/IOS_FSM_FFd6 2 5 FB6_1 STD RESET
|
|
|
|
|
|
iobm/IOS_FSM_FFd7 3 6 FB6_3 STD SET
|
|
|
|
|
|
iobm/IOS_FSM_FFd3 3 5 FB6_4 STD RESET
|
2024-09-29 07:29:49 +00:00
|
|
|
|
iobm/ES<0> 3 6 FB6_5 STD RESET
|
|
|
|
|
|
iobm/ES<3> 4 6 FB6_6 STD RESET
|
|
|
|
|
|
iobm/ES<1> 4 6 FB6_7 STD RESET
|
2024-10-03 22:29:29 +00:00
|
|
|
|
iobm/DoutOE 4 8 FB6_8 STD RESET
|
|
|
|
|
|
IODONE 4 8 FB6_10 STD RESET
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signal Total Total Loc Pwr Reg Init
|
|
|
|
|
|
Name Pts Inps Mode State
|
2024-10-03 22:46:28 +00:00
|
|
|
|
iobm/IOS0 5 12 FB6_13 STD RESET
|
|
|
|
|
|
ALE0M 5 11 FB6_16 STD RESET
|
|
|
|
|
|
IOACT 8 14 FB6_18 STD RESET
|
|
|
|
|
|
cnt/TimerTick 1 6 FB7_1 STD RESET
|
|
|
|
|
|
cnt/Er<1> 1 1 FB7_3 STD RESET
|
|
|
|
|
|
cnt/Timer<2> 2 4 FB7_4 STD RESET
|
|
|
|
|
|
cnt/Timer<0> 2 6 FB7_7 STD RESET
|
|
|
|
|
|
cnt/LTimer<5> 2 6 FB7_10 STD RESET
|
|
|
|
|
|
cnt/LTimer<4> 2 5 FB7_13 STD RESET
|
|
|
|
|
|
RefReq 2 6 FB7_14 STD RESET
|
|
|
|
|
|
cnt/Timer<1> 3 6 FB7_16 STD RESET
|
|
|
|
|
|
RefUrg 3 6 FB7_18 STD RESET
|
2024-10-03 22:29:29 +00:00
|
|
|
|
IOL0 15 19 FB8_1 STD RESET
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cs/Overlay 3 8 FB8_3 STD RESET
|
|
|
|
|
|
ram/RS_FSM_FFd2 1 1 FB8_4 STD RESET
|
|
|
|
|
|
iobs/Sent 11 16 FB8_7 STD RESET
|
2024-10-03 22:29:29 +00:00
|
|
|
|
iobs/TS_FSM_FFd2 12 17 FB8_11 STD RESET
|
|
|
|
|
|
IOWRREQ 13 19 FB8_14 STD RESET
|
|
|
|
|
|
IOU0 15 19 FB8_16 STD RESET
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
** 35 Inputs **
|
|
|
|
|
|
|
|
|
|
|
|
Signal Loc Pin Pin Pin
|
|
|
|
|
|
Name No. Type Use
|
|
|
|
|
|
A_FSB<13> FB1_2 11 I/O I
|
|
|
|
|
|
A_FSB<14> FB1_3 12 I/O I
|
|
|
|
|
|
A_FSB<15> FB1_5 13 I/O I
|
|
|
|
|
|
A_FSB<16> FB1_6 14 I/O I
|
|
|
|
|
|
A_FSB<17> FB1_8 15 I/O I
|
|
|
|
|
|
A_FSB<18> FB1_9 16 I/O I
|
|
|
|
|
|
A_FSB<19> FB1_11 17 I/O I
|
|
|
|
|
|
A_FSB<20> FB1_12 18 I/O I
|
|
|
|
|
|
A_FSB<21> FB1_14 19 I/O I
|
|
|
|
|
|
A_FSB<22> FB1_15 20 I/O I
|
|
|
|
|
|
C16M FB1_17 22 GCK/I/O GCK
|
|
|
|
|
|
A_FSB<5> FB2_6 2 GTS/I/O I
|
|
|
|
|
|
A_FSB<6> FB2_8 3 GTS/I/O I
|
|
|
|
|
|
A_FSB<7> FB2_9 4 GTS/I/O I
|
|
|
|
|
|
A_FSB<8> FB2_11 6 I/O I
|
|
|
|
|
|
A_FSB<9> FB2_12 7 I/O I
|
|
|
|
|
|
A_FSB<10> FB2_14 8 I/O I
|
|
|
|
|
|
A_FSB<11> FB2_15 9 I/O I
|
|
|
|
|
|
A_FSB<12> FB2_17 10 I/O I
|
|
|
|
|
|
C8M FB3_2 23 GCK/I/O GCK/I
|
|
|
|
|
|
A_FSB<23> FB3_5 24 I/O I
|
|
|
|
|
|
E FB3_6 25 I/O I
|
|
|
|
|
|
FCLK FB3_8 27 GCK/I/O GCK
|
|
|
|
|
|
nWE_FSB FB3_11 29 I/O I
|
|
|
|
|
|
nLDS_FSB FB3_12 30 I/O I
|
|
|
|
|
|
nAS_FSB FB3_14 32 I/O I
|
|
|
|
|
|
nUDS_FSB FB3_15 33 I/O I
|
|
|
|
|
|
nIPL2 FB4_9 92 I/O I
|
|
|
|
|
|
A_FSB<1> FB4_12 94 I/O I
|
|
|
|
|
|
A_FSB<2> FB4_14 95 I/O I
|
|
|
|
|
|
A_FSB<3> FB4_15 96 I/O I
|
|
|
|
|
|
A_FSB<4> FB4_17 97 I/O I
|
|
|
|
|
|
nBERR_IOB FB6_5 76 I/O I
|
|
|
|
|
|
nVPA_IOB FB6_6 77 I/O I
|
|
|
|
|
|
nDTACK_IOB FB6_8 78 I/O I
|
|
|
|
|
|
|
|
|
|
|
|
Legend:
|
|
|
|
|
|
Pin No. - ~ - User Assigned
|
|
|
|
|
|
************************** Function Block Details ************************
|
|
|
|
|
|
Legend:
|
|
|
|
|
|
Total Pt - Total product terms used by the macrocell signal
|
|
|
|
|
|
Imp Pt - Product terms imported from other macrocells
|
|
|
|
|
|
Exp Pt - Product terms exported to other macrocells
|
|
|
|
|
|
in direction shown
|
|
|
|
|
|
Unused Pt - Unused local product terms remaining in macrocell
|
|
|
|
|
|
Loc - Location where logic was mapped in device
|
|
|
|
|
|
Pin Type/Use - I - Input GCK - Global Clock
|
|
|
|
|
|
O - Output GTS - Global Output Enable
|
|
|
|
|
|
(b) - Buried macrocell GSR - Global Set/Reset
|
|
|
|
|
|
X - Signal used as input to the macrocell logic.
|
|
|
|
|
|
Pin No. - ~ - User Assigned
|
|
|
|
|
|
*********************************** FB1 ***********************************
|
2024-10-03 22:46:28 +00:00
|
|
|
|
Number of function block inputs used/remaining: 22/32
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 22
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-01 05:09:25 +00:00
|
|
|
|
ram/RS_FSM_FFd4 1 0 0 4 FB1_1 (b) (b)
|
|
|
|
|
|
ram/RASrf 1 0 0 4 FB1_2 11 I/O I
|
2024-10-03 22:46:28 +00:00
|
|
|
|
iobs/Clear1 1 0 0 4 FB1_3 12 I/O I
|
|
|
|
|
|
cnt/LTimer<0> 1 0 0 4 FB1_4 (b) (b)
|
|
|
|
|
|
cnt/C8Mr<3> 1 0 0 4 FB1_5 13 I/O I
|
|
|
|
|
|
cnt/C8Mr<2> 1 0 0 4 FB1_6 14 I/O I
|
|
|
|
|
|
cnt/C8Mr<1> 1 0 0 4 FB1_7 (b) (b)
|
|
|
|
|
|
ALE0S 1 0 0 4 FB1_8 15 I/O I
|
|
|
|
|
|
ram/RS_FSM_FFd5 2 0 0 3 FB1_9 16 I/O I
|
|
|
|
|
|
iobs/TS_FSM_FFd1 2 0 0 3 FB1_10 (b) (b)
|
|
|
|
|
|
iobs/IOU1 2 0 0 3 FB1_11 17 I/O I
|
|
|
|
|
|
iobs/IOL1 2 0 0 3 FB1_12 18 I/O I
|
|
|
|
|
|
cnt/LTimer<3> 2 0 0 3 FB1_13 (b) (b)
|
|
|
|
|
|
cnt/LTimer<2> 2 0 0 3 FB1_14 19 I/O I
|
|
|
|
|
|
cnt/LTimer<1> 2 0 0 3 FB1_15 20 I/O I
|
|
|
|
|
|
cnt/IS<1> 2 0 0 3 FB1_16 (b) (b)
|
|
|
|
|
|
cnt/nPOR 3 0 0 2 FB1_17 22 GCK/I/O GCK
|
|
|
|
|
|
cnt/IS<0> 3 0 0 2 FB1_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-03 22:46:28 +00:00
|
|
|
|
1: cnt/C8Mr<0> 9: cnt/LTimer<2> 16: iobs/TS_FSM_FFd2
|
|
|
|
|
|
2: cnt/C8Mr<1> 10: cnt/LTimerTick 17: nIPL2
|
|
|
|
|
|
3: cnt/C8Mr<2> 11: cnt/TimerTick 18: nLDS_FSB
|
|
|
|
|
|
4: cnt/C8Mr<3> 12: cnt/nPOR 19: nUDS_FSB
|
|
|
|
|
|
5: cnt/IS<0> 13: iobs/IOACTr 20: ram/DTACKr
|
|
|
|
|
|
6: cnt/IS<1> 14: iobs/Load1 21: ram/RS_FSM_FFd5
|
|
|
|
|
|
7: cnt/LTimer<0> 15: iobs/TS_FSM_FFd1 22: ram/RS_FSM_FFd6
|
|
|
|
|
|
8: cnt/LTimer<1>
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
2024-10-03 22:46:28 +00:00
|
|
|
|
ram/RS_FSM_FFd4 ...................XX................... 2
|
|
|
|
|
|
ram/RASrf .....................X.................. 1
|
|
|
|
|
|
iobs/Clear1 ..............XX........................ 2
|
|
|
|
|
|
cnt/LTimer<0> ..........X............................. 1
|
|
|
|
|
|
cnt/C8Mr<3> ..X..................................... 1
|
|
|
|
|
|
cnt/C8Mr<2> .X...................................... 1
|
|
|
|
|
|
cnt/C8Mr<1> X....................................... 1
|
|
|
|
|
|
ALE0S ...............X........................ 1
|
|
|
|
|
|
ram/RS_FSM_FFd5 ...................XXX.................. 3
|
|
|
|
|
|
iobs/TS_FSM_FFd1 ............X.XX........................ 3
|
|
|
|
|
|
iobs/IOU1 .............X....X..................... 2
|
|
|
|
|
|
iobs/IOL1 .............X...X...................... 2
|
|
|
|
|
|
cnt/LTimer<3> ......XXX.X............................. 4
|
|
|
|
|
|
cnt/LTimer<2> ......XX..X............................. 3
|
|
|
|
|
|
cnt/LTimer<1> ......X...X............................. 2
|
|
|
|
|
|
cnt/IS<1> ....XX...X.X............................ 4
|
|
|
|
|
|
cnt/nPOR XXXX.......X............................ 5
|
|
|
|
|
|
cnt/IS<0> ....XX...X.X....X....................... 5
|
2024-09-29 07:29:49 +00:00
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
|
|
|
|
|
*********************************** FB2 ***********************************
|
2024-10-03 22:46:28 +00:00
|
|
|
|
Number of function block inputs used/remaining: 22/32
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 22
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-03 22:46:28 +00:00
|
|
|
|
ram/RS_FSM_FFd1 1 0 0 4 FB2_1 (b) (b)
|
|
|
|
|
|
ram/DTACKr 1 0 0 4 FB2_2 99 GSR/I/O (b)
|
|
|
|
|
|
iobs/IODONEr 1 0 0 4 FB2_3 (b) (b)
|
|
|
|
|
|
iobs/IOACTr 1 0 0 4 FB2_4 (b) (b)
|
|
|
|
|
|
iobm/VPAr 1 0 0 4 FB2_5 1 GTS/I/O (b)
|
|
|
|
|
|
iobm/IOWRREQr 1 0 0 4 FB2_6 2 GTS/I/O I
|
|
|
|
|
|
iobm/IOS_FSM_FFd5 1 0 0 4 FB2_7 (b) (b)
|
|
|
|
|
|
iobm/IOS_FSM_FFd4 1 0 0 4 FB2_8 3 GTS/I/O I
|
|
|
|
|
|
iobm/IOS_FSM_FFd1 1 0 0 4 FB2_9 4 GTS/I/O I
|
|
|
|
|
|
iobm/IORDREQr 1 0 0 4 FB2_10 (b) (b)
|
|
|
|
|
|
iobm/Er 1 0 0 4 FB2_11 6 I/O I
|
|
|
|
|
|
iobm/C8Mr 1 0 0 4 FB2_12 7 I/O I
|
|
|
|
|
|
fsb/ASrf 1 0 0 4 FB2_13 (b) (b)
|
|
|
|
|
|
cnt/Er<0> 1 0 0 4 FB2_14 8 I/O I
|
|
|
|
|
|
cnt/C8Mr<0> 1 0 0 4 FB2_15 9 I/O I
|
|
|
|
|
|
iobm/IOS_FSM_FFd2 2 0 0 3 FB2_16 (b) (b)
|
|
|
|
|
|
IOBERR 2 0 0 3 FB2_17 10 I/O I
|
|
|
|
|
|
iobm/ES<2> 3 0 0 2 FB2_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-03 22:46:28 +00:00
|
|
|
|
1: C8M 9: iobm/ES<0> 16: iobm/IOS_FSM_FFd6
|
|
|
|
|
|
2: E 10: iobm/ES<1> 17: nAS_FSB
|
|
|
|
|
|
3: IOACT 11: iobm/ES<2> 18: nAS_IOB
|
|
|
|
|
|
4: IOBERR 12: iobm/Er 19: nBERR_IOB
|
|
|
|
|
|
5: IODONE 13: iobm/IOS_FSM_FFd2 20: nDTACK_FSB
|
|
|
|
|
|
6: IORDREQ 14: iobm/IOS_FSM_FFd3 21: nVPA_IOB
|
|
|
|
|
|
7: IOWRREQ 15: iobm/IOS_FSM_FFd5 22: ram/RS_FSM_FFd2
|
|
|
|
|
|
8: iobm/C8Mr
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
2024-10-03 22:46:28 +00:00
|
|
|
|
ram/RS_FSM_FFd1 .....................X.................. 1
|
|
|
|
|
|
ram/DTACKr ...................X.................... 1
|
|
|
|
|
|
iobs/IODONEr ....X................................... 1
|
|
|
|
|
|
iobs/IOACTr ..X..................................... 1
|
|
|
|
|
|
iobm/VPAr ....................X................... 1
|
|
|
|
|
|
iobm/IOWRREQr ......X................................. 1
|
|
|
|
|
|
iobm/IOS_FSM_FFd5 ...............X........................ 1
|
|
|
|
|
|
iobm/IOS_FSM_FFd4 ..............X......................... 1
|
|
|
|
|
|
iobm/IOS_FSM_FFd1 ............X........................... 1
|
|
|
|
|
|
iobm/IORDREQr .....X.................................. 1
|
|
|
|
|
|
iobm/Er .X...................................... 1
|
|
|
|
|
|
iobm/C8Mr X....................................... 1
|
|
|
|
|
|
fsb/ASrf ................X....................... 1
|
|
|
|
|
|
cnt/Er<0> .X...................................... 1
|
|
|
|
|
|
cnt/C8Mr<0> X....................................... 1
|
|
|
|
|
|
iobm/IOS_FSM_FFd2 ...XX..X.....X.......................... 4
|
|
|
|
|
|
IOBERR .................XX..................... 2
|
|
|
|
|
|
iobm/ES<2> .X......XXXX............................ 5
|
2024-09-29 07:29:49 +00:00
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
|
|
|
|
|
*********************************** FB3 ***********************************
|
2024-10-03 22:29:29 +00:00
|
|
|
|
Number of function block inputs used/remaining: 39/15
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 39
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/Wait<0> 1 0 0 4 FB3_1 (b) (b)
|
|
|
|
|
|
cnt/LTimerTick 1 0 0 4 FB3_2 23 GCK/I/O GCK/I
|
|
|
|
|
|
BACTr 1 0 0 4 FB3_3 (b) (b)
|
|
|
|
|
|
cnt/LTimer<9> 2 0 0 3 FB3_4 (b) (b)
|
|
|
|
|
|
cnt/LTimer<8> 2 0 0 3 FB3_5 24 I/O I
|
|
|
|
|
|
cnt/LTimer<7> 2 0 0 3 FB3_6 25 I/O I
|
|
|
|
|
|
cnt/LTimer<6> 2 0 \/2 1 FB3_7 (b) (b)
|
|
|
|
|
|
cnt/QS<3> 2 2<- \/5 0 FB3_8 27 GCK/I/O GCK
|
|
|
|
|
|
nDTACK_FSB 14 9<- 0 0 FB3_9 28 I/O O
|
|
|
|
|
|
cnt/LTimer<11> 2 1<- /\4 0 FB3_10 (b) (b)
|
|
|
|
|
|
cnt/LTimer<10> 2 0 /\1 2 FB3_11 29 I/O I
|
|
|
|
|
|
QoSEN 2 0 0 3 FB3_12 30 I/O I
|
|
|
|
|
|
cnt/SndQS<1> 3 0 0 2 FB3_13 (b) (b)
|
|
|
|
|
|
cnt/SndQS<0> 3 0 0 2 FB3_14 32 I/O I
|
|
|
|
|
|
cnt/QS<0> 3 0 0 2 FB3_15 33 I/O I
|
|
|
|
|
|
cnt/QS<2> 4 0 0 1 FB3_16 (b) (b)
|
|
|
|
|
|
nROMWE 1 0 0 4 FB3_17 34 I/O O
|
|
|
|
|
|
cnt/QS<1> 4 0 0 1 FB3_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-03 22:46:28 +00:00
|
|
|
|
1: A_FSB<16> 14: cnt/LTimer<10> 27: cnt/QS<2>
|
|
|
|
|
|
2: A_FSB<17> 15: cnt/LTimer<11> 28: cnt/QS<3>
|
|
|
|
|
|
3: A_FSB<18> 16: cnt/LTimer<1> 29: cnt/QoSCSr
|
|
|
|
|
|
4: A_FSB<19> 17: cnt/LTimer<2> 30: cnt/SndQS<0>
|
|
|
|
|
|
5: A_FSB<20> 18: cnt/LTimer<3> 31: cnt/SndQS<1>
|
|
|
|
|
|
6: A_FSB<21> 19: cnt/LTimer<4> 32: cnt/SndQoSCSr
|
|
|
|
|
|
7: A_FSB<22> 20: cnt/LTimer<5> 33: cnt/TimerTick
|
|
|
|
|
|
8: A_FSB<23> 21: cnt/LTimer<6> 34: cnt/Wait<0>
|
|
|
|
|
|
9: IONPReady 22: cnt/LTimer<7> 35: fsb/ASrf
|
|
|
|
|
|
10: QoSEN 23: cnt/LTimer<8> 36: iobs/Sent
|
|
|
|
|
|
11: RAMReady 24: cnt/LTimer<9> 37: nADoutLE1
|
|
|
|
|
|
12: SndQoSReady 25: cnt/QS<0> 38: nAS_FSB
|
|
|
|
|
|
13: cnt/LTimer<0> 26: cnt/QS<1> 39: nWE_FSB
|
2024-10-01 05:09:25 +00:00
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/Wait<0> .................................XX..X.. 3
|
|
|
|
|
|
cnt/LTimerTick ............XXXXXXXXXXXX........X....... 13
|
|
|
|
|
|
BACTr ..................................X..X.. 2
|
|
|
|
|
|
cnt/LTimer<9> ............X..XXXXXXXX.........X....... 10
|
|
|
|
|
|
cnt/LTimer<8> ............X..XXXXXXX..........X....... 9
|
|
|
|
|
|
cnt/LTimer<7> ............X..XXXXXX...........X....... 8
|
|
|
|
|
|
cnt/LTimer<6> ............X..XXXXX............X....... 7
|
|
|
|
|
|
cnt/QS<3> ........................XXXXX..XX....... 7
|
|
|
|
|
|
nDTACK_FSB XXXXXXXXXXXX......................XXXXX. 17
|
|
|
|
|
|
cnt/LTimer<11> ............XX.XXXXXXXXX........X....... 12
|
|
|
|
|
|
cnt/LTimer<10> ............X..XXXXXXXXX........X....... 11
|
|
|
|
|
|
QoSEN ........................XXXX......X..X.. 6
|
|
|
|
|
|
cnt/SndQS<1> ............................XXXXX....... 5
|
|
|
|
|
|
cnt/SndQS<0> ............................XXXXX....... 5
|
|
|
|
|
|
cnt/QS<0> ........................XXXXX..XX....... 7
|
|
|
|
|
|
cnt/QS<2> ........................XXXXX..XX....... 7
|
|
|
|
|
|
nROMWE ....XXXX.............................XX. 6
|
|
|
|
|
|
cnt/QS<1> ........................XXXXX..XX....... 7
|
2024-10-01 05:09:25 +00:00
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
2024-09-29 07:29:49 +00:00
|
|
|
|
*********************************** FB4 ***********************************
|
2024-10-03 22:46:28 +00:00
|
|
|
|
Number of function block inputs used/remaining: 53/1
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 53
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-03 22:46:28 +00:00
|
|
|
|
ram/RASEN 10 5<- 0 0 FB4_1 (b) (b)
|
|
|
|
|
|
nAoutOE 1 0 \/4 0 FB4_2 87 I/O O
|
|
|
|
|
|
IORDREQ 9 4<- 0 0 FB4_3 (b) (b)
|
|
|
|
|
|
ram/RS_FSM_FFd7 9 4<- 0 0 FB4_4 (b) (b)
|
|
|
|
|
|
nDoutOE 2 1<- /\4 0 FB4_5 89 I/O O
|
|
|
|
|
|
nDinOE 3 0 /\1 1 FB4_6 90 I/O O
|
|
|
|
|
|
SndQoSReady 7 2<- 0 0 FB4_7 (b) (b)
|
|
|
|
|
|
nRES 1 0 /\2 2 FB4_8 91 I/O I/O
|
|
|
|
|
|
cnt/QoSCSr 5 0 0 0 FB4_9 92 I/O I
|
|
|
|
|
|
IONPReady 4 0 0 1 FB4_10 (b) (b)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
nVPA_FSB 3 0 0 2 FB4_11 93 I/O O
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/Wait<1> 3 0 0 2 FB4_12 94 I/O I
|
|
|
|
|
|
cnt/Wait<2> 3 0 0 2 FB4_13 (b) (b)
|
|
|
|
|
|
cnt/Wait<3> 3 0 0 2 FB4_14 95 I/O I
|
|
|
|
|
|
ram/RASEL 3 0 0 2 FB4_15 96 I/O I
|
|
|
|
|
|
nRESout 2 0 0 3 FB4_16 (b) (b)
|
|
|
|
|
|
ram/RS_FSM_FFd6 2 0 \/2 1 FB4_17 97 I/O I
|
|
|
|
|
|
ram/RefDone 2 2<- \/5 0 FB4_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-03 22:46:28 +00:00
|
|
|
|
1: A_FSB<16> 19: cnt/LTimerTick 37: iobs/TS_FSM_FFd1
|
|
|
|
|
|
2: A_FSB<17> 20: cnt/QoSCSr 38: iobs/TS_FSM_FFd2
|
|
|
|
|
|
3: A_FSB<18> 21: cnt/SndQS<0> 39: nADoutLE1
|
|
|
|
|
|
4: A_FSB<19> 22: cnt/SndQS<1> 40: nAS_FSB
|
|
|
|
|
|
5: A_FSB<20> 23: cnt/Wait<0> 41: nAoutOE
|
|
|
|
|
|
6: A_FSB<21> 24: cnt/Wait<1> 42: nBR_IOB
|
|
|
|
|
|
7: BACTr 25: cnt/Wait<2> 43: nRESout
|
|
|
|
|
|
8: A_FSB<22> 26: cnt/Wait<3> 44: nWE_FSB
|
|
|
|
|
|
9: A_FSB<23> 27: cs/Overlay 45: ram/RASEN
|
|
|
|
|
|
10: IONPReady 28: fsb/ASrf 46: ram/RS_FSM_FFd1
|
|
|
|
|
|
11: IORDREQ 29: iobm/DoutOE 47: ram/RS_FSM_FFd2
|
|
|
|
|
|
12: nRES.PIN 30: iobm/IORDREQr 48: ram/RS_FSM_FFd3
|
|
|
|
|
|
13: QoSEN 31: iobm/IOS0 49: ram/RS_FSM_FFd4
|
|
|
|
|
|
14: RefReq 32: iobm/IOWRREQr 50: ram/RS_FSM_FFd6
|
|
|
|
|
|
15: RefUrg 33: iobs/IOACTr 51: ram/RS_FSM_FFd7
|
|
|
|
|
|
16: SndQoSReady 34: iobs/IODONEr 52: ram/RS_FSM_FFd8
|
|
|
|
|
|
17: cnt/IS<0> 35: iobs/IORW1 53: ram/RefDone
|
|
|
|
|
|
18: cnt/IS<1> 36: iobs/Sent
|
|
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 5 6 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
|
|
|
|
ram/RASEN ......XXX....XX............X...........X....XX..X..XX....... 12
|
|
|
|
|
|
nAoutOE ................XX.......................X.................. 3
|
|
|
|
|
|
IORDREQ ....XX.XX.X.X..............X....X.XXXXXX...X................ 15
|
|
|
|
|
|
ram/RS_FSM_FFd7 ......XXX....XX............X...........X....X...X..XX....... 11
|
|
|
|
|
|
nDoutOE ............................XXXX........X................... 5
|
|
|
|
|
|
nDinOE ....XX.XX..............................X...X................ 6
|
|
|
|
|
|
SndQoSReady ...............X...XXXXXXX.X...........X.................... 10
|
|
|
|
|
|
nRES ..........................................X................. 1
|
|
|
|
|
|
cnt/QoSCSr ....XX.XX..X...............X...........X.................... 7
|
|
|
|
|
|
IONPReady XXXXXX.XXX..X..............X.....X.X...X...X................ 15
|
|
|
|
|
|
nVPA_FSB ....XX.XXX.....X...........X...........X.................... 8
|
|
|
|
|
|
cnt/Wait<1> ......................XX...X...........X.................... 4
|
|
|
|
|
|
cnt/Wait<2> ......................XXX..X...........X.................... 5
|
|
|
|
|
|
cnt/Wait<3> ......................XXXX.X...........X.................... 6
|
|
|
|
|
|
ram/RASEL .......XX.................XX...........X....X....X.X........ 8
|
|
|
|
|
|
nRESout ................XXX.......................X................. 4
|
|
|
|
|
|
ram/RS_FSM_FFd6 .......XX.................XX...........X....X......X........ 7
|
|
|
|
|
|
ram/RefDone .............XX..............................XXX..X.X....... 7
|
|
|
|
|
|
0----+----1----+----2----+----3----+----4----+----5----+----6
|
|
|
|
|
|
0 0 0 0 0 0
|
2024-09-29 07:29:49 +00:00
|
|
|
|
*********************************** FB5 ***********************************
|
2024-10-03 22:46:28 +00:00
|
|
|
|
Number of function block inputs used/remaining: 45/9
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 45
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RS_FSM_FFd8 13 8<- 0 0 FB5_1 (b) (b)
|
|
|
|
|
|
nROMOE 2 2<- /\5 0 FB5_2 35 I/O O
|
|
|
|
|
|
(unused) 0 0 /\2 3 FB5_3 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
(unused) 0 0 \/5 0 FB5_4 (b) (b)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nCAS 15 10<- 0 0 FB5_5 36 I/O O
|
|
|
|
|
|
nOE 3 3<- /\5 0 FB5_6 37 I/O O
|
2024-10-03 22:46:28 +00:00
|
|
|
|
ram/RS_FSM_FFd3 1 0 /\3 1 FB5_7 (b) (b)
|
|
|
|
|
|
iobs/Load1 4 0 0 1 FB5_8 39 I/O (b)
|
|
|
|
|
|
RA<4> 2 0 \/3 0 FB5_9 40 I/O O
|
|
|
|
|
|
cnt/SndQoSCSr 8 3<- 0 0 FB5_10 (b) (b)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
RA<3> 2 0 \/2 1 FB5_11 41 I/O O
|
|
|
|
|
|
RA<5> 2 2<- \/5 0 FB5_12 42 I/O O
|
|
|
|
|
|
RAMReady 10 5<- 0 0 FB5_13 (b) (b)
|
|
|
|
|
|
RA<2> 2 0 \/1 2 FB5_14 43 I/O O
|
|
|
|
|
|
RA<6> 2 1<- \/4 0 FB5_15 46 I/O O
|
2024-10-03 22:46:28 +00:00
|
|
|
|
iobs/IORW1 4 4<- \/5 0 FB5_16 (b) (b)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
(unused) 0 0 \/5 0 FB5_17 49 I/O (b)
|
|
|
|
|
|
ram/RASrr 12 10<- \/3 0 FB5_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-03 22:46:28 +00:00
|
|
|
|
1: A_FSB<10> 16: A_FSB<7> 31: nADoutLE1
|
|
|
|
|
|
2: A_FSB<11> 17: A_FSB<8> 32: nAS_FSB
|
|
|
|
|
|
3: A_FSB<12> 18: A_FSB<9> 33: nWE_FSB
|
|
|
|
|
|
4: A_FSB<13> 19: BACTr 34: ram/DTACKr
|
|
|
|
|
|
5: A_FSB<14> 20: A_FSB<22> 35: ram/RASEL
|
|
|
|
|
|
6: A_FSB<15> 21: A_FSB<23> 36: ram/RASEN
|
|
|
|
|
|
7: A_FSB<16> 22: QoSEN 37: ram/RS_FSM_FFd1
|
|
|
|
|
|
8: A_FSB<17> 23: RefReq 38: ram/RS_FSM_FFd2
|
|
|
|
|
|
9: A_FSB<18> 24: RefUrg 39: ram/RS_FSM_FFd3
|
|
|
|
|
|
10: A_FSB<19> 25: cs/Overlay 40: ram/RS_FSM_FFd4
|
|
|
|
|
|
11: A_FSB<20> 26: fsb/ASrf 41: ram/RS_FSM_FFd5
|
|
|
|
|
|
12: A_FSB<21> 27: iobs/IORW1 42: ram/RS_FSM_FFd6
|
|
|
|
|
|
13: A_FSB<3> 28: iobs/Sent 43: ram/RS_FSM_FFd7
|
|
|
|
|
|
14: A_FSB<4> 29: iobs/TS_FSM_FFd1 44: ram/RS_FSM_FFd8
|
|
|
|
|
|
15: A_FSB<5> 30: iobs/TS_FSM_FFd2 45: ram/RefDone
|
|
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 5 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
|
|
|
|
ram/RS_FSM_FFd8 ..................XXX.XXXX.....X...XX..X...XX..... 13
|
|
|
|
|
|
nROMOE ..........XX.......XX...X......XX................. 7
|
|
|
|
|
|
nCAS ..................XXX.XX.X.....X.X.XXXXXX.XXX..... 17
|
|
|
|
|
|
nOE ..................X......X.....XXX................ 5
|
|
|
|
|
|
ram/RS_FSM_FFd3 ..........................................X....... 1
|
|
|
|
|
|
iobs/Load1 ......XXXXXX.......XXX...X.XXXXXX................. 16
|
|
|
|
|
|
RA<4> .X..........X.....................X............... 3
|
|
|
|
|
|
cnt/SndQoSCSr XXXXXXXXXXXX....XX.XX....X.....XX................. 19
|
|
|
|
|
|
RA<3> .........XX.......................X............... 3
|
|
|
|
|
|
RA<5> ..X..........X....................X............... 3
|
|
|
|
|
|
RAMReady ..................XXX.XX.X.....X...XX..XXX.XX..... 14
|
|
|
|
|
|
RA<2> ......X........X..................X............... 3
|
|
|
|
|
|
RA<6> ...X..........X...................X............... 3
|
|
|
|
|
|
iobs/IORW1 ......XXXXXX.......XXX...XXXXXXXX................. 17
|
|
|
|
|
|
ram/RASrr ..................XXX.XXXX.....X...X...X..XXX..... 13
|
|
|
|
|
|
0----+----1----+----2----+----3----+----4----+----5
|
|
|
|
|
|
0 0 0 0 0
|
2024-09-29 07:29:49 +00:00
|
|
|
|
*********************************** FB6 ***********************************
|
2024-10-03 22:29:29 +00:00
|
|
|
|
Number of function block inputs used/remaining: 36/18
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 36
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-03 22:29:29 +00:00
|
|
|
|
iobm/IOS_FSM_FFd6 2 0 0 3 FB6_1 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nVMA_IOB 3 0 0 2 FB6_2 74 I/O O
|
2024-10-03 22:29:29 +00:00
|
|
|
|
iobm/IOS_FSM_FFd7 3 0 0 2 FB6_3 (b) (b)
|
|
|
|
|
|
iobm/IOS_FSM_FFd3 3 0 0 2 FB6_4 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
iobm/ES<0> 3 0 0 2 FB6_5 76 I/O I
|
|
|
|
|
|
iobm/ES<3> 4 0 0 1 FB6_6 77 I/O I
|
|
|
|
|
|
iobm/ES<1> 4 0 0 1 FB6_7 (b) (b)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
iobm/DoutOE 4 0 \/1 0 FB6_8 78 I/O I
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nLDS_IOB 6 1<- 0 0 FB6_9 79 I/O O
|
2024-10-03 22:29:29 +00:00
|
|
|
|
IODONE 4 0 \/1 0 FB6_10 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nUDS_IOB 6 1<- 0 0 FB6_11 80 I/O O
|
|
|
|
|
|
nAS_IOB 4 0 0 1 FB6_12 81 I/O O
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobm/IOS0 5 0 0 0 FB6_13 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nADoutLE1 2 0 0 3 FB6_14 82 I/O O
|
|
|
|
|
|
nADoutLE0 1 0 0 4 FB6_15 85 I/O O
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ALE0M 5 0 0 0 FB6_16 (b) (b)
|
|
|
|
|
|
nDinLE 1 0 \/3 1 FB6_17 86 I/O O
|
|
|
|
|
|
IOACT 8 3<- 0 0 FB6_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-03 22:29:29 +00:00
|
|
|
|
1: ALE0M 13: iobm/ES<1> 25: iobm/IOS_FSM_FFd7
|
|
|
|
|
|
2: ALE0S 14: iobm/ES<2> 26: iobm/IOWRREQr
|
|
|
|
|
|
3: E 15: iobm/ES<3> 27: iobm/VPAr
|
|
|
|
|
|
4: IOACT 16: iobm/Er 28: iobs/Clear1
|
|
|
|
|
|
5: IOBERR 17: iobm/IORDREQr 29: iobs/Load1
|
|
|
|
|
|
6: IODONE 18: iobm/IOS0 30: nADoutLE1
|
|
|
|
|
|
7: IOL0 19: iobm/IOS_FSM_FFd1 31: nAS_IOB
|
|
|
|
|
|
8: IOU0 20: iobm/IOS_FSM_FFd2 32: nAoutOE
|
|
|
|
|
|
9: nRES.PIN 21: iobm/IOS_FSM_FFd3 33: nDTACK_IOB
|
|
|
|
|
|
10: iobm/C8Mr 22: iobm/IOS_FSM_FFd4 34: nLDS_IOB
|
|
|
|
|
|
11: iobm/DoutOE 23: iobm/IOS_FSM_FFd5 35: nUDS_IOB
|
|
|
|
|
|
12: iobm/ES<0> 24: iobm/IOS_FSM_FFd6 36: nVMA_IOB
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
2024-10-03 22:29:29 +00:00
|
|
|
|
iobm/IOS_FSM_FFd6 .........X......X.......XX.....X........ 5
|
|
|
|
|
|
nVMA_IOB ...X.......XXXX...........X....X...X.... 8
|
|
|
|
|
|
iobm/IOS_FSM_FFd7 .........X......X.X.....XX.....X........ 6
|
|
|
|
|
|
iobm/IOS_FSM_FFd3 ....XX...X..........XX.................. 5
|
|
|
|
|
|
iobm/ES<0> ..X........XXXXX........................ 6
|
|
|
|
|
|
iobm/ES<3> ..X........XXXXX........................ 6
|
|
|
|
|
|
iobm/ES<1> ..X........XXXXX........................ 6
|
|
|
|
|
|
iobm/DoutOE .........XX.........XXXXXX.............. 8
|
|
|
|
|
|
nLDS_IOB ......X..X......X...XXXXX......X.X...... 10
|
|
|
|
|
|
IODONE ........X..XXXX...............X.X..X.... 8
|
|
|
|
|
|
nUDS_IOB .......X.X......X...XXXXX......X..X..... 10
|
|
|
|
|
|
nAS_IOB .........X......X...XXXXXX.....X........ 9
|
|
|
|
|
|
iobm/IOS0 .........X......XXXXXXXXXX.....X........ 12
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nADoutLE1 ...........................XXX.......... 3
|
|
|
|
|
|
nADoutLE0 XX...................................... 2
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ALE0M X...............X.XXXXXXXX.....X........ 11
|
|
|
|
|
|
nDinLE ....................XX.................. 2
|
|
|
|
|
|
IOACT ...XXX...X......X.XXXXXXXX.....X........ 14
|
2024-09-29 07:29:49 +00:00
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
|
|
|
|
|
*********************************** FB7 ***********************************
|
2024-10-03 22:46:28 +00:00
|
|
|
|
Number of function block inputs used/remaining: 27/27
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 27
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/TimerTick 1 0 0 4 FB7_1 (b) (b)
|
|
|
|
|
|
RA<1> 2 0 0 3 FB7_2 50 I/O O
|
|
|
|
|
|
cnt/Er<1> 1 0 0 4 FB7_3 (b) (b)
|
|
|
|
|
|
cnt/Timer<2> 2 0 0 3 FB7_4 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
RA<7> 2 0 0 3 FB7_5 52 I/O O
|
|
|
|
|
|
RA<0> 2 0 0 3 FB7_6 53 I/O O
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/Timer<0> 2 0 0 3 FB7_7 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
RA<8> 2 0 0 3 FB7_8 54 I/O O
|
|
|
|
|
|
RA<10> 2 0 0 3 FB7_9 55 I/O O
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/LTimer<5> 2 0 0 3 FB7_10 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
RA<9> 2 0 0 3 FB7_11 56 I/O O
|
2024-10-01 05:09:25 +00:00
|
|
|
|
MCKE 0 0 0 5 FB7_12 58 I/O O
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/LTimer<4> 2 0 0 3 FB7_13 (b) (b)
|
|
|
|
|
|
RefReq 2 0 0 3 FB7_14 59 I/O (b)
|
|
|
|
|
|
GA<23> 1 0 0 4 FB7_15 60 I/O O
|
|
|
|
|
|
cnt/Timer<1> 3 0 0 2 FB7_16 (b) (b)
|
|
|
|
|
|
GA<22> 1 0 0 4 FB7_17 61 I/O O
|
|
|
|
|
|
RefUrg 3 0 0 2 FB7_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-03 22:46:28 +00:00
|
|
|
|
1: A_FSB<10> 10: A_FSB<7> 19: cnt/LTimer<1>
|
|
|
|
|
|
2: A_FSB<14> 11: A_FSB<8> 20: cnt/LTimer<2>
|
|
|
|
|
|
3: A_FSB<15> 12: A_FSB<9> 21: cnt/LTimer<3>
|
|
|
|
|
|
4: A_FSB<17> 13: A_FSB<22> 22: cnt/LTimer<4>
|
|
|
|
|
|
5: A_FSB<18> 14: A_FSB<23> 23: cnt/Timer<0>
|
|
|
|
|
|
6: A_FSB<1> 15: RefUrg 24: cnt/Timer<1>
|
|
|
|
|
|
7: A_FSB<21> 16: cnt/Er<0> 25: cnt/Timer<2>
|
|
|
|
|
|
8: A_FSB<2> 17: cnt/Er<1> 26: cnt/TimerTick
|
|
|
|
|
|
9: A_FSB<6> 18: cnt/LTimer<0> 27: ram/RASEL
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
2024-10-01 03:36:18 +00:00
|
|
|
|
Signal 1 2 3 4 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/TimerTick ..............XXX.....XXX............... 6
|
|
|
|
|
|
RA<1> X......X..................X............. 3
|
|
|
|
|
|
cnt/Er<1> ...............X........................ 1
|
|
|
|
|
|
cnt/Timer<2> ...............XX.....XX................ 4
|
|
|
|
|
|
RA<7> .X......X.................X............. 3
|
|
|
|
|
|
RA<0> .....X.....X..............X............. 3
|
|
|
|
|
|
cnt/Timer<0> ..............XXX.....XXX............... 6
|
|
|
|
|
|
RA<8> ....X.X...................X............. 3
|
|
|
|
|
|
RA<10> ...X.....X................X............. 3
|
|
|
|
|
|
cnt/LTimer<5> .................XXXXX...X.............. 6
|
|
|
|
|
|
RA<9> ..X.......X...............X............. 3
|
2024-10-01 05:09:25 +00:00
|
|
|
|
MCKE ........................................ 0
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/LTimer<4> .................XXXX....X.............. 5
|
|
|
|
|
|
RefReq ..............XXX.....XXX............... 6
|
|
|
|
|
|
GA<23> .............X.......................... 1
|
|
|
|
|
|
cnt/Timer<1> ..............XXX.....XXX............... 6
|
|
|
|
|
|
GA<22> ............X........................... 1
|
|
|
|
|
|
RefUrg ..............XXX.....XXX............... 6
|
2024-10-01 03:36:18 +00:00
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
2024-09-29 07:29:49 +00:00
|
|
|
|
*********************************** FB8 ***********************************
|
2024-10-03 22:46:28 +00:00
|
|
|
|
Number of function block inputs used/remaining: 38/16
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 38
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-03 22:29:29 +00:00
|
|
|
|
IOL0 15 10<- 0 0 FB8_1 (b) (b)
|
|
|
|
|
|
RA<11> 2 2<- /\5 0 FB8_2 63 I/O O
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cs/Overlay 3 0 /\2 0 FB8_3 (b) (b)
|
|
|
|
|
|
ram/RS_FSM_FFd2 1 0 0 4 FB8_4 (b) (b)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nRAS 3 0 0 2 FB8_5 64 I/O O
|
2024-10-01 05:09:25 +00:00
|
|
|
|
nRAMLWE 1 0 \/4 0 FB8_6 65 I/O O
|
2024-10-03 22:46:28 +00:00
|
|
|
|
iobs/Sent 11 6<- 0 0 FB8_7 (b) (b)
|
|
|
|
|
|
nRAMUWE 1 0 /\2 2 FB8_8 66 I/O O
|
|
|
|
|
|
(unused) 0 0 \/5 0 FB8_9 67 I/O (b)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
(unused) 0 0 \/5 0 FB8_10 (b) (b)
|
|
|
|
|
|
iobs/TS_FSM_FFd2 12 10<- \/3 0 FB8_11 68 I/O (b)
|
|
|
|
|
|
nBERR_FSB 3 3<- \/5 0 FB8_12 70 I/O O
|
|
|
|
|
|
(unused) 0 0 \/5 0 FB8_13 (b) (b)
|
|
|
|
|
|
IOWRREQ 13 10<- \/2 0 FB8_14 71 I/O (b)
|
|
|
|
|
|
nBR_IOB 2 2<- \/5 0 FB8_15 72 I/O O
|
|
|
|
|
|
IOU0 15 10<- 0 0 FB8_16 (b) (b)
|
|
|
|
|
|
(unused) 0 0 /\5 0 FB8_17 73 I/O (b)
|
|
|
|
|
|
(unused) 0 0 \/5 0 FB8_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-03 22:46:28 +00:00
|
|
|
|
1: A_FSB<16> 14: QoSEN 27: nAS_FSB
|
|
|
|
|
|
2: A_FSB<17> 15: cnt/IS<0> 28: nBERR_FSB
|
|
|
|
|
|
3: A_FSB<18> 16: cnt/IS<1> 29: nBR_IOB
|
|
|
|
|
|
4: A_FSB<19> 17: cs/Overlay 30: nIPL2
|
|
|
|
|
|
5: A_FSB<20> 18: fsb/ASrf 31: nLDS_FSB
|
|
|
|
|
|
6: A_FSB<21> 19: iobs/IOACTr 32: nUDS_FSB
|
|
|
|
|
|
7: A_FSB<22> 20: iobs/IOL1 33: nWE_FSB
|
|
|
|
|
|
8: A_FSB<23> 21: iobs/IORW1 34: ram/RASEL
|
|
|
|
|
|
9: IOBERR 22: iobs/IOU1 35: ram/RASEN
|
|
|
|
|
|
10: IOL0 23: iobs/Sent 36: ram/RASrf
|
|
|
|
|
|
11: IOU0 24: iobs/TS_FSM_FFd1 37: ram/RASrr
|
|
|
|
|
|
12: IOWRREQ 25: iobs/TS_FSM_FFd2 38: ram/RS_FSM_FFd3
|
|
|
|
|
|
13: nRES.PIN 26: nADoutLE1
|
2024-10-01 05:09:25 +00:00
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
2024-10-03 22:46:28 +00:00
|
|
|
|
IOL0 XXXXXXXX.X...X...X.X..XXXXX...X.X....... 19
|
2024-10-03 22:29:29 +00:00
|
|
|
|
RA<11> ...XX............................X...... 3
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cs/Overlay ....XXXX....X...XX........X............. 8
|
|
|
|
|
|
ram/RS_FSM_FFd2 .....................................X.. 1
|
|
|
|
|
|
nRAS ......XX........X.........X.......XXX... 7
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nRAMLWE ..............................X.XX...... 3
|
2024-10-03 22:46:28 +00:00
|
|
|
|
iobs/Sent XXXXXXXX.....X...X....XXXXX.....X....... 16
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nRAMUWE ...............................XXX...... 3
|
2024-10-03 22:46:28 +00:00
|
|
|
|
iobs/TS_FSM_FFd2 XXXXXXXX.....X...XX...XXXXX.....X....... 17
|
|
|
|
|
|
nBERR_FSB ........X........X....X...XX............ 5
|
|
|
|
|
|
IOWRREQ XXXXXXXX...X.X...XX.X.XXXXX.....X....... 19
|
|
|
|
|
|
nBR_IOB ..............XX............XX.......... 4
|
|
|
|
|
|
IOU0 XXXXXXXX..X..X...X...XXXXXX....XX....... 19
|
2024-10-01 05:09:25 +00:00
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
2024-09-29 07:29:49 +00:00
|
|
|
|
******************************* Equations ********************************
|
|
|
|
|
|
|
|
|
|
|
|
********** Mapped Logic **********
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,C16M,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
ALE0M_D <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND nAoutOE)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
iobm/IOS_FSM_FFd1)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
iobm/IOS_FSM_FFd2)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT ALE0M)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
|
|
|
|
|
NOT iobm/IORDREQr AND NOT iobm/IOWRREQr));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_ALE0S: FDCPE port map (ALE0S,iobs/TS_FSM_FFd2,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_BACTr: FDCPE port map (BACTr,BACTr_D,FCLK,'0','0');
|
2024-10-03 22:29:29 +00:00
|
|
|
|
BACTr_D <= (nAS_FSB AND NOT fsb/ASrf);
|
2024-10-01 05:09:25 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
GA(22) <= A_FSB(22);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
GA(23) <= A_FSB(23);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,C16M,'0','0');
|
|
|
|
|
|
IOACT_D <= ((iobm/IOS_FSM_FFd4)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd5)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT IOBERR AND NOT IODONE AND iobm/IOS_FSM_FFd3)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
OR (iobm/IOS_FSM_FFd7 AND iobm/IOWRREQr AND NOT nAoutOE)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND IOACT AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd3 AND iobm/C8Mr)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd7 AND iobm/IORDREQr AND NOT nAoutOE));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_IOBERR: FDCPE port map (IOBERR,NOT nBERR_IOB,NOT C8M,nAS_IOB,'0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_IODONE: FDCPE port map (IODONE,IODONE_D,NOT C8M,nAS_IOB,'0');
|
|
|
|
|
|
IODONE_D <= ((NOT nRES.PIN)
|
|
|
|
|
|
OR (NOT nDTACK_IOB)
|
|
|
|
|
|
OR (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
|
|
|
|
|
|
iobm/ES(3)));
|
|
|
|
|
|
|
2024-10-03 22:29:29 +00:00
|
|
|
|
FTCPE_IOL0: FTCPE port map (IOL0,IOL0_T,FCLK,'0','0');
|
|
|
|
|
|
IOL0_T <= ((iobs/TS_FSM_FFd1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
OR (NOT A_FSB(20) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(19) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(18) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND nWE_FSB AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT iobs/IOL1 AND NOT IOL0 AND NOT nADoutLE1)
|
|
|
|
|
|
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND
|
|
|
|
|
|
nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND NOT QoSEN AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(17) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (nLDS_FSB AND NOT IOL0 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT nLDS_FSB AND IOL0 AND nADoutLE1)
|
|
|
|
|
|
OR (iobs/IOL1 AND IOL0 AND NOT nADoutLE1));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_IONPReady: FDCPE port map (IONPReady,IONPReady_D,FCLK,'0','0');
|
2024-10-03 22:29:29 +00:00
|
|
|
|
IONPReady_D <= ((NOT iobs/Sent AND NOT IONPReady)
|
|
|
|
|
|
OR (NOT IONPReady AND NOT iobs/IODONEr)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (nAS_FSB AND NOT fsb/ASrf)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT nWE_FSB AND NOT IONPReady));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_IORDREQ: FDCPE port map (IORDREQ,IORDREQ_D,FCLK,'0','0');
|
|
|
|
|
|
IORDREQ_D <= ((NOT iobs/IORW1 AND NOT iobs/TS_FSM_FFd2 AND NOT nADoutLE1)
|
|
|
|
|
|
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND
|
|
|
|
|
|
nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND NOT QoSEN AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
|
|
|
|
|
|
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr)
|
|
|
|
|
|
OR (iobs/TS_FSM_FFd2 AND NOT IORDREQ)
|
|
|
|
|
|
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT nWE_FSB AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_IOU0: FTCPE port map (IOU0,IOU0_T,FCLK,'0','0');
|
|
|
|
|
|
IOU0_T <= ((iobs/TS_FSM_FFd1)
|
|
|
|
|
|
OR (NOT iobs/IOU1 AND NOT IOU0 AND NOT nADoutLE1)
|
|
|
|
|
|
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND
|
|
|
|
|
|
nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND NOT QoSEN AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(17) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
OR (NOT A_FSB(20) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(19) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(18) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND nWE_FSB AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (nUDS_FSB AND NOT IOU0 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT nUDS_FSB AND IOU0 AND nADoutLE1)
|
|
|
|
|
|
OR (iobs/IOU1 AND IOU0 AND NOT nADoutLE1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_IOWRREQ: FDCPE port map (IOWRREQ,IOWRREQ_D,FCLK,'0','0');
|
|
|
|
|
|
IOWRREQ_D <= ((nBERR_FSB_OBUF.EXP)
|
|
|
|
|
|
OR (iobs/TS_FSM_FFd2 AND NOT iobs/IOACTr AND IOWRREQ)
|
|
|
|
|
|
OR (NOT iobs/IORW1 AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND
|
|
|
|
|
|
NOT nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(23) AND NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(23) AND NOT iobs/Sent AND NOT nWE_FSB AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
|
|
|
|
|
|
OR (NOT iobs/Sent AND QoSEN AND NOT nWE_FSB AND NOT nAS_FSB AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2 AND IOWRREQ)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT iobs/Sent AND NOT nWE_FSB AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MCKE <= '1';
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_QoSEN: FDCPE port map (QoSEN,QoSEN_D,FCLK,'0','0',QoSEN_CE);
|
2024-10-03 22:46:28 +00:00
|
|
|
|
QoSEN_D <= (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3));
|
2024-10-03 22:29:29 +00:00
|
|
|
|
QoSEN_CE <= (nAS_FSB AND NOT fsb/ASrf);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(0) <= ((ram/RASEL AND A_FSB(1))
|
|
|
|
|
|
OR (NOT ram/RASEL AND A_FSB(9)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(1) <= ((A_FSB(10) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(2)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(2) <= ((A_FSB(16) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(7)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(3) <= ((A_FSB(20) AND ram/RASEL)
|
|
|
|
|
|
OR (A_FSB(19) AND NOT ram/RASEL));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(4) <= ((A_FSB(11) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(3)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(5) <= ((A_FSB(12) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(4)));
|
|
|
|
|
|
|
|
|
|
|
|
|
2024-10-03 22:29:29 +00:00
|
|
|
|
RA(6) <= ((ram/RASEL AND A_FSB(5))
|
|
|
|
|
|
OR (A_FSB(13) AND NOT ram/RASEL));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(7) <= ((A_FSB(14) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(6)));
|
|
|
|
|
|
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
RA(8) <= ((A_FSB(21) AND ram/RASEL)
|
|
|
|
|
|
OR (A_FSB(18) AND NOT ram/RASEL));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(9) <= ((A_FSB(15) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(8)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(10) <= ((A_FSB(17) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(7)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(11) <= ((A_FSB(20) AND ram/RASEL)
|
|
|
|
|
|
OR (A_FSB(19) AND NOT ram/RASEL));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_RAMReady: FDCPE port map (RAMReady,RAMReady_D,FCLK,'0','0');
|
2024-10-03 22:29:29 +00:00
|
|
|
|
RAMReady_D <= ((RefUrg AND NOT ram/RefDone AND nAS_FSB AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6 AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
2024-09-30 03:15:06 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd6 AND NOT BACTr)
|
2024-10-01 05:09:25 +00:00
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd6 AND NOT BACTr AND fsb/ASrf)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
2024-09-30 03:15:06 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd6 AND NOT BACTr)
|
2024-10-01 05:09:25 +00:00
|
|
|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd6 AND NOT BACTr AND fsb/ASrf)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (NOT ram/RS_FSM_FFd8 AND NOT ram/RS_FSM_FFd4 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
|
|
|
|
|
|
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
|
|
|
|
|
|
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd8 AND
|
2024-10-01 05:09:25 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RASEN AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_RefReq: FDCPE port map (RefReq,RefReq_D,FCLK,'0','0',RefReq_CE);
|
2024-10-03 22:46:28 +00:00
|
|
|
|
RefReq_D <= (RefUrg AND NOT cnt/Timer(0) AND cnt/Timer(1) AND
|
|
|
|
|
|
NOT cnt/Timer(2));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
RefReq_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_RefUrg: FTCPE port map (RefUrg,RefUrg_T,FCLK,'0','0',RefUrg_CE);
|
|
|
|
|
|
RefUrg_T <= ((cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2))
|
|
|
|
|
|
OR (RefUrg AND NOT cnt/Timer(0) AND cnt/Timer(1) AND
|
|
|
|
|
|
NOT cnt/Timer(2) AND NOT cnt/Er(0) AND cnt/Er(1)));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
RefUrg_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FDCPE_SndQoSReady: FDCPE port map (SndQoSReady,SndQoSReady_D,FCLK,'0','0');
|
|
|
|
|
|
SndQoSReady_D <= ((NOT nAS_FSB AND cnt/Wait(0) AND cnt/Wait(1) AND
|
|
|
|
|
|
cnt/Wait(2) AND cnt/Wait(3))
|
|
|
|
|
|
OR (cnt/Wait(0) AND cnt/Wait(1) AND cnt/Wait(2) AND
|
|
|
|
|
|
cnt/Wait(3) AND fsb/ASrf)
|
|
|
|
|
|
OR (SndQoSReady AND NOT nAS_FSB)
|
|
|
|
|
|
OR (SndQoSReady AND fsb/ASrf)
|
|
|
|
|
|
OR (NOT nAS_FSB AND cnt/QoSCSr)
|
|
|
|
|
|
OR (cnt/QoSCSr AND fsb/ASrf)
|
|
|
|
|
|
OR (NOT cnt/SndQS(0) AND NOT cnt/SndQS(1) AND nAS_FSB AND
|
|
|
|
|
|
NOT fsb/ASrf));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/C8Mr0: FDCPE port map (cnt/C8Mr(0),C8M,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/C8Mr1: FDCPE port map (cnt/C8Mr(1),cnt/C8Mr(0),FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/C8Mr2: FDCPE port map (cnt/C8Mr(2),cnt/C8Mr(1),FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/C8Mr3: FDCPE port map (cnt/C8Mr(3),cnt/C8Mr(2),FCLK,'0','0');
|
|
|
|
|
|
|
2024-09-29 07:29:49 +00:00
|
|
|
|
FDCPE_cnt/Er0: FDCPE port map (cnt/Er(0),E,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/Er1: FDCPE port map (cnt/Er(1),cnt/Er(0),FCLK,'0','0');
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/IS0: FTCPE port map (cnt/IS(0),cnt/IS_T(0),FCLK,'0','0');
|
|
|
|
|
|
cnt/IS_T(0) <= ((NOT cnt/nPOR AND cnt/IS(0))
|
|
|
|
|
|
OR (cnt/nPOR AND NOT cnt/IS(1) AND cnt/LTimerTick)
|
|
|
|
|
|
OR (cnt/nPOR AND NOT cnt/IS(0) AND cnt/LTimerTick AND nIPL2));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FDCPE_cnt/IS1: FDCPE port map (cnt/IS(1),cnt/IS_D(1),FCLK,'0','0');
|
|
|
|
|
|
cnt/IS_D(1) <= ((cnt/nPOR AND cnt/IS(1))
|
|
|
|
|
|
OR (cnt/nPOR AND cnt/IS(0) AND cnt/LTimerTick));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/LTimer0: FTCPE port map (cnt/LTimer(0),'1',FCLK,'0','0',cnt/TimerTick);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/LTimer1: FTCPE port map (cnt/LTimer(1),cnt/LTimer(0),FCLK,'0','0',cnt/TimerTick);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/LTimer2: FTCPE port map (cnt/LTimer(2),cnt/LTimer_T(2),FCLK,'0','0',cnt/TimerTick);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/LTimer_T(2) <= (cnt/LTimer(0) AND cnt/LTimer(1));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/LTimer3: FTCPE port map (cnt/LTimer(3),cnt/LTimer_T(3),FCLK,'0','0',cnt/TimerTick);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/LTimer_T(3) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/LTimer4: FTCPE port map (cnt/LTimer(4),cnt/LTimer_T(4),FCLK,'0','0',cnt/TimerTick);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/LTimer_T(4) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/LTimer5: FTCPE port map (cnt/LTimer(5),cnt/LTimer_T(5),FCLK,'0','0',cnt/TimerTick);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/LTimer_T(5) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/LTimer6: FTCPE port map (cnt/LTimer(6),cnt/LTimer_T(6),FCLK,'0','0',cnt/TimerTick);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/LTimer_T(6) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/LTimer7: FTCPE port map (cnt/LTimer(7),cnt/LTimer_T(7),FCLK,'0','0',cnt/TimerTick);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/LTimer_T(7) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/LTimer8: FTCPE port map (cnt/LTimer(8),cnt/LTimer_T(8),FCLK,'0','0',cnt/TimerTick);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/LTimer_T(8) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
|
|
|
|
cnt/LTimer(7));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/LTimer9: FTCPE port map (cnt/LTimer(9),cnt/LTimer_T(9),FCLK,'0','0',cnt/TimerTick);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/LTimer_T(9) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
|
|
|
|
cnt/LTimer(7) AND cnt/LTimer(8));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/LTimer10: FTCPE port map (cnt/LTimer(10),cnt/LTimer_T(10),FCLK,'0','0',cnt/TimerTick);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/LTimer_T(10) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
|
|
|
|
cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/LTimer11: FTCPE port map (cnt/LTimer(11),cnt/LTimer_T(11),FCLK,'0','0',cnt/TimerTick);
|
2024-10-01 05:09:25 +00:00
|
|
|
|
cnt/LTimer_T(11) <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND
|
|
|
|
|
|
cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
|
|
|
|
|
|
cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FDCPE_cnt/LTimerTick: FDCPE port map (cnt/LTimerTick,cnt/LTimerTick_D,FCLK,'0','0');
|
|
|
|
|
|
cnt/LTimerTick_D <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
|
|
|
|
|
|
cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9) AND
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/LTimer(11) AND cnt/TimerTick);
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/QS0: FDCPE port map (cnt/QS(0),cnt/QS_D(0),FCLK,'0','0');
|
|
|
|
|
|
cnt/QS_D(0) <= ((cnt/QS(0) AND cnt/TimerTick AND NOT cnt/QoSCSr AND
|
|
|
|
|
|
NOT cnt/SndQoSCSr)
|
|
|
|
|
|
OR (NOT cnt/QS(0) AND NOT cnt/TimerTick AND NOT cnt/QoSCSr AND
|
|
|
|
|
|
NOT cnt/SndQoSCSr)
|
|
|
|
|
|
OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND
|
|
|
|
|
|
NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/QS1: FDCPE port map (cnt/QS(1),cnt/QS_D(1),FCLK,'0','0');
|
|
|
|
|
|
cnt/QS_D(1) <= ((cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QoSCSr AND
|
|
|
|
|
|
NOT cnt/SndQoSCSr)
|
|
|
|
|
|
OR (NOT cnt/QS(1) AND NOT cnt/TimerTick AND NOT cnt/QoSCSr AND
|
|
|
|
|
|
NOT cnt/SndQoSCSr)
|
|
|
|
|
|
OR (NOT cnt/QS(0) AND cnt/QS(1) AND cnt/TimerTick AND
|
|
|
|
|
|
NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr)
|
|
|
|
|
|
OR (NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND NOT cnt/QoSCSr AND
|
|
|
|
|
|
NOT cnt/SndQoSCSr));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/QS2: FTCPE port map (cnt/QS(2),cnt/QS_T(2),FCLK,'0','0');
|
|
|
|
|
|
cnt/QS_T(2) <= ((NOT cnt/QS(2) AND cnt/QoSCSr)
|
|
|
|
|
|
OR (NOT cnt/QS(2) AND cnt/SndQoSCSr)
|
|
|
|
|
|
OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND cnt/QS(3) AND
|
|
|
|
|
|
cnt/TimerTick)
|
|
|
|
|
|
OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND cnt/QS(2) AND
|
|
|
|
|
|
cnt/TimerTick AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/QS3: FDCPE port map (cnt/QS(3),cnt/QS_D(3),FCLK,'0','0');
|
|
|
|
|
|
cnt/QS_D(3) <= ((NOT cnt/QS(3) AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr)
|
|
|
|
|
|
OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND
|
|
|
|
|
|
cnt/TimerTick AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr));
|
2024-10-03 22:29:29 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/QoSCSr: FDCPE port map (cnt/QoSCSr,cnt/QoSCSr_D,FCLK,'0','0');
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/QoSCSr_D <= ((A_FSB(21) AND NOT A_FSB(23) AND nRES.PIN)
|
|
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND nRES.PIN)
|
|
|
|
|
|
OR (NOT A_FSB(20) AND NOT A_FSB(22) AND nRES.PIN)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND nRES.PIN)
|
|
|
|
|
|
OR (nRES.PIN AND nAS_FSB AND NOT fsb/ASrf));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/SndQS0: FDCPE port map (cnt/SndQS(0),cnt/SndQS_D(0),FCLK,'0','0');
|
|
|
|
|
|
cnt/SndQS_D(0) <= ((cnt/SndQoSCSr)
|
|
|
|
|
|
OR (cnt/SndQS(0) AND NOT cnt/TimerTick AND NOT cnt/QoSCSr)
|
|
|
|
|
|
OR (NOT cnt/SndQS(0) AND cnt/SndQS(1) AND cnt/TimerTick AND
|
|
|
|
|
|
NOT cnt/QoSCSr));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/SndQS1: FDCPE port map (cnt/SndQS(1),cnt/SndQS_D(1),FCLK,'0','0');
|
|
|
|
|
|
cnt/SndQS_D(1) <= ((cnt/SndQoSCSr)
|
|
|
|
|
|
OR (cnt/SndQS(0) AND cnt/SndQS(1) AND NOT cnt/QoSCSr)
|
|
|
|
|
|
OR (cnt/SndQS(1) AND NOT cnt/TimerTick AND NOT cnt/QoSCSr));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/SndQoSCSr: FDCPE port map (cnt/SndQoSCSr,cnt/SndQoSCSr_D,FCLK,'0','0');
|
|
|
|
|
|
cnt/SndQoSCSr_D <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
NOT A_FSB(23) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
|
|
|
|
|
|
NOT nWE_FSB AND A_FSB(8) AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
NOT A_FSB(23) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
|
|
|
|
|
NOT nWE_FSB AND A_FSB(9) AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
NOT A_FSB(23) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
|
|
|
|
|
NOT nWE_FSB AND A_FSB(8) AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
NOT A_FSB(23) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
|
|
|
|
|
|
NOT nWE_FSB AND NOT nAS_FSB AND A_FSB(9))
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
NOT A_FSB(23) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
|
|
|
|
|
|
NOT nWE_FSB AND NOT nAS_FSB AND A_FSB(8))
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
NOT A_FSB(23) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
|
|
|
|
|
|
NOT nWE_FSB AND A_FSB(9) AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
NOT A_FSB(23) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
|
|
|
|
|
NOT nWE_FSB AND NOT nAS_FSB AND A_FSB(9))
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
NOT A_FSB(23) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
|
|
|
|
|
NOT nWE_FSB AND NOT nAS_FSB AND A_FSB(8)));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/Timer0: FTCPE port map (cnt/Timer(0),cnt/Timer_T(0),FCLK,'0','0',cnt/Timer_CE(0));
|
2024-10-03 22:46:28 +00:00
|
|
|
|
cnt/Timer_T(0) <= (RefUrg AND NOT cnt/Timer(0) AND cnt/Timer(1) AND
|
|
|
|
|
|
NOT cnt/Timer(2) AND NOT cnt/Er(0) AND cnt/Er(1));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/Timer_CE(0) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/Timer1: FTCPE port map (cnt/Timer(1),cnt/Timer_T(1),FCLK,'0','0',cnt/Timer_CE(1));
|
|
|
|
|
|
cnt/Timer_T(1) <= ((cnt/Timer(0))
|
|
|
|
|
|
OR (RefUrg AND cnt/Timer(1) AND NOT cnt/Timer(2) AND
|
|
|
|
|
|
NOT cnt/Er(0) AND cnt/Er(1)));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/Timer_CE(1) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FTCPE_cnt/Timer2: FTCPE port map (cnt/Timer(2),cnt/Timer_T(2),FCLK,'0','0',cnt/Timer_CE(2));
|
|
|
|
|
|
cnt/Timer_T(2) <= (cnt/Timer(0) AND cnt/Timer(1));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/Timer_CE(2) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FDCPE_cnt/TimerTick: FDCPE port map (cnt/TimerTick,cnt/TimerTick_D,FCLK,'0','0');
|
|
|
|
|
|
cnt/TimerTick_D <= (RefUrg AND NOT cnt/Timer(0) AND cnt/Timer(1) AND
|
|
|
|
|
|
NOT cnt/Timer(2) AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/Wait0: FTCPE port map (cnt/Wait(0),cnt/Wait_T(0),FCLK,'0','0');
|
|
|
|
|
|
cnt/Wait_T(0) <= (nAS_FSB AND NOT cnt/Wait(0) AND NOT fsb/ASrf);
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/Wait1: FDCPE port map (cnt/Wait(1),cnt/Wait_D(1),FCLK,'0','0');
|
|
|
|
|
|
cnt/Wait_D(1) <= ((nAS_FSB AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (cnt/Wait(0) AND cnt/Wait(1))
|
|
|
|
|
|
OR (NOT cnt/Wait(0) AND NOT cnt/Wait(1)));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/Wait2: FTCPE port map (cnt/Wait(2),cnt/Wait_T(2),FCLK,'0','0');
|
|
|
|
|
|
cnt/Wait_T(2) <= ((nAS_FSB AND cnt/Wait(2) AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (NOT nAS_FSB AND cnt/Wait(0) AND cnt/Wait(1))
|
|
|
|
|
|
OR (cnt/Wait(0) AND cnt/Wait(1) AND fsb/ASrf));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/Wait3: FTCPE port map (cnt/Wait(3),cnt/Wait_T(3),FCLK,'0','0');
|
|
|
|
|
|
cnt/Wait_T(3) <= ((nAS_FSB AND cnt/Wait(3) AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (NOT nAS_FSB AND cnt/Wait(0) AND cnt/Wait(1) AND
|
|
|
|
|
|
cnt/Wait(2))
|
|
|
|
|
|
OR (cnt/Wait(0) AND cnt/Wait(1) AND cnt/Wait(2) AND
|
|
|
|
|
|
fsb/ASrf));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/nPOR: FTCPE port map (cnt/nPOR,cnt/nPOR_T,FCLK,'0','0');
|
|
|
|
|
|
cnt/nPOR_T <= ((NOT cnt/nPOR AND NOT cnt/C8Mr(1) AND cnt/C8Mr(0))
|
|
|
|
|
|
OR (cnt/nPOR AND cnt/C8Mr(1) AND cnt/C8Mr(2) AND
|
|
|
|
|
|
cnt/C8Mr(0) AND cnt/C8Mr(3))
|
|
|
|
|
|
OR (cnt/nPOR AND NOT cnt/C8Mr(1) AND NOT cnt/C8Mr(2) AND
|
|
|
|
|
|
NOT cnt/C8Mr(0) AND NOT cnt/C8Mr(3)));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FTCPE_cs/Overlay: FTCPE port map (cs/Overlay,cs/Overlay_T,FCLK,'0','0');
|
2024-10-03 22:29:29 +00:00
|
|
|
|
cs/Overlay_T <= ((NOT nRES.PIN AND NOT cs/Overlay AND nAS_FSB AND NOT fsb/ASrf)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND A_FSB(22) AND NOT A_FSB(23) AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
cs/Overlay AND NOT nAS_FSB)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND A_FSB(22) AND NOT A_FSB(23) AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
cs/Overlay AND fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/C8Mr: FDCPE port map (iobm/C8Mr,C8M,C16M,'0','0');
|
|
|
|
|
|
|
2024-10-03 22:29:29 +00:00
|
|
|
|
FTCPE_iobm/DoutOE: FTCPE port map (iobm/DoutOE,iobm/DoutOE_T,C16M,'0','0');
|
|
|
|
|
|
iobm/DoutOE_T <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND NOT iobm/DoutOE AND
|
|
|
|
|
|
iobm/IOWRREQr)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
|
|
|
|
|
iobm/DoutOE)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
|
|
|
|
|
iobm/DoutOE)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND iobm/DoutOE AND NOT iobm/IOWRREQr));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),NOT C8M,'0','0');
|
|
|
|
|
|
iobm/ES_T(0) <= ((iobm/ES(0) AND NOT E AND iobm/Er)
|
|
|
|
|
|
OR (NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
|
|
|
|
|
|
NOT iobm/ES(3) AND E)
|
|
|
|
|
|
OR (NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
|
|
|
|
|
|
NOT iobm/ES(3) AND NOT iobm/Er));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),NOT C8M,'0','0');
|
|
|
|
|
|
iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1))
|
|
|
|
|
|
OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
|
|
|
|
|
|
OR (NOT E AND iobm/Er)
|
|
|
|
|
|
OR (iobm/ES(0) AND NOT iobm/ES(2) AND iobm/ES(3)));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_iobm/ES2: FTCPE port map (iobm/ES(2),iobm/ES_T(2),NOT C8M,'0','0');
|
|
|
|
|
|
iobm/ES_T(2) <= ((iobm/ES(0) AND iobm/ES(1) AND E)
|
|
|
|
|
|
OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/Er)
|
|
|
|
|
|
OR (iobm/ES(2) AND NOT E AND iobm/Er));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),NOT C8M,'0','0');
|
|
|
|
|
|
iobm/ES_T(3) <= ((iobm/ES(3) AND NOT E AND iobm/Er)
|
|
|
|
|
|
OR (iobm/ES(0) AND iobm/ES(2) AND iobm/ES(1) AND E)
|
|
|
|
|
|
OR (iobm/ES(0) AND iobm/ES(2) AND iobm/ES(1) AND NOT iobm/Er)
|
|
|
|
|
|
OR (iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
|
|
|
|
|
|
iobm/ES(3)));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E,NOT C8M,'0','0');
|
|
|
|
|
|
|
2024-10-03 22:29:29 +00:00
|
|
|
|
FDCPE_iobm/IORDREQr: FDCPE port map (iobm/IORDREQr,IORDREQ,C16M,'0','0');
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/IOS0: FDCPE port map (iobm/IOS0,iobm/IOS0_D,C16M,'0','0');
|
|
|
|
|
|
iobm/IOS0_D <= ((iobm/IOS_FSM_FFd1)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd7 AND iobm/C8Mr)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd7 AND nAoutOE)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
OR (iobm/IOS_FSM_FFd7 AND NOT iobm/IORDREQr AND
|
|
|
|
|
|
NOT iobm/IOWRREQr)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd2 AND iobm/IOS0));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd2,C16M,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,C16M,'0','0');
|
|
|
|
|
|
iobm/IOS_FSM_FFd2_D <= ((IOBERR AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr)
|
|
|
|
|
|
OR (IODONE AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,C16M,'0','0');
|
|
|
|
|
|
iobm/IOS_FSM_FFd3_D <= ((iobm/IOS_FSM_FFd4)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd3 AND iobm/C8Mr)
|
|
|
|
|
|
OR (NOT IOBERR AND NOT IODONE AND iobm/IOS_FSM_FFd3));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd5,C16M,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/IOS_FSM_FFd5: FDCPE port map (iobm/IOS_FSM_FFd5,iobm/IOS_FSM_FFd6,C16M,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/IOS_FSM_FFd6: FDCPE port map (iobm/IOS_FSM_FFd6,iobm/IOS_FSM_FFd6_D,C16M,'0','0');
|
2024-10-03 22:29:29 +00:00
|
|
|
|
iobm/IOS_FSM_FFd6_D <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IORDREQr AND
|
|
|
|
|
|
NOT nAoutOE)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IOWRREQr AND
|
|
|
|
|
|
NOT nAoutOE));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/IOS_FSM_FFd7: FDCPE port map (iobm/IOS_FSM_FFd7,iobm/IOS_FSM_FFd7_D,C16M,'0','0');
|
|
|
|
|
|
iobm/IOS_FSM_FFd7_D <= ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd1)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
OR (NOT iobm/C8Mr AND NOT iobm/IOS_FSM_FFd1 AND iobm/IORDREQr AND
|
|
|
|
|
|
NOT nAoutOE)
|
|
|
|
|
|
OR (NOT iobm/C8Mr AND NOT iobm/IOS_FSM_FFd1 AND iobm/IOWRREQr AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
NOT nAoutOE));
|
|
|
|
|
|
|
2024-10-03 22:29:29 +00:00
|
|
|
|
FDCPE_iobm/IOWRREQr: FDCPE port map (iobm/IOWRREQr,IOWRREQ,C16M,'0','0');
|
|
|
|
|
|
|
2024-09-29 07:29:49 +00:00
|
|
|
|
FDCPE_iobm/VPAr: FDCPE port map (iobm/VPAr,NOT nVPA_IOB,NOT C8M,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,FCLK,'0','0');
|
|
|
|
|
|
iobs/Clear1_D <= (NOT iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2);
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/IODONEr: FDCPE port map (iobs/IODONEr,IODONE,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,FCLK,'0','0',iobs/Load1);
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,FCLK,'0','0');
|
2024-10-03 22:46:28 +00:00
|
|
|
|
iobs/IORW1_T <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND
|
|
|
|
|
|
iobs/TS_FSM_FFd1 AND nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND
|
|
|
|
|
|
iobs/TS_FSM_FFd2 AND nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
fsb/ASrf AND nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd2 AND
|
|
|
|
|
|
fsb/ASrf AND nADoutLE1));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,FCLK,'0','0',iobs/Load1);
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,FCLK,'0','0');
|
2024-10-03 22:46:28 +00:00
|
|
|
|
iobs/Load1_D <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT QoSEN AND NOT nWE_FSB AND NOT nAS_FSB AND iobs/TS_FSM_FFd1 AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT QoSEN AND NOT nWE_FSB AND NOT nAS_FSB AND iobs/TS_FSM_FFd2 AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd1 AND fsb/ASrf AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd2 AND fsb/ASrf AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nADoutLE1));
|
|
|
|
|
|
|
2024-10-03 22:29:29 +00:00
|
|
|
|
FTCPE_iobs/Sent: FTCPE port map (iobs/Sent,iobs/Sent_T,FCLK,'0','0');
|
2024-10-03 22:46:28 +00:00
|
|
|
|
iobs/Sent_T <= ((A_FSB(21) AND A_FSB(22) AND NOT iobs/Sent AND NOT nAS_FSB AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(22) AND NOT iobs/Sent AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(20) AND A_FSB(22) AND NOT iobs/Sent AND NOT nAS_FSB AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(20) AND A_FSB(22) AND NOT iobs/Sent AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT QoSEN AND NOT nWE_FSB AND NOT nAS_FSB AND nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT QoSEN AND NOT nWE_FSB AND fsb/ASrf AND nADoutLE1)
|
|
|
|
|
|
OR (iobs/Sent AND nAS_FSB AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(23) AND NOT iobs/Sent AND NOT nAS_FSB AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(23) AND NOT iobs/Sent AND NOT iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
|
|
|
|
|
|
OR (NOT iobs/Sent AND QoSEN AND NOT nAS_FSB AND NOT iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT iobs/Sent AND QoSEN AND NOT iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/TS_FSM_FFd1: FDCPE port map (iobs/TS_FSM_FFd1,iobs/TS_FSM_FFd1_D,FCLK,'0','0');
|
|
|
|
|
|
iobs/TS_FSM_FFd1_D <= ((iobs/TS_FSM_FFd2)
|
|
|
|
|
|
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr));
|
|
|
|
|
|
|
2024-10-03 22:29:29 +00:00
|
|
|
|
FDCPE_iobs/TS_FSM_FFd2: FDCPE port map (iobs/TS_FSM_FFd2,iobs/TS_FSM_FFd2_D,FCLK,'0','0');
|
2024-10-03 22:46:28 +00:00
|
|
|
|
iobs/TS_FSM_FFd2_D <= ((EXP13_.EXP)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND
|
|
|
|
|
|
nADoutLE1)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND NOT QoSEN AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(17) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (NOT A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
|
|
|
|
|
|
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nADoutLE0 <= (NOT ALE0M AND NOT ALE0S);
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,FCLK,'0','0');
|
|
|
|
|
|
nADoutLE1_D <= ((iobs/Load1)
|
|
|
|
|
|
OR (NOT iobs/Clear1 AND NOT nADoutLE1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB_I,nAS_IOB,NOT C16M,'0','0');
|
|
|
|
|
|
nAS_IOB <= ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IORDREQr AND
|
|
|
|
|
|
NOT iobm/IOWRREQr));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nAS_IOB <= nAS_IOB_I when nAS_IOB_OE = '1' else 'Z';
|
|
|
|
|
|
nAS_IOB_OE <= NOT nAoutOE;
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nAoutOE: FDCPE port map (nAoutOE,nAoutOE_D,FCLK,'0','0');
|
2024-10-03 22:46:28 +00:00
|
|
|
|
nAoutOE_D <= (NOT nBR_IOB AND cnt/IS(1) AND cnt/IS(0));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_nBERR_FSB: FDCPE port map (nBERR_FSB,nBERR_FSB_D,FCLK,'0','0');
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nBERR_FSB_D <= ((NOT iobs/Sent AND nBERR_FSB)
|
|
|
|
|
|
OR (NOT IOBERR AND nBERR_FSB)
|
|
|
|
|
|
OR (nAS_FSB AND NOT fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
FDCPE_nBR_IOB: FDCPE port map (nBR_IOB,nBR_IOB_D,FCLK,'0','0');
|
|
|
|
|
|
nBR_IOB_D <= ((nBR_IOB AND cnt/IS(1))
|
|
|
|
|
|
OR (cnt/IS(1) AND NOT cnt/IS(0) AND NOT nIPL2));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_nCAS: FDCPE port map (nCAS,nCAS_D,NOT FCLK,'0','0');
|
|
|
|
|
|
nCAS_D <= ((ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (ram/RS_FSM_FFd2)
|
|
|
|
|
|
OR (ram/RS_FSM_FFd3)
|
|
|
|
|
|
OR (NOT RefUrg AND ram/RS_FSM_FFd4)
|
|
|
|
|
|
OR (ram/RefDone AND ram/RS_FSM_FFd8)
|
|
|
|
|
|
OR (ram/RefDone AND ram/RS_FSM_FFd4)
|
|
|
|
|
|
OR (ram/RefDone AND ram/RS_FSM_FFd7)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
OR (NOT RefUrg AND NOT RefReq AND ram/RS_FSM_FFd8)
|
|
|
|
|
|
OR (NOT RefUrg AND ram/RS_FSM_FFd8 AND BACTr)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT RefUrg AND
|
|
|
|
|
|
ram/RS_FSM_FFd8)
|
|
|
|
|
|
OR (NOT RefUrg AND nAS_FSB AND ram/RS_FSM_FFd8 AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT nAS_FSB AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND ram/RASEN)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND ram/RS_FSM_FFd8 AND
|
|
|
|
|
|
ram/RASEN AND fsb/ASrf)
|
|
|
|
|
|
OR (NOT RefUrg AND ram/RS_FSM_FFd7)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (ram/DTACKr AND ram/RS_FSM_FFd5));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,FCLK,'0','0');
|
2024-10-03 22:46:28 +00:00
|
|
|
|
nDTACK_FSB_D <= ((A_FSB(21) AND A_FSB(22) AND NOT IONPReady)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(22) AND NOT SndQoSReady)
|
|
|
|
|
|
OR (A_FSB(20) AND A_FSB(22) AND NOT IONPReady)
|
|
|
|
|
|
OR (A_FSB(20) AND A_FSB(22) AND NOT SndQoSReady)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT IONPReady AND NOT RAMReady)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT SndQoSReady AND NOT RAMReady)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(22) AND A_FSB(23))
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT iobs/Sent AND NOT nWE_FSB AND NOT IONPReady AND
|
|
|
|
|
|
NOT nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT iobs/Sent AND NOT nWE_FSB AND NOT SndQoSReady AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
NOT nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(23) AND NOT IONPReady)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(23) AND NOT SndQoSReady)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
OR (QoSEN AND NOT IONPReady)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (QoSEN AND NOT SndQoSReady)
|
|
|
|
|
|
OR (nAS_FSB AND NOT fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT C16M,'0','0');
|
|
|
|
|
|
nDinLE_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nDinOE <= NOT (((A_FSB(23) AND nWE_FSB AND NOT nAS_FSB)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(22) AND nWE_FSB AND NOT nAS_FSB)
|
|
|
|
|
|
OR (A_FSB(20) AND A_FSB(22) AND nWE_FSB AND NOT nAS_FSB)));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
nDoutOE <= NOT (((NOT iobm/IORDREQr AND iobm/IOS0 AND NOT iobm/IOWRREQr AND
|
|
|
|
|
|
NOT nAoutOE)
|
|
|
|
|
|
OR (iobm/DoutOE AND NOT nAoutOE)));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB_I,nLDS_IOB,NOT C16M,'0','0');
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nLDS_IOB <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND IOL0 AND
|
|
|
|
|
|
iobm/IORDREQr)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd3 AND IOL0)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd4 AND IOL0)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd5 AND IOL0)
|
|
|
|
|
|
OR (NOT nLDS_IOB AND iobm/IOS_FSM_FFd6 AND IOL0));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nLDS_IOB <= nLDS_IOB_I when nLDS_IOB_OE = '1' else 'Z';
|
|
|
|
|
|
nLDS_IOB_OE <= NOT nAoutOE;
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nOE: FDCPE port map (nOE,nOE_D,FCLK,'0','0');
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nOE_D <= ((NOT nWE_FSB)
|
|
|
|
|
|
OR (nAS_FSB AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (ram/DTACKr AND BACTr));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nRAMLWE <= NOT ((NOT nWE_FSB AND NOT nLDS_FSB AND ram/RASEL));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nRAMUWE <= NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND ram/RASEL));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nRAS <= NOT (((ram/RASrf)
|
|
|
|
|
|
OR (ram/RASrr)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND NOT nAS_FSB AND
|
|
|
|
|
|
ram/RASEN)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nRES_I <= '0';
|
|
|
|
|
|
nRES <= nRES_I when nRES_OE = '1' else 'Z';
|
|
|
|
|
|
nRES_OE <= NOT nRESout;
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nRESout: FDCPE port map (nRESout,nRESout_D,FCLK,'0','0');
|
2024-10-03 22:46:28 +00:00
|
|
|
|
nRESout_D <= ((cnt/IS(1) AND cnt/IS(0) AND cnt/LTimerTick)
|
|
|
|
|
|
OR (cnt/IS(1) AND cnt/IS(0) AND nRESout));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nROMOE <= NOT (((cs/Overlay AND nWE_FSB AND NOT nAS_FSB)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND A_FSB(22) AND NOT A_FSB(23) AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nWE_FSB AND NOT nAS_FSB)));
|
|
|
|
|
|
|
|
|
|
|
|
|
2024-10-03 22:46:28 +00:00
|
|
|
|
nROMWE <= NOT ((NOT A_FSB(21) AND NOT A_FSB(20) AND A_FSB(22) AND NOT A_FSB(23) AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
NOT nWE_FSB AND NOT nAS_FSB));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB_I,nUDS_IOB,NOT C16M,'0','0');
|
2024-10-03 22:29:29 +00:00
|
|
|
|
nUDS_IOB <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND IOU0 AND
|
|
|
|
|
|
iobm/IORDREQr)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd3 AND IOU0)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd4 AND IOU0)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd5 AND IOU0)
|
|
|
|
|
|
OR (NOT nUDS_IOB AND iobm/IOS_FSM_FFd6 AND IOU0));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nUDS_IOB <= nUDS_IOB_I when nUDS_IOB_OE = '1' else 'Z';
|
|
|
|
|
|
nUDS_IOB_OE <= NOT nAoutOE;
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB_I,nVMA_IOB_T,C8M,'0','0');
|
|
|
|
|
|
nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
|
|
|
|
|
|
NOT iobm/ES(3))
|
|
|
|
|
|
OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(2) AND NOT iobm/ES(1) AND
|
|
|
|
|
|
NOT iobm/ES(3) AND IOACT AND iobm/VPAr));
|
|
|
|
|
|
nVMA_IOB <= nVMA_IOB_I when nVMA_IOB_OE = '1' else 'Z';
|
|
|
|
|
|
nVMA_IOB_OE <= NOT nAoutOE;
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nVPA_FSB: FDCPE port map (nVPA_FSB,nVPA_FSB_D,FCLK,'0',nAS_FSB);
|
2024-10-03 22:46:28 +00:00
|
|
|
|
nVPA_FSB_D <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(22) AND A_FSB(23) AND
|
|
|
|
|
|
IONPReady AND SndQoSReady AND NOT nAS_FSB)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(22) AND A_FSB(23) AND
|
|
|
|
|
|
IONPReady AND SndQoSReady AND fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/DTACKr: FDCPE port map (ram/DTACKr,NOT nDTACK_FSB,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RASEL_D <= ((ram/RS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND NOT nAS_FSB AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RS_FSM_FFd8 AND ram/RASEN)
|
2024-10-01 05:09:25 +00:00
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RS_FSM_FFd8 AND ram/RASEN AND fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RASEN: FDCPE port map (ram/RASEN,ram/RASEN_D,FCLK,'0','0');
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RASEN_D <= ((RefUrg AND NOT ram/RefDone AND nAS_FSB AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr)
|
|
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr)
|
|
|
|
|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr AND fsb/ASrf)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (NOT ram/RS_FSM_FFd8 AND NOT ram/RS_FSM_FFd4 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd8 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RASEN AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RASrf: FDCPE port map (ram/RASrf,ram/RS_FSM_FFd6,NOT FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RASrr: FDCPE port map (ram/RASrr,ram/RASrr_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RASrr_D <= ((ram/RS_FSM_FFd7)
|
2024-10-03 22:46:28 +00:00
|
|
|
|
OR (iobs/IORW1.EXP)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
ram/RS_FSM_FFd8)
|
|
|
|
|
|
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
ram/RS_FSM_FFd8)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd8 AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT ram/RASEN)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND NOT nAS_FSB AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND ram/RASEN)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd4));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd1: FDCPE port map (ram/RS_FSM_FFd1,ram/RS_FSM_FFd2,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd2: FDCPE port map (ram/RS_FSM_FFd2,ram/RS_FSM_FFd3,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd3: FDCPE port map (ram/RS_FSM_FFd3,ram/RS_FSM_FFd7,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd4: FDCPE port map (ram/RS_FSM_FFd4,ram/RS_FSM_FFd4_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RS_FSM_FFd4_D <= (ram/DTACKr AND ram/RS_FSM_FFd5);
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd5: FDCPE port map (ram/RS_FSM_FFd5,ram/RS_FSM_FFd5_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RS_FSM_FFd5_D <= ((ram/RS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT ram/DTACKr AND ram/RS_FSM_FFd5));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd6: FDCPE port map (ram/RS_FSM_FFd6,ram/RS_FSM_FFd6_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RS_FSM_FFd6_D <= ((NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND NOT nAS_FSB AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RS_FSM_FFd8 AND ram/RASEN)
|
2024-10-01 05:09:25 +00:00
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RS_FSM_FFd8 AND ram/RASEN AND fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd7: FDCPE port map (ram/RS_FSM_FFd7,ram/RS_FSM_FFd7_D,FCLK,'0','0');
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RS_FSM_FFd7_D <= ((A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND NOT BACTr)
|
2024-10-01 05:09:25 +00:00
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RS_FSM_FFd8 AND NOT BACTr AND fsb/ASrf)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RS_FSM_FFd8 AND NOT BACTr)
|
2024-10-01 05:09:25 +00:00
|
|
|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RS_FSM_FFd8 AND NOT BACTr AND fsb/ASrf)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd4)
|
|
|
|
|
|
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
ram/RS_FSM_FFd8)
|
|
|
|
|
|
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
ram/RS_FSM_FFd8)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd8 AND
|
2024-10-01 05:09:25 +00:00
|
|
|
|
NOT ram/RASEN)
|
2024-10-03 22:29:29 +00:00
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND NOT fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd8: FDCPE port map (ram/RS_FSM_FFd8,ram/RS_FSM_FFd8_D,FCLK,'0','0');
|
2024-10-03 22:29:29 +00:00
|
|
|
|
ram/RS_FSM_FFd8_D <= ((A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr)
|
|
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr AND fsb/ASrf)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd4 AND ram/RASEN AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr)
|
|
|
|
|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr AND fsb/ASrf)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd8 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND NOT nAS_FSB AND
|
2024-10-03 22:29:29 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd4 AND ram/RASEN AND NOT ram/RS_FSM_FFd1)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (NOT ram/RS_FSM_FFd8 AND NOT ram/RS_FSM_FFd4 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (RefUrg AND NOT cs/Overlay AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RASEN AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RefDone: FDCPE port map (ram/RefDone,ram/RefDone_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RefDone_D <= ((NOT RefUrg AND NOT RefReq)
|
|
|
|
|
|
OR (NOT ram/RefDone AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd7 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3));
|
|
|
|
|
|
|
|
|
|
|
|
Register Legend:
|
|
|
|
|
|
FDCPE (Q,D,C,CLR,PRE,CE);
|
|
|
|
|
|
FTCPE (Q,D,C,CLR,PRE,CE);
|
|
|
|
|
|
LDCP (Q,D,G,CLR,PRE);
|
|
|
|
|
|
|
|
|
|
|
|
****************************** Device Pin Out *****************************
|
|
|
|
|
|
|
|
|
|
|
|
Device : XC95144XL-10-TQ100
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
--------------------------------------------------
|
|
|
|
|
|
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
|
|
|
|
|
|
| 99 97 95 93 91 89 87 85 83 81 79 77 |
|
|
|
|
|
|
| 1 75 |
|
|
|
|
|
|
| 2 74 |
|
|
|
|
|
|
| 3 73 |
|
|
|
|
|
|
| 4 72 |
|
|
|
|
|
|
| 5 71 |
|
|
|
|
|
|
| 6 70 |
|
|
|
|
|
|
| 7 69 |
|
|
|
|
|
|
| 8 68 |
|
|
|
|
|
|
| 9 67 |
|
|
|
|
|
|
| 10 66 |
|
|
|
|
|
|
| 11 65 |
|
|
|
|
|
|
| 12 64 |
|
|
|
|
|
|
| 13 XC95144XL-10-TQ100 63 |
|
|
|
|
|
|
| 14 62 |
|
|
|
|
|
|
| 15 61 |
|
|
|
|
|
|
| 16 60 |
|
|
|
|
|
|
| 17 59 |
|
|
|
|
|
|
| 18 58 |
|
|
|
|
|
|
| 19 57 |
|
|
|
|
|
|
| 20 56 |
|
|
|
|
|
|
| 21 55 |
|
|
|
|
|
|
| 22 54 |
|
|
|
|
|
|
| 23 53 |
|
|
|
|
|
|
| 24 52 |
|
|
|
|
|
|
| 25 51 |
|
|
|
|
|
|
| 27 29 31 33 35 37 39 41 43 45 47 49 |
|
|
|
|
|
|
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
|
|
|
|
|
|
--------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pin Signal Pin Signal
|
|
|
|
|
|
No. Name No. Name
|
|
|
|
|
|
1 KPR 51 VCC
|
|
|
|
|
|
2 A_FSB<5> 52 RA<7>
|
|
|
|
|
|
3 A_FSB<6> 53 RA<0>
|
|
|
|
|
|
4 A_FSB<7> 54 RA<8>
|
|
|
|
|
|
5 VCC 55 RA<10>
|
|
|
|
|
|
6 A_FSB<8> 56 RA<9>
|
|
|
|
|
|
7 A_FSB<9> 57 VCC
|
|
|
|
|
|
8 A_FSB<10> 58 MCKE
|
|
|
|
|
|
9 A_FSB<11> 59 KPR
|
|
|
|
|
|
10 A_FSB<12> 60 GA<23>
|
|
|
|
|
|
11 A_FSB<13> 61 GA<22>
|
|
|
|
|
|
12 A_FSB<14> 62 GND
|
|
|
|
|
|
13 A_FSB<15> 63 RA<11>
|
|
|
|
|
|
14 A_FSB<16> 64 nRAS
|
|
|
|
|
|
15 A_FSB<17> 65 nRAMLWE
|
|
|
|
|
|
16 A_FSB<18> 66 nRAMUWE
|
|
|
|
|
|
17 A_FSB<19> 67 KPR
|
|
|
|
|
|
18 A_FSB<20> 68 KPR
|
|
|
|
|
|
19 A_FSB<21> 69 GND
|
|
|
|
|
|
20 A_FSB<22> 70 nBERR_FSB
|
|
|
|
|
|
21 GND 71 KPR
|
|
|
|
|
|
22 C16M 72 nBR_IOB
|
|
|
|
|
|
23 C8M 73 KPR
|
|
|
|
|
|
24 A_FSB<23> 74 nVMA_IOB
|
|
|
|
|
|
25 E 75 GND
|
|
|
|
|
|
26 VCC 76 nBERR_IOB
|
|
|
|
|
|
27 FCLK 77 nVPA_IOB
|
|
|
|
|
|
28 nDTACK_FSB 78 nDTACK_IOB
|
|
|
|
|
|
29 nWE_FSB 79 nLDS_IOB
|
|
|
|
|
|
30 nLDS_FSB 80 nUDS_IOB
|
|
|
|
|
|
31 GND 81 nAS_IOB
|
|
|
|
|
|
32 nAS_FSB 82 nADoutLE1
|
|
|
|
|
|
33 nUDS_FSB 83 TDO
|
|
|
|
|
|
34 nROMWE 84 GND
|
|
|
|
|
|
35 nROMOE 85 nADoutLE0
|
|
|
|
|
|
36 nCAS 86 nDinLE
|
|
|
|
|
|
37 nOE 87 nAoutOE
|
|
|
|
|
|
38 VCC 88 VCC
|
|
|
|
|
|
39 KPR 89 nDoutOE
|
|
|
|
|
|
40 RA<4> 90 nDinOE
|
|
|
|
|
|
41 RA<3> 91 nRES
|
|
|
|
|
|
42 RA<5> 92 nIPL2
|
|
|
|
|
|
43 RA<2> 93 nVPA_FSB
|
|
|
|
|
|
44 GND 94 A_FSB<1>
|
|
|
|
|
|
45 TDI 95 A_FSB<2>
|
|
|
|
|
|
46 RA<6> 96 A_FSB<3>
|
|
|
|
|
|
47 TMS 97 A_FSB<4>
|
|
|
|
|
|
48 TCK 98 VCC
|
2024-10-03 22:29:29 +00:00
|
|
|
|
49 KPR 99 KPR
|
2024-09-29 07:29:49 +00:00
|
|
|
|
50 RA<1> 100 GND
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Legend : NC = Not Connected, unbonded pin
|
|
|
|
|
|
PGND = Unused I/O configured as additional Ground pin
|
|
|
|
|
|
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
|
|
|
|
|
|
KPR = Unused I/O with weak keeper (leave unconnected)
|
|
|
|
|
|
VCC = Dedicated Power Pin
|
|
|
|
|
|
GND = Dedicated Ground Pin
|
|
|
|
|
|
TDI = Test Data In, JTAG pin
|
|
|
|
|
|
TDO = Test Data Out, JTAG pin
|
|
|
|
|
|
TCK = Test Clock, JTAG pin
|
|
|
|
|
|
TMS = Test Mode Select, JTAG pin
|
|
|
|
|
|
PROHIBITED = User reserved pin
|
|
|
|
|
|
**************************** Compiler Options ****************************
|
|
|
|
|
|
|
|
|
|
|
|
Following is a list of all global compiler options used by the fitter run.
|
|
|
|
|
|
|
|
|
|
|
|
Device(s) Specified : xc95144xl-10-TQ100
|
|
|
|
|
|
Optimization Method : SPEED
|
|
|
|
|
|
Multi-Level Logic Optimization : ON
|
|
|
|
|
|
Ignore Timing Specifications : OFF
|
|
|
|
|
|
Default Register Power Up Value : LOW
|
|
|
|
|
|
Keep User Location Constraints : ON
|
|
|
|
|
|
What-You-See-Is-What-You-Get : OFF
|
|
|
|
|
|
Exhaustive Fitting : OFF
|
|
|
|
|
|
Keep Unused Inputs : OFF
|
|
|
|
|
|
Slew Rate : FAST
|
|
|
|
|
|
Power Mode : STD
|
|
|
|
|
|
Ground on Unused IOs : OFF
|
|
|
|
|
|
Set I/O Pin Termination : KEEPER
|
|
|
|
|
|
Global Clock Optimization : ON
|
|
|
|
|
|
Global Set/Reset Optimization : ON
|
|
|
|
|
|
Global Ouput Enable Optimization : ON
|
|
|
|
|
|
Input Limit : 54
|
|
|
|
|
|
Pterm Limit : 25
|
