mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-25 13:33:58 +00:00
Back to "old robust"
This commit is contained in:
Zane Kaminski
parent
31fecec90e
commit
10ebdd43ba
62
cpld/CNT.v
62
cpld/CNT.v
@ -1,6 +1,6 @@
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module CNT(
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/* FSB clock and E clock inputs */
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input CLK, input C8M, input E,
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input CLK, input E,
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/* Refresh request */
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output reg RefReq, output reg RefUrg,
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/* Reset, button */
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@ -9,21 +9,13 @@ module CNT(
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output reg AoutOE, output reg nBR_IOB,
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/* QoS control */
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input BACT,
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input BACTr,
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input IOQoSCS,
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input SndQoSCS,
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input IACKCS,
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output reg IOQoSEN,
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output reg MCKE);
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input QoSCS,
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output reg QoSEN);
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/* E clock synchronization */
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reg [1:0] Er; always @(posedge CLK) Er[1:0] <= { Er[0], E };
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wire EFall = Er[1] && !Er[0];
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/* C8M clock synchronization */
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reg [1:0] C8Mr; always @(posedge CLK) C8Mr[1:0] <= { C8Mr[0], C8M };
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wire C8MFall = C8Mr[1] && !C8Mr[0];
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/* NMI and reset synchronization */
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reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
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reg nRESr; always @(posedge CLK) nRESr <= nRESin;
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@ -60,38 +52,35 @@ module CNT(
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end
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end
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/* During init (IS!=3) long timer counts from 0 to 3072.
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* 3073 states == 43.151 ms */
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/* During init (IS!=3) long timer counts from 0 to 4095.
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* 4096 states == 57.516 ms */
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reg [11:0] LTimer;
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wire LTimerTC = LTimer[11:10]==2'b11;
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reg LTimerTC;
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always @(posedge CLK) begin
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if (EFall && TimerTC) LTimer <= LTimer+1;
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if (EFall && TimerTC) begin
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LTimer <= LTimer+1;
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LTimerTC <= LTimer[11:0]==12'hFFE;
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end
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end
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/* QoS select registers */
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reg IOQoSCSr;
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always @(posedge CLK) IOQoSCSr <= (BACT && (IOQoSCS || SndQoSCS || IACKCS)) || !nRESr;
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/* QoS select latch */
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reg QoSCSr;
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always @(posedge CLK) if (BACT) QoSCSr <= QoSCS;
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/* I/O QoS timer */
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reg [3:0] IOQS;
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/* QoS timer
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* In the absence of a QoS trigger, QS==0.
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* When Qos triggered, QS is set to 1 and counts 1, 2, 3, 0.
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* While QS!=0, QoS is enabled.
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* QoS enable period is 28.124 us - 42.240 us */
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reg [1:0] QS;
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always @(posedge CLK) begin
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if (IOQoSCSr) IOQS <= 4'hF;
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else if (IOQS==0) IOQS <= 0;
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else if (EFall && TimerTC) IOQS <= IOQS-1;
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if (!nRESr || QoSCSr) QS[1:0] <= 1;
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else if (QS==0) QS[1:0] <= 0;
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else if (EFall && TimerTC) QS[1:0] <= QS+1;
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end
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/* I/O QoS enable */
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always @(posedge CLK) if (!BACT) IOQoSEN <= IOQS!=0;
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/* MC68K clock enable */
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always @(posedge CLK) MCKE <= 1;//BACT || BACTr || !IOQoSEN || C8MFall;
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/* */
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reg LookReset;
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always @(posedge CLK) begin
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if (!nRESout) LookReset <= 0;
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else if (EFall) LookReset <= 1;
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end
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/* QoS enable control */
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always @(posedge CLK) if (!BACT) QoSEN <= QoSCSr || QS!=0;
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/* Startup sequence state control */
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wire ISTC = EFall && TimerTC && LTimerTC;
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@ -113,8 +102,9 @@ module CNT(
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if (ISTC) IS <= 3;
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end 3: begin
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nRESout <= 1; // Release reset
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if (LookReset && !nRESr) IS <= 0;
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IS <= 3;
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end
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endcase
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end
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endmodule
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19
cpld/CS.v
19
cpld/CS.v
@ -4,12 +4,11 @@ module CS(
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/* AS cycle detection */
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input BACT,
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/* QoS enable input */
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input IOQoSEN,
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input QoSEN,
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/* Device select outputs */
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output IOCS, output IORealCS, output IOPWCS, output IACKCS,
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output IOCS, output IORealCS, output IOPWCS, output IACS,
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output ROMCS, output ROMCS4X,
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output RAMCS, output RAMCS0X,
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output IOQoSCS, output SndQoSCS);
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output RAMCS, output RAMCS0X, output QoSCS);
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/* Overlay control */
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reg Overlay;
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@ -19,7 +18,7 @@ module CS(
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end
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/* I/O select signals */
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assign IACKCS = A[23:20]==4'hF;
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wire IACKCS = A[23:20]==4'hF;
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wire VIACS = A[23:20]==4'hE;
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wire IWMCS = A[23:20]==4'hD;
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wire SCCCS = A[23:20]==4'hB || A[23:20]==4'h9;
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@ -46,13 +45,13 @@ module CS(
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//A[15:12]==4'hD || // 4096 bytes video
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//A[15:12]==4'hE || // 4096 bytes video
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//A[15:12]==4'hF); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
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assign SndQoSCS = VidRAMCSWR64k && (
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wire SndRAMCSWR = VidRAMCSWR64k && (
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((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
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((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
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assign IOQoSCS = IWMCS || VIACS || SCCCS || SCSICS;
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assign QoSCS = IACKCS || VIACS || IWMCS || SCCCS || SCSICS || SndRAMCSWR;
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/* Select signals - IOB domain */
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assign IACKCS = A[23:20]==4'hF; // IACK
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assign IACS = A[23:20]==4'hF; // IACK
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assign IORealCS =
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A[23:20]==4'hF || // IACK
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A[23:20]==4'hE || // VIA
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@ -65,6 +64,6 @@ module CS(
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A[23:20]==4'h7 || // empty (expansion RAM)
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A[23:20]==4'h6 || // empty (expansion RAM)
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A[23:20]==4'h5; // SCSI
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assign IOCS = IORealCS || VidRAMCSWR || IOQoSEN;
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assign IOPWCS = VidRAMCSWR64k && !IOQoSEN; // Posted write to video RAM only when QoS disabled
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assign IOCS = IORealCS || VidRAMCSWR || QoSEN;
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assign IOPWCS = VidRAMCSWR64k && !QoSEN; // Posted write to video RAM only when QoS disabled
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endmodule
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22
cpld/FSB.v
22
cpld/FSB.v
@ -1,37 +1,31 @@
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module FSB(
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/* MC68HC000 interface */
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input FCLK, input nAS, output reg nDTACK, output reg nVPA,
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/* MC68HC000 clock enable */
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input MCKEi, output reg MCKE,
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/* AS cycle detection */
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output BACT, output reg BACTr,
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/* Ready inputs */
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input ROMCS,
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input RAMCS, input RAMReady,
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input IOPWCS, input IOPWReady, input IONPReady,
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input IOQoSEN,
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input QoSEN,
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/* Interrupt acknowledge select */
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input IACKCS);
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/* MC68k clock enable */
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always @(negedge FCLK) MCKE <= MCKEi;
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input IACS);
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/* AS cycle detection */
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reg ASrf = 0;
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always @(negedge FCLK) begin ASrf <= !nAS; end
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assign BACTu = !nAS || ASrf;
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assign BACT = BACTu && MCKE;
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assign BACT = !nAS || ASrf; // BACT - bus active
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always @(posedge FCLK) BACTr <= BACT;
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/* DTACK/VPA control */
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wire Ready = (RAMCS && !IOQoSEN && RAMReady && !IOPWCS) ||
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(RAMCS && !IOQoSEN && RAMReady && IOPWCS && IOPWReady) ||
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(ROMCS && !IOQoSEN) ||
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wire Ready = (RAMCS && !QoSEN && RAMReady && !IOPWCS) ||
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(RAMCS && !QoSEN && RAMReady && IOPWCS && IOPWReady) ||
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(ROMCS && !QoSEN) ||
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(IONPReady);
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always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACKCS);
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always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nVPA <= 1;
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else nVPA <= !(Ready && BACT && IACKCS);
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else nVPA <= !(Ready && BACT && IACS);
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end
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endmodule
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66
cpld/IOBM.v
66
cpld/IOBM.v
@ -1,19 +1,21 @@
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module IOBM(
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/* PDS interface */
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input C16M, input C8M, input E,
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output reg nAS, output reg nLDS, output reg nUDS, output reg RnW, output reg nVMA,
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output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA,
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input nDTACK, input nVPA, input nBERR, input nRES,
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/* PDS address and data latch control */
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input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE,
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/* IO bus slave port interface */
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input IOREQ, input IORW, input IOLDS, input IOUDS,
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input IORDREQ, input IOWRREQ, input IOLDS, input IOUDS,
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output reg IOACT, output reg IODONE, output reg IOBERR);
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/* C8M clock registration */
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reg C8Mr; always @(posedge C16M) C8Mr <= C8M;
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/* I/O request input synchronization */
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reg IOREQr; always @(posedge C16M) IOREQr <= IOREQ;
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reg IORDREQr; always @(posedge C16M) IORDREQr <= IORDREQ;
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reg IOWRREQr; always @(posedge C16M) IOWRREQr <= IOWRREQ;
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wire IOREQr = IORDREQr || IOWRREQr;
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/* VPA synchronization */
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reg VPAr; always @(negedge C8M) VPAr <= !nVPA;
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@ -37,8 +39,8 @@ module IOBM(
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end
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/* DTACK and BERR synchronization */
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always @(negedge C8M, posedge nAS) begin
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if (nAS) begin
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always @(negedge C8M, posedge nASout) begin
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if (nASout) begin
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IODONE <= 0;
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IOBERR <= 0;
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end else begin
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@ -50,8 +52,8 @@ module IOBM(
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/* I/O bus state */
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reg [2:0] IOS = 0;
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reg IOS0;
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always @(posedge C16M) case (IOS[2:0])
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3'h0: begin
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always @(posedge C16M) begin
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if (IOS==0) begin
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if (IOREQr && !C8Mr && AoutOE) begin // "IOS1"
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IOS <= 2;
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IOS0 <= 0;
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@ -59,24 +61,24 @@ module IOBM(
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IOS <= 0;
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IOS0 <= 1;
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end
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IOACT <= IOREQr;
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ALE0 <= IOREQr;
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end 3'h2: begin
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IOACT <= IOREQr && AoutOE;
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ALE0 <= IOREQr && AoutOE;
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end else if (IOS==2) begin
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IOS <= 3;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end 3'h3: begin
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end else if (IOS==3) begin
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IOS <= 4;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end 3'h4: begin
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end else if (IOS==4) begin
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IOS <= 5;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end 3'h5: begin
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end else if (IOS==5) begin
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if (!C8Mr && (IODONE || IOBERR)) begin
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IOS <= 6;
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IOACT <= 0;
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@ -86,55 +88,33 @@ module IOBM(
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end
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IOS0 <= 0;
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ALE0 <= 1;
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end 3'h6: begin
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end else if (IOS==6) begin
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IOS <= 7;
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IOS0 <= 0;
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IOACT <= 0;
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ALE0 <= 0;
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end 3'h7: begin
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end else if (IOS==7) begin
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IOS <= 0;
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IOS0 <= 1;
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IOACT <= 0;
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ALE0 <= 0;
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end
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endcase
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end
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/* PDS address and data latch control */
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always @(negedge C16M) begin nDinLE = IOS==4 || IOS==5; end
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reg DoutOE = 0;
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always @(posedge C16M) begin
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DoutOE <= (IOS==0 && IOREQr && !IORW && !C8Mr) ||
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DoutOE <= (IOS==0 && IOWRREQr && !C8Mr) ||
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(DoutOE && (IOS==2 || IOS==3 || IOS==4 || IOS==5));
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end
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assign nDoutOE = !(AoutOE && (DoutOE || (IOS0 && !IOREQr)));
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/* AS, DS, RW control */
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/* AS, DS control */
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always @(negedge C16M) begin
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nAS <= !(
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(IOS==0 && IOREQr && !C8Mr) ||
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(IOS==2) ||
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(IOS==3) ||
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(IOS==4) ||
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(IOS==5));
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RnW <= !(
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(IOS==0 && IOREQr && !IORW && !C8Mr) ||
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(!IORW && IOS==2) ||
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(!IORW && IOS==3) ||
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(!IORW && IOS==4) ||
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(!IORW && IOS==5) ||
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(!IORW && IOS==6));
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nLDS <= !(
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(IOS==0 && IOREQr && IORW && IOLDS && !C8Mr) ||
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(IOS==2 && IOLDS) ||
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(IOS==3 && IOLDS) ||
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(IOS==4 && IOLDS) ||
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(IOS==5 && IOLDS));
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nUDS <= !(
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(IOS==0 && IOREQr && IORW && IOUDS && !C8Mr) ||
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(IOS==2 && IOUDS) ||
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(IOS==3 && IOUDS) ||
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(IOS==4 && IOUDS) ||
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(IOS==5 && IOUDS));
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nASout <= !((IOS==0 && IOREQr && !C8Mr) || IOS==2 || IOS==3 || IOS==4 || IOS==5);
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nLDS <= !(IOLDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && !nLDS) || IOS==3 || IOS==4 || IOS==5));
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nUDS <= !(IOUDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && !nUDS) || IOS==3 || IOS==4 || IOS==5));
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end
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endmodule
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59
cpld/IOBS.v
59
cpld/IOBS.v
@ -10,7 +10,7 @@ module IOBS(
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/* Read data OE control */
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output nDinOE,
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/* IOB master controller interface */
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output reg IOREQ, output reg IORW,
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output reg IORDREQ, output reg IOWRREQ,
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input IOACT, input IODONEin, input IOBERR,
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/* FIFO primary level control */
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output reg ALE0, output reg IOL0, output reg IOU0,
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@ -56,7 +56,7 @@ module IOBS(
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always @(posedge CLK) begin // ALE clear control
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// Make address latch transparent in cycle after TS3
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// (i.e. first TS2 cycle that's not part of current write)
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if (TS==1) Clear1 <= 1;
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if (TS==3) Clear1 <= 1;
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else Clear1 <= 0;
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end
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always @(posedge CLK) begin // LDS, UDS, ALE control
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@ -70,32 +70,30 @@ module IOBS(
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/* FIFO primary level control */
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always @(posedge CLK) begin
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if (TS==0) begin
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// Start IOREQ if FIFO secondary level occupied or FSB request
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if (ALE1 || (BACT && IOCS && !ALE1 && !Sent)) begin
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// Request transfer from IOBM
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TS <= 1;
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IOREQ <= 1;
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end else begin // Otherwise stay in idle
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TS <= 0;
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IOREQ <= 0;
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end
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// Latch R/W and data strobes from FIFO secondary or FSB
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if (ALE1) begin
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IORW <= IORW1;
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if (ALE1) begin // If FIFO secondary level occupied
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// Request transfer from IOBM and latch R/W from FIFO
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TS <= 3;
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IORDREQ <= IORW1;
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IOWRREQ <= !IORW1;
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IOL0 <= IOL1;
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IOU0 <= IOU1;
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end else begin
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IORW <= nWE;
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end else if (BACT && IOCS && !ALE1 && !Sent) begin // FSB request
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// Request transfer from IOBM and latch R/W from FSB
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TS <= 3;
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IORDREQ <= nWE;
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IOWRREQ <= !nWE;
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IOL0 <= !nLDS;
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IOU0 <= !nUDS;
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end else begin // Otherwise stay in idle
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TS <= 0;
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IORDREQ <= 0;
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IOWRREQ <= 0;
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end
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ALE0 <= 0;
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end else if (TS==1) begin
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TS <= 2; // Always go to TS2
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IOREQ <= 1; // Keep IOREQ active
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end else if (TS==3) begin
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TS <= 2; // Always go to TS2. Keep IORDREQ/IOWRREQ active
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ALE0 <= 1; // Latch address (and data)
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// Latch data strobes again from FIFO or FSB as appropriate
|
||||
// Latch data strobes from FIFO or FSB as appropriate
|
||||
if (ALE1) begin
|
||||
IOL0 <= IOL1;
|
||||
IOU0 <= IOU1;
|
||||
@ -104,20 +102,19 @@ module IOBS(
|
||||
IOU0 <= !nUDS;
|
||||
end
|
||||
end else if (TS==2) begin
|
||||
// Wait for IOACT (transfer started) then withdraw IOREQ and enter TS1
|
||||
// Wait for IOACT then withdraw IOREQ and enter TS1
|
||||
if (IOACTr) begin
|
||||
TS <= 3;
|
||||
IOREQ <= 0;
|
||||
end else begin
|
||||
TS <= 2;
|
||||
IOREQ <= 1;
|
||||
end
|
||||
TS <= 1;
|
||||
IORDREQ <= 0;
|
||||
IOWRREQ <= 0;
|
||||
end else TS <= 2;
|
||||
ALE0 <= 1; // Keep address latched
|
||||
end else if (TS==3) begin
|
||||
end else if (TS==1) begin
|
||||
// Wait for IOACT low (transfer over) before going back to idle
|
||||
if (!IOACTr) TS <= 0;
|
||||
else TS <= 3;
|
||||
IOREQ <= 0;
|
||||
else TS <= 1;
|
||||
IORDREQ <= 0;
|
||||
IOWRREQ <= 0;
|
||||
ALE0 <= 0; // Release addr latch since it's controlled by IOBM now
|
||||
end
|
||||
end
|
||||
|
||||
@ -18,7 +18,6 @@ module WarpSE(
|
||||
output nAS_IOB,
|
||||
output nUDS_IOB,
|
||||
output nLDS_IOB,
|
||||
output RnW_IOB,
|
||||
output nBR_IOB,
|
||||
input nBG_IOB,
|
||||
input nBERR_IOB,
|
||||
@ -41,15 +40,18 @@ module WarpSE(
|
||||
output MCKE,
|
||||
input [5:0] DBG);
|
||||
|
||||
/* MC68k clock enable */
|
||||
assign MCKE = 1;
|
||||
|
||||
/* GA gated (translated) address output */
|
||||
assign GA[23:22] = A_FSB[23:22];
|
||||
/*assign GA[23:22] = (
|
||||
//assign GA[23:22] = A_FSB[23:22];
|
||||
assign GA[23:22] = (
|
||||
// $800000-$8FFFFF to $000000-$0FFFFF (1 MB)
|
||||
(A_FSB[23:20]==4'h8) ||
|
||||
// $700000-$7EFFFF to $300000-$3EFFFF (960 kB)
|
||||
(A_FSB[23:20]==4'h7 && A_FSB[19:16]!=4'hF) ||
|
||||
// $600000-$6FFFFF to $200000-$2FFFFF (1 MB)
|
||||
(A_FSB[23:20]==4'h6)) ? 2'b00 : A_FSB[23:22];*/
|
||||
(A_FSB[23:20]==4'h6)) ? 2'b00 : A_FSB[23:22];
|
||||
|
||||
/* Reset input and open-drain output */
|
||||
wire nRESin = nRES;
|
||||
@ -57,34 +59,30 @@ module WarpSE(
|
||||
assign nRES = !nRESout ? 1'b0 : 1'bZ;
|
||||
|
||||
/* AS cycle detection */
|
||||
wire BACT, BACTr;
|
||||
|
||||
/* MC68k clock enable */
|
||||
wire MCKEi;
|
||||
wire BACT;
|
||||
wire BACTr;
|
||||
|
||||
/* Refresh request/ack signals */
|
||||
wire RefReq, RefUrg;
|
||||
|
||||
/* QoS enable */
|
||||
wire IOQoSEN;
|
||||
wire QoSEN;
|
||||
|
||||
/* FSB chip select signals */
|
||||
wire IOCS, IORealCS, IOPWCS, IACKCS;
|
||||
wire IOCS, IORealCS, IOPWCS, IACS;
|
||||
wire ROMCS, ROMCS4X;
|
||||
wire RAMCS, RAMCS0X;
|
||||
wire IOQoSCS, SndQoSCS;
|
||||
wire RAMCS, RAMCS0X, QoSCS;
|
||||
CS cs(
|
||||
/* MC68HC000 interface */
|
||||
A_FSB[23:08], FCLK, nRESin, nWE_FSB,
|
||||
/* /AS cycle detection */
|
||||
BACT,
|
||||
/* QoS enable input */
|
||||
IOQoSEN,
|
||||
QoSEN,
|
||||
/* Device select outputs */
|
||||
IOCS, IORealCS, IOPWCS, IACKCS,
|
||||
IOCS, IORealCS, IOPWCS, IACS,
|
||||
ROMCS, ROMCS4X,
|
||||
RAMCS, RAMCS0X,
|
||||
IOQoSCS, SndQoSCS);
|
||||
RAMCS, RAMCS0X, QoSCS);
|
||||
|
||||
wire RAMReady;
|
||||
RAM ram(
|
||||
@ -104,7 +102,7 @@ module WarpSE(
|
||||
nRAMLWE, nRAMUWE, nOE, nROMOE, nROMWE);
|
||||
|
||||
wire IONPReady, IOPWReady;
|
||||
wire IOREQ, IORW;
|
||||
wire IORDREQ, IOWRREQ;
|
||||
wire IOL0, IOU0;
|
||||
wire ALE0S, ALE0M, ALE1;
|
||||
assign nADoutLE0 = ~(ALE0S || ALE0M);
|
||||
@ -122,7 +120,7 @@ module WarpSE(
|
||||
/* Read data OE control */
|
||||
nDinOE,
|
||||
/* IOB Master Controller Interface */
|
||||
IOREQ, IORW,
|
||||
IORDREQ, IOWRREQ,
|
||||
IOACT, IODONE, IOBERR,
|
||||
/* FIFO primary level control */
|
||||
ALE0S, IOL0, IOU0,
|
||||
@ -131,26 +129,25 @@ module WarpSE(
|
||||
|
||||
wire AoutOE;
|
||||
assign nAoutOE = !AoutOE;
|
||||
wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, RnW_IOBout, nVMA_IOBout;
|
||||
wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout;
|
||||
assign nAS_IOB = AoutOE ? nAS_IOBout : 1'bZ;
|
||||
assign nLDS_IOB = AoutOE ? nLDS_IOBout : 1'bZ;
|
||||
assign nUDS_IOB = AoutOE ? nUDS_IOBout : 1'bZ;
|
||||
assign RnW_IOB = AoutOE ? RnW_IOBout : 1'bZ;
|
||||
assign nVMA_IOB = AoutOE ? nVMA_IOBout : 1'bZ;
|
||||
IOBM iobm(
|
||||
/* PDS interface */
|
||||
C16M, C8M, E,
|
||||
nAS_IOBout, nLDS_IOBout, nUDS_IOBout, RnW_IOBout, nVMA_IOBout,
|
||||
nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout,
|
||||
nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin,
|
||||
/* PDS address and data latch control */
|
||||
AoutOE, nDoutOE, ALE0M, nDinLE,
|
||||
/* IO bus slave port interface */
|
||||
IOREQ, IORW, IOL0, IOU0,
|
||||
IORDREQ, IOWRREQ, IOL0, IOU0,
|
||||
IOACT, IODONE, IOBERR);
|
||||
|
||||
CNT cnt(
|
||||
/* FSB clock and E clock inputs */
|
||||
FCLK, C8M, E,
|
||||
FCLK, E,
|
||||
/* Refresh request */
|
||||
RefReq, RefUrg,
|
||||
/* Reset, button */
|
||||
@ -158,23 +155,19 @@ module WarpSE(
|
||||
/* Mac PDS bus master control outputs */
|
||||
AoutOE, nBR_IOB,
|
||||
/* QoS control */
|
||||
BACT, BACTr,
|
||||
IOQoSCS, SndQoSCS, IACKCS,
|
||||
IOQoSEN, MCKEi);
|
||||
BACT, QoSCS, QoSEN);
|
||||
|
||||
FSB fsb(
|
||||
/* MC68HC000 interface */
|
||||
FCLK, nAS_FSB, nDTACK_FSB, nVPA_FSB,
|
||||
/* MC68HC000 clock enable */
|
||||
MCKEi, MCKE,
|
||||
/* FSB cycle detection */
|
||||
BACT, BACTr,
|
||||
/* Ready inputs */
|
||||
ROMCS4X,
|
||||
RAMCS0X, RAMReady,
|
||||
IOPWCS, IOPWReady, IONPReady,
|
||||
IOQoSEN,
|
||||
QoSEN,
|
||||
/* Interrupt acknowledge select */
|
||||
IACKCS);
|
||||
IACS);
|
||||
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user