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Fix IOPWReady timing
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@ -136,8 +136,9 @@ module IOBS(
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/* Posted ready */
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/* Posted ready */
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always @(posedge CLK) begin
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always @(posedge CLK) begin
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if (!BACT) IOPWReady <= 0;
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if (Clear1) IOPWReady <= 1;
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else if (Clear1 || !ALE1) IOPWReady <= 1;
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else if (Load1) IOPWReady <= 0;
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else IOPWReady <= !ALE;
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end
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end
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/* BERR control */
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/* BERR control */
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