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Fixed

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This commit is contained in:
Zane Kaminski 2023-04-10 20:33:44 -04:00
parent 22c3dd55ac
commit 443a159063
1 changed files with 34 additions and 36 deletions
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68
cpld/RAM.v
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@ -10,17 +10,16 @@ module RAM(
input RefReqIn, input RefUrgIn,
/* DRAM and NOR flash interface */
output [11:0] RA, output nRAS, output reg nCAS,
output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE);
output nLWE, output nUWE, output reg nOE, output nROMCS, output nROMWE);
/* BACT and /DTACK registration */
reg BACTr; always @(posedge CLK) BACTr <= BACT;
reg DTACKr; always @(posedge CLK) DTACKr <= !nDTACK;
/* RAM control state */
reg [3:0] RS = 0;
reg [2:0] RS = 0;
reg RASEN = 0;
reg RASEL = 0;
reg CAS = 0;
reg RASrr = 0;
reg RASrf = 0;
@ -28,21 +27,21 @@ module RAM(
reg RefDone; // Refresh done "remember"
always @(posedge CLK) begin
if (!RefReqIn && !RefUrgIn) RefDone <= 0;
else if (RS[3]) RefDone <= 1;
else if (RS[2]) RefDone <= 1;
end
wire RefReq = RefReqIn && !RefDone;
wire RefUrg = RefUrgIn && !RefDone;
/* RAM control signals */
assign nRAS = !((!nAS && RAMCS && RASEN) || RASrr || RASrf);
assign nLWE = !(!nLDS && !nWE && RASEL);
assign nUWE = !(!nUDS && !nWE && RASEL);
assign nRAS = !((!nAS && RAMCS && RASEN) || RASrr || RASrf);
assign nLWE = !(!nLDS && !nWE && RASEL);
assign nUWE = !(!nUDS && !nWE && RASEL);
/* ROM control signals */
assign nROMCS = !ROMCS;
assign nROMWE = !(!nAS && !nWE);
/* Shared /OE control */
/* Shared ROM and RAM /OE control */
always @(posedge CLK) nOE <= !(BACT && !nWE && !(BACTr && DTACKr));
/* RAM address mux (and ROM address on RA8) */
@ -62,14 +61,16 @@ module RAM(
assign RA[01] = !RASEL ? A[10] : A[02];
assign RA[00] = !RASEL ? A[09] : A[01];
always @(posedge CLK) begin
case (RS[3:0])
0: begin // Idle/ready
if ((RefReq && BACT && !BACTr && !RAMCS0X) ||
wire RS0toRef = (RefReq && BACT && !BACTr && !RAMCS0X) ||
(RefUrg && !RASEN) ||
(RefUrg && BACT && !RAMCS0X) ||
(RefUrg && !BACT)) begin // Go to refresh
RS <= 8;
(RefUrg && !BACT);
always @(posedge CLK) begin
case (RS[2:0])
0: begin // Idle/ready
if (RS0toRef) begin // Go to refresh
RS <= 4;
RASEL <= 0;
RASrr <= 0;
RASEN <= 0;
@ -117,52 +118,49 @@ module RAM(
end else begin // Cycle ended so go abck to idle/ready
RS <= 0;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
RASEN <= 1;
RAMReady <= 1;
end
end 8: begin // Refresh CAS
end 9: begin // Refresh RAS I
end 4: begin // Refresh RAS I
RS <= 5;
RASEL <= 0;
RASrr <= 1;
RASEN <= 0;
RAMReady <= 0;
end 10: begin // Refresh RAS II
end 5: begin // Refresh RAS II
RS <= 6;
RASEL <= 0;
RASrr <= 1;
RASEN <= 0;
RAMReady <= 0;
end 11: begin // Refresh precharge I
RS <= 6;
RASEL <= 0;
RASrr <= 0;
RASEN <= 0;
RAMReady <= 0;
end 12: begin // Refresh precharge II
RS <= 15;
RASEL <= 0;
RASrr <= 0;
RASEN <= 0;
RAMReady <= 0;
end 15: begin // Reenable RAM and go to idle/ready
end 6: begin // Refresh precharge I / II
if (RASrr) begin
RS <= 6;
RASEL <= 0;
RASrr <= 0;
RASEN <= 0;
RAMReady <= 0;
end else begin
RS <= 7;
RASEL <= 0;
RASrr <= 0;
RASEN <= 0;
RAMReady <= 0;
end
end 7: begin // Reenable RAM and go to idle/ready
RS <= 0;
RASEL <= 0;
RASrr <= 0;
RASEN <= 1;
RAMReady <= 1;
end default: begin
end
endcase
end
always @(negedge CLK) begin
RASrf <= RS==1;
case (RS[2:0])
0: nCAS <= 1;
0: nCAS <= !RS0toRef;
1: nCAS <= 0;
2: nCAS <= DTACKr;
3: nCAS <= !RefUrg;