Macintosh-HW
/
Warp-SE
mirror of https://github.com/garrettsworkshop/Warp-SE.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

idk

This commit is contained in:
Zane Kaminski 2023-03-22 04:32:46 -04:00
parent f8fedc0a14
commit 473dd60fba
6 changed files with 5357 additions and 28563 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29972
PowerAdapter/SEPowerAdapter.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

28
PowerAdapter/SEPowerAdapter.kicad_pro
View File

@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
@ -153,7 +154,8 @@
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@ -337,18 +339,23 @@
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
@ -358,6 +365,7 @@
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "error",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
@ -375,7 +383,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -389,13 +397,15 @@
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
@ -411,6 +421,8 @@
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
@ -442,7 +454,11 @@
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},

3865
PowerAdapter/SEPowerAdapter.kicad_sch
View File

File diff suppressed because it is too large Load Diff

4
PowerAdapter/sym-lib-table Normal file
View File

@ -0,0 +1,4 @@
(sym_lib_table
(version 7)
(lib (name "GW_Logic")(type "KiCad")(uri "${KIPRJMOD}/../../GW_Parts/GW_Logic.kicad_sym")(options "")(descr ""))
)

14
WarpSE.kicad_pro
View File

@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
@ -179,7 +180,8 @@
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@ -401,7 +403,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -415,13 +417,15 @@
"track_width": 0.15,
"via_diameter": 0.5,
"via_drill": 0.2,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {

37
cpld/CS.v
View File

@ -16,15 +16,13 @@ module CS(
always @(posedge CLK, negedge nRES) begin
if (~nRES) nOverlay0 <= 0;
else if (BACT && ODCS) nOverlay0 <= 1;
end
always @(posedge CLK) begin
if (~BACT) nOverlay1 <= nOverlay0;
end
/* Select signals - FSB domain */
wire RAMCS_OverlayOff = A[23:22]==2'b00;
wire RAMCS_OverlayOn = A[23:21]==3'b011;
assign RAMCS = (RAMCS_OverlayOff && ~Overlay) || // 000000-3FFFFF when overlay disabled
assign RAMCS = (RAMCS_OverlayOff && !Overlay) || // 000000-3FFFFF when overlay disabled
(RAMCS_OverlayOn && Overlay); // 600000-7FFFFF when overlay enabled
wire VidRAMCSWR64k = RAMCS && A[21:20]==2'h3 && A[19:16]==4'hF && ~nWE; // 3F0000-3FFFFF / 7F0000-7FFFFF
wire VidRAMCSWR = VidRAMCSWR64k && (
@ -44,23 +42,26 @@ module CS(
(A[15:12]==4'hF && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
(A[15:12]==4'hA && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
assign ROMCS = (A[23:20]==4'h4 && FastROMEN) ||
(A[23:20]==4'h8 && !FastROMEN) ||
(A[23:20]==4'h0 && Overlay);
assign ROMCS = (A[23:20]==4'h0 && FastROMEN && Overlay) ||
(A[23:20]==4'h4 && FastROMEN) ||
(A[23:20]==4'hC && !FastROMEN);
/* Select signals - IOB domain */
assign IACS = A[23:08]==16'hFFFF; // IACK
assign IOCS = (A[23:20]==4'h4 && !FastROMEN) || // Motherboard ROM
A[23:20]==4'h5 || // SCSI
A[23:20]==4'h8 || // empty
A[23:20]==4'h9 || // SCC read/reset
A[23:20]==4'hA || // empty
A[23:20]==4'hB || // SCC write
A[23:20]==4'hC || // empty
A[23:20]==4'hD || // IWM
A[23:20]==4'hE || // VIA
A[23:20]==4'hF || // IACK
VidRAMCSWR;
assign IACS = A[23:08]==16'hFFFF; // IACK
assign IOCS = (A[23:20]==4'h0 && !FastROMEN && !Overlay) ||
(A[23:20]==4'h4 && !FastROMEN) || // Motherboard ROM
A[23:20]==4'h5 || // SCSI
A[23:20]==4'h6 || // empty
A[23:20]==4'h7 || // empty
A[23:20]==4'h8 || // empty
A[23:20]==4'h9 || // SCC read/reset
A[23:20]==4'hA || // empty
A[23:20]==4'hB || // SCC write
(A[23:20]==4'hC && FastROMEN) || // empty / fast ROM
A[23:20]==4'hD || // IWM
A[23:20]==4'hE || // VIA
A[23:20]==4'hF || // IACK
VidRAMCSWR;
assign SCSICS = A[23:20]==4'h5; // SCSI
assign IOPWCS = RAMCS_OverlayOff && ~nWE;