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https://github.com/garrettsworkshop/Warp-SE.git
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Add settings module power-on reset
This commit is contained in:
Zane Kaminski
parent
d92e235e25
commit
4788ad7fe0
@ -1,6 +1,8 @@
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module CNT(
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/* FSB clock and E clock inputs */
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input CLK, input C8M, input E,
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/* Power-on reset */
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output reg nPOR,
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/* Refresh request */
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output reg RefReq, output reg RefUrg,
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/* Reset, button */
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@ -110,7 +112,6 @@ module CNT(
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always @(posedge CLK) LTimerTick <= TimerTick && LTimerTC;
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/* C8M duty cycle check and power-on reset */
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reg nPOR = 0;
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always @(posedge CLK) begin
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if (C8Mr[3:0]==4'b0000 || C8Mr[3:0]==4'b1111) nPOR <= 0;
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else if (C8Mr[1:0]==2'b01) nPOR <= 1;
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12
cpld/SET.v
12
cpld/SET.v
@ -1,5 +1,6 @@
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module SET(
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input CLK,
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input nPOR,
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input BACT,
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input [11:1] A,
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input SetCSWR,
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@ -15,7 +16,16 @@ module SET(
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reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR;
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always @(posedge CLK) begin
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if (SetWRr) begin
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if (!nPOR) begin
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SlowTimeout[3:0] <= 4'hF;
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SlowIACK <= 1;
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SlowVIA <= 1;
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SlowIWM <= 1;
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SlowSCC <= 1;
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SlowSCSI <= 1;
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SlowSnd <= 1;
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SlowClockGate <= 1;
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end else if (SetWRr) begin
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SlowTimeout[3:0] <= A[11:8];
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SlowIACK <= A[7];
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SlowVIA <= A[6];
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@ -55,6 +55,9 @@ module WarpSE(
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wire nRESin = nRES;
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wire nRESout;
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assign nRES = !nRESout ? 1'b0 : 1'bZ;
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/* Power-on reset */
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wire nPOR;
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/* AS cycle detection */
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wire ASrf, BACT, BACTr;
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@ -208,6 +211,7 @@ module WarpSE(
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wire [3:0] SlowTimeout;
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SET set(
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.CLK(FCLK),
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.nPOR(nPOR),
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.BACT(BACT),
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.A(A_FSB[11:1]),
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.SetCSWR(SetCSWR),
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@ -227,6 +231,8 @@ module WarpSE(
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.CLK(FCLK),
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.C8M(C8M),
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.E(E),
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/* Power-on reset */
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.nPOR(nPOR),
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/* Refresh request */
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.RefReq(RefReq),
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.RefUrg(RefUrg),
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@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.10 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.10 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Reading design: WarpSE.prj
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@ -75,7 +75,9 @@ wysiwyg : NO
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../SET.v" in library work
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Compiling verilog file "../RAM.v" in library work
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Module <SET> compiled
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Compiling verilog file "../IOBS.v" in library work
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Module <RAM> compiled
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Compiling verilog file "../IOBM.v" in library work
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@ -106,6 +108,8 @@ Analyzing hierarchy for module <IOBS> in library <work>.
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Analyzing hierarchy for module <IOBM> in library <work>.
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Analyzing hierarchy for module <SET> in library <work>.
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Analyzing hierarchy for module <CNT> in library <work>.
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Analyzing hierarchy for module <FSB> in library <work>.
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@ -129,6 +133,9 @@ Module <IOBS> is correct for synthesis.
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Analyzing module <IOBM> in library <work>.
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Module <IOBM> is correct for synthesis.
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Analyzing module <SET> in library <work>.
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Module <SET> is correct for synthesis.
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Analyzing module <CNT> in library <work>.
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Module <CNT> is correct for synthesis.
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@ -239,11 +246,28 @@ WARNING:Xst:646 - Signal <IOS0> is assigned but never used. This unconnected sig
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Unit <IOBM> synthesized.
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Synthesizing Unit <SET>.
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Related source file is "../SET.v".
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Found 1-bit register for signal <SlowSCC>.
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Found 1-bit register for signal <SlowIACK>.
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Found 1-bit register for signal <SlowIWM>.
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Found 1-bit register for signal <SlowSnd>.
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Found 4-bit register for signal <SlowTimeout>.
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Found 1-bit register for signal <SlowSCSI>.
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Found 1-bit register for signal <SlowVIA>.
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Found 1-bit register for signal <SlowClockGate>.
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Found 1-bit register for signal <SetWRr>.
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Summary:
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inferred 1 D-type flip-flop(s).
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Unit <SET> synthesized.
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Synthesizing Unit <CNT>.
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Related source file is "../CNT.v".
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Found 1-bit register for signal <RefUrg>.
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Found 1-bit register for signal <RefReq>.
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Found 1-bit register for signal <nBR_IOB>.
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Found 1-bit register for signal <nPOR>.
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Found 1-bit register for signal <QoSEN>.
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Found 1-bit register for signal <nRESout>.
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Found 1-bit register for signal <AoutOE>.
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@ -253,15 +277,13 @@ Synthesizing Unit <CNT>.
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Found 2-bit register for signal <IS>.
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Found 12-bit up counter for signal <LTimer>.
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Found 1-bit register for signal <LTimerTick>.
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Found 1-bit register for signal <nPOR>.
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Found 1-bit register for signal <QoSCSr>.
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Found 4-bit down counter for signal <QS>.
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Found 1-bit register for signal <SndQoSCSr>.
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Found 4-bit up counter for signal <Timer>.
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Found 1-bit register for signal <TimerTick>.
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Summary:
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inferred 3 Counter(s).
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inferred 11 D-type flip-flop(s).
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inferred 10 D-type flip-flop(s).
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Unit <CNT> synthesized.
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@ -302,11 +324,11 @@ Macro Statistics
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12-bit up counter : 1
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4-bit down counter : 1
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4-bit up counter : 2
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# Registers : 62
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1-bit register : 58
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# Registers : 70
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1-bit register : 65
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2-bit register : 2
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3-bit register : 1
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4-bit register : 1
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4-bit register : 2
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# Tristates : 7
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1-bit tristate buffer : 7
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@ -374,6 +396,8 @@ Optimizing unit <IOBS> ...
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implementation constraint: INIT=r : Sent
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implementation constraint: INIT=r : TS_FSM_FFd1
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Optimizing unit <SET> ...
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Optimizing unit <IOBM> ...
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implementation constraint: INIT=s : IOS_FSM_FFd7
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implementation constraint: INIT=r : DoutOE
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@ -388,7 +412,6 @@ Optimizing unit <CNT> ...
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implementation constraint: INIT=r : Timer_2
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implementation constraint: INIT=r : IS_0
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implementation constraint: INIT=r : IS_1
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implementation constraint: INIT=r : nPOR
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implementation constraint: INIT=r : Timer_3
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implementation constraint: INIT=r : Timer_0
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implementation constraint: INIT=r : Timer_1
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@ -423,22 +446,23 @@ Design Statistics
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# IOs : 80
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Cell Usage :
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# BELS : 647
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# AND2 : 194
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# AND3 : 27
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# AND4 : 12
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# BELS : 691
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# AND2 : 209
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# AND3 : 26
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# AND4 : 13
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# AND5 : 3
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# AND8 : 2
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# GND : 6
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# INV : 262
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# OR2 : 106
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# OR3 : 9
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# GND : 7
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# INV : 278
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# OR2 : 116
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# OR3 : 10
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# OR4 : 4
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# OR5 : 1
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# OR6 : 1
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# XOR2 : 21
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# FlipFlops/Latches : 102
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# FlipFlops/Latches : 113
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# FD : 61
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# FDCE : 36
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# FDCE : 47
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# FDCP : 1
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# FDP : 4
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# IO Buffers : 73
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@ -450,11 +474,11 @@ Cell Usage :
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Total REAL time to Xst completion: 5.00 secs
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Total CPU time to Xst completion: 5.10 secs
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Total CPU time to Xst completion: 4.96 secs
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-->
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Total memory usage is 262560 kilobytes
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Total memory usage is 263392 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 3 ( 0 filtered)
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