mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-21 17:31:47 +00:00
Add settings module power-on reset
This commit is contained in:
Zane Kaminski
parent
d92e235e25
commit
4788ad7fe0
@ -1,6 +1,8 @@
|
||||
module CNT(
|
||||
/* FSB clock and E clock inputs */
|
||||
input CLK, input C8M, input E,
|
||||
/* Power-on reset */
|
||||
output reg nPOR,
|
||||
/* Refresh request */
|
||||
output reg RefReq, output reg RefUrg,
|
||||
/* Reset, button */
|
||||
@ -110,7 +112,6 @@ module CNT(
|
||||
always @(posedge CLK) LTimerTick <= TimerTick && LTimerTC;
|
||||
|
||||
/* C8M duty cycle check and power-on reset */
|
||||
reg nPOR = 0;
|
||||
always @(posedge CLK) begin
|
||||
if (C8Mr[3:0]==4'b0000 || C8Mr[3:0]==4'b1111) nPOR <= 0;
|
||||
else if (C8Mr[1:0]==2'b01) nPOR <= 1;
|
||||
|
||||
12
cpld/SET.v
12
cpld/SET.v
@ -1,5 +1,6 @@
|
||||
module SET(
|
||||
input CLK,
|
||||
input nPOR,
|
||||
input BACT,
|
||||
input [11:1] A,
|
||||
input SetCSWR,
|
||||
@ -15,7 +16,16 @@ module SET(
|
||||
reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (SetWRr) begin
|
||||
if (!nPOR) begin
|
||||
SlowTimeout[3:0] <= 4'hF;
|
||||
SlowIACK <= 1;
|
||||
SlowVIA <= 1;
|
||||
SlowIWM <= 1;
|
||||
SlowSCC <= 1;
|
||||
SlowSCSI <= 1;
|
||||
SlowSnd <= 1;
|
||||
SlowClockGate <= 1;
|
||||
end else if (SetWRr) begin
|
||||
SlowTimeout[3:0] <= A[11:8];
|
||||
SlowIACK <= A[7];
|
||||
SlowVIA <= A[6];
|
||||
|
||||
@ -56,6 +56,9 @@ module WarpSE(
|
||||
wire nRESout;
|
||||
assign nRES = !nRESout ? 1'b0 : 1'bZ;
|
||||
|
||||
/* Power-on reset */
|
||||
wire nPOR;
|
||||
|
||||
/* AS cycle detection */
|
||||
wire ASrf, BACT, BACTr;
|
||||
|
||||
@ -208,6 +211,7 @@ module WarpSE(
|
||||
wire [3:0] SlowTimeout;
|
||||
SET set(
|
||||
.CLK(FCLK),
|
||||
.nPOR(nPOR),
|
||||
.BACT(BACT),
|
||||
.A(A_FSB[11:1]),
|
||||
.SetCSWR(SetCSWR),
|
||||
@ -227,6 +231,8 @@ module WarpSE(
|
||||
.CLK(FCLK),
|
||||
.C8M(C8M),
|
||||
.E(E),
|
||||
/* Power-on reset */
|
||||
.nPOR(nPOR),
|
||||
/* Refresh request */
|
||||
.RefReq(RefReq),
|
||||
.RefUrg(RefUrg),
|
||||
|
||||
@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.10 secs
|
||||
Total CPU time to Xst completion: 0.08 secs
|
||||
|
||||
--> Parameter xsthdpdir set to xst
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.10 secs
|
||||
Total CPU time to Xst completion: 0.08 secs
|
||||
|
||||
--> Reading design: WarpSE.prj
|
||||
|
||||
@ -75,7 +75,9 @@ wysiwyg : NO
|
||||
=========================================================================
|
||||
* HDL Compilation *
|
||||
=========================================================================
|
||||
Compiling verilog file "../SET.v" in library work
|
||||
Compiling verilog file "../RAM.v" in library work
|
||||
Module <SET> compiled
|
||||
Compiling verilog file "../IOBS.v" in library work
|
||||
Module <RAM> compiled
|
||||
Compiling verilog file "../IOBM.v" in library work
|
||||
@ -106,6 +108,8 @@ Analyzing hierarchy for module <IOBS> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <IOBM> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <SET> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <CNT> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <FSB> in library <work>.
|
||||
@ -129,6 +133,9 @@ Module <IOBS> is correct for synthesis.
|
||||
Analyzing module <IOBM> in library <work>.
|
||||
Module <IOBM> is correct for synthesis.
|
||||
|
||||
Analyzing module <SET> in library <work>.
|
||||
Module <SET> is correct for synthesis.
|
||||
|
||||
Analyzing module <CNT> in library <work>.
|
||||
Module <CNT> is correct for synthesis.
|
||||
|
||||
@ -239,11 +246,28 @@ WARNING:Xst:646 - Signal <IOS0> is assigned but never used. This unconnected sig
|
||||
Unit <IOBM> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <SET>.
|
||||
Related source file is "../SET.v".
|
||||
Found 1-bit register for signal <SlowSCC>.
|
||||
Found 1-bit register for signal <SlowIACK>.
|
||||
Found 1-bit register for signal <SlowIWM>.
|
||||
Found 1-bit register for signal <SlowSnd>.
|
||||
Found 4-bit register for signal <SlowTimeout>.
|
||||
Found 1-bit register for signal <SlowSCSI>.
|
||||
Found 1-bit register for signal <SlowVIA>.
|
||||
Found 1-bit register for signal <SlowClockGate>.
|
||||
Found 1-bit register for signal <SetWRr>.
|
||||
Summary:
|
||||
inferred 1 D-type flip-flop(s).
|
||||
Unit <SET> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <CNT>.
|
||||
Related source file is "../CNT.v".
|
||||
Found 1-bit register for signal <RefUrg>.
|
||||
Found 1-bit register for signal <RefReq>.
|
||||
Found 1-bit register for signal <nBR_IOB>.
|
||||
Found 1-bit register for signal <nPOR>.
|
||||
Found 1-bit register for signal <QoSEN>.
|
||||
Found 1-bit register for signal <nRESout>.
|
||||
Found 1-bit register for signal <AoutOE>.
|
||||
@ -253,15 +277,13 @@ Synthesizing Unit <CNT>.
|
||||
Found 2-bit register for signal <IS>.
|
||||
Found 12-bit up counter for signal <LTimer>.
|
||||
Found 1-bit register for signal <LTimerTick>.
|
||||
Found 1-bit register for signal <nPOR>.
|
||||
Found 1-bit register for signal <QoSCSr>.
|
||||
Found 4-bit down counter for signal <QS>.
|
||||
Found 1-bit register for signal <SndQoSCSr>.
|
||||
Found 4-bit up counter for signal <Timer>.
|
||||
Found 1-bit register for signal <TimerTick>.
|
||||
Summary:
|
||||
inferred 3 Counter(s).
|
||||
inferred 11 D-type flip-flop(s).
|
||||
inferred 10 D-type flip-flop(s).
|
||||
Unit <CNT> synthesized.
|
||||
|
||||
|
||||
@ -302,11 +324,11 @@ Macro Statistics
|
||||
12-bit up counter : 1
|
||||
4-bit down counter : 1
|
||||
4-bit up counter : 2
|
||||
# Registers : 62
|
||||
1-bit register : 58
|
||||
# Registers : 70
|
||||
1-bit register : 65
|
||||
2-bit register : 2
|
||||
3-bit register : 1
|
||||
4-bit register : 1
|
||||
4-bit register : 2
|
||||
# Tristates : 7
|
||||
1-bit tristate buffer : 7
|
||||
|
||||
@ -374,6 +396,8 @@ Optimizing unit <IOBS> ...
|
||||
implementation constraint: INIT=r : Sent
|
||||
implementation constraint: INIT=r : TS_FSM_FFd1
|
||||
|
||||
Optimizing unit <SET> ...
|
||||
|
||||
Optimizing unit <IOBM> ...
|
||||
implementation constraint: INIT=s : IOS_FSM_FFd7
|
||||
implementation constraint: INIT=r : DoutOE
|
||||
@ -388,7 +412,6 @@ Optimizing unit <CNT> ...
|
||||
implementation constraint: INIT=r : Timer_2
|
||||
implementation constraint: INIT=r : IS_0
|
||||
implementation constraint: INIT=r : IS_1
|
||||
implementation constraint: INIT=r : nPOR
|
||||
implementation constraint: INIT=r : Timer_3
|
||||
implementation constraint: INIT=r : Timer_0
|
||||
implementation constraint: INIT=r : Timer_1
|
||||
@ -423,22 +446,23 @@ Design Statistics
|
||||
# IOs : 80
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 647
|
||||
# AND2 : 194
|
||||
# AND3 : 27
|
||||
# AND4 : 12
|
||||
# BELS : 691
|
||||
# AND2 : 209
|
||||
# AND3 : 26
|
||||
# AND4 : 13
|
||||
# AND5 : 3
|
||||
# AND8 : 2
|
||||
# GND : 6
|
||||
# INV : 262
|
||||
# OR2 : 106
|
||||
# OR3 : 9
|
||||
# GND : 7
|
||||
# INV : 278
|
||||
# OR2 : 116
|
||||
# OR3 : 10
|
||||
# OR4 : 4
|
||||
# OR5 : 1
|
||||
# OR6 : 1
|
||||
# XOR2 : 21
|
||||
# FlipFlops/Latches : 102
|
||||
# FlipFlops/Latches : 113
|
||||
# FD : 61
|
||||
# FDCE : 36
|
||||
# FDCE : 47
|
||||
# FDCP : 1
|
||||
# FDP : 4
|
||||
# IO Buffers : 73
|
||||
@ -450,11 +474,11 @@ Cell Usage :
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 5.00 secs
|
||||
Total CPU time to Xst completion: 5.10 secs
|
||||
Total CPU time to Xst completion: 4.96 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 262560 kilobytes
|
||||
Total memory usage is 263392 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 3 ( 0 filtered)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user