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Extra 1/2 FCLK IODONE delay

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This commit is contained in:
Zane Kaminski 2024-10-07 06:09:43 -04:00
parent d14ca62644
commit 7c6787352b
1 changed files with 2 additions and 1 deletions
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3
cpld/IOBS.v
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@ -21,8 +21,9 @@ module IOBS(
reg IOACTr = 0; always @(posedge CLK) IOACTr <= IOACT;
/* IODTACK input synchronization */
reg IODONErf; always @(negedge CLK) IODONErf <= IODONEin;
reg [1:0] IODONEr;
always @(posedge CLK) IODONEr[1:0] <= {IODONEr[0], IODONEin};
always @(posedge CLK) IODONEr[1:0] <= {IODONEr[0], IODONErf};
wire IODONE = !IODONEr[1] && IODONEr[0];
/* Read data OE control */