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Register /DTACK at C16M clock edge instead
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19
cpld/IOBM.v
19
cpld/IOBM.v
@ -39,22 +39,17 @@ module IOBM(
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/* I/O bus state */
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reg [2:0] IOS = 0;
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reg IOS0;
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/* Cycle termination signal enable */
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reg TermEN;
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always @(posedge C16M) begin
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TermEN <= IOS==2 || IOS==3 || IOS==4 || IOS==5;
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end
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/* DTACK/"ETACK"/BERR/reset falling edge synchronization */
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/* DTACK/"ETACK"/BERR/reset synchronization */
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reg IODONEr;
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always @(negedge C8M, posedge nAS) begin
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if (nAS) IODONEr <= 0;
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else IODONEr <= TermEN && (!nDTACK || ETACK || !nBERR || !nRES);
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always @(posedge C16M) begin
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if ((IOS==3 || IOS==5) && !C8Mr) begin
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IODONEr <= !nDTACK || ETACK || !nBERR || !nRES;
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end else if (IOS==0) IODONEr <= 0;
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end
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/* DTACK/"ETACK"/BERR/reset output */
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assign IODONE = IODONEr && TermEN;
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assign IODONE = IODONEr;
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/* I/O bus control */
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always @(posedge C16M) case (IOS[2:0])
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