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Works with new Ready. RAM still untested

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This commit is contained in:
Zane Kaminski 2023-04-07 00:41:16 -04:00
parent a60c54fb6c
commit 804e84d1e2
41 changed files with 10239 additions and 10244 deletions
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2
cpld/CS.v
View File

@ -45,7 +45,7 @@ module CS(
((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3))));
/* Select signals - IOB domain */
assign IACS = (A[23:20]==4'hF); // IACK
assign IACS = (A[23:20]==4'hF) && (A[19:18]==2'b11); // IACK
assign IOCS = (A[23:20]==4'hF) || // IACK
(A[23:20]==4'hE) || // VIA
(A[23:20]==4'hD) || // IWM

2
cpld/FSB.v
View File

@ -20,7 +20,7 @@ module FSB(
/* DTACK/VPA control */
wire Ready = /*(RAMCS && RAMReady && !IOPWCS) ||*/
(/*RAMCS && RAMReady &&*/ IOPWCS && IOPWReady /*&& !QoSCS*/) ||
/*(RAMCS && RAMReady && IOPWCS && IOPWReady && QoSCS && QoSReady)*/ ||
/*(RAMCS && RAMReady && IOPWCS && IOPWReady && QoSCS && QoSReady) ||*/
(ROMCS) || (IONPReady);
always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
always @(posedge FCLK, posedge nAS) begin

55
cpld/IOBM.v
View File

@ -16,6 +16,27 @@ module IOBM(
reg IORDREQr; always @(posedge C16M) IORDREQr <= IORDREQ;
reg IOWRREQr; always @(posedge C16M) IOWRREQr <= IOWRREQ;
wire IOREQr = IORDREQr || IOWRREQr;
/* VPA synchronization */
reg VPAr; always @(negedge C8M) VPAr <= !nVPA;
/* E clock synchronization */
reg Er; always @(negedge C8M) begin Er <= E; end
/* E clock state */
reg [3:0] ES;
always @(negedge C8M) begin
if (!E && Er) ES <= 1;
else if (ES==0 || ES==9) ES <= 0;
else ES <= ES+1;
end
/* ETACK and VMA generation */
wire ETACK = (ES==8) && !nVMA;
always @(posedge C8M) begin
if ((ES==5) && IOACT && VPAr) nVMA <= 0;
else if(ES==0) nVMA <= 1;
end
/* DTACK and BERR synchronization */
always @(negedge C8M, posedge nASout) begin
@ -24,34 +45,10 @@ module IOBM(
IOBERR <= 0;
end else begin
IODONE <= (!nDTACK || ETACK || !nRES);
IOBERR <= !nIOBERR;
IOBERR <= !nBERR;
end
end
/* VPA and RESET synchronization */
reg RESr; always @(posedge C16M) RESr <= !nRES;
reg VPAr; always @(posedge C16M) VPAr <= !nVPA;
/* E clock synchronization */
reg Er; always @(negedge C8M) begin Er <= E; end
reg Er2; always @(posedge C16M) begin Er2 <= Er; end
/* E clock state */
reg [4:0] ES;
always @(posedge C16M) begin
if (Er2 && ~Er) ES <= 1;
else if (ES==0 || ES==19) ES <= 0;
else ES <= ES+1;
end
/* ETACK and VMA generation */
reg ETACK = 0;
always @(posedge C16M) begin ETACK <= ES==16 && ~nVMA; end
always @(posedge C16M) begin
if (ES==7 && IOACT && VPAr) nVMA <= 0;
else if (ES==0) nVMA <= 1;
end
/* I/O bus state */
reg [2:0] IOS = 0;
reg IOS0;
@ -111,13 +108,13 @@ module IOBM(
DoutOE <= (IOS==0 && IOWRREQr && !C8Mr) ||
(DoutOE && (IOS==2 || IOS==3 || IOS==4 || IOS==5));
end
assign nDoutOE = !(AoutOE && (DoutOE || (IOS==0 && !IOREQr)));
assign nDoutOE = !(AoutOE && (DoutOE || (IOS0 && !IOREQr)));
/* AS, DS control */
always @(negedge C16M) begin
nASout <= ~((IOS==0 && IOREQr && !C8Mr) || IOS==2 || IOS==3 || IOS==4 || IOS==5);
nLDS <= ~(IOLDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && IORDREQr) || IOS==3 || IOS==4 || IOS==5));
nUDS <= ~(IOUDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && IORDREQr) || IOS==3 || IOS==4 || IOS==5));
nASout <= !((IOS==0 && IOREQr && !C8Mr) || IOS==2 || IOS==3 || IOS==4 || IOS==5);
nLDS <= !(IOLDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && !nLDS) || IOS==3 || IOS==4 || IOS==5));
nUDS <= !(IOUDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && !nUDS) || IOS==3 || IOS==4 || IOS==5));
end
endmodule

12
cpld/IOBS.v
View File

@ -21,10 +21,9 @@ module IOBS(
reg IOACTr = 0; always @(posedge CLK) IOACTr <= IOACT;
/* IODTACK input synchronization */
reg [1:0] IODONErr; reg [1:0] IODONErf;
always @(posedge CLK) IODONErr[1:0] <= { IODONErr[0], IODONEin };
always @(posedge CLK) IODONErf[1:0] <= { IODONErf[0], IODONEin };
wire IODONE = IODONErr[1];
reg [1:0] IODONEr;
always @(posedge CLK) IODONEr[1:0] <= { IODONEr[0], IODONEin };
wire IODONE = IODONEr[0];
/* Read data OE control */
assign nDinOE = !(!nAS && IOCS && nWE && !ROMCS);
@ -42,7 +41,6 @@ module IOBS(
* transitions to TS1 when IOACT false */
reg [1:0] TS = 0;
reg Sent = 0;
reg PostSent = 0;
/* FIFO secondary level control */
reg Load1;
@ -81,11 +79,15 @@ module IOBS(
TS <= 3;
IORDREQ <= IORW1;
IOWRREQ <= !IORW1;
IOL0 <= IOL1;
IOU0 <= IOU1;
end else if (BACT && IOCS && !ALE1 && !Sent) begin // FSB request
// Request transfer from IOBM and latch R/W from FSB
TS <= 3;
IORDREQ <= nWE;
IOWRREQ <= !nWE;
IOL0 <= !nLDS;
IOU0 <= !nUDS;
end else begin // Otherwise stay in idle
TS <= 0;
IORDREQ <= 0;

20
cpld/RAM.v
View File

@ -13,15 +13,6 @@ module RAM(
/* BACT saved from last cycle */
reg BACTr; always @(posedge CLK) BACTr <= BACT;
/* Refresh command generation */
reg RefDone; // Refresh done "remember"
always @(posedge CLK) begin
if (!RefReqIn && !RefUrgIn) RefDone <= 0;
else if (RS==4 || RS==5) RefDone <= 1;
end
wire RefReq = RefReqIn && !RefDone;
wire RefUrg = RefUrgIn && !RefDone;
/* RAM control state */
reg [2:0] RS = 0;
@ -32,6 +23,15 @@ module RAM(
reg RASrr = 0;
reg RASrf = 0;
/* Refresh command generation */
reg RefDone; // Refresh done "remember"
always @(posedge CLK) begin
if (!RefReqIn && !RefUrgIn) RefDone <= 0;
else if (RS==4 || RS==5) RefDone <= 1;
end
wire RefReq = RefReqIn && !RefDone;
wire RefUrg = RefUrgIn && !RefDone;
/* RAM control signals */
assign nRAS = !((!nAS && RAMCS && RAMEN) || RASrr || RASrf);
assign nOE = !((!nAS && nWE)); // Shared with ROM
@ -65,7 +65,7 @@ module RAM(
wire RefFromRS2 = RefUrg;
wire RAMStart = BACT && RAMCS && RAMEN;
always @(posedge CLK) begin
case (RS[3:0])
case (RS[2:0])
0: begin
if (RAMStart) begin
RS <= 1;

89
cpld/XC95144XL/WarpSE.cmd_log
View File

@ -303,3 +303,92 @@ cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt
XSLTProcess WarpSE_build.xml
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
taengine -intstyle ise -f WarpSE -l WarpSE.tim -e {C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\taengine.err}
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
taengine -intstyle ise -f WarpSE -l WarpSE.tim -e {C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\taengine.err}
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE

922
cpld/XC95144XL/WarpSE.data Normal file
View File

@ -0,0 +1,922 @@
MODELDATA
MODELDATA_VERSION "v1998.8"
DESIGN "WarpSE";
/* port drive, load, max capacitance and max transition in data file */
PORTDATA
A_FSB<23>: MAXTRANS(0.0);
A_FSB<22>: MAXTRANS(0.0);
A_FSB<21>: MAXTRANS(0.0);
A_FSB<20>: MAXTRANS(0.0);
A_FSB<19>: MAXTRANS(0.0);
A_FSB<18>: MAXTRANS(0.0);
C8M: MAXTRANS(0.0);
C16M: MAXTRANS(0.0);
FCLK: MAXTRANS(0.0);
nAS_FSB: MAXTRANS(0.0);
nWE_FSB: MAXTRANS(0.0);
nBERR_IOB: MAXTRANS(0.0);
nDTACK_IOB: MAXTRANS(0.0);
nLDS_FSB: MAXTRANS(0.0);
nUDS_FSB: MAXTRANS(0.0);
E: MAXTRANS(0.0);
nIPL2: MAXTRANS(0.0);
nVPA_IOB: MAXTRANS(0.0);
A_FSB<10>: MAXTRANS(0.0);
A_FSB<11>: MAXTRANS(0.0);
A_FSB<12>: MAXTRANS(0.0);
A_FSB<13>: MAXTRANS(0.0);
A_FSB<14>: MAXTRANS(0.0);
A_FSB<15>: MAXTRANS(0.0);
A_FSB<16>: MAXTRANS(0.0);
A_FSB<17>: MAXTRANS(0.0);
A_FSB<9>: MAXTRANS(0.0);
nRES: MAXTRANS(0.0);
nVMA_IOB: MAXTRANS(0.0);
nAS_IOB: MAXTRANS(0.0);
nLDS_IOB: MAXTRANS(0.0);
nUDS_IOB: MAXTRANS(0.0);
nBERR_FSB: MAXTRANS(0.0);
nVPA_FSB: MAXTRANS(0.0);
nBR_IOB: MAXTRANS(0.0);
nOE: MAXTRANS(0.0);
nROMWE: MAXTRANS(0.0);
nADoutLE0: MAXTRANS(0.0);
nCAS: MAXTRANS(0.0);
nDTACK_FSB: MAXTRANS(0.0);
nDinLE: MAXTRANS(0.0);
RA<1>: MAXTRANS(0.0);
RA<4>: MAXTRANS(0.0);
RA<5>: MAXTRANS(0.0);
RA<6>: MAXTRANS(0.0);
RA<7>: MAXTRANS(0.0);
RA<9>: MAXTRANS(0.0);
RA<2>: MAXTRANS(0.0);
RA<10>: MAXTRANS(0.0);
RA<8>: MAXTRANS(0.0);
RA<3>: MAXTRANS(0.0);
RA<11>: MAXTRANS(0.0);
RA<0>: MAXTRANS(0.0);
nADoutLE1: MAXTRANS(0.0);
nAoutOE: MAXTRANS(0.0);
nDinOE: MAXTRANS(0.0);
nDoutOE: MAXTRANS(0.0);
nRAMLWE: MAXTRANS(0.0);
nRAMUWE: MAXTRANS(0.0);
nRAS: MAXTRANS(0.0);
nROMCS: MAXTRANS(0.0);
C20MEN: MAXTRANS(0.0);
C25MEN: MAXTRANS(0.0);
ENDPORTDATA
/* timing arc data */
TIMINGDATA
ARCDATA
A_FSB<9>_RA<0>_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<17>_RA<10>_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<19>_RA<11>_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<10>_RA<1>_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<16>_RA<2>_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<19>_RA<3>_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<11>_RA<4>_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<12>_RA<5>_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<13>_RA<6>_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<14>_RA<7>_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<18>_RA<8>_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<15>_RA<9>_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
nAS_FSB_nDinOE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
nWE_FSB_nDinOE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<23>_nDinOE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<22>_nDinOE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<20>_nDinOE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<21>_nDinOE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
nWE_FSB_nOE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
nAS_FSB_nOE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
nWE_FSB_nRAMLWE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
nAS_FSB_nRAMLWE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
nLDS_FSB_nRAMLWE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
nUDS_FSB_nRAMUWE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
nWE_FSB_nRAMUWE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
nAS_FSB_nRAMUWE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<20>_nROMCS_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<22>_nROMCS_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<23>_nROMCS_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A_FSB<21>_nROMCS_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
nAS_FSB_nROMWE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
nWE_FSB_nROMWE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
FCLK_nRES_delay:
CELL_RISE(scalar) {
VALUES("14.5");
}
CELL_FALL(scalar) {
VALUES("14.5");
}
ENDARCDATA
ARCDATA
FCLK_nVMA_IOB_delay:
CELL_RISE(scalar) {
VALUES("14.5");
}
CELL_FALL(scalar) {
VALUES("14.5");
}
ENDARCDATA
ARCDATA
FCLK_nAS_IOB_delay:
CELL_RISE(scalar) {
VALUES("14.5");
}
CELL_FALL(scalar) {
VALUES("14.5");
}
ENDARCDATA
ARCDATA
FCLK_nLDS_IOB_delay:
CELL_RISE(scalar) {
VALUES("14.5");
}
CELL_FALL(scalar) {
VALUES("14.5");
}
ENDARCDATA
ARCDATA
FCLK_nUDS_IOB_delay:
CELL_RISE(scalar) {
VALUES("14.5");
}
CELL_FALL(scalar) {
VALUES("14.5");
}
ENDARCDATA
ARCDATA
FCLK_nBERR_FSB_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
FCLK_nVPA_FSB_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
FCLK_nBR_IOB_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
FCLK_nADoutLE0_delay:
CELL_RISE(scalar) {
VALUES("13.5");
}
CELL_FALL(scalar) {
VALUES("13.5");
}
ENDARCDATA
ARCDATA
FCLK_nCAS_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
FCLK_nDTACK_FSB_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
FCLK_nADoutLE1_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
FCLK_nAoutOE_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
FCLK_nDinOE_delay:
CELL_RISE(scalar) {
VALUES("13.5");
}
CELL_FALL(scalar) {
VALUES("13.5");
}
ENDARCDATA
ARCDATA
FCLK_nDoutOE_delay:
CELL_RISE(scalar) {
VALUES("13.5");
}
CELL_FALL(scalar) {
VALUES("13.5");
}
ENDARCDATA
ARCDATA
FCLK_nRAMLWE_delay:
CELL_RISE(scalar) {
VALUES("13.5");
}
CELL_FALL(scalar) {
VALUES("13.5");
}
ENDARCDATA
ARCDATA
FCLK_nRAMUWE_delay:
CELL_RISE(scalar) {
VALUES("13.5");
}
CELL_FALL(scalar) {
VALUES("13.5");
}
ENDARCDATA
ARCDATA
FCLK_nRAS_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
FCLK_nROMCS_delay:
CELL_RISE(scalar) {
VALUES("13.5");
}
CELL_FALL(scalar) {
VALUES("13.5");
}
ENDARCDATA
ARCDATA
C16M_nAS_IOB_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
C16M_nLDS_IOB_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
C16M_nUDS_IOB_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
C16M_nADoutLE0_delay:
CELL_RISE(scalar) {
VALUES("13.5");
}
CELL_FALL(scalar) {
VALUES("13.5");
}
ENDARCDATA
ARCDATA
C16M_nDinLE_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
C16M_nDoutOE_delay:
CELL_RISE(scalar) {
VALUES("13.5");
}
CELL_FALL(scalar) {
VALUES("13.5");
}
ENDARCDATA
ARCDATA
C8M_nVMA_IOB_delay:
CELL_RISE(scalar) {
VALUES("5.8");
}
CELL_FALL(scalar) {
VALUES("5.8");
}
ENDARCDATA
ARCDATA
A_FSB<18>_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("10.5");
}
ENDARCDATA
ARCDATA
A_FSB<19>_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("10.5");
}
ENDARCDATA
ARCDATA
A_FSB<20>_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("10.5");
}
ENDARCDATA
ARCDATA
A_FSB<21>_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("10.5");
}
ENDARCDATA
ARCDATA
A_FSB<22>_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("10.5");
}
ENDARCDATA
ARCDATA
A_FSB<23>_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("10.5");
}
ENDARCDATA
ARCDATA
E_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("9.5");
}
ENDARCDATA
ARCDATA
nAS_FSB_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("10.5");
}
ENDARCDATA
ARCDATA
nIPL2_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("9.5");
}
ENDARCDATA
ARCDATA
nLDS_FSB_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("9.5");
}
ENDARCDATA
ARCDATA
nRES_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("9.5");
}
ENDARCDATA
ARCDATA
nUDS_FSB_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("9.5");
}
ENDARCDATA
ARCDATA
nWE_FSB_FCLK_setup:
CONSTRAINT(scalar) {
VALUES("10.5");
}
ENDARCDATA
ARCDATA
A_FSB<18>_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-4");
}
ENDARCDATA
ARCDATA
A_FSB<19>_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-4");
}
ENDARCDATA
ARCDATA
A_FSB<20>_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-4");
}
ENDARCDATA
ARCDATA
A_FSB<21>_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-4");
}
ENDARCDATA
ARCDATA
A_FSB<22>_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-4");
}
ENDARCDATA
ARCDATA
A_FSB<23>_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-4");
}
ENDARCDATA
ARCDATA
E_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-3");
}
ENDARCDATA
ARCDATA
nAS_FSB_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-4");
}
ENDARCDATA
ARCDATA
nIPL2_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-3");
}
ENDARCDATA
ARCDATA
nLDS_FSB_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-3");
}
ENDARCDATA
ARCDATA
nRES_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-3");
}
ENDARCDATA
ARCDATA
nUDS_FSB_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-3");
}
ENDARCDATA
ARCDATA
nWE_FSB_FCLK_hold:
CONSTRAINT(scalar) {
VALUES("-4");
}
ENDARCDATA
ARCDATA
C8M_C16M_setup:
CONSTRAINT(scalar) {
VALUES("9.5");
}
ENDARCDATA
ARCDATA
C8M_C16M_hold:
CONSTRAINT(scalar) {
VALUES("-3");
}
ENDARCDATA
ARCDATA
E_C8M_setup:
CONSTRAINT(scalar) {
VALUES("9.5");
}
ENDARCDATA
ARCDATA
nBERR_IOB_C8M_setup:
CONSTRAINT(scalar) {
VALUES("9.5");
}
ENDARCDATA
ARCDATA
nDTACK_IOB_C8M_setup:
CONSTRAINT(scalar) {
VALUES("9.5");
}
ENDARCDATA
ARCDATA
nRES_C8M_setup:
CONSTRAINT(scalar) {
VALUES("9.5");
}
ENDARCDATA
ARCDATA
nVPA_IOB_C8M_setup:
CONSTRAINT(scalar) {
VALUES("9.5");
}
ENDARCDATA
ARCDATA
E_C8M_hold:
CONSTRAINT(scalar) {
VALUES("-3");
}
ENDARCDATA
ARCDATA
nBERR_IOB_C8M_hold:
CONSTRAINT(scalar) {
VALUES("-3");
}
ENDARCDATA
ARCDATA
nDTACK_IOB_C8M_hold:
CONSTRAINT(scalar) {
VALUES("-3");
}
ENDARCDATA
ARCDATA
nRES_C8M_hold:
CONSTRAINT(scalar) {
VALUES("-3");
}
ENDARCDATA
ARCDATA
nVPA_IOB_C8M_hold:
CONSTRAINT(scalar) {
VALUES("-3");
}
ENDARCDATA
ENDTIMINGDATA
ENDMODELDATA

15
cpld/XC95144XL/WarpSE.gise
View File

@ -67,7 +67,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1680351689" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1680351681">
<transform xil_pn:end_ts="1680841285" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1680841277">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -87,7 +87,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1680351694" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1680351689">
<transform xil_pn:end_ts="1680841290" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1680841285">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="WarpSE.bld"/>
@ -96,7 +96,7 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1680351716" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1680351694">
<transform xil_pn:end_ts="1680841304" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1680841290">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -114,17 +114,14 @@
<outfile xil_pn:name="WarpSE_html"/>
<outfile xil_pn:name="WarpSE_pad.csv"/>
</transform>
<transform xil_pn:end_ts="1680351718" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1680351716">
<transform xil_pn:end_ts="1680841306" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1680841304">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="WarpSE.jed"/>
</transform>
<transform xil_pn:end_ts="1679815119" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1679815117">
<status xil_pn:value="AbortedRun"/>
<status xil_pn:value="WarningsGenerated"/>
<transform xil_pn:end_ts="1680841425" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1680841423">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
</transforms>

95
cpld/XC95144XL/WarpSE.gyd
View File

@ -11,18 +11,10 @@ A_FSB<16> S:PIN14
A_FSB<17> S:PIN15
A_FSB<18> S:PIN16
A_FSB<19> S:PIN17
A_FSB<1> S:PIN94
A_FSB<20> S:PIN18
A_FSB<21> S:PIN19
A_FSB<22> S:PIN20
A_FSB<23> S:PIN24
A_FSB<2> S:PIN95
A_FSB<3> S:PIN96
A_FSB<4> S:PIN97
A_FSB<5> S:PIN2
A_FSB<6> S:PIN3
A_FSB<7> S:PIN4
A_FSB<8> S:PIN6
A_FSB<9> S:PIN7
C16M S:PIN22
C8M S:PIN23
@ -36,21 +28,21 @@ nLDS_FSB S:PIN30
nUDS_FSB S:PIN33
nVPA_IOB S:PIN77
nWE_FSB S:PIN29
RA<11> S:PIN63
RA<10> S:PIN55
C25MEN S:PIN58
C20MEN S:PIN59
nRES S:PIN91
RA<0> S:PIN53
RA<1> S:PIN50
RA<2> S:PIN43
RA<3> S:PIN41
RA<4> S:PIN40
RA<5> S:PIN42
RA<6> S:PIN46
RA<7> S:PIN52
RA<8> S:PIN54
RA<9> S:PIN56
RA<2> S:PIN43
RA<10> S:PIN55
RA<8> S:PIN54
RA<3> S:PIN41
RA<11> S:PIN63
RA<0> S:PIN53
nRES S:PIN91
C20MEN S:PIN59
C25MEN S:PIN58
nADoutLE0 S:PIN85
nADoutLE1 S:PIN82
nAS_IOB S:PIN81
@ -77,40 +69,39 @@ nVPA_FSB S:PIN93
;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.
PARTITION FB1_1 ram/RefUrg ram/RefReqSync ram/RefReq ram/RefRAS
iobs/IODTACKr iobm/RESrf iobm/Er2 iobm/Er
iobm/DTACKrf iobm/BERRrf cnt/nIPL2r cnt/Er<0>
ram/RefDone iobs/TS_FSM_FFd1 iobs/IOU1 iobs/IOL1
iobm/IOS_FSM_FFd1 IOU0
PARTITION FB2_17 iobm/VPAr iobm/IOREQr
PARTITION FB3_1 fsb/VPA EXP10_ iobs/IOACTr iobs/Clear1
fsb/ASrf ALE0S iobs/Load1 $OpTx$$OpTx$FX_DC$47_INV$153
nDTACK_FSB_OBUF EXP11_ fsb/Ready0r cs/ODCSr
iobs/Sent EXP12_ EXP13_ fsb/Ready1r
nROMWE_OBUF ram/BACTr
PARTITION FB4_2 nAoutOE_OBUF
PARTITION FB4_4 ram/RegUrgSync nDoutOE_OBUF nDinOE_OBUF nRESout
N0 cnt/Er<1> cnt/TimerTC nVPA_FSB_OBUF
cnt/Timer<0> cnt/LTimerTC cnt/LTimer<12> RefReq
cnt/Timer<1> cnt/Timer<2> RefUrg
PARTITION FB5_1 IOL0 nROMCS_OBUF iobs/IORW1 EXP14_
nCAS_OBUF nOE_OBUF iobs/TS_FSM_FFd2 EXP15_
RA_4_OBUF iobs/DTACKEN RA_3_OBUF RA_5_OBUF
IOREQ RA_2_OBUF RA_6_OBUF EXP16_
IORW0 EXP17_
PARTITION FB6_1 iobm/ETACK nVMA_IOBout ALE0M iobm/IOS_FSM_FFd3
iobm/ES<3> iobm/ES<1> iobm/ES<0> iobm/DoutOE
nLDS_IOBout iobm/IOS_FSM_FFd2 nUDS_IOBout nAS_IOBout
iobm/ES<4> nADoutLE1_OBUF nADoutLE0_OBUF iobm/ES<2>
nDinLE_OBUF IOACT
PARTITION FB7_1 cnt/LTimer<0> RA_1_OBUF cs/nOverlay cnt/LTimer<9>
RA_7_OBUF RA_0_OBUF cnt/LTimer<8> RA_8_OBUF
A_FSB_21_IBUF$BUF0 cnt/LTimer<7> RA_9_OBUF C25MEN_OBUF
cnt/LTimer<3> C25MEN_OBUF$BUF0 cnt/LTimer<2> cnt/LTimer<1>
PARTITION FB1_1 iobm/Er
PARTITION FB1_11 cs/nOverlay iobm/ES<2> iobm/ES<0> iobm/ES<3>
iobm/ES<1> IODONE IOU0 IOL0
PARTITION FB2_15 iobm/VPAr cnt/nIPL2r IOBERR cnt/Timer<1>
PARTITION FB3_4 ram/RS_FSM_FFd4 ram/RS_FSM_FFd1 iobs/IODONEr<0> cnt/INITS_FSM_FFd1
cnt/Er<0> nDTACK_FSB_OBUF cnt/TimerTC cnt/LTimer<3>
cnt/LTimer<2> cnt/LTimer<1> cnt/INITS_FSM_FFd2 RefReq
cnt/Timer<2> nROMWE_OBUF RefUrg
PARTITION FB4_1 ram/BACTr nAoutOE_OBUF nRESout iobs/Clear1
nDoutOE_OBUF nDinOE_OBUF ram/Once C20MEN_OBUF
iobs/TS_FSM_FFd1 cs/ODCSr nVPA_FSB_OBUF IOWRREQ
iobs/Load1 iobs/IORW1 IONPReady iobs/TS_FSM_FFd2
IORDREQ iobs/Sent
PARTITION FB5_1 cnt/LTimerTC nROMCS_OBUF cnt/LTimer<9> cnt/LTimer<8>
nCAS_OBUF nOE_OBUF cnt/LTimer<7> cnt/LTimer<6>
A_FSB_11_IBUF$BUF0 cnt/LTimer<5> A_FSB_19_IBUF$BUF0 A_FSB_12_IBUF$BUF0
cnt/LTimer<4> A_FSB_16_IBUF$BUF0 A_FSB_13_IBUF$BUF0 cnt/LTimer<12>
cnt/LTimer<11> cnt/LTimer<10>
PARTITION FB8_1 EXP18_ A_FSB_19_IBUF$BUF0 ram/RAMEN ram/RAMReady
nRAS_OBUF nRAMLWE_OBUF ram/RS_FSM_FFd2 nRAMUWE_OBUF
ram/RS_FSM_FFd3 ram/RS_FSM_FFd1 cnt/INITS_FSM_FFd2 nBERR_FSB_OBUF
cnt/LTimer<4> cnt/LTimer<5> nBR_IOB_OBUF cnt/LTimer<6>
cnt/INITS_FSM_FFd1 ram/RASEL
PARTITION FB6_2 nVMA_IOBout
PARTITION FB6_5 iobs/IOACTr iobm/IOS_FSM_FFd5 iobm/IOS_FSM_FFd4 iobm/IOS_FSM_FFd1
nLDS_IOBout iobm/C8Mr nUDS_IOBout nAS_IOBout
iobm/IOS_FSM_FFd6 nADoutLE1_OBUF nADoutLE0_OBUF iobm/IOS_FSM_FFd7
nDinLE_OBUF ALE0M
PARTITION FB7_1 iobm/IOWRREQr A_FSB_10_IBUF$BUF0 iobm/IORDREQr cnt/LTimer<0>
A_FSB_14_IBUF$BUF0 A_FSB_9_IBUF$BUF0 cnt/Er<1> A_FSB_18_IBUF$BUF0
A_FSB_17_IBUF$BUF0 iobm/IOS_FSM_FFd2 A_FSB_15_IBUF$BUF0 C25MEN_OBUF
cnt/Timer<0> C20MEN_OBUF$BUF0 iobm/IOS_FSM_FFd3 iobm/DoutOE
iobm/IOS0 IOACT
PARTITION FB8_1 ram/RS_FSM_FFd3 A_FSB_19_IBUF$BUF1 ram/RS_FSM_FFd2 fsb/ASrf
nRAS_OBUF nRAMLWE_OBUF ALE0S nRAMUWE_OBUF
ram/RefDone iobs/IOU1 iobs/IOL1 nBERR_FSB_OBUF
IOPWReady ram/RS_FSM_FFd6 nBR_IOB_OBUF ram/RS_FSM_FFd8
ram/CAS ram/RAMEN

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cpld/XC95144XL/WarpSE.jed
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cpld/XC95144XL/WarpSE.mfd
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cpld/XC95144XL/WarpSE.mod Normal file
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@ -0,0 +1,170 @@
MODEL
MODEL_VERSION "v1998.8";
DESIGN "WarpSE";
/* port names and type */
INPUT S:PIN24 = A_FSB<23>;
INPUT S:PIN20 = A_FSB<22>;
INPUT S:PIN19 = A_FSB<21>;
INPUT S:PIN18 = A_FSB<20>;
INPUT S:PIN17 = A_FSB<19>;
INPUT S:PIN16 = A_FSB<18>;
INPUT S:PIN23 = C8M;
INPUT S:PIN22 = C16M;
INPUT S:PIN27 = FCLK;
INPUT S:PIN32 = nAS_FSB;
INPUT S:PIN29 = nWE_FSB;
INPUT S:PIN76 = nBERR_IOB;
INPUT S:PIN78 = nDTACK_IOB;
INPUT S:PIN30 = nLDS_FSB;
INPUT S:PIN33 = nUDS_FSB;
INPUT S:PIN25 = E;
INPUT S:PIN92 = nIPL2;
INPUT S:PIN77 = nVPA_IOB;
INPUT S:PIN8 = A_FSB<10>;
INPUT S:PIN9 = A_FSB<11>;
INPUT S:PIN10 = A_FSB<12>;
INPUT S:PIN11 = A_FSB<13>;
INPUT S:PIN12 = A_FSB<14>;
INPUT S:PIN13 = A_FSB<15>;
INPUT S:PIN14 = A_FSB<16>;
INPUT S:PIN15 = A_FSB<17>;
INPUT S:PIN7 = A_FSB<9>;
TRIOUT S:PIN91 = nRES;
TRIOUT S:PIN74 = nVMA_IOB;
TRIOUT S:PIN81 = nAS_IOB;
TRIOUT S:PIN79 = nLDS_IOB;
TRIOUT S:PIN80 = nUDS_IOB;
OUTPUT S:PIN70 = nBERR_FSB;
OUTPUT S:PIN93 = nVPA_FSB;
OUTPUT S:PIN72 = nBR_IOB;
OUTPUT S:PIN37 = nOE;
OUTPUT S:PIN34 = nROMWE;
OUTPUT S:PIN85 = nADoutLE0;
OUTPUT S:PIN36 = nCAS;
OUTPUT S:PIN28 = nDTACK_FSB;
OUTPUT S:PIN86 = nDinLE;
OUTPUT S:PIN50 = RA<1>;
OUTPUT S:PIN40 = RA<4>;
OUTPUT S:PIN42 = RA<5>;
OUTPUT S:PIN46 = RA<6>;
OUTPUT S:PIN52 = RA<7>;
OUTPUT S:PIN56 = RA<9>;
OUTPUT S:PIN43 = RA<2>;
OUTPUT S:PIN55 = RA<10>;
OUTPUT S:PIN54 = RA<8>;
OUTPUT S:PIN41 = RA<3>;
OUTPUT S:PIN63 = RA<11>;
OUTPUT S:PIN53 = RA<0>;
OUTPUT S:PIN82 = nADoutLE1;
OUTPUT S:PIN87 = nAoutOE;
OUTPUT S:PIN90 = nDinOE;
OUTPUT S:PIN89 = nDoutOE;
OUTPUT S:PIN65 = nRAMLWE;
OUTPUT S:PIN66 = nRAMUWE;
OUTPUT S:PIN64 = nRAS;
OUTPUT S:PIN35 = nROMCS;
OUTPUT S:PIN59 = C20MEN;
OUTPUT S:PIN58 = C25MEN;
/* timing arc definitions */
A_FSB<9>_RA<0>_delay: DELAY A_FSB<9> RA<0>;
A_FSB<17>_RA<10>_delay: DELAY A_FSB<17> RA<10>;
A_FSB<19>_RA<11>_delay: DELAY A_FSB<19> RA<11>;
A_FSB<10>_RA<1>_delay: DELAY A_FSB<10> RA<1>;
A_FSB<16>_RA<2>_delay: DELAY A_FSB<16> RA<2>;
A_FSB<19>_RA<3>_delay: DELAY A_FSB<19> RA<3>;
A_FSB<11>_RA<4>_delay: DELAY A_FSB<11> RA<4>;
A_FSB<12>_RA<5>_delay: DELAY A_FSB<12> RA<5>;
A_FSB<13>_RA<6>_delay: DELAY A_FSB<13> RA<6>;
A_FSB<14>_RA<7>_delay: DELAY A_FSB<14> RA<7>;
A_FSB<18>_RA<8>_delay: DELAY A_FSB<18> RA<8>;
A_FSB<15>_RA<9>_delay: DELAY A_FSB<15> RA<9>;
nAS_FSB_nDinOE_delay: DELAY nAS_FSB nDinOE;
nWE_FSB_nDinOE_delay: DELAY nWE_FSB nDinOE;
A_FSB<23>_nDinOE_delay: DELAY A_FSB<23> nDinOE;
A_FSB<22>_nDinOE_delay: DELAY A_FSB<22> nDinOE;
A_FSB<20>_nDinOE_delay: DELAY A_FSB<20> nDinOE;
A_FSB<21>_nDinOE_delay: DELAY A_FSB<21> nDinOE;
nWE_FSB_nOE_delay: DELAY nWE_FSB nOE;
nAS_FSB_nOE_delay: DELAY nAS_FSB nOE;
nWE_FSB_nRAMLWE_delay: DELAY nWE_FSB nRAMLWE;
nAS_FSB_nRAMLWE_delay: DELAY nAS_FSB nRAMLWE;
nLDS_FSB_nRAMLWE_delay: DELAY nLDS_FSB nRAMLWE;
nUDS_FSB_nRAMUWE_delay: DELAY nUDS_FSB nRAMUWE;
nWE_FSB_nRAMUWE_delay: DELAY nWE_FSB nRAMUWE;
nAS_FSB_nRAMUWE_delay: DELAY nAS_FSB nRAMUWE;
A_FSB<20>_nROMCS_delay: DELAY A_FSB<20> nROMCS;
A_FSB<22>_nROMCS_delay: DELAY A_FSB<22> nROMCS;
A_FSB<23>_nROMCS_delay: DELAY A_FSB<23> nROMCS;
A_FSB<21>_nROMCS_delay: DELAY A_FSB<21> nROMCS;
nAS_FSB_nROMWE_delay: DELAY nAS_FSB nROMWE;
nWE_FSB_nROMWE_delay: DELAY nWE_FSB nROMWE;
FCLK_nRES_delay: DELAY (ENABLE_HIGH) FCLK nRES;
FCLK_nVMA_IOB_delay: DELAY (ENABLE_HIGH) FCLK nVMA_IOB;
FCLK_nAS_IOB_delay: DELAY (ENABLE_HIGH) FCLK nAS_IOB;
FCLK_nLDS_IOB_delay: DELAY (ENABLE_HIGH) FCLK nLDS_IOB;
FCLK_nUDS_IOB_delay: DELAY (ENABLE_HIGH) FCLK nUDS_IOB;
FCLK_nBERR_FSB_delay: DELAY FCLK nBERR_FSB;
FCLK_nVPA_FSB_delay: DELAY FCLK nVPA_FSB;
FCLK_nBR_IOB_delay: DELAY FCLK nBR_IOB;
FCLK_nADoutLE0_delay: DELAY FCLK nADoutLE0;
FCLK_nCAS_delay: DELAY FCLK nCAS;
FCLK_nDTACK_FSB_delay: DELAY FCLK nDTACK_FSB;
FCLK_nADoutLE1_delay: DELAY FCLK nADoutLE1;
FCLK_nAoutOE_delay: DELAY FCLK nAoutOE;
FCLK_nDinOE_delay: DELAY FCLK nDinOE;
FCLK_nDoutOE_delay: DELAY FCLK nDoutOE;
FCLK_nRAMLWE_delay: DELAY FCLK nRAMLWE;
FCLK_nRAMUWE_delay: DELAY FCLK nRAMUWE;
FCLK_nRAS_delay: DELAY FCLK nRAS;
FCLK_nROMCS_delay: DELAY FCLK nROMCS;
C16M_nAS_IOB_delay: DELAY (ENABLE_HIGH) C16M nAS_IOB;
C16M_nLDS_IOB_delay: DELAY (ENABLE_HIGH) C16M nLDS_IOB;
C16M_nUDS_IOB_delay: DELAY (ENABLE_HIGH) C16M nUDS_IOB;
C16M_nADoutLE0_delay: DELAY C16M nADoutLE0;
C16M_nDinLE_delay: DELAY C16M nDinLE;
C16M_nDoutOE_delay: DELAY C16M nDoutOE;
C8M_nVMA_IOB_delay: DELAY (ENABLE_HIGH) C8M nVMA_IOB;
/* timing check arc definitions */
A_FSB<18>_FCLK_setup: SETUP(POSEDGE) A_FSB<18> FCLK;
A_FSB<19>_FCLK_setup: SETUP(POSEDGE) A_FSB<19> FCLK;
A_FSB<20>_FCLK_setup: SETUP(POSEDGE) A_FSB<20> FCLK;
A_FSB<21>_FCLK_setup: SETUP(POSEDGE) A_FSB<21> FCLK;
A_FSB<22>_FCLK_setup: SETUP(POSEDGE) A_FSB<22> FCLK;
A_FSB<23>_FCLK_setup: SETUP(POSEDGE) A_FSB<23> FCLK;
E_FCLK_setup: SETUP(POSEDGE) E FCLK;
nAS_FSB_FCLK_setup: SETUP(POSEDGE) nAS_FSB FCLK;
nIPL2_FCLK_setup: SETUP(POSEDGE) nIPL2 FCLK;
nLDS_FSB_FCLK_setup: SETUP(POSEDGE) nLDS_FSB FCLK;
nRES_FCLK_setup: SETUP(POSEDGE) nRES FCLK;
nUDS_FSB_FCLK_setup: SETUP(POSEDGE) nUDS_FSB FCLK;
nWE_FSB_FCLK_setup: SETUP(POSEDGE) nWE_FSB FCLK;
A_FSB<18>_FCLK_hold: HOLD(POSEDGE) A_FSB<18> FCLK;
A_FSB<19>_FCLK_hold: HOLD(POSEDGE) A_FSB<19> FCLK;
A_FSB<20>_FCLK_hold: HOLD(POSEDGE) A_FSB<20> FCLK;
A_FSB<21>_FCLK_hold: HOLD(POSEDGE) A_FSB<21> FCLK;
A_FSB<22>_FCLK_hold: HOLD(POSEDGE) A_FSB<22> FCLK;
A_FSB<23>_FCLK_hold: HOLD(POSEDGE) A_FSB<23> FCLK;
E_FCLK_hold: HOLD(POSEDGE) E FCLK;
nAS_FSB_FCLK_hold: HOLD(POSEDGE) nAS_FSB FCLK;
nIPL2_FCLK_hold: HOLD(POSEDGE) nIPL2 FCLK;
nLDS_FSB_FCLK_hold: HOLD(POSEDGE) nLDS_FSB FCLK;
nRES_FCLK_hold: HOLD(POSEDGE) nRES FCLK;
nUDS_FSB_FCLK_hold: HOLD(POSEDGE) nUDS_FSB FCLK;
nWE_FSB_FCLK_hold: HOLD(POSEDGE) nWE_FSB FCLK;
C8M_C16M_setup: SETUP(POSEDGE) C8M C16M;
C8M_C16M_hold: HOLD(POSEDGE) C8M C16M;
E_C8M_setup: SETUP(POSEDGE) E C8M;
nBERR_IOB_C8M_setup: SETUP(POSEDGE) nBERR_IOB C8M;
nDTACK_IOB_C8M_setup: SETUP(POSEDGE) nDTACK_IOB C8M;
nRES_C8M_setup: SETUP(POSEDGE) nRES C8M;
nVPA_IOB_C8M_setup: SETUP(POSEDGE) nVPA_IOB C8M;
E_C8M_hold: HOLD(POSEDGE) E C8M;
nBERR_IOB_C8M_hold: HOLD(POSEDGE) nBERR_IOB C8M;
nDTACK_IOB_C8M_hold: HOLD(POSEDGE) nDTACK_IOB C8M;
nRES_C8M_hold: HOLD(POSEDGE) nRES C8M;
nVPA_IOB_C8M_hold: HOLD(POSEDGE) nVPA_IOB C8M;
ENDMODEL

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cpld/XC95144XL/WarpSE.nga
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cpld/XC95144XL/WarpSE.ngc
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cpld/XC95144XL/WarpSE.ngd
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cpld/XC95144XL/WarpSE.ngr
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cpld/XC95144XL/WarpSE.pad
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@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
4- 1-2023 8:21AM
4- 7-2023 0:29AM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
@ -19,11 +19,11 @@ Pinout by Pin Number:
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|{blank}|Slew Rate|Termination|{blank}|Voltage|Constraint|
P1|TIE||I/O/GTS3||||||||||
P2|A_FSB<5>|I|I/O/GTS4|INPUT|||||||||
P3|A_FSB<6>|I|I/O/GTS1|INPUT|||||||||
P4|A_FSB<7>|I|I/O/GTS2|INPUT|||||||||
P2|TIE||I/O/GTS4||||||||||
P3|TIE||I/O/GTS1||||||||||
P4|TIE||I/O/GTS2||||||||||
P5|VCC||VCCINT||||||||||
P6|A_FSB<8>|I|I/O|INPUT|||||||||
P6|TIE||I/O||||||||||
P7|A_FSB<9>|I|I/O|INPUT|||||||||
P8|A_FSB<10>|I|I/O|INPUT|||||||||
P9|A_FSB<11>|I|I/O|INPUT|||||||||
@ -111,10 +111,10 @@ P90|nDinOE|O|I/O|OUTPUT|||||||||
P91|nRES|I/O|I/O|BIDIR|||||||||
P92|nIPL2|I|I/O|INPUT|||||||||
P93|nVPA_FSB|O|I/O|OUTPUT|||||||||
P94|A_FSB<1>|I|I/O|INPUT|||||||||
P95|A_FSB<2>|I|I/O|INPUT|||||||||
P96|A_FSB<3>|I|I/O|INPUT|||||||||
P97|A_FSB<4>|I|I/O|INPUT|||||||||
P94|TIE||I/O||||||||||
P95|TIE||I/O||||||||||
P96|TIE||I/O||||||||||
P97|TIE||I/O||||||||||
P98|VCC||VCCINT||||||||||
P99|TIE||I/O/GSR||||||||||
P100|GND||GND||||||||||

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cpld/XC95144XL/WarpSE.pnx
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@ -15,4 +15,4 @@
sr (SLOW|FAST|slow|fast) "SLOW"
dir (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
]>
<ibis><part arch="xc9500xl" device="XC95144XL" pkg="TQ100" spg="-10"/><pin dir="input" nm="A_FSB&lt;9&gt;" no="7"/><pin dir="input" nm="A_FSB&lt;8&gt;" no="6"/><pin dir="input" nm="A_FSB&lt;15&gt;" no="13"/><pin dir="input" nm="A_FSB&lt;14&gt;" no="12"/><pin dir="input" nm="A_FSB&lt;13&gt;" no="11"/><pin dir="input" nm="A_FSB&lt;12&gt;" no="10"/><pin dir="input" nm="A_FSB&lt;11&gt;" no="9"/><pin dir="input" nm="A_FSB&lt;10&gt;" no="8"/><pin dir="input" nm="A_FSB&lt;23&gt;" no="24"/><pin dir="input" nm="A_FSB&lt;22&gt;" no="20"/><pin dir="input" nm="A_FSB&lt;21&gt;" no="19"/><pin dir="input" nm="A_FSB&lt;20&gt;" no="18"/><pin dir="input" nm="A_FSB&lt;19&gt;" no="17"/><pin dir="input" nm="A_FSB&lt;18&gt;" no="16"/><pin dir="input" nm="A_FSB&lt;17&gt;" no="15"/><pin dir="input" nm="A_FSB&lt;16&gt;" no="14"/><pin dir="input" nm="C16M" no="22"/><pin dir="input" nm="nWE_FSB" no="29"/><pin dir="input" nm="FCLK" no="27"/><pin dir="input" nm="nAS_FSB" no="32"/><pin dir="input" nm="nLDS_FSB" no="30"/><pin dir="input" nm="nUDS_FSB" no="33"/><pin dir="input" nm="C8M" no="23"/><pin dir="input" nm="E" no="25"/><pin dir="input" nm="nIPL2" no="92"/><pin dir="input" nm="nBERR_IOB" no="76"/><pin dir="input" nm="nDTACK_IOB" no="78"/><pin dir="input" nm="nVPA_IOB" no="77"/><pin dir="input" nm="A_FSB&lt;1&gt;" no="94"/><pin dir="input" nm="A_FSB&lt;2&gt;" no="95"/><pin dir="input" nm="A_FSB&lt;3&gt;" no="96"/><pin dir="input" nm="A_FSB&lt;4&gt;" no="97"/><pin dir="input" nm="A_FSB&lt;5&gt;" no="2"/><pin dir="input" nm="A_FSB&lt;6&gt;" no="3"/><pin dir="input" nm="A_FSB&lt;7&gt;" no="4"/><pin dir="output" nm="nVMA_IOB" no="74" sr="fast"/><pin dir="output" nm="nAS_IOB" no="81" sr="fast"/><pin dir="output" nm="nLDS_IOB" no="79" sr="fast"/><pin dir="output" nm="nUDS_IOB" no="80" sr="fast"/><pin dir="output" nm="nDTACK_FSB" no="28" sr="fast"/><pin dir="output" nm="nBR_IOB" no="72" sr="fast"/><pin dir="output" nm="RA&lt;0&gt;" no="53" sr="fast"/><pin dir="output" nm="RA&lt;1&gt;" no="50" sr="fast"/><pin dir="output" nm="RA&lt;2&gt;" no="43" sr="fast"/><pin dir="output" nm="RA&lt;3&gt;" no="41" sr="fast"/><pin dir="output" nm="RA&lt;4&gt;" no="40" sr="fast"/><pin dir="output" nm="RA&lt;5&gt;" no="42" sr="fast"/><pin dir="output" nm="RA&lt;6&gt;" no="46" sr="fast"/><pin dir="output" nm="RA&lt;7&gt;" no="52" sr="fast"/><pin dir="output" nm="RA&lt;8&gt;" no="54" sr="fast"/><pin dir="output" nm="RA&lt;9&gt;" no="56" sr="fast"/><pin dir="output" nm="nBERR_FSB" no="70" sr="fast"/><pin dir="output" nm="nDoutOE" no="89" sr="fast"/><pin dir="output" nm="nOE" no="37" sr="fast"/><pin dir="output" nm="nROMWE" no="34" sr="fast"/><pin dir="output" nm="nVPA_FSB" no="93" sr="fast"/><pin dir="output" nm="nADoutLE0" no="85" sr="fast"/><pin dir="output" nm="nCAS" no="36" sr="fast"/><pin dir="output" nm="nDinLE" no="86" sr="fast"/><pin dir="output" nm="nRAS" no="64" sr="fast"/><pin dir="output" nm="RA&lt;11&gt;" no="63" sr="fast"/><pin dir="output" nm="RA&lt;10&gt;" no="55" sr="fast"/><pin dir="output" nm="nADoutLE1" no="82" sr="fast"/><pin dir="output" nm="nAoutOE" no="87" sr="fast"/><pin dir="output" nm="nDinOE" no="90" sr="fast"/><pin dir="output" nm="nRAMLWE" no="65" sr="fast"/><pin dir="output" nm="nRAMUWE" no="66" sr="fast"/><pin dir="output" nm="nROMCS" no="35" sr="fast"/><pin dir="output" nm="C25MEN" no="58" sr="fast"/><pin dir="output" nm="C20MEN" no="59" sr="fast"/><pin dir="bidir" nm="nRES" no="91" sr="fast"/></ibis>
<ibis><part arch="xc9500xl" device="XC95144XL" pkg="TQ100" spg="-10"/><pin dir="input" nm="A_FSB&lt;23&gt;" no="24"/><pin dir="input" nm="A_FSB&lt;22&gt;" no="20"/><pin dir="input" nm="A_FSB&lt;21&gt;" no="19"/><pin dir="input" nm="A_FSB&lt;20&gt;" no="18"/><pin dir="input" nm="A_FSB&lt;19&gt;" no="17"/><pin dir="input" nm="A_FSB&lt;18&gt;" no="16"/><pin dir="input" nm="C8M" no="23"/><pin dir="input" nm="C16M" no="22"/><pin dir="input" nm="FCLK" no="27"/><pin dir="input" nm="nAS_FSB" no="32"/><pin dir="input" nm="nWE_FSB" no="29"/><pin dir="input" nm="nBERR_IOB" no="76"/><pin dir="input" nm="nDTACK_IOB" no="78"/><pin dir="input" nm="nLDS_FSB" no="30"/><pin dir="input" nm="nUDS_FSB" no="33"/><pin dir="input" nm="E" no="25"/><pin dir="input" nm="nIPL2" no="92"/><pin dir="input" nm="nVPA_IOB" no="77"/><pin dir="input" nm="A_FSB&lt;10&gt;" no="8"/><pin dir="input" nm="A_FSB&lt;11&gt;" no="9"/><pin dir="input" nm="A_FSB&lt;12&gt;" no="10"/><pin dir="input" nm="A_FSB&lt;13&gt;" no="11"/><pin dir="input" nm="A_FSB&lt;14&gt;" no="12"/><pin dir="input" nm="A_FSB&lt;15&gt;" no="13"/><pin dir="input" nm="A_FSB&lt;16&gt;" no="14"/><pin dir="input" nm="A_FSB&lt;17&gt;" no="15"/><pin dir="input" nm="A_FSB&lt;9&gt;" no="7"/><pin dir="output" nm="nVMA_IOB" no="74" sr="fast"/><pin dir="output" nm="nAS_IOB" no="81" sr="fast"/><pin dir="output" nm="nLDS_IOB" no="79" sr="fast"/><pin dir="output" nm="nUDS_IOB" no="80" sr="fast"/><pin dir="output" nm="nBERR_FSB" no="70" sr="fast"/><pin dir="output" nm="nVPA_FSB" no="93" sr="fast"/><pin dir="output" nm="nBR_IOB" no="72" sr="fast"/><pin dir="output" nm="nOE" no="37" sr="fast"/><pin dir="output" nm="nROMWE" no="34" sr="fast"/><pin dir="output" nm="nADoutLE0" no="85" sr="fast"/><pin dir="output" nm="nCAS" no="36" sr="fast"/><pin dir="output" nm="nDTACK_FSB" no="28" sr="fast"/><pin dir="output" nm="nDinLE" no="86" sr="fast"/><pin dir="output" nm="RA&lt;1&gt;" no="50" sr="fast"/><pin dir="output" nm="RA&lt;4&gt;" no="40" sr="fast"/><pin dir="output" nm="RA&lt;5&gt;" no="42" sr="fast"/><pin dir="output" nm="RA&lt;6&gt;" no="46" sr="fast"/><pin dir="output" nm="RA&lt;7&gt;" no="52" sr="fast"/><pin dir="output" nm="RA&lt;9&gt;" no="56" sr="fast"/><pin dir="output" nm="RA&lt;2&gt;" no="43" sr="fast"/><pin dir="output" nm="RA&lt;10&gt;" no="55" sr="fast"/><pin dir="output" nm="RA&lt;8&gt;" no="54" sr="fast"/><pin dir="output" nm="RA&lt;3&gt;" no="41" sr="fast"/><pin dir="output" nm="RA&lt;11&gt;" no="63" sr="fast"/><pin dir="output" nm="RA&lt;0&gt;" no="53" sr="fast"/><pin dir="output" nm="nADoutLE1" no="82" sr="fast"/><pin dir="output" nm="nAoutOE" no="87" sr="fast"/><pin dir="output" nm="nDinOE" no="90" sr="fast"/><pin dir="output" nm="nDoutOE" no="89" sr="fast"/><pin dir="output" nm="nRAMLWE" no="65" sr="fast"/><pin dir="output" nm="nRAMUWE" no="66" sr="fast"/><pin dir="output" nm="nRAS" no="64" sr="fast"/><pin dir="output" nm="nROMCS" no="35" sr="fast"/><pin dir="output" nm="C20MEN" no="59" sr="fast"/><pin dir="output" nm="C25MEN" no="58" sr="fast"/><pin dir="bidir" nm="nRES" no="91" sr="fast"/></ibis>

1869
cpld/XC95144XL/WarpSE.rpt
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File diff suppressed because it is too large Load Diff

210
cpld/XC95144XL/WarpSE.syr
View File

@ -144,6 +144,8 @@ Performing bidirectional port resolution...
Synthesizing Unit <CS>.
Related source file is "../CS.v".
WARNING:Xst:647 - Input <A<17:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <VidRAMCSWR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 1-bit register for signal <nOverlay>.
Found 1-bit register for signal <ODCSr>.
Summary:
@ -156,54 +158,56 @@ Synthesizing Unit <RAM>.
Found finite state machine <FSM_0> for signal <RS>.
-----------------------------------------------------------------------
| States | 8 |
| Transitions | 21 |
| Inputs | 6 |
| Outputs | 9 |
| Transitions | 11 |
| Inputs | 3 |
| Outputs | 8 |
| Clock | CLK (rising_edge) |
| Power Up State | 000 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <nCAS>.
Found 1-bit register for signal <BACTr>.
Found 1-bit register for signal <RAMEN>.
Found 1-bit register for signal <RAMReady>.
Found 1-bit register for signal <BACTr>.
Found 1-bit register for signal <CAS>.
Found 1-bit register for signal <Once>.
Found 1-bit register for signal <RAMEN>.
Found 1-bit register for signal <RASEL>.
Found 1-bit register for signal <RASrf>.
Found 1-bit register for signal <RASrr>.
Found 1-bit register for signal <RefDone>.
Found 1-bit register for signal <RefRAS>.
Found 1-bit register for signal <RefReq>.
Found 1-bit register for signal <RefReqSync>.
Found 1-bit register for signal <RefUrg>.
Found 1-bit register for signal <RegUrgSync>.
Summary:
inferred 1 Finite State Machine(s).
inferred 10 D-type flip-flop(s).
inferred 6 D-type flip-flop(s).
Unit <RAM> synthesized.
Synthesizing Unit <IOBS>.
Related source file is "../IOBS.v".
WARNING:Xst:646 - Signal <IODONEr<1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found finite state machine <FSM_1> for signal <TS>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 10 |
| Inputs | 5 |
| Outputs | 6 |
| Outputs | 5 |
| Clock | CLK (rising_edge) |
| Power Up State | 00 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <IOREQ>.
Found 1-bit register for signal <IORW0>.
Found 1-bit register for signal <IOPWReady>.
Found 1-bit register for signal <IORDREQ>.
Found 1-bit register for signal <IOL0>.
Found 1-bit register for signal <IOWRREQ>.
Found 1-bit register for signal <IONPReady>.
Found 1-bit register for signal <IOU0>.
Found 1-bit register for signal <ALE0>.
Found 1-bit register for signal <ALE1>.
Found 1-bit register for signal <nBERR_FSB>.
Found 1-bit register for signal <Clear1>.
Found 1-bit register for signal <DTACKEN>.
Found 1-bit register for signal <IOACTr>.
Found 1-bit register for signal <IODTACKr>.
Found 2-bit register for signal <IODONEr>.
Found 1-bit register for signal <IOL1>.
Found 1-bit register for signal <IORW1>.
Found 1-bit register for signal <IOU1>.
@ -211,7 +215,7 @@ Synthesizing Unit <IOBS>.
Found 1-bit register for signal <Sent>.
Summary:
inferred 1 Finite State Machine(s).
inferred 10 D-type flip-flop(s).
inferred 9 D-type flip-flop(s).
Unit <IOBS> synthesized.
@ -219,31 +223,31 @@ Synthesizing Unit <IOBM>.
Related source file is "../IOBM.v".
Found finite state machine <FSM_2> for signal <IOS>.
-----------------------------------------------------------------------
| States | 8 |
| Transitions | 16 |
| Inputs | 7 |
| Outputs | 8 |
| States | 7 |
| Transitions | 13 |
| Inputs | 5 |
| Outputs | 7 |
| Clock | C16M (rising_edge) |
| Power Up State | 000 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <IOBERR>.
Found 1-bit register for signal <nASout>.
Found 1-bit register for signal <IOACT>.
Found 1-bit register for signal <IODONE>.
Found 1-bit register for signal <nLDS>.
Found 1-bit register for signal <nUDS>.
Found 1-bit register for signal <nDinLE>.
Found 1-bit register for signal <ALE0>.
Found 1-bit register for signal <nVMA>.
Found 1-bit register for signal <BERRrf>.
Found 1-bit register for signal <C8Mr>.
Found 1-bit register for signal <DoutOE>.
Found 1-bit register for signal <DTACKrf>.
Found 1-bit register for signal <Er>.
Found 1-bit register for signal <Er2>.
Found 5-bit up counter for signal <ES>.
Found 1-bit register for signal <ETACK>.
Found 1-bit register for signal <IOREQr>.
Found 1-bit register for signal <RESrf>.
Found 4-bit up counter for signal <ES>.
Found 1-bit register for signal <IORDREQr>.
Found 1-bit register for signal <IOS0>.
Found 1-bit register for signal <IOWRREQr>.
Found 1-bit register for signal <VPAr>.
Summary:
inferred 1 Finite State Machine(s).
@ -284,14 +288,15 @@ Unit <CNT> synthesized.
Synthesizing Unit <FSB>.
Related source file is "../FSB.v".
WARNING:Xst:647 - Input <QoSCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <QoSReady> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RAMCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RAMReady> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit register for signal <nVPA>.
Found 1-bit register for signal <nDTACK>.
Found 1-bit register for signal <ASrf>.
Found 1-bit register for signal <Ready0r>.
Found 1-bit register for signal <Ready1r>.
Found 1-bit register for signal <Ready2r>.
Found 1-bit register for signal <VPA>.
Summary:
inferred 1 D-type flip-flop(s).
inferred 3 D-type flip-flop(s).
Unit <FSB> synthesized.
@ -299,7 +304,6 @@ Synthesizing Unit <WarpSE>.
Related source file is "../WarpSE.v".
WARNING:Xst:647 - Input <SW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <nBG_IOB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <SndRAMCSWR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 1-bit tristate buffer for signal <nAS_IOB>.
Found 1-bit tristate buffer for signal <nLDS_IOB>.
Found 1-bit tristate buffer for signal <nRES>.
@ -316,11 +320,10 @@ HDL Synthesis Report
Macro Statistics
# Counters : 3
13-bit up counter : 1
4-bit up counter : 1
5-bit up counter : 1
# Registers : 57
1-bit register : 56
2-bit register : 1
4-bit up counter : 2
# Registers : 56
1-bit register : 54
2-bit register : 2
# Tristates : 5
1-bit tristate buffer : 5
@ -341,18 +344,17 @@ Optimizing FSM <cnt/INITS/FSM> on signal <INITS[1:2]> with johnson encoding.
11 | 10
-------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <iobm/IOS/FSM> on signal <IOS[1:3]> with gray encoding.
Optimizing FSM <iobm/IOS/FSM> on signal <IOS[1:7]> with one-hot encoding.
-------------------
State | Encoding
-------------------
000 | 000
001 | 001
010 | 011
011 | 010
100 | 110
101 | 111
110 | 101
111 | 100
000 | 0000001
010 | 0000010
011 | 0000100
100 | 0001000
101 | 0010000
110 | 0100000
111 | 1000000
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <iobs/TS/FSM> on signal <TS[1:2]> with johnson encoding.
@ -365,19 +367,25 @@ Optimizing FSM <iobs/TS/FSM> on signal <TS[1:2]> with johnson encoding.
01 | 10
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <ram/RS/FSM> on signal <RS[1:3]> with user encoding.
Optimizing FSM <ram/RS/FSM> on signal <RS[1:8]> with one-hot encoding.
-------------------
State | Encoding
-------------------
000 | 000
010 | 010
001 | 001
101 | 101
011 | 011
100 | 100
111 | 111
110 | 110
000 | 00000001
001 | 00000010
011 | 00000100
010 | 00001000
111 | 00010000
100 | 00100000
101 | 01000000
110 | 10000000
-------------------
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <FFd5>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <FFd7>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <RASEL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <RASrf>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2257 - FF/Latches <FFd5> is unconnected in block <FSM>.
WARNING:Xst:2257 - FF/Latches <FFd7> is unconnected in block <FSM>.
=========================================================================
Advanced HDL Synthesis Report
@ -386,16 +394,17 @@ Macro Statistics
# FSMs : 4
# Counters : 3
13-bit up counter : 1
4-bit up counter : 1
5-bit up counter : 1
# Registers : 45
Flip-Flops : 45
4-bit up counter : 2
# Registers : 42
Flip-Flops : 42
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <RAMReady> (without init value) has a constant value of 0 in block <RAM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <IODONEr_1> of sequential type is unconnected in block <IOBS>.
Optimizing unit <WarpSE> ...
@ -403,32 +412,39 @@ Optimizing unit <CS> ...
implementation constraint: INIT=r : nOverlay
Optimizing unit <RAM> ...
implementation constraint: INIT=r : RAMEN
implementation constraint: INIT=r : RAMReady
implementation constraint: INIT=s : RS_FSM_FFd8
implementation constraint: INIT=r : RASEL
implementation constraint: INIT=r : RefRAS
implementation constraint: INIT=r : CAS
implementation constraint: INIT=r : RASrr
implementation constraint: INIT=r : RS_FSM_FFd6
implementation constraint: INIT=r : RASrf
implementation constraint: INIT=r : RS_FSM_FFd7
implementation constraint: INIT=r : Once
implementation constraint: INIT=r : RAMEN
implementation constraint: INIT=r : RS_FSM_FFd1
implementation constraint: INIT=r : RS_FSM_FFd2
implementation constraint: INIT=r : RS_FSM_FFd3
Optimizing unit <IOBS> ...
implementation constraint: INIT=r : IOACTr
implementation constraint: INIT=r : IODTACKr
implementation constraint: INIT=r : TS_FSM_FFd2
implementation constraint: INIT=r : DTACKEN
implementation constraint: INIT=r : Sent
implementation constraint: INIT=r : TS_FSM_FFd1
implementation constraint: INIT=r : RS_FSM_FFd4
implementation constraint: INIT=r : RS_FSM_FFd5
Optimizing unit <FSB> ...
implementation constraint: INIT=r : ASrf
Optimizing unit <IOBS> ...
implementation constraint: INIT=r : IOACTr
implementation constraint: INIT=r : TS_FSM_FFd2
implementation constraint: INIT=r : Sent
implementation constraint: INIT=r : TS_FSM_FFd1
Optimizing unit <IOBM> ...
implementation constraint: INIT=r : IOREQr
implementation constraint: INIT=r : ETACK
implementation constraint: INIT=s : IOS_FSM_FFd7
implementation constraint: INIT=r : DoutOE
implementation constraint: INIT=r : IOS_FSM_FFd6
implementation constraint: INIT=r : IOS_FSM_FFd1
implementation constraint: INIT=r : IOS_FSM_FFd2
implementation constraint: INIT=r : IOS_FSM_FFd3
implementation constraint: INIT=r : IOS_FSM_FFd4
implementation constraint: INIT=r : IOS_FSM_FFd5
Optimizing unit <CNT> ...
implementation constraint: INIT=r : Timer_3
@ -437,6 +453,10 @@ Optimizing unit <CNT> ...
implementation constraint: INIT=r : INITS_FSM_FFd2
implementation constraint: INIT=r : Timer_2
implementation constraint: INIT=r : INITS_FSM_FFd1
WARNING:Xst:1293 - FF/Latch <RASEL> has a constant value of 0 in block <ram>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <RS_FSM_FFd7> has a constant value of 0 in block <ram>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RASrf> has a constant value of 0 in block <ram>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <RS_FSM_FFd5> has a constant value of 0 in block <ram>. This FF/Latch will be trimmed during the optimization process.
=========================================================================
* Partition Report *
@ -468,24 +488,28 @@ Design Statistics
# IOs : 75
Cell Usage :
# BELS : 578
# AND2 : 172
# AND3 : 27
# AND4 : 8
# BELS : 457
# AND2 : 129
# AND3 : 20
# AND4 : 7
# AND5 : 2
# AND6 : 3
# AND8 : 3
# GND : 7
# INV : 234
# OR2 : 95
# OR3 : 7
# AND6 : 1
# AND7 : 1
# AND8 : 1
# GND : 6
# INV : 190
# OR2 : 69
# OR3 : 10
# OR4 : 2
# VCC : 1
# XOR2 : 19
# FlipFlops/Latches : 90
# FD : 54
# FDCE : 36
# IO Buffers : 71
# IBUF : 35
# XOR2 : 18
# FlipFlops/Latches : 92
# FD : 56
# FDC : 2
# FDCE : 33
# FDP : 1
# IO Buffers : 63
# IBUF : 27
# IOBUFE : 1
# OBUF : 31
# OBUFE : 4
@ -493,13 +517,13 @@ Cell Usage :
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.01 secs
Total CPU time to Xst completion: 4.96 secs
-->
Total memory usage is 261444 kilobytes
Total memory usage is 261316 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)
Number of warnings : 22 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

983
cpld/XC95144XL/WarpSE.tim
View File

@ -0,0 +1,983 @@
Performance Summary Report
--------------------------
Design: WarpSE
Device: XC95144XL-10-TQ100
Speed File: Version 3.0
Program: Timing Report Generator: version P.20131013
Date: Fri Apr 07 00:23:44 2023
Performance Summary:
Pad to Pad (tPD) : 10.0ns (1 macrocell levels)
Pad 'nAS_FSB' to Pad 'nOE'
Clock net 'FCLK' path delays:
Clock Pad to Output Pad (tCO) : 14.5ns (2 macrocell levels)
Clock Pad 'FCLK' to Output Pad 'nRES' (GCK)
Clock to Setup (tCYC) : 11.0ns (1 macrocell levels)
Clock to Q, net 'iobs/Sent.Q' to DFF Setup(D) at 'iobs/Sent.D' (GCK)
Target FF drives output net 'iobs/Sent'
Setup to Clock at the Pad (tSU) : 7.5ns (0 macrocell levels)
Data signal 'A_FSB<23>' to DFF D input Pin at 'iobs/Sent.D'
Clock pad 'FCLK' (GCK)
Minimum Clock Period: 11.0ns
Maximum Internal Clock Speed: 90.9Mhz
(Limited by Cycle Time)
Clock net 'C16M' path delays:
Clock Pad to Output Pad (tCO) : 13.5ns (2 macrocell levels)
Clock Pad 'C16M' to Output Pad 'nADoutLE0' (GCK)
Clock to Setup (tCYC) : 11.0ns (1 macrocell levels)
Clock to Q, net 'iobm/IOS_FSM_FFd7.Q' to DFF Setup(D) at 'nLDS_IOB.D' (GCK)
Target FF drives output net 'nLDS_IOB'
Setup to Clock at the Pad (tSU) : 6.5ns (0 macrocell levels)
Data signal 'C8M' to DFF D input Pin at 'iobm/C8Mr.D'
Clock pad 'C16M' (GCK)
Minimum Clock Period: 11.0ns
Maximum Internal Clock Speed: 90.9Mhz
(Limited by Cycle Time)
Clock net 'C8M' path delays:
Clock Pad to Output Pad (tCO) : 5.8ns (1 macrocell levels)
Clock Pad 'C8M' to Output Pad 'nVMA_IOB' (GCK)
Clock to Setup (tCYC) : 11.0ns (1 macrocell levels)
Clock to Q, net 'nVMA_IOB.Q' to DFF Setup(D) at 'IODONE.D' (GCK)
Target FF drives output net 'IODONE'
Setup to Clock at the Pad (tSU) : 6.5ns (0 macrocell levels)
Data signal 'nBERR_IOB' to DFF D input Pin at 'IOBERR.D'
Clock pad 'C8M' (GCK)
Minimum Clock Period: 11.0ns
Maximum Internal Clock Speed: 90.9Mhz
(Limited by Cycle Time)
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From A A A A A A A A A A A
\ _ _ _ _ _ _ _ _ _ _ _
\ F F F F F F F F F F F
\ S S S S S S S S S S S
\ B B B B B B B B B B B
\ < < < < < < < < < < <
\ 1 1 1 1 1 1 1 1 1 1 2
\ 0 1 2 3 4 5 6 7 8 9 0
\ > > > > > > > > > > >
To \------------------------------------------------------------------
RA<0>
RA<10> 10.0
RA<11> 10.0
RA<1> 10.0
RA<2> 10.0
RA<3> 10.0
RA<4> 10.0
RA<5> 10.0
RA<6> 10.0
RA<7> 10.0
RA<8> 10.0
RA<9> 10.0
nDinOE 10.0
nOE
nRAMLWE
nRAMUWE
nROMCS 10.0
nROMWE
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From A A A A n n n n
\ _ _ _ _ A L U W
\ F F F F S D D E
\ S S S S _ S S _
\ B B B B F _ _ F
\ < < < < S F F S
\ 2 2 2 9 B S S B
\ 1 2 3 > B B
\ > > >
To \------------------------------------------------
RA<0> 10.0
RA<10>
RA<11>
RA<1>
RA<2>
RA<3>
RA<4>
RA<5>
RA<6>
RA<7>
RA<8>
RA<9>
nDinOE 10.0 10.0 10.0 10.0 10.0
nOE 10.0 10.0
nRAMLWE 10.0 10.0 10.0
nRAMUWE 10.0 10.0 10.0
nROMCS 10.0 10.0 10.0
nROMWE 10.0 10.0
--------------------------------------------------------------------------------
Clock Pad to Output Pad (tCO) (nsec)
\ From C C F
\ 1 8 C
\ 6 M L
\ M K
\
\
\
\
\
\
To \------------------
nADoutLE0 13.5 13.5
nADoutLE1 5.8
nAS_IOB 5.8 14.5
nAoutOE 5.8
nBERR_FSB 5.8
nBR_IOB 5.8
nCAS 5.8
nDTACK_FSB 5.8
nDinLE 5.8
nDinOE 13.5
nDoutOE 13.5 13.5
nLDS_IOB 5.8 14.5
nRAMLWE 13.5
nRAMUWE 13.5
nRAS 5.8
nRES 14.5
nROMCS 13.5
nUDS_IOB 5.8 14.5
nVMA_IOB 5.8 14.5
nVPA_FSB 5.8
--------------------------------------------------------------------------------
Setup to Clock at Pad (tSU or tSUF) (nsec)
\ From C C F
\ 1 8 C
\ 6 M L
\ M K
\
\
\
\
\
\
To \------------------
A_FSB<18> 7.5
A_FSB<19> 7.5
A_FSB<20> 7.5
A_FSB<21> 7.5
A_FSB<22> 7.5
A_FSB<23> 7.5
C8M 6.5
E 6.5 6.5
nAS_FSB 7.5
nBERR_IOB 6.5
nDTACK_IOB 6.5
nIPL2 6.5
nLDS_FSB 6.5
nRES 6.5 6.5
nUDS_FSB 6.5
nVPA_IOB 6.5
nWE_FSB 7.5
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: FCLK)
\ From I I I I I I R R c c
\ O O O O O O e e n n
\ L N P R U W f f t t
\ 0 P W D 0 R R U / /
\ . R R R . R e r E E
\ Q e e E Q E q g r r
\ a a Q Q . . < <
\ d d . . Q Q 0 1
\ y y Q Q > >
\ . . . .
\ Q Q Q Q
\
\
\
\
\
\
\
\
\
To \------------------------------------------------------------
ALE0S.D
IOL0.D 11.0
IONPReady.D 10.0
IOPWReady.D 10.0
IORDREQ.D 10.0
IOU0.D 11.0
IOWRREQ.D 10.0
RefReq.CE 10.0 10.0
RefReq.D 10.0
RefUrg.CE 10.0 10.0
RefUrg.D 10.0 10.0 10.0
cnt/Er<1>.D 10.0
cnt/INITS_FSM_FFd1.D 10.0 10.0
cnt/INITS_FSM_FFd2.D 10.0 10.0
cnt/LTimer<0>.CE 10.0 10.0
cnt/LTimer<10>.CE 10.0 10.0
cnt/LTimer<10>.D
cnt/LTimer<11>.CE 10.0 10.0
cnt/LTimer<11>.D
cnt/LTimer<12>.CE 10.0 10.0
cnt/LTimer<12>.D
cnt/LTimer<1>.CE 10.0 10.0
cnt/LTimer<1>.D
cnt/LTimer<2>.CE 10.0 10.0
cnt/LTimer<2>.D
cnt/LTimer<3>.CE 10.0 10.0
cnt/LTimer<3>.D
cnt/LTimer<4>.CE 10.0 10.0
cnt/LTimer<4>.D
cnt/LTimer<5>.CE 10.0 10.0
cnt/LTimer<5>.D
cnt/LTimer<6>.CE 10.0 10.0
cnt/LTimer<6>.D
cnt/LTimer<7>.CE 10.0 10.0
cnt/LTimer<7>.D
cnt/LTimer<8>.CE 10.0 10.0
cnt/LTimer<8>.D
cnt/LTimer<9>.CE 10.0 10.0
cnt/LTimer<9>.D
cnt/LTimerTC.CE 10.0 10.0
cnt/LTimerTC.D
cnt/Timer<0>.CE 10.0 10.0
cnt/Timer<0>.D 10.0 10.0
cnt/Timer<1>.CE 10.0 10.0
cnt/Timer<1>.D 10.0 10.0
cnt/Timer<2>.CE 10.0 10.0
cnt/Timer<2>.D 10.0 10.0
cnt/TimerTC.CE 10.0 10.0
cnt/TimerTC.D 10.0
cs/ODCSr.D
cs/nOverlay.D
iobs/Clear1.D
iobs/IOL1.CE
iobs/IORW1.D
iobs/IOU1.CE
iobs/Load1.D
iobs/Sent.D
iobs/TS_FSM_FFd1.D
iobs/TS_FSM_FFd2.D
nADoutLE1.D
nAoutOE.D
nBERR_FSB.D
nBR_IOB.D
nCAS.D
nDTACK_FSB.D 11.0 11.0
nRAS.D
nRESout.D
nVPA_FSB.D 10.0
ram/BACTr.D
ram/CAS.D 10.0 10.0
ram/Once.CE
ram/Once.D
ram/RAMEN.D 11.0 11.0
ram/RS_FSM_FFd1.D
ram/RS_FSM_FFd2.D
ram/RS_FSM_FFd3.D
ram/RS_FSM_FFd4.D
ram/RS_FSM_FFd6.D 10.0 10.0
ram/RS_FSM_FFd8.D 10.0 10.0
ram/RefDone.D 10.0 10.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: FCLK)
\ From c c c c c c c c c c
\ n n n n n n n n n n
\ t t t t t t t t t t
\ / / / / / / / / / /
\ I I L L L L L L L L
\ N N T T T T T T T T
\ I I i i i i i i i i
\ T T m m m m m m m m
\ S S e e e e e e e e
\ _ _ r r r r r r r r
\ F F < < < < < < < <
\ S S 0 1 1 1 1 2 3 4
\ M M > 0 1 2 > > > >
\ _ _ . > > > . . . .
\ F F Q . . . Q Q Q Q
\ F F Q Q Q
\ d d
\ 1 2
\ . .
\ Q Q
To \------------------------------------------------------------
ALE0S.D
IOL0.D
IONPReady.D
IOPWReady.D
IORDREQ.D
IOU0.D
IOWRREQ.D
RefReq.CE
RefReq.D
RefUrg.CE
RefUrg.D
cnt/Er<1>.D
cnt/INITS_FSM_FFd1.D 10.0 10.0
cnt/INITS_FSM_FFd2.D 10.0 10.0
cnt/LTimer<0>.CE
cnt/LTimer<10>.CE
cnt/LTimer<10>.D 10.0 10.0 10.0 10.0 10.0
cnt/LTimer<11>.CE
cnt/LTimer<11>.D 10.0 10.0 10.0 10.0 10.0 10.0
cnt/LTimer<12>.CE
cnt/LTimer<12>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
cnt/LTimer<1>.CE
cnt/LTimer<1>.D 10.0
cnt/LTimer<2>.CE
cnt/LTimer<2>.D 10.0 10.0
cnt/LTimer<3>.CE
cnt/LTimer<3>.D 10.0 10.0 10.0
cnt/LTimer<4>.CE
cnt/LTimer<4>.D 10.0 10.0 10.0 10.0
cnt/LTimer<5>.CE
cnt/LTimer<5>.D 10.0 10.0 10.0 10.0 10.0
cnt/LTimer<6>.CE
cnt/LTimer<6>.D 10.0 10.0 10.0 10.0 10.0
cnt/LTimer<7>.CE
cnt/LTimer<7>.D 10.0 10.0 10.0 10.0 10.0
cnt/LTimer<8>.CE
cnt/LTimer<8>.D 10.0 10.0 10.0 10.0 10.0
cnt/LTimer<9>.CE
cnt/LTimer<9>.D 10.0 10.0 10.0 10.0 10.0
cnt/LTimerTC.CE
cnt/LTimerTC.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
cnt/Timer<0>.CE
cnt/Timer<0>.D
cnt/Timer<1>.CE
cnt/Timer<1>.D
cnt/Timer<2>.CE
cnt/Timer<2>.D
cnt/TimerTC.CE
cnt/TimerTC.D
cs/ODCSr.D
cs/nOverlay.D
iobs/Clear1.D
iobs/IOL1.CE
iobs/IORW1.D
iobs/IOU1.CE
iobs/Load1.D
iobs/Sent.D
iobs/TS_FSM_FFd1.D
iobs/TS_FSM_FFd2.D
nADoutLE1.D
nAoutOE.D 10.0 10.0
nBERR_FSB.D
nBR_IOB.D 10.0 10.0
nCAS.D
nDTACK_FSB.D
nRAS.D
nRESout.D 10.0 10.0
nVPA_FSB.D
ram/BACTr.D
ram/CAS.D
ram/Once.CE
ram/Once.D
ram/RAMEN.D
ram/RS_FSM_FFd1.D
ram/RS_FSM_FFd2.D
ram/RS_FSM_FFd3.D
ram/RS_FSM_FFd4.D
ram/RS_FSM_FFd6.D
ram/RS_FSM_FFd8.D
ram/RefDone.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: FCLK)
\ From c c c c c c c c c c
\ n n n n n n n n n n
\ t t t t t t t t t t
\ / / / / / / / / / /
\ L L L L L L T T T T
\ T T T T T T i i i i
\ i i i i i i m m m m
\ m m m m m m e e e e
\ e e e e e e r r r r
\ r r r r r r < < < T
\ < < < < < T 0 1 2 C
\ 5 6 7 8 9 C > > > .
\ > > > > > . . . . Q
\ . . . . . Q Q Q Q
\ Q Q Q Q Q
\
\
\
\
\
To \------------------------------------------------------------
ALE0S.D
IOL0.D
IONPReady.D
IOPWReady.D
IORDREQ.D
IOU0.D
IOWRREQ.D
RefReq.CE
RefReq.D 10.0 10.0
RefUrg.CE
RefUrg.D 10.0 10.0 10.0 10.0
cnt/Er<1>.D
cnt/INITS_FSM_FFd1.D 10.0 10.0
cnt/INITS_FSM_FFd2.D 10.0 10.0
cnt/LTimer<0>.CE 10.0
cnt/LTimer<10>.CE 10.0
cnt/LTimer<10>.D 10.0 10.0 10.0 10.0 10.0
cnt/LTimer<11>.CE 10.0
cnt/LTimer<11>.D 10.0 10.0 10.0 10.0 10.0
cnt/LTimer<12>.CE 10.0
cnt/LTimer<12>.D 10.0 10.0 10.0 10.0 10.0
cnt/LTimer<1>.CE 10.0
cnt/LTimer<1>.D
cnt/LTimer<2>.CE 10.0
cnt/LTimer<2>.D
cnt/LTimer<3>.CE 10.0
cnt/LTimer<3>.D
cnt/LTimer<4>.CE 10.0
cnt/LTimer<4>.D
cnt/LTimer<5>.CE 10.0
cnt/LTimer<5>.D
cnt/LTimer<6>.CE 10.0
cnt/LTimer<6>.D 10.0
cnt/LTimer<7>.CE 10.0
cnt/LTimer<7>.D 10.0 10.0
cnt/LTimer<8>.CE 10.0
cnt/LTimer<8>.D 10.0 10.0 10.0
cnt/LTimer<9>.CE 10.0
cnt/LTimer<9>.D 10.0 10.0 10.0 10.0
cnt/LTimerTC.CE 10.0
cnt/LTimerTC.D 10.0 10.0 10.0 10.0 10.0
cnt/Timer<0>.CE
cnt/Timer<0>.D 10.0 10.0
cnt/Timer<1>.CE
cnt/Timer<1>.D 10.0 10.0 10.0
cnt/Timer<2>.CE
cnt/Timer<2>.D 10.0 10.0 10.0 10.0
cnt/TimerTC.CE
cnt/TimerTC.D 10.0 10.0 10.0
cs/ODCSr.D
cs/nOverlay.D
iobs/Clear1.D
iobs/IOL1.CE
iobs/IORW1.D
iobs/IOU1.CE
iobs/Load1.D
iobs/Sent.D
iobs/TS_FSM_FFd1.D
iobs/TS_FSM_FFd2.D
nADoutLE1.D
nAoutOE.D
nBERR_FSB.D
nBR_IOB.D
nCAS.D
nDTACK_FSB.D
nRAS.D
nRESout.D
nVPA_FSB.D
ram/BACTr.D
ram/CAS.D
ram/Once.CE
ram/Once.D
ram/RAMEN.D
ram/RS_FSM_FFd1.D
ram/RS_FSM_FFd2.D
ram/RS_FSM_FFd3.D
ram/RS_FSM_FFd4.D
ram/RS_FSM_FFd6.D
ram/RS_FSM_FFd8.D
ram/RefDone.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: FCLK)
\ From c c c f i i i i i i
\ n s s s o o o o o o
\ t / / b b b b b b b
\ / O n / s s s s s s
\ n D O A / / / / / /
\ I C v S C I I I I I
\ P S e r l O O O O O
\ L r r f e A D L R U
\ 2 . l . a C O 1 W 1
\ r Q a Q r T N . 1 .
\ . y 1 r E Q . Q
\ Q . . . r Q
\ Q Q Q <
\ 0
\ >
\ .
\ Q
\
\
\
To \------------------------------------------------------------
ALE0S.D
IOL0.D 11.0 11.0 11.0
IONPReady.D 11.0 10.0
IOPWReady.D 10.0 10.0
IORDREQ.D 11.0 11.0 10.0 11.0
IOU0.D 11.0 11.0 11.0
IOWRREQ.D 11.0 11.0 10.0 11.0
RefReq.CE
RefReq.D
RefUrg.CE
RefUrg.D
cnt/Er<1>.D
cnt/INITS_FSM_FFd1.D 10.0
cnt/INITS_FSM_FFd2.D
cnt/LTimer<0>.CE
cnt/LTimer<10>.CE
cnt/LTimer<10>.D
cnt/LTimer<11>.CE
cnt/LTimer<11>.D
cnt/LTimer<12>.CE
cnt/LTimer<12>.D
cnt/LTimer<1>.CE
cnt/LTimer<1>.D
cnt/LTimer<2>.CE
cnt/LTimer<2>.D
cnt/LTimer<3>.CE
cnt/LTimer<3>.D
cnt/LTimer<4>.CE
cnt/LTimer<4>.D
cnt/LTimer<5>.CE
cnt/LTimer<5>.D
cnt/LTimer<6>.CE
cnt/LTimer<6>.D
cnt/LTimer<7>.CE
cnt/LTimer<7>.D
cnt/LTimer<8>.CE
cnt/LTimer<8>.D
cnt/LTimer<9>.CE
cnt/LTimer<9>.D
cnt/LTimerTC.CE
cnt/LTimerTC.D
cnt/Timer<0>.CE
cnt/Timer<0>.D
cnt/Timer<1>.CE
cnt/Timer<1>.D
cnt/Timer<2>.CE
cnt/Timer<2>.D
cnt/TimerTC.CE
cnt/TimerTC.D
cs/ODCSr.D 10.0
cs/nOverlay.D 10.0 10.0 10.0
iobs/Clear1.D
iobs/IOL1.CE
iobs/IORW1.D 10.0 10.0
iobs/IOU1.CE
iobs/Load1.D 10.0
iobs/Sent.D 11.0 10.0
iobs/TS_FSM_FFd1.D 10.0
iobs/TS_FSM_FFd2.D 11.0 11.0 10.0
nADoutLE1.D 10.0
nAoutOE.D
nBERR_FSB.D 10.0
nBR_IOB.D 10.0
nCAS.D
nDTACK_FSB.D 10.0
nRAS.D
nRESout.D
nVPA_FSB.D 10.0
ram/BACTr.D 11.0
ram/CAS.D 10.0
ram/Once.CE 10.0
ram/Once.D 10.0
ram/RAMEN.D 11.0
ram/RS_FSM_FFd1.D
ram/RS_FSM_FFd2.D
ram/RS_FSM_FFd3.D
ram/RS_FSM_FFd4.D
ram/RS_FSM_FFd6.D 10.0
ram/RS_FSM_FFd8.D 10.0
ram/RefDone.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: FCLK)
\ From i i i i n n n n r r
\ o o o o A A B B a a
\ b b b b D o E R m m
\ s s s s o u R _ / /
\ / / / / u t R I B C
\ L S T T t O _ O A A
\ o e S S L E F B C S
\ a n _ _ E . S . T .
\ d t F F 1 Q B Q r Q
\ 1 . S S . . .
\ . Q M M Q Q Q
\ Q _ _
\ F F
\ F F
\ d d
\ 1 2
\ . .
\ Q Q
\
\
To \------------------------------------------------------------
ALE0S.D 10.0
IOL0.D 10.0 10.0 11.0 11.0
IONPReady.D 10.0
IOPWReady.D 10.0
IORDREQ.D 10.0 10.0 11.0 11.0
IOU0.D 10.0 10.0 11.0 11.0
IOWRREQ.D 10.0 10.0 11.0 11.0
RefReq.CE
RefReq.D
RefUrg.CE
RefUrg.D
cnt/Er<1>.D
cnt/INITS_FSM_FFd1.D
cnt/INITS_FSM_FFd2.D
cnt/LTimer<0>.CE
cnt/LTimer<10>.CE
cnt/LTimer<10>.D
cnt/LTimer<11>.CE
cnt/LTimer<11>.D
cnt/LTimer<12>.CE
cnt/LTimer<12>.D
cnt/LTimer<1>.CE
cnt/LTimer<1>.D
cnt/LTimer<2>.CE
cnt/LTimer<2>.D
cnt/LTimer<3>.CE
cnt/LTimer<3>.D
cnt/LTimer<4>.CE
cnt/LTimer<4>.D
cnt/LTimer<5>.CE
cnt/LTimer<5>.D
cnt/LTimer<6>.CE
cnt/LTimer<6>.D
cnt/LTimer<7>.CE
cnt/LTimer<7>.D
cnt/LTimer<8>.CE
cnt/LTimer<8>.D
cnt/LTimer<9>.CE
cnt/LTimer<9>.D
cnt/LTimerTC.CE
cnt/LTimerTC.D
cnt/Timer<0>.CE
cnt/Timer<0>.D
cnt/Timer<1>.CE
cnt/Timer<1>.D
cnt/Timer<2>.CE
cnt/Timer<2>.D
cnt/TimerTC.CE
cnt/TimerTC.D
cs/ODCSr.D
cs/nOverlay.D
iobs/Clear1.D 10.0 10.0
iobs/IOL1.CE 10.0
iobs/IORW1.D 10.0 10.0 10.0 10.0
iobs/IOU1.CE 10.0
iobs/Load1.D 10.0 10.0 10.0 10.0
iobs/Sent.D 11.0 11.0 11.0 10.0
iobs/TS_FSM_FFd1.D 10.0 10.0
iobs/TS_FSM_FFd2.D 10.0 10.0 11.0 11.0
nADoutLE1.D 10.0 10.0
nAoutOE.D 10.0 10.0
nBERR_FSB.D 10.0 10.0
nBR_IOB.D 10.0
nCAS.D 10.0
nDTACK_FSB.D
nRAS.D
nRESout.D
nVPA_FSB.D
ram/BACTr.D
ram/CAS.D 10.0
ram/Once.CE
ram/Once.D
ram/RAMEN.D 11.0
ram/RS_FSM_FFd1.D
ram/RS_FSM_FFd2.D
ram/RS_FSM_FFd3.D
ram/RS_FSM_FFd4.D
ram/RS_FSM_FFd6.D 10.0
ram/RS_FSM_FFd8.D 10.0
ram/RefDone.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: FCLK)
\ From r r r r r r r r r
\ a a a a a a a a a
\ m m m m m m m m m
\ / / / / / / / / /
\ O R R R R R R R R
\ n A S S S S S S e
\ c M _ _ _ _ _ _ f
\ e E F F F F F F D
\ . N S S S S S S o
\ Q . M M M M M M n
\ Q _ _ _ _ _ _ e
\ F F F F F F .
\ F F F F F F Q
\ d d d d d d
\ 1 2 3 4 6 8
\ . . . . . .
\ Q Q Q Q Q Q
\
\
\
To \------------------------------------------------------
ALE0S.D
IOL0.D
IONPReady.D
IOPWReady.D
IORDREQ.D
IOU0.D
IOWRREQ.D
RefReq.CE
RefReq.D
RefUrg.CE
RefUrg.D
cnt/Er<1>.D
cnt/INITS_FSM_FFd1.D
cnt/INITS_FSM_FFd2.D
cnt/LTimer<0>.CE
cnt/LTimer<10>.CE
cnt/LTimer<10>.D
cnt/LTimer<11>.CE
cnt/LTimer<11>.D
cnt/LTimer<12>.CE
cnt/LTimer<12>.D
cnt/LTimer<1>.CE
cnt/LTimer<1>.D
cnt/LTimer<2>.CE
cnt/LTimer<2>.D
cnt/LTimer<3>.CE
cnt/LTimer<3>.D
cnt/LTimer<4>.CE
cnt/LTimer<4>.D
cnt/LTimer<5>.CE
cnt/LTimer<5>.D
cnt/LTimer<6>.CE
cnt/LTimer<6>.D
cnt/LTimer<7>.CE
cnt/LTimer<7>.D
cnt/LTimer<8>.CE
cnt/LTimer<8>.D
cnt/LTimer<9>.CE
cnt/LTimer<9>.D
cnt/LTimerTC.CE
cnt/LTimerTC.D
cnt/Timer<0>.CE
cnt/Timer<0>.D
cnt/Timer<1>.CE
cnt/Timer<1>.D
cnt/Timer<2>.CE
cnt/Timer<2>.D
cnt/TimerTC.CE
cnt/TimerTC.D
cs/ODCSr.D
cs/nOverlay.D
iobs/Clear1.D
iobs/IOL1.CE
iobs/IORW1.D
iobs/IOU1.CE
iobs/Load1.D
iobs/Sent.D
iobs/TS_FSM_FFd1.D
iobs/TS_FSM_FFd2.D
nADoutLE1.D
nAoutOE.D
nBERR_FSB.D
nBR_IOB.D
nCAS.D
nDTACK_FSB.D
nRAS.D 10.0 10.0
nRESout.D
nVPA_FSB.D
ram/BACTr.D
ram/CAS.D 10.0 10.0 10.0 10.0
ram/Once.CE
ram/Once.D
ram/RAMEN.D 10.0 10.0 10.0 11.0 11.0
ram/RS_FSM_FFd1.D 10.0
ram/RS_FSM_FFd2.D 10.0
ram/RS_FSM_FFd3.D 10.0
ram/RS_FSM_FFd4.D 10.0
ram/RS_FSM_FFd6.D 10.0 10.0 10.0
ram/RS_FSM_FFd8.D 10.0 10.0 10.0 10.0
ram/RefDone.D 10.0 10.0 10.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C16M)
\ From A I i i i i i i i i
\ L O o o o o o o o o
\ E A b b b b b b b b
\ 0 C m m m m m m m m
\ M T / / / / / / / /
\ . . C D I I I I I I
\ Q Q 8 o O O O O O O
\ M u R S S S S S
\ r t D 0 _ _ _ _
\ . O R . F F F F
\ Q E E Q S S S S
\ . Q M M M M
\ Q r _ _ _ _
\ . F F F F
\ Q F F F F
\ d d d d
\ 1 2 3 4
\ . . . .
\ Q Q Q Q
To \------------------------------------------------------------
ALE0M.D 10.0 10.0 10.0 10.0 10.0 10.0
IOACT.D 11.0 10.0 10.0 11.0 11.0 11.0 10.0
iobm/DoutOE.D 10.0 10.0 10.0 10.0
iobm/IOS0.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
iobm/IOS_FSM_FFd1.D 10.0
iobm/IOS_FSM_FFd2.D 10.0 10.0
iobm/IOS_FSM_FFd3.D 10.0 10.0 10.0
iobm/IOS_FSM_FFd4.D
iobm/IOS_FSM_FFd5.D
iobm/IOS_FSM_FFd6.D 10.0 10.0
iobm/IOS_FSM_FFd7.D 10.0 10.0 10.0
nAS_IOB.D 10.0 10.0 10.0 10.0
nDinLE.D 10.0 10.0
nLDS_IOB.D 11.0 11.0 10.0 10.0
nUDS_IOB.D 11.0 11.0 10.0 10.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C16M)
\ From i i i i n n
\ o o o o L U
\ b b b b D D
\ m m m m S S
\ / / / / _ _
\ I I I I I I
\ O O O O O O
\ S S S W B B
\ _ _ _ R . .
\ F F F R Q Q
\ S S S E
\ M M M Q
\ _ _ _ r
\ F F F .
\ F F F Q
\ d d d
\ 5 6 7
\ . . .
\ Q Q Q
To \------------------------------------
ALE0M.D 10.0 10.0 10.0 10.0
IOACT.D 10.0 10.0 11.0 11.0
iobm/DoutOE.D 10.0 10.0 10.0 10.0
iobm/IOS0.D 10.0 10.0 10.0 10.0
iobm/IOS_FSM_FFd1.D
iobm/IOS_FSM_FFd2.D
iobm/IOS_FSM_FFd3.D
iobm/IOS_FSM_FFd4.D 10.0
iobm/IOS_FSM_FFd5.D 10.0
iobm/IOS_FSM_FFd6.D 10.0 10.0
iobm/IOS_FSM_FFd7.D 10.0 10.0
nAS_IOB.D 10.0 10.0 10.0 10.0
nDinLE.D
nLDS_IOB.D 10.0 10.0 11.0 10.0
nUDS_IOB.D 10.0 10.0 11.0 10.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C8M)
\ From i i i i i i n
\ o o o o o o V
\ b b b b b b M
\ m m m m m m A
\ / / / / / / _
\ E E E E E V I
\ S S S S r P O
\ < < < < . A B
\ 0 1 2 3 Q r .
\ > > > > . Q
\ . . . . Q
\ Q Q Q Q
To \------------------------------------------
IODONE.D 11.0 11.0 11.0 11.0 11.0
iobm/ES<0>.D 10.0 10.0 10.0 10.0 10.0
iobm/ES<1>.D 10.0 10.0 10.0 10.0 10.0
iobm/ES<2>.D 10.0 10.0 10.0 10.0
iobm/ES<3>.D 10.0 10.0 10.0 10.0 10.0
nVMA_IOB.D 10.0 10.0 10.0 10.0 10.0 10.0
Path Type Definition:
Pad to Pad (tPD) - Reports pad to pad paths that start
at input pads and end at output pads.
Paths are not traced through
registers.
Clock Pad to Output Pad (tCO) - Reports paths that start at input
pads trace through clock inputs of
registers and end at output pads.
Paths are not traced through PRE/CLR
inputs of registers.
Setup to Clock at Pad (tSU or tSUF) - Reports external setup time of data
to clock at pad. Data path starts at
an input pad and ends at register
(Fast Input Register for tSUF) D/T
input. Clock path starts at input pad
and ends at the register clock input.
Paths are not traced through
registers. Pin-to-pin setup
requirement is not reported or
guaranteed for product-term clocks
derived from macrocell feedback
signals.
Clock to Setup (tCYC) - Register to register cycle time.
Include source register tCO and
destination register tSU. Note that
when the computed Maximum Clock Speed
is limited by tCYC it is computed
assuming that all registers are
rising-edge sensitive.

10712
cpld/XC95144XL/WarpSE.vm6
View File

File diff suppressed because it is too large Load Diff

2
cpld/XC95144XL/WarpSE.xml
View File

File diff suppressed because one or more lines are too long

44
cpld/XC95144XL/WarpSE_ngdbuild.xrpt
View File

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Sat Apr 01 08:21:33 2023">
<application stringID="NgdBuild" timeStamp="Fri Apr 07 00:28:58 2023">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -66,34 +66,38 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="172"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="27"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="129"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="20"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="54"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="36"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="234"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="56"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="27"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="190"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="31"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="95"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="69"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="19"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="18"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="172"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="27"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="129"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="20"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="61"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="65"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="40"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="234"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="190"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="31"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="95"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="69"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="19"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="18"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>

18
cpld/XC95144XL/WarpSE_pad.csv
View File

@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
4- 1-2023 8:21AM
4- 7-2023 0:29AM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The comma ','
@ -19,11 +19,11 @@ Pinout by Pin Number:
-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,{blank},Slew Rate,Termination,{blank},Voltage,Constraint,
P1,TIE,,I/O/GTS3,,,,,,,,,,
P2,A_FSB<5>,I,I/O/GTS4,INPUT,,,,,,,,,
P3,A_FSB<6>,I,I/O/GTS1,INPUT,,,,,,,,,
P4,A_FSB<7>,I,I/O/GTS2,INPUT,,,,,,,,,
P2,TIE,,I/O/GTS4,,,,,,,,,,
P3,TIE,,I/O/GTS1,,,,,,,,,,
P4,TIE,,I/O/GTS2,,,,,,,,,,
P5,VCC,,VCCINT,,,,,,,,,,
P6,A_FSB<8>,I,I/O,INPUT,,,,,,,,,
P6,TIE,,I/O,,,,,,,,,,
P7,A_FSB<9>,I,I/O,INPUT,,,,,,,,,
P8,A_FSB<10>,I,I/O,INPUT,,,,,,,,,
P9,A_FSB<11>,I,I/O,INPUT,,,,,,,,,
@ -111,10 +111,10 @@ P90,nDinOE,O,I/O,OUTPUT,,,,,,,,,
P91,nRES,I/O,I/O,BIDIR,,,,,,,,,
P92,nIPL2,I,I/O,INPUT,,,,,,,,,
P93,nVPA_FSB,O,I/O,OUTPUT,,,,,,,,,
P94,A_FSB<1>,I,I/O,INPUT,,,,,,,,,
P95,A_FSB<2>,I,I/O,INPUT,,,,,,,,,
P96,A_FSB<3>,I,I/O,INPUT,,,,,,,,,
P97,A_FSB<4>,I,I/O,INPUT,,,,,,,,,
P94,TIE,,I/O,,,,,,,,,,
P95,TIE,,I/O,,,,,,,,,,
P96,TIE,,I/O,,,,,,,,,,
P97,TIE,,I/O,,,,,,,,,,
P98,VCC,,VCCINT,,,,,,,,,,
P99,TIE,,I/O/GSR,,,,,,,,,,
P100,GND,,GND,,,,,,,,,,

1 Release 8.1i - Fit P.20131013
2 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3 4- 1-2023 8:21AM 4- 7-2023 0:29AM
4 NOTE: This file is designed to be imported into a spreadsheet program
5 such as Microsoft Excel for viewing, printing and sorting. The comma ','
6 character is used as the data field separator.
7 This file is also designed to support parsing.
19 P4,A_FSB<7>,I,I/O/GTS2,INPUT,,,,,,,,, P4,TIE,,I/O/GTS2,,,,,,,,,,
20 P5,VCC,,VCCINT,,,,,,,,,,
21 P6,A_FSB<8>,I,I/O,INPUT,,,,,,,,, P6,TIE,,I/O,,,,,,,,,,
22 P7,A_FSB<9>,I,I/O,INPUT,,,,,,,,,
23 P8,A_FSB<10>,I,I/O,INPUT,,,,,,,,,
24 P9,A_FSB<11>,I,I/O,INPUT,,,,,,,,,
25 P10,A_FSB<12>,I,I/O,INPUT,,,,,,,,,
26 P11,A_FSB<13>,I,I/O,INPUT,,,,,,,,,
27 P12,A_FSB<14>,I,I/O,INPUT,,,,,,,,,
28 P13,A_FSB<15>,I,I/O,INPUT,,,,,,,,,
29 P14,A_FSB<16>,I,I/O,INPUT,,,,,,,,,
111 P96,A_FSB<3>,I,I/O,INPUT,,,,,,,,, P96,TIE,,I/O,,,,,,,,,,
112 P97,A_FSB<4>,I,I/O,INPUT,,,,,,,,, P97,TIE,,I/O,,,,,,,,,,
113 P98,VCC,,VCCINT,,,,,,,,,,
114 P99,TIE,,I/O/GSR,,,,,,,,,,
115 P100,GND,,GND,,,,,,,,,,
116 To preserve the pinout above for future design iterations in
117 Project Navigator simply execute the (Lock Pins) process
118 located under the (Implement Design) process in a toolbox named
119 (Optional Implementation Tools) or invoke PIN2UCF from the
120 command line. The location constraints will be written into your

12
cpld/XC95144XL/WarpSE_summary.html
View File

@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (04/01/2023 - 08:21:58)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (04/02/2023 - 23:02:28)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>WarpSE.xise</TD>
@ -25,7 +25,7 @@ No Errors</TD>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/*.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/*.xmsgs?&DataKey=Warning'>22 Warnings (0 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
@ -65,9 +65,9 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Apr 1 08:21:27 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Apr 1 08:21:33 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sat Apr 1 08:21:50 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>5 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Apr 7 00:28:53 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>22 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Apr 7 00:28:58 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Fri Apr 7 00:29:10 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>13 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
@ -77,5 +77,5 @@ System Settings</A>
</TABLE>
<br><center><b>Date Generated:</b> 04/01/2023 - 08:21:58</center>
<br><center><b>Date Generated:</b> 04/07/2023 - 00:31:39</center>
</BODY></HTML>

46
cpld/XC95144XL/WarpSE_xst.xrpt
View File

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sat Apr 01 08:21:22 2023">
<application stringID="Xst" timeStamp="Fri Apr 07 00:28:48 2023">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -76,11 +76,11 @@
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_COUNTERS" value="3">
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="57">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="56"/>
<item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_REGISTERS" value="56">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="54"/>
<item dataType="int" stringID="XST_2BIT_REGISTER" value="2"/>
</item>
<item dataType="int" stringID="XST_TRISTATES" value="5">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="5"/>
@ -89,10 +89,10 @@
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_FSMS" value="4"/>
<item dataType="int" stringID="XST_COUNTERS" value="3">
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="45">
<item dataType="int" stringID="XST_FLIPFLOPS" value="45"/>
<item dataType="int" stringID="XST_REGISTERS" value="42">
<item dataType="int" stringID="XST_FLIPFLOPS" value="42"/>
</item>
</section>
<section stringID="XST_PARTITION_REPORT">
@ -112,29 +112,31 @@
<item stringID="XST_IOS" value="75"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="578">
<item dataType="int" stringID="XST_AND2" value="172"/>
<item dataType="int" stringID="XST_AND3" value="27"/>
<item dataType="int" stringID="XST_AND4" value="8"/>
<item dataType="int" stringID="XST_GND" value="7"/>
<item dataType="int" stringID="XST_INV" value="234"/>
<item dataType="int" stringID="XST_OR2" value="95"/>
<item dataType="int" stringID="XST_BELS" value="457">
<item dataType="int" stringID="XST_AND2" value="129"/>
<item dataType="int" stringID="XST_AND3" value="20"/>
<item dataType="int" stringID="XST_AND4" value="7"/>
<item dataType="int" stringID="XST_GND" value="6"/>
<item dataType="int" stringID="XST_INV" value="190"/>
<item dataType="int" stringID="XST_OR2" value="69"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XOR2" value="19"/>
<item dataType="int" stringID="XST_XOR2" value="18"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="90">
<item dataType="int" stringID="XST_FD" value="54"/>
<item dataType="int" stringID="XST_FDCE" value="36"/>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="92">
<item dataType="int" stringID="XST_FD" value="56"/>
<item dataType="int" stringID="XST_FDC" value="2"/>
<item dataType="int" stringID="XST_FDCE" value="33"/>
<item dataType="int" stringID="XST_FDP" value="1"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="71">
<item dataType="int" stringID="XST_IBUF" value="35"/>
<item dataType="int" stringID="XST_IO_BUFFERS" value="63">
<item dataType="int" stringID="XST_IBUF" value="27"/>
<item dataType="int" stringID="XST_OBUF" value="31"/>
</item>
</section>
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="4"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="22"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
</section>
</application>

2
cpld/XC95144XL/_ngo/netlist.lst
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@ -1,2 +1,2 @@
C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\WarpSE.ngc 1680351687
C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\WarpSE.ngc 1680841732
OK

24
cpld/XC95144XL/_xmsgs/cpldfit.xmsgs
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@ -17,6 +17,30 @@
<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal &apos;<arg fmt="%s" index="1">FCLK</arg>&apos; based upon the LOC constraint &apos;<arg fmt="%s" index="2">P27</arg>&apos;. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
</msg>
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">A_FSB&lt;1&gt;</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">A_FSB&lt;2&gt;</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">A_FSB&lt;3&gt;</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">A_FSB&lt;4&gt;</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">A_FSB&lt;5&gt;</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">A_FSB&lt;6&gt;</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">A_FSB&lt;7&gt;</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">A_FSB&lt;8&gt;</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">SW&lt;1&gt;</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>

58
cpld/XC95144XL/_xmsgs/xst.xmsgs
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@ -5,7 +5,28 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompilers" num="259" delta="old" ><arg fmt="%s" index="1">&quot;../WarpSE.v&quot; line 141 </arg>Connection to input port &apos;<arg fmt="%s" index="2">Ready2</arg>&apos; does not match port size
<msg type="warning" file="HDLCompilers" num="259" delta="old" ><arg fmt="%s" index="1">&quot;../WarpSE.v&quot; line 150 </arg>Connection to input port &apos;<arg fmt="%s" index="2">QoSReady</arg>&apos; does not match port size
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">A&lt;17:8&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">VidRAMCSWR</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">IODONEr&lt;1&gt;</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">QoSCS</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">QoSReady</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RAMCS</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RAMReady</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">SW</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
@ -14,7 +35,40 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">nBG_IOB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">SndRAMCSWR</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">FFd5</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">FFd7</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">RASEL</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">RASrf</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="2257" delta="old" ><arg fmt="%s" index="1">FF/Latches</arg> &lt;<arg fmt="%s" index="2">FFd5</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="3">FSM</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2257" delta="old" ><arg fmt="%s" index="1">FF/Latches</arg> &lt;<arg fmt="%s" index="2">FFd7</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="3">FSM</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">RAMReady</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">RAM</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">IODONEr_1</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">IOBS</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">RASEL</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">ram</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">RS_FSM_FFd7</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">ram</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">RASrf</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">ram</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">RS_FSM_FFd5</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">ram</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
</messages>

4
cpld/XC95144XL/iseconfig/WarpSE.xreport
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@ -1,9 +1,9 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2023-04-01T07:54:43</DateModified>
<DateModified>2023-04-07T00:31:41</DateModified>
<ModuleName>WarpSE</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SummaryTimeStamp>2023-04-02T23:02:28</SummaryTimeStamp>
<SavedFilePath>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\</ImplementationReportsDirectory>
<DateInitialized>2023-03-26T03:17:53</DateInitialized>

4
cpld/XC95144XL/webtalk_pn.xml
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@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat Apr 01 08:21:22 2023">
<application name="pn" timeStamp="Fri Apr 07 00:28:47 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="17F4E7DEC0A14EDB82C58FCA99308E56" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
@ -12,7 +12,6 @@ This means code written to parse this file will need to be revisited each subseq
</section>
<section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
@ -21,7 +20,6 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2023-03-26T03:17:42" type="design"/>
<property name="PROP_intWbtProjectID" value="17F4E7DEC0A14EDB82C58FCA99308E56" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>

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cpld/XC95144XL/xst/work/hdllib.ref
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@ -1,7 +1,7 @@
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1680351683
MO CS NULL ../CS.v vlg22/_c_s.bin 1680351683
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1680351683
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1680351683
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1680351683
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1680351683
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1680351683
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1680841728
MO CS NULL ../CS.v vlg22/_c_s.bin 1680841728
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1680841728
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1680841728
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1680841728
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1680841728
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1680841728

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