mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-24 06:33:32 +00:00
final version?
This commit is contained in:
Zane Kaminski
parent
aa30aa8a55
commit
8631b52104
@ -760,7 +760,7 @@
|
||||
(property "Reference" "R12" (at 181.61 82.55 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Value" "47" (at 181.61 85.09 0)
|
||||
(property "Value" "DNP" (at 181.61 85.09 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Footprint" "stdpads:R_0603" (at 180.34 83.82 0)
|
||||
@ -769,9 +769,6 @@
|
||||
(property "Datasheet" "~" (at 180.34 83.82 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "LCSC Part" "C23182" (at 180.34 83.82 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 5bbb8993-4e6a-4e14-a5ee-022b9c51492e))
|
||||
(pin "2" (uuid e5a1d3af-4f0b-4d33-8d30-bf829f96aed1))
|
||||
(instances
|
||||
|
||||
124
ClkBuf.kicad_sch
124
ClkBuf.kicad_sch
@ -231,32 +231,32 @@
|
||||
)
|
||||
)
|
||||
|
||||
(junction (at 113.03 135.89) (diameter 0) (color 0 0 0 0)
|
||||
(junction (at 113.03 133.35) (diameter 0) (color 0 0 0 0)
|
||||
(uuid 00f39b0e-0aed-4b24-a2e2-a9c9b824f8cd)
|
||||
)
|
||||
(junction (at 133.35 140.97) (diameter 0) (color 0 0 0 0)
|
||||
(junction (at 133.35 138.43) (diameter 0) (color 0 0 0 0)
|
||||
(uuid 9a68c344-66a2-4175-abc0-6bf94315e5ea)
|
||||
)
|
||||
(junction (at 123.19 135.89) (diameter 0) (color 0 0 0 0)
|
||||
(junction (at 123.19 133.35) (diameter 0) (color 0 0 0 0)
|
||||
(uuid c756a70c-92e7-4fb8-9b0b-ed747e568d90)
|
||||
)
|
||||
(junction (at 123.19 140.97) (diameter 0) (color 0 0 0 0)
|
||||
(junction (at 123.19 138.43) (diameter 0) (color 0 0 0 0)
|
||||
(uuid ffca5546-1aae-44a7-a6f2-9e7ac0755ad3)
|
||||
)
|
||||
|
||||
(no_connect (at 123.19 116.84) (uuid 11c9a459-ad10-4d8f-b220-908a3f5c128a))
|
||||
(no_connect (at 123.19 114.3) (uuid 11c9a459-ad10-4d8f-b220-908a3f5c128a))
|
||||
(no_connect (at 123.19 83.82) (uuid c92a2db0-cfdc-422f-adfe-b1ccf9cc9613))
|
||||
(no_connect (at 123.19 99.06) (uuid dd35394c-7b65-4e8a-9463-294dcc3a1583))
|
||||
|
||||
(wire (pts (xy 123.19 135.89) (xy 133.35 135.89))
|
||||
(wire (pts (xy 123.19 133.35) (xy 133.35 133.35))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 131caff9-fc69-41eb-81d9-de7b3376f4e3)
|
||||
)
|
||||
(wire (pts (xy 143.51 121.92) (xy 142.24 121.92))
|
||||
(wire (pts (xy 143.51 119.38) (xy 142.24 119.38))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 20d398fe-73aa-43d3-8ca2-985ab624712c)
|
||||
)
|
||||
(wire (pts (xy 123.19 140.97) (xy 133.35 140.97))
|
||||
(wire (pts (xy 123.19 138.43) (xy 133.35 138.43))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 43633c9c-12f6-4a10-b038-b4ae0b8507d3)
|
||||
)
|
||||
@ -268,15 +268,15 @@
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 4e70bcb1-1c99-42f8-9bcb-691ed0c0e257)
|
||||
)
|
||||
(wire (pts (xy 113.03 140.97) (xy 123.19 140.97))
|
||||
(wire (pts (xy 113.03 138.43) (xy 123.19 138.43))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 51440c5c-2d59-4abd-a099-98d28226c02b)
|
||||
)
|
||||
(wire (pts (xy 149.86 121.92) (xy 148.59 121.92))
|
||||
(wire (pts (xy 149.86 119.38) (xy 148.59 119.38))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 86719e92-6039-4290-a257-62e8ec159e7d)
|
||||
)
|
||||
(wire (pts (xy 113.03 135.89) (xy 123.19 135.89))
|
||||
(wire (pts (xy 113.03 133.35) (xy 123.19 133.35))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid bf2ba4bb-7ac2-40cf-8ee8-f02432bc04a9)
|
||||
)
|
||||
@ -293,11 +293,11 @@
|
||||
(effects (font (size 1.27 1.27)) (justify left))
|
||||
(uuid 03d9488b-7216-44d9-92d3-60b15a49cb60)
|
||||
)
|
||||
(hierarchical_label "BC16M" (shape output) (at 149.86 121.92 0) (fields_autoplaced)
|
||||
(hierarchical_label "BC16M" (shape output) (at 149.86 119.38 0) (fields_autoplaced)
|
||||
(effects (font (size 1.27 1.27)) (justify left))
|
||||
(uuid 1d5aea67-2a78-47d6-8e05-9c1977ced792)
|
||||
)
|
||||
(hierarchical_label "C16M" (shape input) (at 121.92 119.38 180) (fields_autoplaced)
|
||||
(hierarchical_label "C16M" (shape input) (at 121.92 116.84 180) (fields_autoplaced)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
(uuid 30d2aca3-d3a7-45ec-98c3-490c92e6c6bc)
|
||||
)
|
||||
@ -314,22 +314,22 @@
|
||||
(uuid c9d52ffd-d66f-41e6-9cc7-3bb354eea84c)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:C_Small") (at 113.03 138.43 0) (unit 1)
|
||||
(symbol (lib_id "Device:C_Small") (at 113.03 135.89 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 162509bc-62f6-43aa-9778-dcb0500e3a76)
|
||||
(property "Reference" "C26" (at 114.3 137.16 0)
|
||||
(property "Reference" "C26" (at 114.3 134.62 0)
|
||||
(effects (font (size 1.27 1.27)) (justify left))
|
||||
)
|
||||
(property "Value" "2u2" (at 114.3 139.7 0)
|
||||
(property "Value" "2u2" (at 114.3 137.16 0)
|
||||
(effects (font (size 1.27 1.27)) (justify left))
|
||||
)
|
||||
(property "Footprint" "stdpads:C_0603" (at 113.03 138.43 0)
|
||||
(property "Footprint" "stdpads:C_0603" (at 113.03 135.89 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "~" (at 113.03 138.43 0)
|
||||
(property "Datasheet" "~" (at 113.03 135.89 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "LCSC Part" "C23630" (at 113.03 138.43 0)
|
||||
(property "LCSC Part" "C23630" (at 113.03 135.89 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 35235e5c-be54-4016-b691-b1c31abd106c))
|
||||
@ -410,19 +410,19 @@
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "power:GND") (at 121.92 121.92 0) (unit 1)
|
||||
(symbol (lib_id "power:GND") (at 121.92 119.38 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 57ccc073-6454-4be7-b99e-2e52a3079b38)
|
||||
(property "Reference" "#PWR02" (at 121.92 128.27 0)
|
||||
(property "Reference" "#PWR02" (at 121.92 125.73 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Value" "GND" (at 121.92 125.73 0)
|
||||
(property "Value" "GND" (at 121.92 123.19 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (at 121.92 121.92 0)
|
||||
(property "Footprint" "" (at 121.92 119.38 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 121.92 121.92 0)
|
||||
(property "Datasheet" "" (at 121.92 119.38 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 9e0996dd-9786-4e6e-86fb-95736c1a4117))
|
||||
@ -460,22 +460,22 @@
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:C_Small") (at 133.35 138.43 0) (unit 1)
|
||||
(symbol (lib_id "Device:C_Small") (at 133.35 135.89 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 6445de36-399d-4395-a340-6144ff8e4de7)
|
||||
(property "Reference" "C28" (at 134.62 137.16 0)
|
||||
(property "Reference" "C28" (at 134.62 134.62 0)
|
||||
(effects (font (size 1.27 1.27)) (justify left))
|
||||
)
|
||||
(property "Value" "2u2" (at 134.62 139.7 0)
|
||||
(property "Value" "2u2" (at 134.62 137.16 0)
|
||||
(effects (font (size 1.27 1.27)) (justify left))
|
||||
)
|
||||
(property "Footprint" "stdpads:C_0603" (at 133.35 138.43 0)
|
||||
(property "Footprint" "stdpads:C_0603" (at 133.35 135.89 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "~" (at 133.35 138.43 0)
|
||||
(property "Datasheet" "~" (at 133.35 135.89 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "LCSC Part" "C23630" (at 133.35 138.43 0)
|
||||
(property "LCSC Part" "C23630" (at 133.35 135.89 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 640c16e5-872a-44be-bd5c-44a0677fc6de))
|
||||
@ -492,19 +492,19 @@
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "power:GND") (at 133.35 140.97 0) (mirror y) (unit 1)
|
||||
(symbol (lib_id "power:GND") (at 133.35 138.43 0) (mirror y) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 6fc26917-0234-48cd-9c6d-d98338822069)
|
||||
(property "Reference" "#PWR0159" (at 133.35 147.32 0)
|
||||
(property "Reference" "#PWR0159" (at 133.35 144.78 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Value" "GND" (at 133.35 144.78 0)
|
||||
(property "Value" "GND" (at 133.35 142.24 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (at 133.35 140.97 0)
|
||||
(property "Footprint" "" (at 133.35 138.43 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 133.35 140.97 0)
|
||||
(property "Datasheet" "" (at 133.35 138.43 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 94d51cc1-7d13-4b87-b5e5-37484853de53))
|
||||
@ -555,22 +555,22 @@
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:C_Small") (at 123.19 138.43 0) (unit 1)
|
||||
(symbol (lib_id "Device:C_Small") (at 123.19 135.89 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 80948367-5a1c-4ed0-a3b4-d5c216f5fabd)
|
||||
(property "Reference" "C27" (at 124.46 137.16 0)
|
||||
(property "Reference" "C27" (at 124.46 134.62 0)
|
||||
(effects (font (size 1.27 1.27)) (justify left))
|
||||
)
|
||||
(property "Value" "2u2" (at 124.46 139.7 0)
|
||||
(property "Value" "2u2" (at 124.46 137.16 0)
|
||||
(effects (font (size 1.27 1.27)) (justify left))
|
||||
)
|
||||
(property "Footprint" "stdpads:C_0603" (at 123.19 138.43 0)
|
||||
(property "Footprint" "stdpads:C_0603" (at 123.19 135.89 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "~" (at 123.19 138.43 0)
|
||||
(property "Datasheet" "~" (at 123.19 135.89 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "LCSC Part" "C23630" (at 123.19 138.43 0)
|
||||
(property "LCSC Part" "C23630" (at 123.19 135.89 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 2c5ccc0d-1783-4464-b314-c36abdd87d91))
|
||||
@ -587,19 +587,19 @@
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "power:+3V3") (at 113.03 135.89 0) (unit 1)
|
||||
(symbol (lib_id "power:+3V3") (at 113.03 133.35 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 84038a3a-ec03-4561-af51-4c2bf6577707)
|
||||
(property "Reference" "#PWR0158" (at 113.03 139.7 0)
|
||||
(property "Reference" "#PWR0158" (at 113.03 137.16 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Value" "+3V3" (at 113.03 132.08 0)
|
||||
(property "Value" "+3V3" (at 113.03 129.54 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (at 113.03 135.89 0)
|
||||
(property "Footprint" "" (at 113.03 133.35 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 113.03 135.89 0)
|
||||
(property "Datasheet" "" (at 113.03 133.35 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 0c09ed82-7797-4e39-a3f0-32d1205e0707))
|
||||
@ -644,19 +644,19 @@
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "GW_Logic:741G04GW") (at 132.08 119.38 0) (unit 1)
|
||||
(symbol (lib_id "GW_Logic:741G04GW") (at 132.08 116.84 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 92d63a38-8fa6-4814-9313-4bd8cadaf786)
|
||||
(property "Reference" "U28" (at 132.08 113.03 0)
|
||||
(property "Reference" "U28" (at 132.08 110.49 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Value" "74LVC1G07GW" (at 132.08 125.73 0)
|
||||
(property "Value" "74LVC1G07GW" (at 132.08 123.19 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "stdpads:SOT-353" (at 132.08 127 0)
|
||||
(property "Footprint" "stdpads:SOT-353" (at 132.08 124.46 0)
|
||||
(effects (font (size 1.27 1.27)) (justify top) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 132.08 124.46 0)
|
||||
(property "Datasheet" "" (at 132.08 121.92 0)
|
||||
(effects (font (size 1.524 1.524)) hide)
|
||||
)
|
||||
(pin "1" (uuid e4abcf12-5a81-4dc4-be2f-e287cdbf6fd0))
|
||||
@ -698,19 +698,19 @@
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "power:+3V3") (at 142.24 116.84 0) (unit 1)
|
||||
(symbol (lib_id "power:+3V3") (at 142.24 114.3 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no) (fields_autoplaced)
|
||||
(uuid 9ae89df8-7591-49aa-9807-698d82c3cde2)
|
||||
(property "Reference" "#PWR017" (at 142.24 120.65 0)
|
||||
(property "Reference" "#PWR017" (at 142.24 118.11 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Value" "+3V3" (at 142.24 113.03 0)
|
||||
(property "Value" "+3V3" (at 142.24 110.49 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (at 142.24 116.84 0)
|
||||
(property "Footprint" "" (at 142.24 114.3 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 142.24 116.84 0)
|
||||
(property "Datasheet" "" (at 142.24 114.3 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid d6d42e78-5c9f-4e37-a9f7-3e9025b4b4db))
|
||||
@ -748,22 +748,22 @@
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:R_Small") (at 146.05 121.92 270) (unit 1)
|
||||
(symbol (lib_id "Device:R_Small") (at 146.05 119.38 270) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid af63e236-063d-4e9a-91c6-e1aaeb08194d)
|
||||
(property "Reference" "R2" (at 146.05 118.11 90)
|
||||
(property "Reference" "R2" (at 146.05 115.57 90)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Value" "47" (at 146.05 120.65 90)
|
||||
(property "Value" "47" (at 146.05 118.11 90)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom))
|
||||
)
|
||||
(property "Footprint" "stdpads:R_0603" (at 146.05 121.92 0)
|
||||
(property "Footprint" "stdpads:R_0603" (at 146.05 119.38 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "~" (at 146.05 121.92 0)
|
||||
(property "Datasheet" "~" (at 146.05 119.38 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "LCSC Part" "C23182" (at 146.05 121.92 0)
|
||||
(property "LCSC Part" "C23182" (at 146.05 119.38 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid cd9bf5a8-7226-4f49-a738-e9b34ab17a2e))
|
||||
|
||||
@ -182,30 +182,23 @@ The Ready signals are always high during ROM access so all ROM accesses complete
|
||||
|
||||
<h3 id="t5">5. Back-to-Back RAM Access</h3><script type="WaveDrom">{signal: [
|
||||
{name: 'MCLK', wave: 'p.........', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x..2............x..2............x......', phase: 0.00, period: 0.5, data:['000000-3FFFFF','000000-3FFFFF']},
|
||||
{name: 'RW', wave: 'x....2..........x....2..........x......', phase: 0.00, period: 0.5, data:['read or write','read or write']},
|
||||
{name: 'AS', wave: '1...x0........x1....x0........x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'BACT', wave: '2.0.x.1...........0.x.1...........0.x.2', phase: 0.00, period: 0.5},
|
||||
{name: 'BACTr', wave: '201..01..0', phase: 0.00, period: 2.0},
|
||||
{name: 'DS (RD)', wave: '1...x0........x1....x0........x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1.0.1.0.1.', phase:-0.10, period: 2.0},
|
||||
{name: 'DS (WR)', wave: '1.......x0....x1........x0....x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'WE (WR)', wave: '1.......x.0...x.1.......x.0...x.1......', phase:-0.10, period: 0.5},
|
||||
{name: 'RAMReady',wave: '1.........', phase: 0.00, period: 2},
|
||||
{name: 'DTACK', wave: '210..10..1', phase:-0.10, period: 2},
|
||||
{name: 'DTACKr', wave: '2.10..10..', phase: 0.00, period: 2},
|
||||
{name: 'D (FPMR)',wave: 'z.........x.2.xz..........x.2.xz.......', phase: 0.05, period: 0.5},
|
||||
{name: 'D (EDOR)',wave: 'z.........x.2...xz........x.2...xz.....', phase: 0.05, period: 0.5},
|
||||
{name: 'D (WR)', wave: 'z.....x.2.......xz....x.2.......xz.....', phase: 0.05, period: 0.5},
|
||||
{name: 'RS', wave: '2222222222', phase: 0.00, period: 2, data:[0,0,1,2,3,0,1,2,3,0]},
|
||||
{name: 'RASEN', wave: '1..0.1.0.1', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrr', wave: '1.01..01..', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrf', wave: '1..01..01.', phase: 1.00, period: 2.0},
|
||||
{name: 'RAS', wave: '1...x.0.......x1....x.0.......x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.1.0.1.0.', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2..x2..x.', phase: 0.25, period: 2, data:['000000-3FFFFF','000000-3FFFFF']},
|
||||
{name: 'RW', wave: 'x..1....x..1....x...', phase: 0.25, period: 1, data:['read or write','read or write']},
|
||||
{name: 'AS', wave: '1...x0........x1....x0........x1....x2.', phase:-0.25, period: 0.5},
|
||||
{name: 'DS (RD)', wave: '1...x0........x1....x0........x1.......', phase:-0.25, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1...x.0.......x.1...x.0.......x.1......', phase:-0.35, period: 0.5},
|
||||
{name: 'DS (WR)', wave: '1.......x0....x1........x0....x1.......', phase:-0.25, period: 0.5},
|
||||
{name: 'WE (WR)', wave: '1.......x.0...x.1.......x.0...x.1......', phase:-0.35, period: 0.5},
|
||||
{name: 'Ready', wave: 'x10.x10.x.', phase:-0.20, period: 2},
|
||||
{name: 'DTACK', wave: '1.0..10..1', phase:-0.20, period: 2},
|
||||
{name: 'D (RD)', wave: 'z....x2.z....x2.z...', phase:-0.30},
|
||||
{name: 'D (WR)', wave: 'z......x.2......z......x.2......z......', phase:-0.30, period:0.5},
|
||||
{name: 'RS', wave: '2222222222', phase:-0.20, period: 2, data:[0,0,5,6,7,0,5,6,7,0]},
|
||||
{name: 'RAS', wave: '1...x.0.......x.1...x.0.......x.1......', phase:-0.35, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.1.0.1.0.', phase:-0.20, period: 2},
|
||||
{name: 'RA', wave: 'x...x2..x2......x....2..x2......x......', phase:-0.20, period:0.5, data:['row','col','row','col']},
|
||||
{name: 'CAS', wave: '1..01..01.', phase: 0.90, period: 2},
|
||||
]}</script><p>
|
||||
{name: 'CAS', wave: '1..0.1.0.1', phase: 0.80, period: 2},
|
||||
]}</script><br/><p>
|
||||
This diagram introduces the DRAM access timing.
|
||||
</p><p>
|
||||
At 25 MHz for a 4-clock read cycle, there are only 2.5 clock cycles (100 ns) between
|
||||
@ -221,149 +214,112 @@ which outputs row addresses to the DRAM array when RASEL is low and column addre
|
||||
The /CAS signal is a function of RASEL. RASEL changes after FCLK rises. If RASEL is high at the next falling edge, /CAS is asserted.
|
||||
Otherwise if RASEL is low, /CAS is deasserted at the next falling edge.
|
||||
</p><p>
|
||||
"RS" is the RAM state. The RS state changes after the rising edge of the clock
|
||||
and can take on values 0-7. <br/>
|
||||
In RS0, the RAM is considered to be idle. <br/>
|
||||
At the rising edge of the clock in RS0 a RAM cycle begins if, if /AS is asserted,
|
||||
a RAM address is present, and a RAM cycle has not already occurred for this /AS cycle. <br/>
|
||||
In this case, we know that /RAS has been active for at least 10 nanoseconds, so RASEL is brogught high. <br/>
|
||||
This switches the RA bus from row to column addresses and RS0 transitions to RS5. <br/>
|
||||
At the falling edge in the middle of RS5, /CAS is brought low. RS5 always transitions to RS6. <br/>
|
||||
At the end of RS6, RASEL is brought low again, switching the RA multiplexers back to row addresses
|
||||
in preparation for the next DRAM access cycle. RS6 always transitions to RS7. <br/>
|
||||
RS7 is the state in which a RAM access or refresh is concluded. At the falling edge in the middle of RS7, /CAS is brought high. <br/>
|
||||
RS7 transitions to RS2 if a refresh request is pending, otherwise RS7 transitions to RS0. <br/>
|
||||
The states RS1 and RS2-RS4 will be discussed in association with the subsequent refresh cycle diagrams. <br/>
|
||||
The RS and RAMCS signals are used to generate the Ready0 ready signal input to the FSB.
|
||||
Ready0 is high if and only if RS==0 and RAMCS is active.<br/>
|
||||
</p><p>
|
||||
Also notice how, during write cycles,
|
||||
it is undefined whether the cycle is conducted as an "early write" or an "OE-controlled write" cycle. <br/>
|
||||
/OE is held high at all times during write cycles,
|
||||
but /LWE and /UWE are asynchronous functions of MC68k's /LDS and /UDS signals. <br/>
|
||||
It is undefined during a write cycle whether /LWE and /UWE will go low before or after /CAS falls. <br/>
|
||||
Since /OE is held high during write cycles, the order of the /WE signals and /CAS is of no consequence.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t6">6. Long-running RAM Access</h3><script type="WaveDrom">{signal: [
|
||||
{name: 'MCLK', wave: 'p.........', phase: 0.00, period: 2.0},
|
||||
{name: 'A', wave: 'x..2............................x......', phase: 0.00, period: 0.5, data:['000000-3FFFFF']},
|
||||
{name: 'RW', wave: 'x....2..........................x......', phase: 0.00, period: 0.5, data:['read or write']},
|
||||
{name: 'AS', wave: '1...x0........................x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'BACT', wave: '2.0.x.1...........................0.x.2', phase: 0.00, period: 0.5},
|
||||
{name: 'BACTr', wave: '201......0', phase: 0.00, period: 2.0},
|
||||
{name: 'DS (RD)', wave: '1...x0........................x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1.0.....1.', phase:-0.10, period: 2.0},
|
||||
{name: 'DS (WR)', wave: '1.......x0....................x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'WE (WR)', wave: '1.......x.0.....x1.....................', phase:-0.10, period: 0.5},
|
||||
{name: 'RAMReady',wave: '1.........', phase: 0.00, period: 2.0},
|
||||
{name: 'DTACK', wave: '21....0..1', phase:-0.10, period: 2.0},
|
||||
{name: 'DTACKr', wave: '2.1....0..', phase: 0.00, period: 2.0},
|
||||
{name: 'D (RD)', wave: 'z.........x.2...................xz.....', phase: 0.05, period: 0.5},
|
||||
{name: 'D (WR)', wave: 'z.....x.2.......................xz.....', phase: 0.05, period: 0.5},
|
||||
{name: 'RS', wave: '2222222222', phase: 0.00, period: 2.0, data:[0,0,1,2,2,2,2,2,3,0]},
|
||||
{name: 'RASEN', wave: '1..0.....1', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrr', wave: '1.01......', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrf', wave: '1..01.....', phase: 1.00, period: 2.0},
|
||||
{name: 'RAS', wave: '1...x.0.......x1....................x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.1.0.....', phase: 0.00, period: 2.0},
|
||||
{name: 'RA', wave: 'x...2...x2......x2..............x......', phase: 0.00, period: 0.5, data:['row','col','row']},
|
||||
{name: 'CAS', wave: '1..0....1.', phase: 0.90, period: 2.0},
|
||||
{name: 'MCLK', wave: 'p.........', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2......x.', phase: 0.25, period: 2, data:['000000-3FFFFF']},
|
||||
{name: 'RW', wave: 'x..1............x...', phase: 0.25, period: 1, data:['read or write','read or write']},
|
||||
{name: 'AS', wave: '1...x0........................x1.......', phase:-0.25, period: 0.5},
|
||||
{name: 'Ready', wave: '0....1....', phase:-0.20, period: 2},
|
||||
{name: 'DTACK', wave: '1.....0..1', phase:-0.20, period: 2},
|
||||
{name: 'D (RD)', wave: 'z....x2..z..........', phase:-0.30},
|
||||
{name: 'D (WR)', wave: 'z..x2...........z...', phase: 0.00},
|
||||
{name: 'RS', wave: '2222222222', phase:-0.20, period: 2, data:[0,0,5,6,7,0,0,0,0,0]},
|
||||
{name: 'RAS', wave: '1...x.0.......................x.1......', phase:-0.25, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.1.0.....', phase:-0.20, period: 2},
|
||||
{name: 'RA', wave: 'x...x2..x2......2...............x........', phase:-0.20, period:0.5, data:['row','col','row']},
|
||||
{name: 'CAS', wave: '1..0.1....', phase: 0.80, period: 2},
|
||||
]}</script><br/><p>
|
||||
This diagram shows the timing for a long-running RAM access, in which the RAM read or write completes sooner than MC68k removes /AS.
|
||||
This diagram shows the timing for a long-running RAM access,
|
||||
in which the RAM read or write completes sooner than MC68k removes /AS. <br/>
|
||||
</p><p>
|
||||
There are cases in which a DRAM access completes in time for termination of a 4-clock bus cycle,
|
||||
but the bus cycle is lengthened because not all of the Ready signals to the FSB controller have gone high. <br/>
|
||||
If RS0 is returned to after a DRAM access but /AS remains asserted,
|
||||
then the DRAM must not enter RS5-7 and thus not initiate any additional /CAS cycles. <br/>
|
||||
Notice how /CAS goes high in the middle of RS7 but /RAS stays low until the end of the /AS cycle.
|
||||
Using EDO DRAM allows the data bus output to be maintained while /RAS is low. <br/>
|
||||
However, if FPM DRAM is used or if a refresh cycle occurs before /AS rises,
|
||||
then maintenance of read data on the data bus falls to the bus capacitance and the bus hold resistors. <br/>
|
||||
Therefore it is best not to prolong DRAM read cycles, even when using EDO DRAM, so that there is no possibility of
|
||||
an intervening DRAM refresh cycle causing the data outputs to tristate. <br/>
|
||||
Fortunately, although DRAM write cycles shadowed to main sound and video memory need to be extended
|
||||
when the posted write FIFO is full, there is no need to extend DRAM read cycles. <br/>
|
||||
Therefore we do not attempt to extend the /CAS pulse to fix this problem until /AS rises since the /CAS pulse
|
||||
could be interrupted by a refresh cycle anyway. <br/>
|
||||
To fix this problem, we could extend the /CAS pulse until /AS is high and have the
|
||||
DRAM controller conform to the DRAM "hidden refresh" protocol but it is not necessary.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t7">7. Refresh During Idle</h3><script type="WaveDrom">{signal: [
|
||||
{name: 'MCLK', wave: 'p.......', phase: 0.00, period: 2.0},
|
||||
{name: 'A', wave: 'x...............................', phase: 0.00, period: 0.5, data:['000000-3FFFFF']},
|
||||
{name: 'RW', wave: 'x...............................', phase: 0.00, period: 0.5, data:['read or write']},
|
||||
{name: 'AS', wave: '1...............................', phase:-0.10, period: 0.5},
|
||||
{name: 'BACT', wave: '1...............................', phase: 0.00, period: 0.5},
|
||||
{name: 'BACTr', wave: '1.......', phase: 0.00, period: 2.0},
|
||||
{name: 'DS', wave: '1...............................', phase:-0.10, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1.......', phase:-0.10, period: 2.0},
|
||||
{name: 'WE (WR)', wave: '1...............................', phase:-0.10, period: 0.5},
|
||||
{name: 'RAMReady', wave: '1.......', phase: 0.00, period: 2.0},
|
||||
{name: 'DTACK', wave: '1.......', phase:-0.10, period: 2.0},
|
||||
{name: 'DTACKr', wave: '1.......', phase: 0.00, period: 2.0},
|
||||
{name: 'RS', wave: '22222222', phase: 0.00, period: 2.0, data:[0,0,4,5,6,7,0,0]},
|
||||
{name: 'RASEN', wave: '1.0...1.', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrr', wave: '1.0.1...', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrf', wave: '1.......', phase: 1.00, period: 2.0},
|
||||
{name: 'RAS', wave: '1.......x0......x1..............', phase:-0.10, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.......', phase: 0.00, period: 2.0},
|
||||
{name: 'RA', wave: 'x...............................', phase: 0.00, period: 0.5, data:['row','col','row']},
|
||||
{name: 'CAS', wave: '1.0.1...', phase: 0.90, period: 2.0},
|
||||
{name: 'MCLK', wave: 'p......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '1............', phase:-0.75},
|
||||
{name: 'RS', wave: '2222222', phase:-0.2, period: 2, data:[0,0,2,3,4,7,0,0,0]},
|
||||
{name: 'RefReq', wave: '01..0..', phase:-0.2, period: 2},
|
||||
{name: 'RASEN', wave: '1.0...1', phase:-0.2, period: 2},
|
||||
{name: 'RRAS', wave: '1.....0...1...', phase:-0.20},
|
||||
{name: 'RAS', wave: '1.....0...1...', phase:-0.40},
|
||||
{name: 'CAS', wave: '1..0.1.', phase: 0.80, period: 2},
|
||||
]}</script><br/><p>
|
||||
This diagram shows the timing of a refresh occurring after the bus and DRAM are and have been idle for at least one clock cycle.
|
||||
</p>
|
||||
</p><p>
|
||||
RAM states RS2, RS3, RS4, and RS7 are used for refresh. <br/>
|
||||
RS2-RS4 implement the main refresh behavior. <br/>
|
||||
When a refresh request is pending at the rising edge ending RS0 or RS7 while /RAS is inactive,
|
||||
RASEN is brought low and RS2 is entered. <br/>
|
||||
With RASEN low, /AS activity does not cause a /RAS pulse and the DRAM controller uses the registered /RRAS signal
|
||||
to initiate refresh cycles. <br/>
|
||||
At the falling edge in the middle of RS2, /CAS is activated. Then at the rising edge concluding RS2, /RAS is activated
|
||||
and RS2 transitions to RS3. <br/>
|
||||
In RS3, /RAS and /CAS remain active, and RS3 transitions to RS4.
|
||||
RS3 and RS4 serve to implement the requisite /RAS pulse width for a refresh. <br/>
|
||||
At the falling edge in the middle of RS4, /CAS is deactivated. Then at the rising edge concluding RS4, /RAS is deactivated
|
||||
and RS4 transitions to RS7. <br/>
|
||||
RREQ is cleared after the first rising edge on which RefRAS is active.<br/>
|
||||
In RS7, /RAS and /CAS remain inactive. RS7 serves to implement the requisite RAS precharge time between DRAM cycles.<br/>
|
||||
RASEN is brought high again after the rising edge concluding RS7 and RS7 transitions to RS0 and the DRAM is considered idle again.<br/>
|
||||
</p><p>
|
||||
Also notice how a RASEN can only be disabled if /RAS is high or if a DRAM cycle is complete, otherwise
|
||||
there may be a tRAS timing violation. This constrains the timing of a refresh.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t8">8A. Refresh Immediately Following DRAM Access - Idle afterwards</h3>
|
||||
<h3 id="t8">8. Refresh Immediately Following DRAM Access - Bus Transaction Terminated Immediately</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p............', phase: 0.00, period: 2.0},
|
||||
{name: 'A', wave: '2...x...............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'RW', wave: '2...x...............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'AS', wave: '0.x1................................................', phase:-0.10, period: 0.5},
|
||||
{name: 'BACT', wave: '1.....0.............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'BACTr', wave: '1.0..........', phase: 0.00, period: 2.0},
|
||||
{name: 'DS', wave: '0.x1................................................', phase:-0.10, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '01...........', phase:-0.10, period: 2.0},
|
||||
{name: 'WE (WR)', wave: '2.x.1...............................................', phase:-0.10, period: 0.5},
|
||||
{name: 'RAMReady', wave: '1............', phase: 0.00, period: 2.0},
|
||||
{name: 'DTACK', wave: '0.1..........', phase:-0.10, period: 2.0},
|
||||
{name: 'DTACKr', wave: '0..1.........', phase: 0.00, period: 2.0},
|
||||
{name: 'RS', wave: '2222222222222', phase: 0.00, period: 2.0, data:[2,3,4,5,6,7,0,0,0,0,0,0,0]},
|
||||
{name: 'RASEN', wave: '0.....1......', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrr', wave: '1.0.1........', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrf', wave: '1............', phase: 1.00, period: 2.0},
|
||||
{name: 'RAS', wave: '2.x1....x0......x1..................................', phase:-0.10, period: 0.5},
|
||||
{name: 'RASEL', wave: '20...........', phase: 0.00, period: 2.0},
|
||||
{name: 'RA', wave: '2...x...............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'CAS', wave: '010.1........', phase: 0.90, period: 2.0},
|
||||
]}
|
||||
</script><br/>
|
||||
|
||||
|
||||
<h3 id="t8">8B. Refresh Immediately Following DRAM Access - RAM access immediately afterwards</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p............', phase: 0.00, period: 2.0},
|
||||
{name: 'A', wave: '2...x...............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'RW', wave: '2...x...............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'AS', wave: '0.x1....x0..........................................', phase:-0.10, period: 0.5},
|
||||
{name: 'BACT', wave: '1.....0.x.1.........................................', phase: 0.00, period: 0.5},
|
||||
{name: 'BACTr', wave: '1.01.........', phase: 0.00, period: 2.0},
|
||||
{name: 'DS (RD)', wave: '0.x1....x0..........................................', phase:-0.10, period: 0.5},
|
||||
{name: 'DS (WR)', wave: '0.x1........x0......................................', phase:-0.10, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '010..........', phase:-0.10, period: 2.0},
|
||||
{name: 'WE (WR)', wave: '2.x..1......................x0......................', phase:-0.10, period: 0.5},
|
||||
{name: 'RAMReady', wave: '1............', phase: 0.00, period: 2.0},
|
||||
{name: 'DTACK', wave: '0.1..........', phase:-0.10, period: 2.0},
|
||||
{name: 'DTACKr', wave: '0..1.........', phase: 0.00, period: 2.0},
|
||||
{name: 'RS', wave: '2222222222222', phase: 0.00, period: 2.0, data:[2,3,4,5,6,7,0,1,2,3,0,0,0]},
|
||||
{name: 'RASEN', wave: '0.....1......', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrr', wave: '1.0.1..01....', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrf', wave: '1.......01...', phase: 1.00, period: 2.0},
|
||||
{name: 'RAS', wave: '2.x1....x0......x1......x0........x1................', phase:-0.10, period: 0.5},
|
||||
{name: 'RASEL', wave: '20.....1.0...', phase: 0.00, period: 2.0},
|
||||
{name: 'RA', wave: '2...x...............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'CAS', wave: '010.1...01...', phase: 0.90, period: 2.0},
|
||||
]}
|
||||
</script><br/>
|
||||
|
||||
|
||||
<h3 id="t8">9. Refresh Immediately Following DRAM Access - Bus Transaction Terminated Immediately</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.x1....................x0..', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '2222222', phase:-0.20, period: 2, data:[2,3,4,5,6,7,0]},
|
||||
{name: 'RASEN', wave: '0.....1', phase: 0.00, period: 2},
|
||||
{name: 'RASrr', wave: '1.0.1..', phase: 0.00, period: 2},
|
||||
{name: 'RASrf', wave: '01.....', phase: 1.00, period: 2},
|
||||
{name: 'RAS', wave: '0x1....x0......x1.......x0..', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0....1.', phase: 0.80, period: 2},
|
||||
{name: 'RASEL', wave: '0...1..', phase: 0.00, period: 2},
|
||||
]}
|
||||
</script><br/>
|
||||
|
||||
|
||||
<h3 id="t8">10. Refresh Immediately Following DRAM Access - Bus Transaction Terminated Immediately</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.x1....x0..................', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '2222222', phase:-0.20, period: 2, data:[2,3,4,5,6,7,0]},
|
||||
{name: 'RASEN', wave: '0.....1', phase: 0.00, period: 2},
|
||||
{name: 'RASrr', wave: '1.0.1..', phase: 0.00, period: 2},
|
||||
{name: 'RASrf', wave: '01.....', phase: 1.00, period: 2},
|
||||
{name: 'RAS', wave: '0x1....x0......x1......x.0..', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0....1.', phase: 0.80, period: 2},
|
||||
{name: 'RASEL', wave: '0...1..', phase: 0.00, period: 2},
|
||||
{name: 'MCLK', wave: 'p...', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.x1....x.......', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '2222', phase:-0.20, period: 2, data:[6,7,2,3,4]},
|
||||
{name: 'RefReq', wave: '21..', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '1.0.', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1..0', phase:-0.20, period:2},
|
||||
{name: 'RAS', wave: '0.x.1.......0..', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0.10', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the timing of a refresh occurring immediately after a RAM access cycle.
|
||||
@ -379,6 +335,113 @@ The purpose of this diagram is mainly to demonstrate that adequate /RAS and /CAS
|
||||
after the previous DRAM access is terminated before /RAS is pulsed for refresh.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t9">9. Refresh Immediately Following DRAM Access - Bus Transaction Terminated While Refresh In-Progress</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.............x1....x......', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '2222222', phase:-0.20, period: 2, data:[6,7,2,3,4,7,0,0,0,0]},
|
||||
{name: 'RefReq', wave: '21..0..', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '1.0...1', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1..0.1.', phase:-0.20, period:2},
|
||||
{name: 'RAS', wave: '0.......1...0.......1...x..', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0.10.1.', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the case where a refresh request occurs during a long-running DRAM access
|
||||
and the /AS cycle terminates before the refresh ends.
|
||||
</p><p>
|
||||
It is possible for a DRAM access cycle to be extended for a long time, during which the DRAM may be deprived of refresh. <br/>
|
||||
Therefore we must provide for the case where a DRAM access completes and a refresh begins but before /AS ever goes high. <br/>
|
||||
In this case, the rising edge of RASEN causes /RAS to go inactive, as opposed to the rising edge of /AS. <br/>
|
||||
Therefore, the /RAS precharge pulse width in this case is much shorter than
|
||||
a refresh occurring during idle or immediately following a DRAM access. <br/>
|
||||
At 25 MHz, the /RAS precharge width is only 40ns. This is the minimum tRP for 60ns DRAM and is the tightest timing parameter in the Warp-SE. <br/>
|
||||
We could purpose RS1 to add additional precharge time if necessary.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t10">10. Refresh Immediately Following DRAM Access - Bus Transaction Terminated After Refresh Completes</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p........', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.........................x1....x...', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '222222222', phase:-0.20, period: 2, data:[6,7,2,3,4,7,0,0,0]},
|
||||
{name: 'RefReq', wave: '21..0....', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '1.0.....1', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1..0.1...', phase:-0.20, period:2},
|
||||
{name: 'RAS', wave: '0.......1...0.......1...........x...', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0.10.1...', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the case where a refresh request occurs during a long-running DRAM access
|
||||
and the /AS cycle does not terminate before the refresh ends.
|
||||
</p><p>
|
||||
This case is similar to the previous but there is a key difference.
|
||||
/AS does not rise until after the refresh cycle completes. <br/>
|
||||
Therefore if RASEN were brought high upon exit from RS7 into RS0, there may be an improperly-short /RAS pulse
|
||||
terminated by the rising edge of the /AS. <br/>
|
||||
Consequently RASEN enablement is held off the first rising edge during which BACT is low.
|
||||
</p>
|
||||
|
||||
<h3 id="t11">11. Refresh in the "Middle" of DRAM Access</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0...........................', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '2222222', phase:-0.20, period: 2, data:[6,7,0,0,0,2,3]},
|
||||
{name: 'RefReq', wave: '0...1..', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '1....0.', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1.....0', phase:-0.20, period:2},
|
||||
{name: 'RAS', wave: '0...................1...0...', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0.1...0', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the case where a refresh request occurs in the "middle" of a long-running DRAM access. <br/>
|
||||
The remainder of the timing is given by diagrams 9 or 10.
|
||||
</p>
|
||||
|
||||
<h3 id="t12">12. Concurrent DRAM Access and Refresh Requests</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p.........', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2......x.', phase: 0.25, period: 2, data:['000000-4FFFFF']},
|
||||
{name: '/AS', wave: '1..x0........................x1........', phase:-0.75, period: 0.5},
|
||||
{name: 'DTACK', wave: '1.....0..1', phase:-0.30, period: 2},
|
||||
{name: 'DS (RD)', wave: '1..x0........................x1.......', phase:-0.75, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1...x.0......................x.1.....', phase:-0.75, period: 0.5},
|
||||
{name: 'DS (WR)', wave: '1......x0....................x1.......', phase:-0.75, period: 0.5},
|
||||
{name: 'WE (WR)', wave: '1.......................0....x.1......', phase:-0.75, period: 0.5},
|
||||
{name: 'RS', wave: '2222222222', phase:-0.20, period: 2, data:[0,2,3,4,7,0,5,6,7,0]},
|
||||
{name: 'Ready0', wave: 'x0...10.x.', phase:-0.20, period: 2},
|
||||
{name: 'RefReq', wave: '1..0......', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '10...1....', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1...0...1...........', phase:-0.20},
|
||||
{name: '/RAS', wave: '1.......0.......1...0.........x.1......', phase:-0.45, period: 0.5},
|
||||
{name: '/CAS', wave: '1.0.1..0.1', phase: 0.70, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the timing of a refresh starting concurrently with the beginning of a RAM access cycle.
|
||||
</p><p>
|
||||
Here we see the timing of refresh being entered concurrently with the start of a RAM access.
|
||||
In this case, there is a little bit of a race condition. <br/>
|
||||
RASEN and /AS both fall following the rising edge of FCLK. /AS causes /RAS activation asynchronously,
|
||||
but RASEN gates this from occurring. <br/>
|
||||
Therefore the internal RASEN feedback in the CPLD must occur sooner than /AS transitions,
|
||||
otherwise an erroneous /RAS pulse will be generated. <br/>
|
||||
Fortunately the CPLDs intended to be used (ispMACH4000, XC9500XL) are some 10 years newer than MC68HC000,
|
||||
so their speed advantage mitigates the problem. <br/>
|
||||
The negation of Ready0 causes /DTACK generation and termination of the bus cycle
|
||||
to be delayed until completion of the refresh. <br/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Before showing the timing for the I/O bus slave port on the FSB,
|
||||
it's instructive to understand the timing of the I/O bus master controller.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t13">13. I/O Bus E State, VMA, "ETACK"</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
@ -420,7 +483,7 @@ terminate the /AS cycle in synchronization with the E clock going low.
|
||||
<h3 id="t14">14. I/O Bus Access (Even Phase)</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'IOS', wave:'22222222222222222222|222222', period: 1,data:[0,0,0,0,0,0,0,2,3,4,5,6,7,0,1,2,3,4,5,5,5,6,7,0,0,0,0]},
|
||||
{name: 'IOS', wave:'22222222222222222222|222222', period: 1,data:[0,0,0,0,0,0,1,2,3,4,5,6,7,0,1,2,3,4,5,5,5,6,7,0,0,0,0]},
|
||||
{name: 'C16M', wave:'p...................|......', period: 1},
|
||||
{name: 'C8M', wave:'10101010101010101010|101010', phase:-0.25, period: 1},
|
||||
{name: 'C8Mr', wave:'01010101010101010101|010101', phase:-0.10, period: 1},
|
||||
|
||||
432
Power.kicad_sch
432
Power.kicad_sch
@ -56,49 +56,6 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol "GW_Power:AZ1117CH2" (pin_names (offset 0.254)) (in_bom yes) (on_board yes)
|
||||
(property "Reference" "U" (at -3.81 3.175 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Value" "AZ1117CH2" (at 0 3.175 0)
|
||||
(effects (font (size 1.27 1.27)) (justify left))
|
||||
)
|
||||
(property "Footprint" "Package_TO_SOT_SMD:SOT-223-3_TabPin2" (at 0 5.08 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "http://www.diodes.com/datasheets/AP1117.pdf" (at 2.54 -6.35 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_keywords" "linear regulator ldo fixed positive obsolete" (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_description" "1A Low Dropout regulator, positive, 1.5V fixed output, SOT-223" (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_fp_filters" "SOT?223*TabPin2*" (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(symbol "AZ1117CH2_0_1"
|
||||
(rectangle (start -5.08 -5.08) (end 5.08 1.905)
|
||||
(stroke (width 0.254) (type default))
|
||||
(fill (type background))
|
||||
)
|
||||
)
|
||||
(symbol "AZ1117CH2_1_1"
|
||||
(pin power_in line (at -7.62 0 0) (length 2.54)
|
||||
(name "VI" (effects (font (size 1.27 1.27))))
|
||||
(number "1" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin power_in line (at 0 -7.62 90) (length 2.54)
|
||||
(name "GND" (effects (font (size 1.27 1.27))))
|
||||
(number "2" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin power_out line (at 7.62 0 180) (length 2.54)
|
||||
(name "VO" (effects (font (size 1.27 1.27))))
|
||||
(number "3" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol "Regulator_Linear:AP1117-33" (pin_names (offset 0.254)) (in_bom yes) (on_board yes)
|
||||
(property "Reference" "U" (at -3.81 3.175 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
@ -288,108 +245,111 @@
|
||||
)
|
||||
)
|
||||
|
||||
(junction (at 153.67 73.66) (diameter 0) (color 0 0 0 0)
|
||||
(uuid 0774b60f-e343-428b-9125-3ca983239ad5)
|
||||
)
|
||||
(junction (at 143.51 81.28) (diameter 0) (color 0 0 0 0)
|
||||
(uuid 0844b132-5386-469c-86ff-d527c8a00608)
|
||||
(junction (at 153.67 60.96) (diameter 0) (color 0 0 0 0)
|
||||
(uuid 1ee5518b-ccdc-4d65-abc1-f029e274dbf5)
|
||||
)
|
||||
(junction (at 133.35 60.96) (diameter 0) (color 0 0 0 0)
|
||||
(uuid 248d15cd-dd0c-425d-94cb-b44ccf865457)
|
||||
)
|
||||
(junction (at 163.83 60.96) (diameter 0) (color 0 0 0 0)
|
||||
(uuid 32bb1cf8-0770-4fb5-9d58-b3b107fb90a1)
|
||||
)
|
||||
(junction (at 118.11 60.96) (diameter 0) (color 0 0 0 0)
|
||||
(uuid 6cf4c995-24c3-4139-b7f9-08f8dc6734e9)
|
||||
)
|
||||
(junction (at 153.67 53.34) (diameter 0) (color 0 0 0 0)
|
||||
(uuid 7c3fa13a-5250-4394-8d82-80430597df04)
|
||||
)
|
||||
(junction (at 143.51 53.34) (diameter 0) (color 0 0 0 0)
|
||||
(uuid 8afefa03-006b-4e40-b19e-6596c7cc472e)
|
||||
)
|
||||
(junction (at 118.11 73.66) (diameter 0) (color 0 0 0 0)
|
||||
(uuid a12c94a5-1fd0-4cb6-9bfe-f7529f451405)
|
||||
(junction (at 107.95 53.34) (diameter 0) (color 0 0 0 0)
|
||||
(uuid 8c16244d-15ee-4444-ac35-03149dbbc04c)
|
||||
)
|
||||
(junction (at 118.11 53.34) (diameter 0) (color 0 0 0 0)
|
||||
(uuid a6460cc6-b11c-4dff-a0ea-9de680e68ca8)
|
||||
)
|
||||
(junction (at 143.51 73.66) (diameter 0) (color 0 0 0 0)
|
||||
(uuid f17daa22-500e-4b54-81a7-f5c3878a87d9)
|
||||
(junction (at 173.99 53.34) (diameter 0) (color 0 0 0 0)
|
||||
(uuid ec048a2c-81fb-4fbe-a8a8-0c8b56bc6417)
|
||||
)
|
||||
(junction (at 163.83 53.34) (diameter 0) (color 0 0 0 0)
|
||||
(uuid ed1ba302-39e8-4d2f-8c70-2af62de1967c)
|
||||
)
|
||||
(junction (at 143.51 60.96) (diameter 0) (color 0 0 0 0)
|
||||
(uuid f368b66f-c8a4-4ccf-b925-3f03c13bf28f)
|
||||
)
|
||||
(junction (at 133.35 81.28) (diameter 0) (color 0 0 0 0)
|
||||
(uuid f8fd3b2c-9550-4b51-be47-a8d9567c972f)
|
||||
)
|
||||
|
||||
(wire (pts (xy 133.35 81.28) (xy 143.51 81.28))
|
||||
(wire (pts (xy 163.83 53.34) (xy 173.99 53.34))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 0452da17-4ccf-4bdc-9fc3-b0a09600bd55)
|
||||
(uuid 016bea59-b0cc-46a2-946f-c4c0aea931c9)
|
||||
)
|
||||
(wire (pts (xy 163.83 60.96) (xy 153.67 60.96))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 07957d36-e6de-4293-889f-dd48aa7442e6)
|
||||
)
|
||||
(wire (pts (xy 133.35 60.96) (xy 143.51 60.96))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 0a83f85d-78ad-480a-a5ba-773caced8f09)
|
||||
)
|
||||
(wire (pts (xy 118.11 73.66) (xy 125.73 73.66))
|
||||
(wire (pts (xy 153.67 53.34) (xy 163.83 53.34))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 0ea0e524-3bbd-4f05-896d-54b702c204b2)
|
||||
(uuid 0b759af8-bc66-4f0b-86a0-7a6dc50423b8)
|
||||
)
|
||||
(wire (pts (xy 118.11 53.34) (xy 107.95 53.34))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 169a33b2-843e-459e-8e80-c0b1e6d66af5)
|
||||
)
|
||||
(wire (pts (xy 118.11 53.34) (xy 125.73 53.34))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 172b515f-13aa-42a2-b6ac-db67c2e524e7)
|
||||
)
|
||||
(wire (pts (xy 140.97 73.66) (xy 143.51 73.66))
|
||||
(wire (pts (xy 107.95 60.96) (xy 118.11 60.96))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 1d20c966-0439-42a1-b5e3-5e76b52f827f)
|
||||
)
|
||||
(wire (pts (xy 118.11 81.28) (xy 133.35 81.28))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 2fe436e0-75bf-42a2-b14a-09df5c2be702)
|
||||
)
|
||||
(wire (pts (xy 143.51 73.66) (xy 153.67 73.66))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 42012069-f136-4cdf-8386-a5e648d61587)
|
||||
(uuid 33c4cf3f-b59f-4098-b639-a6a94ab44646)
|
||||
)
|
||||
(wire (pts (xy 118.11 59.69) (xy 118.11 60.96))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 42688fc6-3e24-4a56-9963-828da46dcdfb)
|
||||
)
|
||||
(wire (pts (xy 107.95 53.34) (xy 107.95 54.61))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 6071a42e-4a1d-4c0a-8ac3-7b542cb47894)
|
||||
)
|
||||
(wire (pts (xy 153.67 59.69) (xy 153.67 60.96))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 6afdccaa-d9c7-4949-88e8-e04bfdac5efc)
|
||||
)
|
||||
(wire (pts (xy 153.67 81.28) (xy 143.51 81.28))
|
||||
(wire (pts (xy 163.83 59.69) (xy 163.83 60.96))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 6b847b8a-c935-4366-8f7b-7cdbe96384da)
|
||||
(uuid 6b2e8b27-fbf2-402a-89ca-78389e82fa1d)
|
||||
)
|
||||
(wire (pts (xy 118.11 80.01) (xy 118.11 81.28))
|
||||
(wire (pts (xy 163.83 53.34) (xy 163.83 54.61))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 7195a7f5-2a0f-4cae-8649-2cc5cbdffe2b)
|
||||
)
|
||||
(wire (pts (xy 143.51 81.28) (xy 143.51 80.01))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 82bf2831-f69a-4cf1-ad28-e7c6c4e8c86f)
|
||||
(uuid 75b0aef6-fcee-4461-a833-3483a1b0bdb1)
|
||||
)
|
||||
(wire (pts (xy 153.67 53.34) (xy 153.67 54.61))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 8634edb8-50db-43d2-95bb-5918d2cd24cc)
|
||||
)
|
||||
(wire (pts (xy 107.95 59.69) (xy 107.95 60.96))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 88f55395-290d-4308-a5f9-c42c34fbdc37)
|
||||
)
|
||||
(wire (pts (xy 143.51 60.96) (xy 143.51 59.69))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 9116f42f-8d27-4055-8fab-af8b6ed6959f)
|
||||
)
|
||||
(wire (pts (xy 118.11 73.66) (xy 118.11 74.93))
|
||||
(wire (pts (xy 173.99 59.69) (xy 173.99 60.96))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid 920101e0-4dde-4453-ba02-4211cb357ea2)
|
||||
)
|
||||
(wire (pts (xy 143.51 73.66) (xy 143.51 74.93))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid a0e74fdd-2272-42b1-9d9a-65553efcd00a)
|
||||
(uuid 91a179d2-763d-4e9f-a662-f86f9fff7695)
|
||||
)
|
||||
(wire (pts (xy 140.97 53.34) (xy 143.51 53.34))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid a5c35670-98af-44c6-a3f4-bbad7ffecfd3)
|
||||
)
|
||||
(wire (pts (xy 153.67 73.66) (xy 153.67 74.93))
|
||||
(wire (pts (xy 173.99 53.34) (xy 173.99 54.61))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid aafd680e-f3de-44c3-b8d2-897188909f89)
|
||||
(uuid a6d1d31d-b40a-40d5-907b-55385f150648)
|
||||
)
|
||||
(wire (pts (xy 118.11 60.96) (xy 133.35 60.96))
|
||||
(stroke (width 0) (type default))
|
||||
@ -411,9 +371,9 @@
|
||||
(stroke (width 0) (type default))
|
||||
(uuid d32a1d0f-6a8f-45b4-822f-8b613131fd8a)
|
||||
)
|
||||
(wire (pts (xy 153.67 80.01) (xy 153.67 81.28))
|
||||
(wire (pts (xy 173.99 60.96) (xy 163.83 60.96))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid eb14ae89-b776-4a7c-b1cb-51227ede5631)
|
||||
(uuid d545442f-50b0-4b83-a1a6-14023c5e60d0)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Regulator_Linear:AP1117-33") (at 133.35 53.34 0) (unit 1)
|
||||
@ -422,7 +382,7 @@
|
||||
(property "Reference" "U3" (at 133.35 48.26 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Value" "AZ1117EH-3.3" (at 133.35 50.8 0)
|
||||
(property "Value" "AZ1117CH-3.3" (at 133.35 50.8 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom))
|
||||
)
|
||||
(property "Footprint" "stdpads:SOT-223" (at 133.35 48.26 0)
|
||||
@ -446,19 +406,19 @@
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "power:+5V") (at 118.11 53.34 0) (unit 1)
|
||||
(symbol (lib_id "power:+5V") (at 107.95 53.34 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 00000000-0000-0000-0000-000061b3bd83)
|
||||
(property "Reference" "#PWR0129" (at 118.11 57.15 0)
|
||||
(property "Reference" "#PWR0129" (at 107.95 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Value" "+5V" (at 118.11 49.53 0)
|
||||
(property "Value" "+5V" (at 107.95 49.53 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (at 118.11 53.34 0)
|
||||
(property "Footprint" "" (at 107.95 53.34 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 118.11 53.34 0)
|
||||
(property "Datasheet" "" (at 107.95 53.34 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid fd280548-080f-491d-8485-51ae1657051d))
|
||||
@ -496,31 +456,6 @@
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "power:+3V3") (at 153.67 53.34 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 00000000-0000-0000-0000-000061b3d39e)
|
||||
(property "Reference" "#PWR0131" (at 153.67 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Value" "+3V3" (at 153.67 49.53 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (at 153.67 53.34 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 153.67 53.34 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid dd93ec60-b84b-4853-b486-c06d6c1e5026))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "#PWR0131") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:C_Small") (at 118.11 57.15 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 00000000-0000-0000-0000-000061b3df5f)
|
||||
@ -579,166 +514,6 @@
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:C_Small") (at 143.51 77.47 0) (mirror y) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 00000000-0000-0000-0000-000061b3ee84)
|
||||
(property "Reference" "C9" (at 146.05 76.2 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Value" "10u" (at 146.05 78.74 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Footprint" "stdpads:C_0805" (at 143.51 77.47 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "~" (at 143.51 77.47 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "LCSC Part" "C15850" (at 143.51 77.47 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 34de68e5-d1e4-4d02-a1cb-2a1379b3eaf9))
|
||||
(pin "2" (uuid 22ba32b4-365e-448b-b6f7-f583a824e6c0))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "C9") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "GW_Power:AZ1117CH2") (at 133.35 73.66 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 00000000-0000-0000-0000-000061b4296a)
|
||||
(property "Reference" "U4" (at 133.35 68.58 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Value" "DNP-AZ1117CH2-3.3" (at 133.35 71.12 0)
|
||||
(effects (font (size 1.27 1.27)) (justify bottom))
|
||||
)
|
||||
(property "Footprint" "stdpads:SOT-223" (at 133.35 68.58 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "http://www.diodes.com/datasheets/AP1117.pdf" (at 135.89 80.01 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid cce2c676-c672-4797-85a4-57c0a3198a5b))
|
||||
(pin "2" (uuid 2f98599d-49e6-43ee-9e2f-c58f195bd81d))
|
||||
(pin "3" (uuid a4338cca-4794-4652-b587-def866d15162))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "U4") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "power:+5V") (at 118.11 73.66 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 00000000-0000-0000-0000-000061b42970)
|
||||
(property "Reference" "#PWR0136" (at 118.11 77.47 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Value" "+5V" (at 118.11 69.85 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (at 118.11 73.66 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 118.11 73.66 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid ed619012-0670-467c-ad33-ba1729b8733f))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "#PWR0136") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "power:GND") (at 133.35 81.28 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 00000000-0000-0000-0000-000061b42978)
|
||||
(property "Reference" "#PWR0137" (at 133.35 87.63 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Value" "GND" (at 133.35 85.09 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (at 133.35 81.28 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 133.35 81.28 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 3979143c-9aaf-4fbf-8ff0-d14d88a64d42))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "#PWR0137") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "power:+3V3") (at 153.67 73.66 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 00000000-0000-0000-0000-000061b4297e)
|
||||
(property "Reference" "#PWR0139" (at 153.67 77.47 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Value" "+3V3" (at 153.67 69.85 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (at 153.67 73.66 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 153.67 73.66 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 7d8be866-44ba-4bb2-8897-3ceba4fb52e1))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "#PWR0139") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:C_Small") (at 118.11 77.47 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 00000000-0000-0000-0000-000061b42984)
|
||||
(property "Reference" "C4" (at 115.57 76.2 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Value" "10u" (at 115.57 78.74 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Footprint" "stdpads:C_0805" (at 118.11 77.47 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "~" (at 118.11 77.47 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "LCSC Part" "C15850" (at 118.11 77.47 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 093ec4a0-0ee4-4594-8bdb-2d21e6fbf11f))
|
||||
(pin "2" (uuid 9b95814f-669b-409a-9290-19c501fed11b))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "C4") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:C_Small") (at 153.67 57.15 0) (mirror y) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 00000000-0000-0000-0000-000061b4298f)
|
||||
@ -768,26 +543,109 @@
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:C_Small") (at 153.67 77.47 0) (mirror y) (unit 1)
|
||||
(symbol (lib_id "Device:C_Small") (at 163.83 57.15 0) (mirror y) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 00000000-0000-0000-0000-000061b42999)
|
||||
(property "Reference" "C10" (at 156.21 76.2 0)
|
||||
(uuid 1b4b01dc-3e66-4759-89d3-fd312939f66e)
|
||||
(property "Reference" "C9" (at 166.37 55.88 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Value" "10u" (at 156.21 78.74 0)
|
||||
(property "Value" "10u" (at 166.37 58.42 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Footprint" "stdpads:C_0805" (at 153.67 77.47 0)
|
||||
(property "Footprint" "stdpads:C_0805" (at 163.83 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "~" (at 153.67 77.47 0)
|
||||
(property "Datasheet" "~" (at 163.83 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "LCSC Part" "C15850" (at 153.67 77.47 0)
|
||||
(property "LCSC Part" "C15850" (at 163.83 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid c6d248c1-3a60-47cd-ba0f-1abdfcd1cfdb))
|
||||
(pin "2" (uuid a155eac0-c833-4bed-b97d-1f5e65d354bc))
|
||||
(pin "1" (uuid 07344bba-5ce6-4a5d-8286-68fcbc8a47cd))
|
||||
(pin "2" (uuid bd9f67ae-1e2c-49d6-abcf-99e80b4104ae))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "C9") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "power:+3V3") (at 173.99 53.34 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 5c6352b1-8792-4bf7-b620-189e229be5d1)
|
||||
(property "Reference" "#PWR025" (at 173.99 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Value" "+3V3" (at 173.99 49.53 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (at 173.99 53.34 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 173.99 53.34 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 470aada9-829c-480d-9232-756b34522830))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "#PWR025") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:C_Small") (at 107.95 57.15 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 9774af56-8e6c-43f2-b1a4-812a34de1810)
|
||||
(property "Reference" "C4" (at 105.41 55.88 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Value" "10u" (at 105.41 58.42 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Footprint" "stdpads:C_0805" (at 107.95 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "~" (at 107.95 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "LCSC Part" "C15850" (at 107.95 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid af556cd9-cdfa-4414-b548-84662ff8466a))
|
||||
(pin "2" (uuid 542182e8-a04e-4d15-bf62-22259bef9898))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "C4") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:C_Small") (at 173.99 57.15 0) (mirror y) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 9d3d51a8-d1d0-4ba6-9980-26c7d1d1c409)
|
||||
(property "Reference" "C10" (at 176.53 55.88 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Value" "10u" (at 176.53 58.42 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Footprint" "stdpads:C_0805" (at 173.99 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "~" (at 173.99 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "LCSC Part" "C15850" (at 173.99 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid dfcfb5ab-1d5f-432b-b554-6209ece946c2))
|
||||
(pin "2" (uuid 136d4e5d-dbec-47fa-a193-e06c732d1a8b))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
|
||||
965
Prog.kicad_sch
965
Prog.kicad_sch
File diff suppressed because it is too large
Load Diff
138131
WarpSE.kicad_pcb
138131
WarpSE.kicad_pcb
File diff suppressed because it is too large
Load Diff
@ -3,8 +3,8 @@
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"board_outline_line_width": 0.15,
|
||||
"copper_line_width": 0.15239999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
@ -38,7 +38,7 @@
|
||||
"height": 0.4,
|
||||
"width": 0.4
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_line_width": 0.15,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
@ -66,13 +66,13 @@
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"copper_sliver": "error",
|
||||
"courtyards_overlap": "warning",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"duplicate_footprints": "error",
|
||||
"extra_footprint": "error",
|
||||
"footprint": "error",
|
||||
"footprint_type_mismatch": "error",
|
||||
"hole_clearance": "error",
|
||||
@ -82,13 +82,13 @@
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_issues": "ignore",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"missing_footprint": "error",
|
||||
"net_conflict": "error",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
@ -97,7 +97,7 @@
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"solder_mask_bridge": "warning",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_thickness": "warning",
|
||||
@ -117,20 +117,20 @@
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.508,
|
||||
"min_clearance": 0.15,
|
||||
"min_connection": 0.12,
|
||||
"min_copper_edge_clearance": 0.4064,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_hole_to_hole": 0.254,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_resolved_spokes": 2,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_text_height": 0.7999999999999999,
|
||||
"min_text_thickness": 0.08,
|
||||
"min_through_hole_diameter": 0.19999999999999998,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.15,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_annular_width": 0.09999999999999999,
|
||||
"min_via_diameter": 0.5,
|
||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
@ -186,11 +186,8 @@
|
||||
0.45,
|
||||
0.5,
|
||||
0.6,
|
||||
0.7,
|
||||
0.8,
|
||||
1.0,
|
||||
1.2,
|
||||
1.2,
|
||||
1.27,
|
||||
1.524
|
||||
],
|
||||
@ -201,7 +198,7 @@
|
||||
},
|
||||
{
|
||||
"diameter": 0.5,
|
||||
"drill": 0.2
|
||||
"drill": 0.3
|
||||
},
|
||||
{
|
||||
"diameter": 0.6,
|
||||
@ -215,18 +212,6 @@
|
||||
"diameter": 1.0,
|
||||
"drill": 0.5
|
||||
},
|
||||
{
|
||||
"diameter": 1.2,
|
||||
"drill": 0.6
|
||||
},
|
||||
{
|
||||
"diameter": 1.27,
|
||||
"drill": 0.635
|
||||
},
|
||||
{
|
||||
"diameter": 1.5,
|
||||
"drill": 0.75
|
||||
},
|
||||
{
|
||||
"diameter": 1.524,
|
||||
"drill": 0.762
|
||||
@ -477,7 +462,7 @@
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.15,
|
||||
"via_diameter": 0.5,
|
||||
"via_drill": 0.2,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
(fp_lib_table
|
||||
(lib (name stdpads)(type KiCad)(uri ${KIPRJMOD}/../stdpads.pretty)(options "")(descr ""))
|
||||
(version 7)
|
||||
(lib (name "stdpads")(type "KiCad")(uri "$(KIPRJMOD)/../stdpads.pretty")(options "")(descr ""))
|
||||
)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user